Abstract

Digital Logic Technology has a strong impact in our daily lives. Therefore a course in Digital Logic
Design Concepts becomes a standard requirement for undergraduates majoring in computer science,
physics, and electrical engineering. In most cases, students have a problem in getting the books which
are simply written so that they understand the concepts.
In this book, emphasis is on digital logic design. This book assumes no background in computers on the
part of the student but a good background in physics and mathematics is a requirement. Our intention, as
authors of this book, is to present a set of procedures commonly encountered in Digital Logic Design to
help students grasp the basic concepts.
Our philosophy as authors of this book is that an introductory course in Digital Logic Design should
establish a strong foundation on the basic principles that are provided by a more traditional approach to
the design of combinational and sequential circuits before one engages on the use of computer-aided
design tools. Once the basic concepts and principles have been mastered then the use of design software
becomes more meaningful and allows the student to use the design software more effectively. The book
provides a lot of worked examples and self-assessment exercises which enables students to evaluate
themselves.

i
Acknowledgements
This book would not be complete without acknowledging the great assistance and support received
from the various members of academic staff in the School of Information and Communications
Technology and in from the university at large. For the successful completion of this book, I would
like to thank the editor and head of the engineering department, Dr Josephat Kalezhi for devoting his
precious time to go through the whole book making suggestions and corrections.

ii
Table of Contents
LECTURE 1 HISTORY OF COMPUTERS ..................................................................................................................... 1
1.1 Introduction .....................................................................................................................................................1
1.2 First Generation (1946-1954). .........................................................................................................................1
Limitations or disadvantages of first generation computers ...............................................................................2
1.3 Second Generation (1955-1964)......................................................................................................................2
Features of second generation computers ...........................................................................................................3
1.4 Third Generation (1964-1977) .........................................................................................................................3
1.5 Fourth Generation (1971-1980).......................................................................................................................4
1.6 Fifth Generation (1991- onwards) .............................................................................................................5
LECTURE 2 COMPUTER COMPONENTS ................................................................................................................... 7
2.1 Major components of a computer system......................................................................................................7
2.3 Components and their functions.....................................................................................................................9
2.3.1 Input Unit...................................................................................................................................................9
2.3.2 The Control Unit........................................................................................................................................9
2.3.3 The Main Memory .....................................................................................................................................9
2.3.4 Arithmetic and Logic units (ALU) ............................................................................................................9
2.3.5 Output Unit ............................................................................................................................................. 10
2.3.6 The secondary storage ............................................................................................................................ 10
LECTURE 3 NUMBER SYSTEMS .............................................................................................................................. 12
3.1 Introduction .................................................................................................................................................. 12
3.2 Base Values ................................................................................................................................................... 12
3.3 Decimal Number System (Base 10) ........................................................................................................ 12
3.4 Binary Number system (Base 2) ............................................................................................................. 12
3.5 Octal Base System (Base 8)........................................................................................................................... 12
3.6 Hexadecimal Number System (Base16) ....................................................................................................... 13
3.8 Method 2: Using the Binary Exponential Placeholders. .............................................................................. 14
3.9 Method 3: Using the Multiplication method to convert decimal fractions to binary ................................ 15
3.10 Converting decimal numbers to octal number system ............................................................................. 17
Method 1: Using the remainder theorem ......................................................................................................... 17
3.11 Converting decimal numbers to Hexadecimal number system ................................................................ 18
3.12 Converting from binary numbers to octal number system ....................................................................... 20
3.13 Converting binary numbers to hexadecimal number system ................................................................... 21

iii
LECTURER 4 COMBINATIONAL LOGIC CIRCUITS ................................................................................................... 23
4.1. Boolean algebra ........................................................................................................................................... 23
4.2 Laws of Boolean algebra ............................................................................................................................... 24
LECTURE 5 TRUTH TABLES ................................................................................................................................... 29
5.1 Introduction .................................................................................................................................................. 29
5.2 Forms of Boolean Expressions ...................................................................................................................... 30
5.3 The Sum of Products (SOP) form .................................................................................................................. 31
5.4 The Product of Sums (POS) form .................................................................................................................. 31
LECTURE 6 DIGITAL LOGIC GATES ......................................................................................................................... 35
6.1 Introduction .................................................................................................................................................. 35
6.2 NOT Logic gate ........................................................................................................................................ 35
6.3 Buffer............................................................................................................................................................. 35
6.4 The OR Logic Gate ......................................................................................................................................... 36
6.5 The AND logic gate ........................................................................................................................................ 36
6.6 The NOR logic gate........................................................................................................................................ 37
6.7 The NAND logic gate ..................................................................................................................................... 37
6.8 Exclusive OR (XOR) logic gate ....................................................................................................................... 38
6.9 Exclusive NOR (XNOR) logic gate .................................................................................................................. 39
6.10 Deriving Boolean functions from truth tables ........................................................................................... 40
7.1 Introduction .................................................................................................................................................. 43
7.3 The Karnaugh Map Method of Minimizing Boolean Functions .................................................................. 44
7.4 Two variable Karnaugh map ......................................................................................................................... 45
7.5 Examples of minimizing 2-Boolean variables functions .............................................................................. 46
7.6 Karnaugh Maps Rules used in the Simplification of Boolean Functions ..................................................... 47
7.7 The three variable Karnaugh map ................................................................................................................ 48
LECTURE 8 THE TABULAR METHOD ...................................................................................................................... 51
8.1 Introduction .................................................................................................................................................. 51
8.2 Rules of Tabular Method .............................................................................................................................. 51
8.3Using a chart to remove redundant prime implicates. .................................................................................... 58
LECTURE 9 COMBINATIONAL LOGIC CIRCUIT BUILDING BLOCKS ........................................................................ 63
9.1 Implementation of Logic Gates .................................................................................................................... 63
9.2 Adders ........................................................................................................................................................... 63
............................................................................................................................................................................... 64
9.3 Full Adder (FA) .............................................................................................................................................. 64
iv
9.4 Comparators ................................................................................................................................................. 67
9.5 Comparator for equality ............................................................................................................................... 67
9.6 Full Comparator ............................................................................................................................................ 69
10.1 Multiplexers ................................................................................................................................................ 72
10.2 DE multiplexor ............................................................................................................................................ 74
LECTURE 11 COMBINATIONAL LOGIC CIRCUIT BUILDING BLOCKS ....................................................................... 81
11.1 Decoders ..................................................................................................................................................... 81
11.2 Encoders ...................................................................................................................................................... 82
11.3 Priority encoder .......................................................................................................................................... 84
LECTURE 12 SEQUENTIAL LOGIC CIRCUITS ........................................................................................................... 87
12.1 Introduction ................................................................................................................................................ 87
12.2 The SR Latch ................................................................................................................................................ 88
LECTURE 13 SEQUENTIAL LOGIC CIRCUITS ........................................................................................................... 94
13.1 The Clocked JK flip flop ............................................................................................................................... 94
13.2 The JK Master-Slave Flip Flop ............................................................................................................... 97
13.3 The T (Toggle) Flip Flop ............................................................................................................................... 98
13.4 The D (data) Flip flop ................................................................................................................................ 100
LECTURE 14 EDGE TRIGGERED FLIP FLOPS.......................................................................................................... 102
14.1 Positive edge transition and negative edge transition ............................................................................ 102
14.2 Negative edge clock transition ................................................................................................................. 103
14.3 Flip flop state diagrams ............................................................................................................................ 103
LECTURER 15 SEQUENTIAL CIRCUIT EQUATIONS................................................................................................ 106
15.1 Typical sequential circuit diagram ........................................................................................................... 106
15.3 Full design of a sequential circuit ............................................................................................................. 107
LECTURE 16 BINARY COUNTERS.......................................................................................................................... 111
16.2 Counter Types ........................................................................................................................................... 111
16.3 4 –bit Asynchronous binary up counter ................................................................................................... 111
16.4 A 4-bit Asynchronous binary down counter ............................................................................................ 113
LECTURE 17 SYNCHRONOUS BINARY COUNTERS ............................................................................................... 116
17.1 Introduction .............................................................................................................................................. 116
17.2 A 4-bit binary synchronous up counter.................................................................................................... 116
17.3 A 4-bit binary synchronous down counter .............................................................................................. 117
17.3 synchronous reversible counters ............................................................................................................. 118
LECTURE 18 COMPUTER REGISTERS ................................................................................................................... 120
v
18.1 Introduction .............................................................................................................................................. 120
18.2 Computer register operations .................................................................................................................. 120
18.3 Shift Registers ....................................................................................................................................... 124
18.4 Serial in serial out register ........................................................................................................................ 124
18.5 Serial in parallel out (SIPO) register ......................................................................................................... 126
18.6 Parallel in Serial out (PISO) register ......................................................................................................... 127
REFERENCES ........................................................................................................................................................ 130

vi
LECTURE 1 HISTORY OF COMPUTERS

1.1 Introduction
History of computers is generally referred to as computer generation. The term generation will be used
throughout this module to refer to the history of computers. Each computer generation is differentiated
from the other by the technological development (i.e. the technology used to implement/build the
computer). This in turn changed how the computers operated. To date, five (5) computer generations are
known and these are based on the characteristics of computers developed from time to time. A computer
generation is roughly a period of ten years.

Computer

Generations

First Second Third Fourth Fifth

Generation Generation Generation Generation Generation

1946-1959 1959-1965 1965-1971 1971-1980 1980-onwards

Figure 1: Computer Generations

Authors differ on the dates (years) of computer generations but the best classification is using the
technology used to implement computers in each generation. Previously, only the technology was used
to define a computer generation but presently both the technology and software are used to characterize
computer generations ((Computer generations n.d. www.tutorialspoint.com).

1.2 First Generation (1946-1954).

These digital computers were using electronic valves (Vacuum tubes). The vacuum tubes were costly
and this prevented their use for main memory. They stored information in the form of propagating sound
waves. The vacuum tube by its nature consumes a lot of power and these computers were large in size
and writing programs on them was difficult. Some of the images of electronic vacuum tubes or valves:

1
Figure 2: Images of electronic tubes or valves

Limitations or disadvantages of first generation computers

 used valves or vacuum tubes as their main electronic component.

 were large in size, slow in processing and had less storage capacity.
 consumed lots of electricity and produced lots of heat.
 their computing capabilities were limited.
 were not so accurate and reliable.
 they used machine level language for programming.
 they were very expensive.

Examples of popular First generation computers include:

 Electronic Numerical Integrator and Calculator (ENIAC) developed in 1946

 Electronic Delay Storage Automatic Computer(EDSAC) 1949
 Universal Accounting Computer (UNIVAC-1) developed 1951 and was the first computer to
be used commercially.
 International Business Machine (IBM 650) and others.

1.3 Second Generation (1955-1964)

The second-generation computer used transistors for the Central Processing Unit (CPU) components,
ferrite cores for main memory and magnetic disks for secondary memory. They used high-level
languages such as Formula Translation (FORTRAN 1956), Algorithm Language (ALGOL 1960) and
Common Business Oriented Language (COBOL 1960 - 1961). The Second generation computers
included an Input/output Processor to control the Input/output operations.

Figure 3: (a) Transistor image

2
Figure 4: (a) n-p-n transistor diagram (b) p-n-p transistor diagram

In figure 4(a) and (b) B is the base, C is the collector and E is the emitter.

In the second generation computers, programming languages such as COBOL, FORTRAN were
developed. Some examples of the computers of the Second Generation computers
included:

 IBM 1620: Its size was smaller as compared to First Generation computers and mostly used for
scientific purpose
 IBM 1401: Its size was small to medium and used for business applications
 CDC 3600: Its size was large and is used for scientific purposes.

Features of second generation computers

 Transistors were used instead of Vacuum Tubes.

 Processing speed is faster than First Generation Computers (Micro Second)
 Smaller in Size (51 square feet)
 The input and output devices were faster.

Example: IBM 1400 and 7000 Series, Control Data 3600 and others.

1.4 Third Generation (1964-1977)

These computers were implemented using integrated circuits (ICs) or chips. A small chip has capacity
of the 300 transistors. These ICs are popularly known as Chips. A single IC has many transistors,
registers and capacitors built on a single thin slice of silicon. Since the transistors are small in size
compared to the vacuum tubes, the size of the computers got further reduced. Some of the computers
developed during this period were IBM-360, ICL-1900, IBM-370, and VAX-750. Higher level language
such as BASIC (Beginners All-purpose Symbolic Instruction Code) was developed during this
period. Computers of this generation were small in size, low cost, large memory and processing speed is
very high.

3
Figure 5: Image of an integrated circuit

Features of third generation computers

 They used Integrated Circuit (IC) chips in place of the transistors.

 Semi-conductor memory devices were used.
 The size was greatly reduced, the speed of processing was high, and they were more accurate
and reliable.
 Large Scale Integration (LSI) and Very Large Scale Integration (VLSI) were also developed.
 The mini computers were introduced in this generation.
 They used high level language for programming.

Most popular examples of this generation are: IBM 360, IBM 370 and others.

1.5 Fourth Generation (1971-1980)

The 4th generation computers were developed using Large Scale Integrated circuits (LSIs). An IC
containing about 100 components is called LSI (Large Scale Integration) and the one, which has more
than 1000 such components, is called as VLSI (Very Large Scale Integration). It uses large scale
Integrated Circuits (LSIC) built on a single silicon chip called microprocessors. This chip (Intel 4004)
developed by Intel in 1971, helped in the reduction of the size of the computer. Due to the development
of a microprocessor it is possible to place a computer‟s central processing unit (CPU), memory and
input/out controls on a single chip (Burns, D. n.d. The five generations of computer,
www.btob.co.nz).These computers are called microcomputers. Later very large scale Integrated Circuits
(VLSIC) replaced LSICs. So a computer which was occupying a very large room in earlier days could
now be placed on a table.

Figure 6: Very Large Scale Integration (VLSI)

The personal computer (PC) that we now see in our schools or at our homes are fourth generation
computers. The main memory used fast semiconductors chips with a capacity of up to 4 MB. Hard disks
were used as secondary memory. Keyboards, dot matrix printers etc. were developed. Operating systems
such as MS-DOS, UNIX, and Apple‟s Macintosh were available. Object oriented language, C++ and
others were developed.

4
Features of fourth generation computers

 They used Microprocessor (VLSI) as their main switching element.

 They are also called as micro computers or personal computers.
 Their size varies from desktop to laptop or palmtop.
 They have very high speed of processing; they are 100% accurate, reliable, diligent and
versatile.
 They have very large storage capacity.

Examples of the fourth generation computers include: IBM PC, Apple-Macintosh and others.

1.6 Fifth Generation (1991- onwards)

Classifying 5th generation according to technology alone is debatable. Some authors argue that the
technology is still the same (integrated circuits) and it is only the scaling that has changed.5th generation
computers use ULSI (Ultra-Large Scale Integration) chips. Millions of transistors are placed in a single
IC in ULSI chips. 64 bit microprocessors have been developed during this period. Data flow & EPIC
architecture of these processors have been developed.

Figure 7: Ultra-Large Scale Integration (ULSI) images

Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computers (CISC), both these
types of designs are used in modern processors. Memory chips and flash memory up to 1 GB, hard disks
up to 600 GB & optical disks up to 50 GB have been developed. Fifth generation digital computer are
Artificial intelligence.

Characteristics of Fifth Generation Computers

The Fifth Generation Computers have special characteristics and the following are some of them:

 Use intelligent programming languages such as List Processor (LISP), Programming Logic
(PROLOG), Python and others
 Use high performance multi-processor system
 Have easy human computer interfaces
 Use knowledge based problem solving techniques

5
Activity
1 Consider the size of the 1st generation computer to present day laptops and say what you think about
the following: Size, Speed, Reliability and Accuracy. What is your conclusion?
2 The difference between fourth and fifth generation computers is debatable in terms of hardware
technology used. Support or refute this statement.
3 What is most remarkable about 4th generation computers?
Resources for exploration:

William Stallings, Computer Organization and Architecture, p 17-18 Computer Generations:

http://www.tutorialspoint.com/computer_fundamentals/computer_generations.htm

Vangie Beal The five Generations of Computer, September 01, 2016

www.webopedia.com/DidYouKnow/Hardware_software/FiveGenerations.asp

Najmi , ( Aug. 13, 2004) http://www.techiwarehouse.com/engine/a046ee08/Generations-of-Computer

Dinesh Thakur. Nd History of Computers http://ecomputernotes.com/fundamental/introduction-to-

computer/what-are-different-computer-generations-explain-in-brief

Exercise
1 There is no technological differences in terms of hardware implementation between the 4th and the 5th
generation computers. How can you then distinguish between 4th and 5th generation computers?
2 Compare and contrast the 3rd and 4th generation computers in terms of the following:

 Implementation technology
 Software
 Size
 Speed
 Application areas
3 The first generation computers were built on Von Neumann‟s stored program principle. Explain
the basic concept of this principle

6
LECTURE 2 COMPUTER COMPONENTS
2.1 Major components of a computer system
The major components of a computer system are:

 Input unit
 Central Processing Unit (CPU)
 Main Memory
 Output unit.
 Secondary Storage

Figure 7: Basic Components of a Computer

2.2 Functional components of a computer system

The components of a computer system in figure 7 above can be expanded into functional components as
shown in figure 8 below. These are:

 CPU
 ALU
 Main Memory
 Input Unit
 Output Unit
 Secondary Storage

7
 CPU and Main Memory

MAIN MEMORY

INPUT UNIT CONTROL UNIT OUTPUT UNIT

ARITHMETIC & LOGIC

UNITS (ALU)

SECONDARY STORAGE

Figure 8: Functional components of a computer system

Key

Data flow
Instruction flow

8
2.3 Components and their functions

2.3.1 Input Unit

The purpose of the input unit is to accept data and convert it into an acceptable form, for example
decimal or alphabetic data must be converted to binary data (a series of binary ones and zeros) which the
computer understands. There is now a variety of input devices but the keyboard and the mouse are the
most widely used these days. Examples of input devices are:

 Keyboard
 Mouse
 Card reader
 Bar code reader
 Voice input and others.

2.3.2 The Control Unit

The purpose of the control unit is to fetch instructions from main memory, decode the instruction and
prompt its execution by any of the other units, for example an arithmetic instruction would be executed
by the Arithmetic unit (AU) and a logic or Boolean instruction would be executed by the Logic Unit
(LU). So the control unit coordinates the operation of the entire computer system.

2.3.3 The Main Memory

The main memory is made up of two parts:

 Random Access Memory (RAM)

 Read Only Memory (ROM)

The RAM is used to store data that is in current use. This type of memory is volatile and will lose all its
contents should there be any interruption in power supply. ROM is used to store data or information
permanently and if there interruption of power, the previous stored information or data is not lost. So it
is called non- volatile. ROM is programmed and inserted by the manufacturer.

Note that ROM is also randomly accessed but the random is silent in ROM. ROM is used to store
operating system programs (systems software) that used to start up the computer system.

2.3.4 Arithmetic and Logic units (ALU)

The purpose of this unit is to carry out all arithmetic operations such as addition, subtraction, division
and others. The function of the logic unit is process logic or Boolean operations such as comparing two
numbers to find out whether they are the same or ORing two binary numbers and others.

9
2.3.5 Output Unit

The purpose of this unit is to convert data from machine form into a form suitable for human
understanding for example from binary data to decimal or text which humans can understand. There are
a range of output devices but most common are:

 Printer
 Visual Display Unit(VDU)
 Plotter
 Computer output on Microfilm(COM)
 Voice Synthesizer and others.

2.3.6 The secondary storage

This unit is known by several names such permanent storage, mass storage, bulky storage and others. Its
purpose is to store data permanently for future use. Examples of secondary storage devices include
among others:

 Magnetic disks
 Magnetic tapes
 Floppy disks
 USB flash disks and others.

Exercise
1 The designer of a computer system had a manual system in mind. Draw a diagram of a manual system
that corresponds to a computer system and explain:

 Its basic parts (components)

 Its operation
2 A computer is better than a human being. Is this a true reflection of a computer system?
3 Consider the various input and output devices available and classify them according to application
areas.
Resources for exploration:

French, C.S. (1996) Data Processing and Information Technology

William Stalling (2006), Computer Organization and architecture, p 19-20

Manas Singh Basic functional units of a computer system, January 04, 2013. Can be accessed
From:www.discuss.desk.com/what-are-the-basic-functional-units-of-a-computer-system.htm.

French, C.S.(1996) Data Processing and Information Technology

http://searchsoftwarequality.techtarget.com/definition/garbage-in-garbage-out
10
http://bpastudio.csudh.edu/fac/lpress/vbmodules/hdts/computerComponents.htm

Exercise

1 A computer is defined as a system, why would it e wrong to define it as a device?

2 The main memory of a computer is divided into Random Access Memory (RAM) and Read Only
Memory (ROM), tablet the major distinguishing between these two memories.

3 The computer system is associated with the principle” garbage in, garbage out (GIGO)” do you agree
with this principle? Yes/no? Explain your answer in either case.

11
LECTURE 3 NUMBER SYSTEMS
3.1 Introduction
A number system defines a set of values used to represent quantity. We talk about the number of people
attending class, the number of modules taken per student, and also use numbers to represent grades
achieved by students in tests. Quantifying values and items in relation to each other is helpful for us to
make sense of our environment. The study of number systems is not just limited to computers. We apply
numbers every day, and knowing how numbers work will give us an insight into how a computer
manipulates and stores numbers.
3.2 Base Values
The base value of a number system is the number of different values the set has before repeating itself.
For example, decimal has a base of ten values, 0 to 9.
Decimal = 10 (0 - 9)
Binary = 2 (0, 1)
Octal = 8 (0 - 7)
Hexadecimal = 16 (0 - 9, A-F)
We will limit ourselves to the above number base systems due to their usage in the area of computing.
3.3 Decimal Number System (Base 10)
This number base system is also called denary system and is the most common to us as human beings as
we use it in our daily lives to do calculations and counting. It uses ten (10) different symbols to represent
values. The set values used in decimal are 0 1 2 3 4 5 6 7 8 9 and 0 has the least value and nine has the
greatest value. The digit on the left has the greatest value, whilst the digit on the right has the least value.
To count in base ten, you go from 0 to 9, and then do combinations of two digits starting with 10 all the
way to 99. To count in base ten, you go from 0 to 9, then do combinations of two digits starting with 10
all the way to 99 After 99 comes three-digit combinations from 100 – 999, etc. This combination system
is true for any base you use. The only difference is how many digits you have before you go to the next
combination
Although this is the most common number base system in use in our daily lives, the computers do not
use this base for representing data/information.
3.4 Binary Number system (Base 2)
The binary number system uses two values to represent numbers. The values are, 0 and a 1. These two
values have also the interpretations of FALSE for a 0 and TRUE for a 1, LOW for a 0 and HIGH for a 1,
OFF for 0 and ON for a 1. Zero (0) has the least value, and one (1) has the greatest value. The least
value is also called the least significant bit (LSB), the greatest value the most significant bit (MSB). To
count in base two, you count 0,1, then switch to two digit combinations, 10,11, then to three digit
combos, 100, 101,110,111, then four digit, 1000, _____,_______, …, 1111
3.5 Octal Base System (Base 8)
The octal number system uses eight values to represent numbers. The values are 0, 1,2, 3, 4, 5, 6, 7 with
0 having the least value and seven having the greatest value. These numbers can be used by machine
language programmers as short hand for binary Numbers. Three binary digits are equivalent to 1 octal
digit. For example 68  110 2 .

12
3.6 Hexadecimal Number System (Base16)
The hexadecimal number system uses sixteen values to represent numbers. The values are, 0 1 2 3 4 5 6
7 8 9 A B C D E F with 0 having the least value and F having the greatest value. These numbers like
octal numbers can also be used by machine and assembly language programmers to help simply low
level programming. Four binary digits are equivalent to 1 hexadecimal digit. For example 916  10012

3.7 Converting decimal numbers to binary numbers

There are a number of ways to convert between decimal and binary. This book will consider three
methods; the remainder theorem also called the division method and the Binary Exponential
Placeholders method for the whole numbers (integral part) and the multiplication method for decimal
values (fractional part).

Method 1: Using the remainder theorem

Steps
1. Divide the decimal number by 2, and note down the remainder
2. Divide the quotient by 2 and note the remainder
3. Repeat step 2 until the number is no longer divisible by 2
4. Write down the remainder values in reverse order.
Example 1
Convert 15010 to binary using the division method

13
Example 2

Convert 13210 to binary equivalent

Thus the binary equivalent of 13210 is 100001002

3.8 Method 2: Using the Binary Exponential Placeholders.

This method uses the binary weighting system and is also sometimes referred to as the 8:4:2:1 approach.
Each column represents a power of 2. To make things easy one must to know the binary exponential
holders.

Example 1

Convert 1110 to its binary equivalent.

The highest power of two number nearest to eleven is 3, so 23 is 8

We write 8 4 2 1
1 0 1 1

We ask ourselves the question, can 8 be subtracted from 11? The answer is yes, we write a one under the
column 8. We subtract 8 from 11 and the answer is 3. The next highest power of two is 4. Ask ourselves
the question; can 4 be subtracted from 3? Answer is no. Write a zero (o) under column 4. The next
highest power of 2 is two. Ask ourselves the question, can two be subtracted from 3. The answer is yes
and we write 1 under column 2. We subtract 2 from 3. The answer is 1. The next highest power of two is
1. We ask ourselves the question; can 1 be subtracted from 1? The answer is yes, we write a 1under
column 1.

So 1110 is equivalent to 10112

14
Example 2:

Convert 19710 to binary using Binary Exponential Placeholders. The highest Binary Exponential
Placeholders next to 197 is 128, which is 27. If 128 can be subtracted from 197, we write a 1 in column
128, Subtract 128 from 197. The answer is 69. If 64 can be subtracted from 69, we put a 1 in column in
64. We subtract 64 from 69. The answer is 5. 32 cannot be subtracted from 5. We put a zero (0) in
column 32. Next is column is 8, which cannot be subtracted from 5 and we put a 0 in column 8. Next is
column 4. 4 can be subtracted from 5, so we put a 1 in column 4. Subtract 4 from 5 and the answer is 1.
Next column is 2 and 2 cannot be subtracted from 1 and we write a 0 in column 2. Next column is 1 and
1 can be subtracted from 1, so we put a 1 in column 1.

Positional weight 27 26 25 24 23 22 21 20
Value 128 64 32 16 8 4 2 1
Number 1 1 0 0 0 1 0 1

So 1 1 0 0 0 1 0 12 is equivalent to 19710

3.9 Method 3: Using the Multiplication method to convert decimal fractions to binary

Decimal fractions are converted to binary fractions equivalent using the multiplication method.

Steps

1. Write down the decimal fraction

2. Multiply the decimal fraction by 2
3. Write down the whole number part
4. Repeat steps 2 and 3 until the degree of accuracy has been achieved.
5. Write down the whole numbers in the order you produced them.

Note that when converting decimal fractions to their binary equivalents, we should do this to a given
degree of accuracy, i.e. the number of decimal points places that are needed. When using binary
fractions it is recommended to use a less number of decimal places as the fractions become very
inaccurate as the number of decimal points increases.

Example1:

Convert 0.12510 to binary equivalent

.125  2  0.250 whole number part  0 MSB

.250  2  0.500 whole number part  0
.500  2  1.000 whole number part  1 LSB

Thus the binary equivalent of 0.12510 is 0012

15
Example 2:

Convert 0.25510 to binary equivalent

.255  2  0.510 whole number part  0 MSB

.510  2  1.020 whole number part  1
.020  2  0.040 whole number part  0 LSB

Thus the binary equivalent of 0.25510 is 0.0102

The major disadvantage of converting decimal fractions to binary fractions is that some precision can be
lost in the process of conversion, for example not all terminating decimal fractions have a terminating
binary equivalent, and example 2 above is non-terminating binary fraction. When we covert 0.0102 back
to decimal, we will get 0.25010 and not 0.25510.

Example 3:

Convert 132.12510 to binary equivalent

This example involves converting mixed decimal numbers to binary. Use the steps below to convert
such number:

Steps

1. Use the remainder theorem to convert the decimal number to binary

2. Use the multiplication method to convert the decimal fraction to binary fraction
3. Write the binary integer part, followed by a period and then the fraction part.

We convert the whole number (integer) part using the division method

Activity
1 Why is it that when converting decimal fractions we should be concerned with the degree of accuracy?
2 Convert 0.64710 to help you answer the question.
3 You can also verify the correctness of your answer by working with decimal fractions with 4 or 5
decimal places

Convert (.12510) to a binary fraction

We convert the fraction part (.12510) to binary equivalent using the multiplication method.

.125  2  0.250 whole number part  0 MSB

.250  2  0.500 whole number part  0
.500  2  1.000 whole number part  1 LSB

Therefore 132.12510 is equivalent to 10000100.0012

16
3.10 Converting decimal numbers to octal number system

To convert from decimal and octal, two methods will be used; the remainder theorem also called the
division method and integers and the multiplication method for decimal fraction.

Method 1: Using the remainder theorem

Steps

1. Divide the decimal number by 8 and note down the remainder

2. Divide what's left (quotient) by 8 and note the remainder
3. Repeat step 2 until the number is no longer divisible by 8
4. Write down the remainders values in reverse order.

Example 1

Convert 17610 in octal to decimal

176
 22 remainder 0 LSB
8
22
 2 remainder 6
8
2
 0 remainder 2 M SB
8

Thus the Octal equivalent of 17610 is 2608

Method 2: Using the multiplication method to convert decimal fractions to octal system
Steps
1. Write down the decimal fraction
2. Multiply the decimal fraction by 8
3. Write down the whole number part
4. Repeat steps 2 and 3 until the degree of accuracy has been achieved.
5. Write down the whole numbers in the order you produced them.

17
Example 1:

Convert 0.062510 to octal number system equivalent

.0625  8  0.500 whole number part  0 MSB

.500  8  4. 000 whole number part  4 LSB

Thus the Octal equivalent of 0.062510 is 0.48

Example 2:

Convert 176.062510 to octal equivalent

This example involves converting mixed decimal numbers to octal. Use the steps below to convert such
number:

Steps

1. Use the remainder theorem to convert the decimal number to octal

2. Use the multiplication method to convert the decimal fraction to octal fraction
3. Write the octal integer part, followed by a period and then the fraction part.

We convert the whole number (integer) part using the division method

176
 22 remainder 0 LSB
8
22
 2 remainder 6
8
2
 0 remainder 2 M SB
8

Thus the octal equivalent is 2608

We convert the fraction part (0.062510) to binary equivalent using the multiplication method.

.0625  8  0.500 whole number part  0 MSB

.500  8  4. 000 whole number part  4 LSB

Therefore 176.062510 is equivalent to 260.048

3.11 Converting decimal numbers to Hexadecimal number system

The steps used to convert decimal numbers to binary and to octal also apply when converting decimal
numbers to hexadecimal.

18
Method 1: Using the remainder theorem

Steps

1. Divide the decimal number by 16 and note down the remainder

2. Divide what's left by 16 and note the remainder
3. Repeat step 2 until the number is no longer divisible by 16
4. Write down the remainder values in reverse order.

Example

Convert 51010 to hexadecimal number system

510
 31 remainder 14 LSB
16
31
 1 remainder 15
16
1
 0 remainder 1 M SB
16

Thus the hexadecimal equivalent is EF116

Method 2: Using the multiplication method to convert decimal fractions to Hexadecimal

Steps

1. Write down the decimal fraction

2. Multiply the decimal fraction by 16
3. Write down the whole number part
4. Repeat steps 2 and 3 until the degree of accuracy has been achieved.
5. Write down the whole numbers in the order you produced them.

Example1:

Convert 0.0312510 to hexadecimal number system equivalent

.03125  16  0.500 whole number part  0 MSB

.50000  16  8. 000 whole number part  8 LSB

Thus the Hexadecimal equivalent of 0.0312510 is 0.816

19
Example 2:

Convert 510.0312510 to hexadecimal equivalent

This example involves converting mixed decimal numbers to hexadecimal. Use the steps below to
convert such number:

Steps

1. Use the remainder theorem to convert the decimal number to hexadecimal

2. Use the multiplication method to convert the decimal fraction to hexadecimal fraction
3. Write the hexadecimal integer part, followed by a period and then the fraction part.

We convert the whole number (integer) part using the division method.

510
 31 remainder 14 LSB
16
31
 1 remainder 15
16
1
 0 remainder 1 M SB
16

Thus the octal equivalent is EF116

We convert the fraction part (0.0312510) to hexadecimal equivalent using the multiplication method.

.03125  16  0.500 whole number part  0 MSB

.50000  16  8. 000 whole number part  8 LSB

Therefore 510.0312510 is equivalent to EF1.0816

3.12 Converting from binary numbers to octal number system

One of the advantages of the binary number system representation is the easy conversion to octal and
hexadecimal number systems.

Steps

1. Write down the binary number

2. Dive the binary bits into groups of three bits starting from the least significant bit
3. If the number of bits to the left most bit is less than three bits, add zero(s)
4. Convert the groups of three bits each to decimal
5. Put together the converted groups and this gives the equivalent octal number

20
Example

Convert 110100110012 to octal number system

011 010 011 001
011 = 3; 010 = 2; 011 = 3; 001= 1
Thus 110100110012 is equivalent to 32318

3.13 Converting binary numbers to hexadecimal number system

The same steps used to convert binary numbers to octal number system apply except that instead of
diving the binary bits into groups of three, subdivide them into groups of four (4).

Steps

1. Write down the binary number

2. Divide the binary bits into groups of four bits starting from the least significant bit
3. If the number of bits to the left most bit is less than four bits, then add zero(s)
4. Convert the groups of four bits each to decimal
5. Put together the converted groups and this gives the hexadecimal number

Example

Convert 110100110012 to hexadecimal number system

0110 1001 1001
0110 = 6; 1001 = 9; 1001 = 9
So 110100110012 = 69916

Activity

1 Consider the following numbers in different bases:

 6210 and 628 – which of the two numbers is larger in value

 Why is it really necessary to know the computer number base systems?

2 How would you quickly convert the following numbers base 10 numbers to bases 2, 8 and 16:

(i) 25610,
(ii) 28010

3 Is it possible to use the binary exponential placeholders when converting decimal numbers to octal or
hexadecimal equivalents?

21
Resources for further exploration:

William Stalling (2006), Computer organization and architecture, pp 693-699

Number Bases: Introduction and Binary Numbers, Purple math, Can be accessed at:
www.purplemath.com/module/numbbase.htm

https://betterexplained.com/articles/numbers-and-bases/

Exercise

1 Imagine a world without number systems, what problems would be encountered?

2 Why do you think the binary number system is preferred for use in computers rather than the decimal
number system?

3 In small computers systems such as desk tops, laptops and others, octal decimal or hexadecimal
numbers systems are preferred rather than binary. Explain any two reasons why?

22
LECTURER 4 COMBINATIONAL LOGIC CIRCUITS
4.1. Boolean algebra
Boolean algebra is the most fundamental tool used to analyze and describe the operations of digital logic
circuits. Digital computers are built on digital logic circuits and the digital logic circuits are derived
from Boolean functions /expressions.
The obvious way to look at Boolean functions is to manipulate them in the same way as
conventional/normal algebraic expressions but one has to stick to the set of rules formulated by the
English Mathematician George Boole.
In Boolean algebra, a variable say A can take only two valuations, i.e. A = 1 or 0, which have also the
logic interpretations True for A = 1 and False for A= 0 or High for A=1 and Low for A = 0, and On for
A = 1 and Off for A = 0. A = 0 is also known as A (NOT A).
The basic Boolean operators are:

 AND (∙)
 OR (+)
 NOT (-)

Boolean equations/expressions are formed by combining Boolean variables with Boolean operators for
example: F  A.B  B(C  D) . The application A.B can be written simply as AB. When Boolean
variables are combined with Boolean operators a number of rules can be derived from these relations.
These basic rules are called postulates or rules of Boolean algebra. Postulates are basic axioms that are
rules that have proven beyond any reasonable doubt that they are correct, so they do not need any proof.

Examples of Postulates

P1: A = 0 or A = 1

P2: 0.0 = 0

P3: 1+0 = 1

P4: 0+0 = 0

P5: 1.1= 1

P6: 1+1=1

P7: 1.0 = 0

These Boolean postulates are used to prove laws and theorems of Boolean algebra.

23
4.2 Laws of Boolean algebra

The basic laws/properties of Boolean algebra are:

 Commutative
 Distributive
 Identity
 Complement
 Associative

The commutative property sates that: The order that two Boolean variables appear in an AND or OR
function is not significant, for example (AB = BA), (A+B) = (B+A).

The distributive property shows how a Boolean variable is distributed over an expression with which it is
ANDed, for example A (B+C) = AB+AC or A+BC= (A+B) (A+C).

The identity property states that a variable that is ANDEd or is ORed with itself produces the original
variable, for example A.A = A or A + A = A.

The complement is derived from the involution theorem which states that the complement of a
complement leaves the original variable unchanged.

AA
For example:
AA

The Associative law/property states that the order of ORing or ANDing Boolean variables is logically of
no consequence, for example (A+B) +C =A+ (B+C) or (A.B) C = A (BC).

4.3 The De Morgan’s Theorem

This theorem has the most significance in that it is a technique for substituting AND operators for OR
operators and vice-versa OR NOR for NAND function using group complementation. For example the
logic function A+B when subjected to De Morgan theorem forms the equality:

A  B  A.B or AB  A  B

Group complementation means a long bar extending over two or more variables, for example:

AB The bar (-) above AB is a group complementation because it extends over two Boolean variables.

24
Examples of simplifying Boolean expression using De Morgan’s theorem

Method 1: Breaking the long bar

A  BC

Breaking long bar changes ORing (+) to ANDing

A BC

Applying Complement law A  A to BC

A BC

So A  BC reduces/simplifies to A BC

Method 2: Breaking the short bar first

A  BC

Breaking the shortest bar changes ORing to ANDing

A  ( B  C ) Applying the associative property to remove parenthesis

A  B  C Breaking the long bar into two places between 1st and 2nd terms

A  B C and between 2nd and 3rd terms

A BC

25
Summary of Relationships in Boolean algebra

T1 (a) A+B = B+A

(b) A.B = B.A

T2 (a) (A+B) +C = A+ (B+C)

(b) (A.B). C = A. (B.C)

T3 (a) A. (B+C) = A.B+A.C

(b) (A+B). (A+C) = A+B.C

T4 (a) A+A=A

(b) A.A = A

AA
T5
AA

T6 (a) A+A.B = A

(b) A. (A+B) =A

T7 (a) 0+A = A

(b) 1+A =1

(c) 1.A = A

(d) 0.A = 0

T8 (a) A  A  1

(b) A. A  0

T9 (a) A  A.B  A  B

(b) A.( A  B)  A.B

26
T10 De Morgan’s theorem

a) A  B  A.B
b) AB  A  B

Worked examples

Use postulates to show that:

A  AB  A  B

 A 1  AB  A  B
 A(1  B)  A B  A  B
 A  AB  A B  A  B
 A  B( A  A )  A  B
 A B A B

Show that:

A  AC  A  C
 A  1  AC  A  C
 A (1  C )  AC  A  C
 A  A C  AC  A  C
 A  C ( A  A)  A  C
 A C  A C

Show that:

( A  B)( A  C )  A  BC
 A  A  A  C  B  A  B  C  A  BC
 A  AC  AB  BC  A  BC
 A(1  C )  AB  BC  A  BC
 A  AB  BC  A  BC
 A(1  B)  BC  A  BC
 A  BC  A  BC

27
Exercise

1 Show that: F  ( A  B  C )( A  B  C )  A  C

2 Simplify the Boolean function: F  A B C D  A B CD  AB C D  AB CD  ABC D  ABCD

3 Show that: F  ( A  B  AB)( A  C  AC )  A  BC

Material for further exploration:

Nave, R. De Morgan’s Theorem Retrieved from:http://www.hyperphysics-

phyastr.gsu.edu/base/Electronic/DeMorgan.html#3

Morris, Mano, (1997) Computer Systems Architecture

William Stallings (2006) Computer organization and architecture p 701-702

Exercise for self-assessment

1 Define the following laws of Boolean algebra giving examples in each case:
 Commutative
 Distributive
 Identity

1 De Morgan‟s theorem is significant in design of digital logic circuits. Use De Morgan‟s theorem to
simplify the Boolean expressions below:

( A B  C )( A  B)( B  AC )

3 Which postulates in Boolean algebra have the same effects as in conventional algebra?

References

http://mathworld.wolfram.com/BooleanAlgebra.html

http://www.probabilityformula.org/demorgans-law.html#

William Stallings (2006)

28
LECTURE 5 TRUTH TABLES
5.1 Introduction

A truth table, in Boolean algebra is a table used to calculate the functional value of a Boolean function
or expression on each of the Boolean variables. The truth tables are used to show or tell whether a
Boolean function returns a 1 (true) or a 0 (false) for all the valid input values. The truth tables are
popular with logic gates, combinational and sequential circuits. This is because it does not matter how
complex a Boolean function is, the final output value computes to a 1(true) or 0 (false) value. A truth
table is made up of columns for each input variable, for example (for example, A, and B) and one final
(output) column for all the possible outputs (results) of the logical operation the truth table is meant to
represent for example for the function: F = A+B, truth table will appear as shown in table 1 below:

Input Variables Output

A B F
0 0 0
0 1 1
1 0 1
1 1 1

Table 1: Truth table for Boolean function F= A + B

A and B are the two Boolean variables and F is the output. The values under columns A and B are
known as possible input combinations and those under column F are called possible results for each
input combination for A and B. If only one Boolean variable is used, the truth table has only two
columns, one column for variable and another for the results (output). The possible input combinations
for one Boolean variable are two and the outputs are also two. See table below the Boolean function F =
A:

Table 2: Truth table for the Boolean function F = A

Input Output
A F
0 0
1 1

If a Boolean function has three (3) variables, then there are three input columns and one output (results)
column. There are eight possible input combinations and eight possible results that is one for each input
combination. To calculate the number of possible input combinations, raise the number of input
variables as a power of two for example for one input variable, 21= 2, for two input variables 22 = 4 and
for three input variables, 23= 8, and for four inputs, 24 = 16. In this module only Boolean functions with
four variables will be used. The table below shows a three variable truth table:

29
 Table 3: A three variable Boolean function truth table

Input variables Output

A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

The results (outputs) in column F can be given arbitrary and do not worry about how they have been
computed) calculated. There is a chapter devoted to the calculations of the outputs of Boolean functions.

5.2 Forms of Boolean Expressions

Consider the numeric representation of a Boolean function given in a three variable table below:

Table 4: Three variable truth table

Dec A B C F
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0

In the above truth table, Dec values are the decimal values, that is base ten representations, A, B, C are
the Boolean variables and F is the output (result).The input combinations of A.B and C are listed in
ascending order from 000 to 111. This does not necessarily mean that the function operates in this order
but rather the ascending order is used so that no input combination can be mistakenly left out.

Looking at the truth table, it can be seen that the function F has a value of 1 for the following input
combinations: 000, 011,101, and 110. This can be written as: F (A, B, C) =
A B C  A BC  AB C  ABC . The (A, B, C) in parenthesis are used to show that the function is three
variable.

This function can also be written as: F (A, B, C) = 000+011+101+110. This can still further be reduced
to the form: F (A, B, C) = ∑ (000, 011, 101, 110). This form can further be written in a more convenient
decimal form: F (A, B, C) =∑ (0, 3, 5, 6).

30
5.3 The Sum of Products (SOP) form

So from the truth table the ORing (+) of input combinations where F =1, gives the sum of products form
(SOP).

The forms F = A B C  A BC  AB C  ABC and F (A, B, C) = ∑ (0, 3, 5, 6).are called the sum of
products form. The two expressions above are most popular for expressing Boolean functions.

As already noted above, the sum of products form is derived from the truth table by noting where F = 1
and then writing the corresponding input combinations. If F = 1 in more than one instance the input
combinations are combined or joined by the OR (+) operator.

Activity

1 What is the meaning of the sum of products (SOP) in simple terms?

2 Show that sum of products (SOP) and product of sums (POS) are really the same

3 What is the really meaning of POS in operation terms?

5.4 The Product of Sums (POS) form

Consider the previous table 4 below.

Dec A B C F
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 0
From the truth table above, the product of sums (POS) is formed by looking at output instances in
column F, where F is equal to 0 and then applying group complementation and De Morgan‟s theorem.
For example F = 0 in the following input combinations, 001, 010,100,111. This can be written as:
F ( A, B, C )  A B C  A BC  AB C  ABC . Since we rarely work with negative functions, the above
function must be converted to a positive function. This is done by using the complement law of Boolean
algebra, that is A  A . The above function can be written as:

F ( A, B, C )  F ( A, B, C )  A B C  A BC  AB C  ABC . Applying De Morgan‟s theorem, this can be

written as: F ( A, B, C )  ( A B C )  ( A BC )  ( AB C )  ( ABC ) . Applying De Morgan theorem, this can
further be written as: F ( A, B, C )  ( A  B  C )  ( A  B  C )  ( A  B  C )  ( A  B  C ) This last
expression is the product of sums. The product of sums (POS) simply means ANDing first and then
ORing as opposed to the sum of products (SOP) which means ORing first and then ANDing.

31
Worked example 1
Given the Boolean function below expressed in the sum of products (SOP), convert it to the product of
sum (POS) form: F ( A, B, C )   (1,2,4,7) What the Boolean expression/function means is that at the
input combinations in parenthesis, the output F =1. So to convert this function into POS, use input
combinations where F = 0. From the above expression F = 0 in the following input combinations, that is
those input combinations absent in the function, 000, 011, 101, 110. This can now be written as:
F ( A, B, C)  A B C  A BC  AB C  ABC . Change this negative function to a positive one using the
complement law, for example: F ( A, B, C )  F ( A, B, C )  A B C  AB C  AB C  ABC The principle
that what you do to the left, do it also to the right. That is why there is that long negation/complement
bar over the expression. This can then be written as: F ( A, B, C )  ( A B C )  ( AB C )  ( AB C )  ( ABC )

This can then be written as F  ( A  B  C )  ( A  B  C )  ( A  B  C )  ( A  B  C ) . This is POS

form.
The sum of products (SOP) and the product of sums (POS) represent the same Boolean function. This
can be shown by using the input combination values in the truth table and the values of the output
column F which remain the same. Sometimes it is also necessary to draw the logic circuit of the POS
and simulate or trace the input values and the output values.

Given the Boolean function F ( A, B, C )   (1,2,3.5,6) :

(i) Produce the product of sum (POS) form

(ii) Draw the corresponding diagram
(iii) Show that the sum of product (SOP) and the product of sums (POS) represent the same
function.

Worked example 2

F ( A, B, C )   (0,4,7)
F ( A, B, C )  A B C  AB C  ABC
(i) F ( A, B, C )  F ( A, B, C )  A B C  AB C  ABC :
F ( A, B, C )  ( A B C )  ( AB C )  ( ABC )
F ( A, B, C )  ( A  B  C )  ( A  B  C )  ( A  B  C )

(ii)

32
Figure 4: Product of sums (POS) logic circuit for F  ( A  B  C )( A  B  C )( A  B  C )

(iii) To show that the SOP and POS are the same the values of F should be the same in the truth table
which ever form is used. In the SOP truth table F=1 in the following input combinations: 001, 010, 011,
101, and 110. Any one of these input combinations can be traced on the logic circuit or substituted on
the POS form of Boolean function.

F  ( A  B  C )( A  B  C )( A  B  C ) . Taking the first input combination (000)

F = (0+0+0) ∙ (1+0+0) ∙ (1+1+0)

F = (0) ∙ (1) ∙ (1) = 0

F  ( A  B  C )( A  B  C )( A  B  C ) Taking input combination (101)

F = (1+0+1) ∙ (0+1+1) ∙ (0+1+0)

F = (1) ∙ (1) ∙ (1) = 1
It is clear the value of F remains the same regardless of which Boolean form is used.

Exercise

1 Consider the Boolean function: F  A B C  A BC  AB C  AB C  ABC

Produce the product of sums (POS)
Produce the corresponding logic circuit
Simplify the above expression (POS)

2 Given that F ( A, B, C )   (0,1,4,7) Produce the product of sums (POS) and draw the logic circuit

3 Given a 3- variable function in form of a truth table, how would you find the:
SOP?
POS?
Resources for exploration:

William Stallings, Computer Organization and Architecture, p 706-707

Nave, R. De Morgan’s Theorem Retrieved from:http://www.hyperphysics-

phyastr.gsu.edu/base/Electronic/DeMorgan.html#3

Statements, truth values and truth tables

http://www.math.csusb.edu/notes/logic/lognot/node1.html

The SOP and POS forms of Boolean Functions

http://mcs.uwsuper.edu/sb/461/PDF/sop.html

33
Peter Williams, Sept 2, 1996.How to convert an SOP expression to POS form and vice versa in Boolean
Algebra?

https://electronics.stackexchange.com/questions/9817/how-to-convert-an-expression-from-sop-to-pos-and-
back-in-boolean-algebra

34
LECTURE 6 DIGITAL LOGIC GATES
6.1 Introduction
A logic gate is a physical device that implements a simple Boolean function. The Logic gates form the
hardware basis on which digital computers are built. Logic gates are also called logic circuits. The
elementary (basic) logic gates are: NOT, BUFFER, OR, AND, NOR, NAND, EXCLUSIVE OR (XOR)
and Exclusive NOR (XNOR).
6.2 NOT Logic gate

The NOT logic gate is also called an Inventor or Complement and it produces a 1 at its output for a
zero (0) input and a 0 output for a 1 input, that is, the output is always the opposite or complement of the
input.

Standard symbol

F= A

Truth Table

A F
0 1
1 0

6.3 Buffer

A buffer simply copies its input to its output. A buffer has no logical significance, but it serves an
important practical role as an amplifier, that is, it allows a number of logical gates to be driven by a
single signal.

Symbol

35
 Truth table

A F
0 0
1 1

6.4 The OR Logic Gate

A basic OR logic gate works with two inputs and 1 output. The output of the OR gate is true (logical 1)
when either one or both inputs are logical ones (1s) and is false otherwise (0).

Standard symbol

Truth Table

A B F
0 0 0
0 1 1
1 0 1
1 1 1

Note that the output value is 1 when at least one input value is 1
6.5 The AND logic gate
A basic AND logic gate operates with two inputs and one output. The output of an AND gate is a
logical 1, only and only when both of its inputs are logical 1s and is false otherwise

Standard symbol

Truth Table

A B F
0 0 0
0 1 0
1 0 0
1 1 1

36
Note that in the AND logic gate, the output is 1 only when both inputs are 1

Activity
1 Consider the proposition: If it is raining or the weather forecast is bad then I take an umbrella. What
logic gate can you use to implement the truth table for the above proposition?
2 Produce a truth table using the input variables: RAINING, NO CAR and the output variable
UMBRELLA. The input combinations are: FALSE and TRUE, the output UMBRELLA can only be
TRUE or FALSE.
6.6 The NOR logic gate

The NOR gate is formed by connecting an INVERTER (NOT gate) at the output of an OR gate. This
gate produces complementary outputs to the OR gate for example:

Standard symbol

F  A B

Truth Table

A B F
0 0 1
0 1 0
1 0 0
1 1 0

6.7 The NAND logic gate

The NAND logic gate is formed by connecting a NOT gate at the output of an AND gate and this gate
produces complementary outputs to the AND gate for example

37
Standard symbol

F  AB

Truth Table

A B F
0 0 1
0 1 1
1 0 1
1 1 0

6.8 Exclusive OR (XOR) logic gate

Exclusive OR (XOR) logic gate produces a logical 1 at its output when either one of its input is a 1,
excluding cases when both inputs are logical 1s and logical 0s (zeros).

Symbol

F  A B

A B F
0 0 0
0 1 1
1 0 1
1 1 0

Note that when both inputs are 1s the output is a 0.

38
Activity

1 Which of the following cases would be cases of OR or XOR, explain why?

a) A man marrying a woman or a woman marrying a man

b) A woman marrying another woman or a man marrying another man

2 Consider the proposition: If it is raining and I have no car then I will take an umbrella. Which logic
gate will you choose to implement the truth table of the above proposition?

3 Produce the truth table. Note the input variables are RAINING and NOR CAR. The output variable is
UMBRELLA.

6.9 Exclusive NOR (XNOR) logic gate

This logic gate is formed by connecting an INVERTER to the Exclusive OR gate and it produces
outputs that are complementary to those of the Exclusive OR gate for example

Standard symbol

F = A B

Truth Table

A B F
0 0 1
0 1 0
1 0 0
1 1 1

39
6.10 Deriving Boolean functions from truth tables

A Boolean function can be represented in the form of a truth table and sometimes it becomes necessary
to necessary to convert a truth table to a product of sum or sum of products form.

Consider the truth table below:

A B F
0 0 0
0 1 1
1 0 1
1 1 1

To convert this truth table to a Boolean function, the following steps need to be followed:

 Note where F =1 in the truth table and write the input combination
 If F= 1 in more than one instance, the input combinations of the respective outputs are joined by
an OR(+) sign
 Simplify the formed Boolean function if it is complex

In the above truth table F = 1 in three instances, so the Boolean expression can be written as:

F  A B  AB  AB
 A B  A( B  B)
 A B  A  A  AB
 A B

Consider the truth table below:

A B F
0 0 1
0 1 1
1 0 1
1 1 0

F  A B  A B  AB
 A ( B  B)  AB
 A  AB
AB

Consider the truth table below:

A B F

40
 0 0 0
0 1 1
1 0 1
1 1 0

F  A B  AB
 A B

A  B Can be written as (A+B) ( A  B ) This can be simplified by cross multiplication to:

A A  A B  A  B  B B
 0  AB  A B  0
 AB  A B  A  B

Note that A  B is a basic logic gate that is, Exclusive OR logic gate. So the expression F  A  B
is a simplification of AB  A B

6.12 Drawing Logic Circuits from given Boolean Functions

Sometimes it is necessary to produce a corresponding logic circuit from a given Boolean expression.
Usually when asked to draw a logic circuit from a given Boolean expression it is not necessary to
simplify the expression and then draw the logic circuit.

Example 1

Given the Boolean expression below, draw the corresponding logic circuit: F  ( A  B ) B( B  C )

Start by drawing the logic gates in parenthesis. Note that the long bar is also a bracket. So the first logic
gate to be drawn is the OR, then the NOR, the Buffer which can be represented by a straight line (B) and
then the NAND gate, for example:

Figure 5: Logic circuit for the Boolean expression F  ( A  B ) B( B  C )

Example 2

41
Given the Boolean expression F = AB + C (A  B), draw the corresponding logic circuit. Start by the
logic gate in parenthesis.

Figure 6: Logic circuit for the Boolean expression F = AB + C (A  B)

Exercise for self-assessment

1 Consider the logic circuit in figure 6. Produce its truth table

2 Consider a malfunctioning AND logic gate. Explain how would quickly verify this without going
through the entire AND gate truth table.

3 Given a NAND logic gate show how you can produce a NOT gate. (Use logic circuit diagrams

Material for exploration

William Stallings (2006), Computer organization and architecture, p 703-704

Morris Mano (1997), Computer systems architecture
An Introduction to Digital Logic - Signals and Gates. Can be accessed from:
http://www.facstaff.bucknell.edu/mastascu/eLessonsHtml/Logic/Logic1.html

42
LECTURE 7 MINIMIZING BOOLEAN FUNCTIONS

7.1 Introduction
Minimizing a Boolean function simply means simplifying it. There are several reasons for minimizing
Booleans functions. Booleans functions are used to implement logic gates or digital logic circuits, so a
simple Boolean function will use a smaller number of logic gates and this will in turn offer the following
benefits to the designers:

 The Boolean function becomes easy to understand and implement

 When minimized, the function is less prone to errors and in its interpretation
 Minimized Boolean functions reduce the cost of implementation
 They reduce propagation delays in the circuits and improve circuit performance
 Power consumption is also reduced.
Consider the Boolean function:

F  A  AB . The digital logic circuit of this Boolean function is shown below:

This Boolean function minimizes to F = A which is a Buffer

It is clear from the above that a minimized Boolean function has many advantages compared to a
complex Boolean function. Minimization can be achieved by a number of methods, four well known
methods are:

 Algebraic method of minimizing Boolean Functions/Expressions

 Karnaugh Maps
 Tabular Method of Minimization
 Tree reduction
This module is limited to the algebraic, Karnaugh maps and the tabular methods.

43
7.2 Algebraic Method of Minimizing Boolean Expressions
The algebraic method makes use of the postulates/properties/laws of Boolean algebra as well as
theorems of Boolean algebra. For example, given the Boolean function below, minimize it using
postulates and theorems of Boolean algebra:

Example 1

F  A B  A B  AB
 A ( B  B)  AB
 A  AB
AB
Example 2

F  A B C  A BC  AB C  ABC
 A ( B C  BC )  A( B C  BC )
 A ( B  C )  A( B  C )
 A BC

Example 3
F  ( A  B  AB)( A  C  AC ) Minimize using the algebraic method

F  A B C D  A B CD  AB C D  AB C D  AB CD  ABC D  ABCD
 A B D(C  C )  AB D(C  C )  ABD (C  C )
 A B D  AB D  ABD
 B D( A  A)  ABD
 B D  ABD  D( B  AB )  D( B  A)  D( A  B )

7.3 The Karnaugh Map Method of Minimizing Boolean Functions

The Karnaugh map provides a pictorial method of grouping together expressions with common factors.
It is a variation of the truth table, for example the two-variable truth table below can be represented in a
2- variable K map as shown below:

Table 1: A 2-variable truth table

A B F
0 0 a
0 1 b
1 0 c
1 1 d

44
 Table 2: Two variable K-map

The squares also called cells have specific numbers. See table below:

The zero (0) and one (1) coordinates on the variables means that A and have a value of 0 and 1 and so is
variable B. When labeling the cells (squares), start with a column and then row, for example the top
most column is A B or (00). This also means that this cell is at the intersection of column A and B .
This can also be written as cell number (00). The same applies to the rest of the cells. It is important to
know that the cells represent the input combinations where the value of F (output of the function) will be
written for minimizing purposes.

7.4 Two variable Karnaugh map

The two- variables K - map has four possible states and each variable is represented by half the total
number of cells/squares (see example below). The cells are represented by numbers, which can be used
to quicken the process of minimization, for example 00 is (0), 01 is 1, 10 is 2 and 11 is 3.
B A 0 1

0 00 10

1 01 11

45
7.5 Examples of minimizing 2-Boolean variables functions

Example 1

Consider the Boolean function: F (A, B) = ∑ (2, 3) = AB  AB

This function means that at the input combination 10(2) and (11) 3, the value of F = 1. A truth table of
same function is shown below:

A B F
0 0 0
0 1 0
1 0 1
1 1 1
There are simple steps to be followed when using K maps to minimize Boolean functions:
1. Draw the 2-variables K map
2. Fill the out values of F in the corresponding squares (where F = 1 only)
3. Put the binary 1s in groups of 2s, 4s, 8s in general 2n where n = 1, 2, 3 e.t.c
For a 2-variable K map the maximum number of 1s in a group is 2, for a 3-variable K map the maximum
is 4 and for a 4-varible K map the maximum number of 1s in a group is 8.
4. Discard the variable that has changed its value (toggled) and the one that has not changed is the
answer or part of the answer. If there are more than one group, the variables that have not toggled are
combined by the OR (+) sign. These steps apply to all K maps.
As can be seen below, there is one vertical group. Looking at variables A and B, in the only vertical
group in the K map, B has changed (toggled) its value from 0 to 1. A has not changed its value. So B is
discarded and so the answer is F =1.

This can be proved using algebraic method but this is not necessary. For example:

F = AB  AB = A ( B  B) since B  B) = 1: F = A

46
Example 2

Minimize the Boolean function below using the K map method.

F (A, B, C) = ∑ (0, 1, 2) = F  A B  A B  AB . It is not really necessary to be converting to the

expanded sum of products.

Following the previous steps, there are two groups that are group I (horizontal) and group II (vertical).
Looking at the horizontal group (I), variable A has toggled its value from 0 to 1, so it is discarded.
Variable B is constant, so the part answer in group I is B , this is because B = 0.

Looking at group II (vertical group), B has changed its value from 0 to 1, so it is discarded, A is
constantly 0 . The final answer considering the two groups is: F  A  B

FAB

7.6 Karnaugh Maps Rules used in the Simplification of Boolean Functions

Below is a list of rules used in the simplification of Boolean functions using the K map method.
1 .A group may not include any cell that contains a zero.
2. Groups can be horizontal or vertical but not diagonal
3. Groups should contain 1, 2, 4, 8 in general 2n cells
4. A group should be as large as possible
5. Groups may wrap around the table
6. Groups may overlap
7. Groups may wrap around the table.
8. Each cell containing a one (1) must be in one group or at least in a group of its own.
These rules apply to all Karnaugh maps.

47
7.7 The three variable Karnaugh map

A three variable K map has 23 cells or squares and each variable occupies exactly half the total number
of cells. The cells are represented by numbers, for example (000) is 0, (001) is, (010) is 2, (011) is 3,
(100) is 4, (101) is 5, (110) is 6 and (111) is 7. This numbering quicken the process of inserting the ones
(1s) in cells during minimization of Boolean functions.

Example
Minimize the Boolean function below using the K map method:
F (A, B, C) = ∑ (0, 2, 3, 5, 6, 7). After filling in the values of F in their respective cell positions, three
groups are formed as shown below.

(I)

(II) (III)

Looking at group one (I), consider variables A and B. In this group B has toggled from 1 to 0, A is
constant, so variable B falls away or is discarded. Looking at C in the same group, it is seen that C is
constantly 0, so part answer is A C . Group two (II) is the vertical group with four 1s. In this group
looking at variables A and B, it is clear that A has toggled from 0 to 1, so is discarded, C has also
toggled from 0 to 1 and so is discarded. On the other had B is constantly 1, so part answer is B. Looking
at the third group (III), B has toggled from 1 to 0 and A is constantly 1. C is also constantly 1, so the part
answer is AC. The full answer is:

F  A C  B  AC

48
Activity
1 Suppose you are given a 3-variable Boolean function to minimize. What technique would you use and
why?
2 Consider the Boolean function:

F (A, B, C)  A B C  AB C  ABC , which technique would you use to simplify and why
3 Compare the algebraic method of solving on solving the above (2) Boolean function with the K map
method and drive own conclusions.

Example 2

Minimize the Boolean function below using the K map method:

F (A, B, C) = ∑(2, 3, 4, 6, 7)

(II) (I)

Looking at group one (I) B has toggled, discard, A is constantly 1, C is constantly o, so part answer is
AC . For group two (II), A has toggled from 0 to 1, discard, C has also toggled from 0 to 1 discard, B is
constantly 1, so part answer is B. The full answer is therefore: F  AC  B

Resources for further exploration:

Morris Mano, Computer systems architecture

Logic Simplification with Karnaugh Maps Retrieved from: www.allaboutcircuits.co/textbook/digital/chpt-8/logic-

simplification-karnaugh-maps/

Morris Mano & Michael Ciletti, (2013) Digital Design, 5th Edit, Prentice Hall

49
Exercise
Consider the Boolean function below:

F  A B C D  A BC  A BC  AB C  ABC  ABC

1 Which minimizing technique would be the best to use and why?

2 Use both the K map and the Tabular methods to help you answer (i) above
3 Minimize using tabular method: F(A, B, C) =∑(0,1,2,3,4,5,6,7,8,9,10,11)

Material for further reading

Minimization of Boolean Functions using Karnaugh Maps:

http://www.cs.colostate.edu/~cs530dl/s12/minimization

http://www.ee.surrey.ac.uk/Projects/Labview/minimisation/karnaugh.html

C E Stroud, Karnaugh Maps http://www.eng.auburn.edu/~strouce/class/elec2200/elec2200-6.pdf

50
LECTURE 8 THE TABULAR METHOD
8.1 Introduction
The tabular method is also known as the Quine - McCuskey method and is very useful particularly when
dealing with Boolean functions that have large number of variables, for example five, six or more.
This was the first programmable method. The method reduces a function in standard sum of products
(SOP) form to a set of prime implicates from which as many variables can be eliminated. The prime
implicates are examined to see if some are redundant. The tabular method makes repeated use of the
Boolean law A+ A  1
This method uses both the binary and decimal notations in the function. In the binary notation, a variable
in true form is denoted by a binary 1, in complement form by a 0 and the absence of a variable by a dash
(-).

8.2 Rules of Tabular Method

Consider a three variable Boolean function F (A, B, C):

A BC is represented by 011, where A= 0, B = 1 and C = 1

AB C is represented by 100, where A=1, B = 0, and C = 0

AC is represented by 1-0, where A = 1, B is absent and C = 0

BC is represented by -11, where A is absent, B = 1 and C = 1

Consider the Boolean function:

F (A, B, C, D) =∑ (1110, 1111) = ABCD  ABCD  ABC

The two minterms can be listed and combines as shown:
ABCD
11 1 0 Can combine because they differ in one digit position.
11 1 1
11 1 -
Consider the following Boolean function:

F (A, B, C, D) =∑ (1101, 1110) = ABC D  ABCD

These minterms can also be listed as:

ABCD
1 1 0 1 cannot combine because they differ in more than one digit
1 1 1 0 position

51
Rule 1: For two terms two combine and eliminate one variable, they must differ in only one digit
position.
The tabular method makes use of indices. The index in a minterm means the number of binary ones (1s).
Consider the Boolean function: F (A, B, C, D) which can be tabulated as shown below:
A B C D
0 0 0 0 Index 0
0 0 0 1 Index 1
0 0 1 0 Index 1
1 0 1 0 Index 2
1 1 1 0 Index 3
1 1 1 1 Index 4

Examples of minimizing a three variable Boolean function using the tabular method
Example 1

Consider the Boolean function: F (A, B, C) = A B C  A B C  AB C  AB C or F (A, B, C) = ∑ (0, 1, 4,

5)

Step 1
The above function must be changed into binary notation, for example:
F (A, B, C) =∑ (000, 001,100,101)

Step 2
Create List 1 or First List
List 1 is a table showing the function broken down into respective groups using indices. Groups are
separated by horizontal lines.

LIST 1
Index Dec A B C
Group 1 0 0 0 0 0
Group 2 1 1 0 0 1

52
 1 4 1 0 0
Group 3 2 5 1 0 1

LIST 2
List two is formed by combining group 1 with group 2 and group 2 with group 3. Groups are not
allowed to overlap. After combining any two groups, horizontal line is used to separate the new group
from the next following group. New groups will be formed as a result. The new groups can still be
combined to remove some redundancies, for example, the new groups are 1 and 2.
Dec A B C
1) 0, 1 0 0 - 
0, 4 - 0 0
2) 1, 5 - 0 1
4, 5 1 0 - 
LIST 3
List 3 is formed in a similar way to list two, but in this list those minterms that have combined must be
identified by some mark and those that have not combined must be identified by a different symbol or
mark.
Dec A B C
0, 1, 4, 5 - 0 -
0, 4, 1, 5 - 0 -

From the results of list three, (3) it is clear that the result cannot be reduced any further, so, F  B is the
minimized function.
Example 2
Minimize the Boolean function below using the tabular method: F (A, B, C) =∑ (0, 1, 2, 3, 4, 6)
Convert to binary notation:
F (A, B, C) =∑ (000, 001, 010, 011, 100, 110)
The conversion allows us to produce a list or table where minterms with the same index (no of binary
ones (1s) are put in respective groups. For example 000 has zero ones so it will be in a group of its own.
001 and 010 have one binary each so they will be in the same group. The same applies to 011 and 101,
they have each two binary one so they will be in the same group also.
See list 1 below

53
LIST 1
Index Dec A B C
Group 1 0 0 0 0 0
Group 2 1 1 0 0 1
2 0 1 0
4 1 0 0
Group 3 2 3 0 1 1
6 1 1 0

LIST 2
1) Dec A B C
0, 1 0 0 -
0, 2 0 - 0
0, 4 - 0 0
1, 3 0 - 1
2, 3 0 1 -
2) 2, 6 - 1 0
4, 6 1 - 0
LIST 3
Dec A B C
0, 1, 2, 3 0 - -
0, 2, 1, 3 0 - -
0, 2, 4, 6 - - 0
0 ,4, 2, 6 - - 0

From the above it is clear that the minimized function F = A  C

54
Example 3
Minimize the Boolean function below using the tabular method:
F(A, B, C, D) =∑(1,3,5,7,8,9,10,11,12,13,14,15)
Convert the decimal numbers to binary as follows:
F (A, B, C, D) =∑ (0001, 0011, 0101, 0111, 1000, 1001, 1001, 1010, 1011, 1100, 1101, 1110,1111)
Form the List 1 or first List table as shown below:
LIST 1
Index Dec A B C D
Group 1 1 1 0 0 0 1
8 1 0 0 0
3 0 0 1 1
5 0 1 0 1
Group 2 2 9 1 0 0 1
10 1 0 1 0
12 1 1 0 0
7 0 1 1 1
11 1 0 1 1
Group 3 3 13 1 1 0 1
14 1 1 1 0
Group 4 4 15 1 1 1 1

Form List 2 by combining the groups, group 1 with group 2, group 2 with group 3 and group 3 with
group 4. Groups are not allowed to overlap, for example group 0ne cannot be combined with group 3.

55
LIST 2
Dec A B C D
1, 3 0 0 - 1
1 1, 5 0 - 0 1
1, 9 - 0 0 1
8, 9 1 0 0 -
8, 10 1 0 - 0
8, 12 1 - 0 0
3, 7 0 - 1 1
` 3, 11 - 0 1 1
5, 7 0 1 - 1
2 5, 13 - 1 0 1
9, 11 1 0 - 1
9, 13 1 - 0 1
10, 11 1 0 1 -
10, 14 1 - 1 0

12, 13 1 1 0 -

12, 14 1 1 - 0
7, 15 - 1 1 1
3 11, 15 1 - 1 1
13, 15 1 1 - 1
14, 15 1 1 1 -
From list 2 above, it is clear that the new groups can still combine and remove some redundant
implicates. List three is created as shown in the next page.

56
LIST 3
Dec A B C D
1, 3, 5, 7 0 - - 1
1,5, 3, 7 0 - - 1
1, 3, 9, 11 - 0 - 1
1, 9, 3, 11 - 0 - 1
1, 5, 9, 13 - - 0 1
1, 9, 5, 13 - - 0 1
8, 9, 12, 13 1 - 0 -
8, 12, 9, 13 1 - 0 -
8, 10, 12, 14 1 - - 0
8, 10, 9, 11 1 0 - -
8, 9, 10, 11 1 0 - -

8, 12, 10, 14 1 - - 0

3, 7, 11, 15 - - 1 1

3,11,7, 15 - - 1 1

5, 7, 13, 15 - 1 - 1

5, 13, 7, 15 - 1 - 1

12,13,14,15 1 1 - -

12, 14, 13, 15 1 1 - -

10, 11, 13, 15 1 - - 1

10, 11, 14, 15 1 - 1 -

9, 11, 13, 15 1 - - 1

10, 14, 11, 15 1 - 1 -

There are still redundant implicates and this calls for the creation of list four

57
LIST 4

Dec A B C D

1, 3, 5, 7,10,11,13,15, - - - 1

1, 5, 3, 7 ,9 ,11,13 ,15 - - - 1

1, 3, 9, 11,5,7,13,15 - - - 1

1,9,3, 11,5,13,7,15 - - - 1

1,5,9, 13,3,7,11,15 - - - 1

1,9, 5, 13,3, 11, 7, 15 - - - 1

8,9, 12, 13,10, 11, 14, 15 1 - - -

8,12, 9, 13,10, 14, 11, 15 1 - - -

8, 10, 9, 11, 12, 13, 14, 15 1 - - -

8, 9 , 10, 11, 12, 14, 13, 15 1 - - -

8, 12,10, 14,10, 11, 13, 15 1 - - -

It is clear from list 4 that there are no more redundant implicates, so the minimized function is:

F=A+D

8.3Using a chart to remove redundant prime implicates.

Charts can be used to minimize Boolean functions in the tabular methods. This case arises when the
result of minimized function produces more than four minterms in the final answer. Consider the
example of minimizing the Boolean function below using the tabular method:

Consider the Boolean function:

F(A, B, C, D) =∑(0,1,2,3,5,7,8,10,12,13,15). Convert the decimal form to binary form as shown below:
F(A, B, C, D) =∑(0000, 0001,0010,0011,0101,0111,1000,1010,1100,1101,1111)

58
LIST 1
Index Dec A B C D
Group 1 0 0 0 0 0 0
1 0 0 0 1
Group 2 1 2 0 0 1 0
8 1 0 0 0

3 0 0 1 1
5 0 1 0 1
Group 3 2 10 1 0 1 0
12 1 1 0 0
Group 4 3 7 0 1 1 1
13 1 1 0 1
Group 5 4 15 1 1 1 1

LIST 2 Dec A B C D
0, 1 0 0 0 -
0, 2 0 0 - 0
0, 8 - 0 0 0
1, 3 0 0 - 1
1,5 0 - 0 1
2, 3 0 0 1 -
2, 10 - 0 1 0
8, 10 1 0 - 0
8, 12 1 - 0 0
3, 7 0 - 1 1

59
 5, 7 0 1 - 1
5, 13 - 1 0 1
12, 13 1 1 0 -
7, 15 - 1 1 1
13, 15 1 1 - 1
The minterms marked with the asteristic () have not combined with any minterms and should be part
of the final answer

LIST 3
Dec A B C D
0, 1, 2, 3 0 0 - -
0, 2 ,1 ,3 0 0 - -
0, 2, 8, 10 - 0 - 0
0, 8, 2, 10 - 0 - 0
1, 3, 5, 7 0 - - 1
1, 5, 3, 7 0 - - 1
5, 7, 13, 15 - 1 - 1
5, 13, 7, 15 - 1 - 1

The prime implicates from list 3 and 4 are:

F  A B  B C  A D  BD  AC D  ABC

The prime implicates AC D , ABC are from list 2 and are marked with an asterisk to show that they have
not combined with any other minterm. This means that they should be included in the final list of prime
implicates.

Rule 2
Any minterm(s) that has not combined with any other, starting from list 2 onwards must be part of the
final function.

A look at the Boolean expression: F  A B  B C  A D  BD  AC D  ABC shows that there are

redundant implicates. These can be reduced by using a chart.
The chart is a grid made up of implicates listed at the left and all the minterms of the function along the
top. This means the implicants represent the rows and the minterms the columns. Each minterm
represented by a given implicate is marked in the appropriate position (see diagram below):
60
Figure 7: Tabular method minimizing chart
The x‟s are essential implicates. The implicants marked  are most essential which must always feature
in the final answer.
From the above chart, identify essential implicates, for example BD is an essential prime implicate as it
is the only prime implicate that covers the minterm decimal 15 and also includes 5, 7 and 13. B D is
also an essential prime implicant. It is the only prime implicate that covers the minterm denoted by
decimal 10 and it also includes the terms 0, 2 and 8. The other minterms of the function are 1, 3 and 12.
Minterm 1 is present in A B and A D . The same is for minterm 3. Therefore either of these prime
implicants can be used for these minterms. Minterm 12 is present in AC D and ABC , so either one of
them can be used.
The essential implicants marked with the symbol  must always be part of the final answer
So we have more than one final answer:

F  B D  BD  A B  AC D
F  B D  BD  A D  ABC

61
Exercise
Minimize the Boolean functions below using the tabular method:
1 F (A, B, C) = ∑ (1, 3, 4, 5, 6, 7)
2 F(A,B,C,D) =∑(1,3,4,5,6,7,9,11,12,13, ,15)
3 F(A, B, C, D) = ∑(1,3,4,5,7,9,11,12,13,15)
Resources for further exploration

http://www.ee.surrey.ac.uk/Projects/CAL/digital-logic/minimisation/index.html

https://www.computer.org/csdl/trans/tc/1971/08/01671966.html

https://www.tutorialspoint.com/digital_circuits/digital_circuits_quine_mccluskey_tabular_method.htm

62
LECTURE 9 COMBINATIONAL LOGIC CIRCUIT BUILDING BLOCKS
9.1 Implementation of Logic Gates
Combinational logic circuits are a logic circuit whose outputs entirely depend on the present inputs. This
type of circuit has no memory capabilities. This type of logic circuit gets its name from the way output
are obtained, that is the output value a binary one or zero, depends on the inputs which would have been
applied at the inputs.

Figure 10: Block diagram of basic combinational logic circuit

The array of outputs fo – fn entirely depend on the array of inputs xo- xn. Combinational logic circuits
can be used to build devices for solving problems of simple logic nature. The typical examples of
combinational logic circuits are logic gates, half adders, full adders, multiplexers, decoders, comparators
and others.
9.2 Adders
An Adder is a logic circuit used to perform binary addition operations in a digital computer. The Adders
are of two types:

 Half Adders
 Full Adders
A half Adder is a digital logic circuit that can compute the sum of two binary numbers and a carry to the
left. It is only good for 1-bit binary additions. The logic circuit for a Half Adder is shown below:

Figure: 11 Half Adder logic circuit

The operations of a Half Adder (like any other logic circuit) can best be described by a truth table

63
 CARRY SUM B A
0 0 0 0
0 1 0 1
0 1 1 0
1 0 1 1

From the truth table, it is easy to derive the Boolean functions used to implement the Half Adder logic
circuit. For example SUM = B A  BA  A  B and CARRY = BA

Symbol for a Half Adder

A Sum
HA
B Carry

The Major disadvantage of a Half Adder is its inability to take a carry from the right.

9.3 Full Adder (FA)

The Full Adder was developed to eliminate the major disadvantage of the Half Adder that is its inability
handle carries from the right. The Full Adder is implemented on two Half Adders. The operation of a
Full Adder is best described by a truth table.
Full Adder truth table
Carryout(Cout) Sum Carry in (Cin) B A
0 0 0 0 0
0 1 0 0 1
0 1 0 1 0
1 0 0 1 1
0 1 1 0 0
1 0 1 0 1
1 0 1 1 0
1 1 1 1 1

64
Figure 12: Full Adder Logic Circuit
The Boolean expressions for implementing the Full Adder are derived from the truth table for example:

Cout  C inBA  CINB A  CinBA  CinBA

 C inBA  CinBA  CINB A  Cin BA
 BA(C IN  CIN )  CIN ( B A  BA )
 BA  Cin ( B  A)

Sum  C in B A  C in BA  CINB A  Cin BA

 C in ( B  A)  Cin ( B A  BA)
 C in ( B  A)  Cin ( B  A)
 Cin  B  A  Cin  A  B

65
 To add binary numbers with four or more bits the Full Adder must be cascaded, for example to add two
four –bit binary numbers the full adder must be cascaded four times.

Figure 13 cascaded full adder

Assume A = A3A2A1A0 = 0101 and B = B3B2B2B1 = 1111

S0 = 0 C0= 0; S1 = 0, C1 = 1; S2 = 1, C2 = 1; S3 = 0, C3 = 1.

66
9.4 Comparators
A comparator is a logic circuit used to compare two binary numbers. There are two types of
comparators:

 Comparator for equality

 Full comparator
A comparator for equality has n inputs and one output and a Full comparator has n inputs and three (3)
outputs. But both comparators can compare a maximum of two binary numbers at a time. For example
given two n – bit magnitude binary numbers A and B a comparator for equality will indicate that either
the two binary numbers are equal in which case output F=1 or the two binary numbers are not equal in
which case F= 0. Using the same binary numbers a full comparator will indicate whether:

 A>B or
 A<B or
 A=B
9.5 Comparator for equality
A comparator for equality is the simplest since it is based on the Exclusive NOR (XNOR) logic gate.
Consider the truth table of the XNOR logic gate below:

Truth Table

A B F
0 0 1
0 1 0
1 0 0
1 1 1

Analysis of the above truth table shows that when the input variables A and B have the same input
values (equal) output F = 1 and when A and B have different values out F = 0.

Example
Compare for equality the two binary numbers below:
A = A2A1A0 = 101
B = B2B1B0 = 101
The block diagram would look as shown below:

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Figure 14: Comparator for equality block diagram

The logic circuit diagram would be:

Figure 15: Comparator for equality logic circuit

This comparator logic circuit shows that the two binary numbers are equal (F = 1). If the numbers are
not equal F = 0. For example A = A2A1A0 =100 AND B = B2N1B0 = 110 the result would be as shown
in the logic circuit below:

68
The major disadvantage (problem) with the comparator for equality is that if the numbers are not equal,
it does not show which number is greater or less than the other.

Activity
1 Given an XOR gate truth table, explain why it is used as a comparator for equality?
2 Is it possible to use NOR gates to design a comparator for equality? Design a comparator for equality
using NOR gates instead of XNOR gates
3 What is the reason behind comparisons?

9.6 Full Comparator

A full comparator is more helpful than a comparator for equality. Consider the design of a 1- bit
magnitude full comparator.
Consider two 1-bit binary numbers A and B to be compared for:

 Greater than (A > B)

 Less than (A < B)
 Equality (A = B)
The relationship between the inputs (A and B) and the outputs say X, Y, Z is as follows:
X Y Z
A>B 1 0 0
A<B 0 1 0
A=B 0 0 1
In order to design this full comparator the following steps are needed:

Step 1: Produce the truth table

Produce the truth table
A B X Y Z
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

69
Step 2: Produce the Boolean equations
From the truth table, it is clear that X = 1 in the input combination, AB = 10, so this is written as:

X  AB ; Y = 1, in the input combination, AB = 01, the Boolean equation is: Y  A B , similarly Z is =1

in the input combinations AB =00 and AB =11, the Boolean equation is:

Z  A B  AB . This expression reduces to: Z  A  B

The logic circuit diagram is produced using the above three Boolean expressions.

Figure 17: Full Comparator logic circuit

Only one output is active at a time depending on the input combinations of A and B. The active output
will give a signal of binary one (1) and the inactive ones will give out binary zeros (0).
Example of input combination AB = 00 giving an output of Z = 1.

Figure 18: Full Comparator operation

70
Exercise
1 Given that A = 101 and B = 111. Draw a comparator for equality and compare the two binary
numbers.
2 Write the output expression for F
3 Use a cascaded Adder to compute the sum of the following two binary numbers:
A = 1011
B = 1010

Resources for further reading

William Stallings, (2006) Computer Organization and Architecture

https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/adder.html

http://www.electronics-tutorials.ws/combination/comb_8.html

71
LECTURER 10 COMBINATIONAL LOGIC CIRCUITS BUILDING BLOCKS
10.1 Multiplexers
A multiplexer (MUX) is a logic circuit (electronic device) that combines two or more inputs into a
single output line. The are several types of multiplexers but in digital signal processing, a multiplexer
selects data from several input lines, combines the data using one of the three popular techniques (
Frequency division Multiplexing, Time Division Multiplexing and Statistical Time Division
Multiplexing)to a high speed output line.

Figure 19: Symbol of a 4-1 multiplexer

As can be seen from the block diagram, a multiplexer connects multiple inputs to a single output. At any
one given time only one input is selected with data to be passed to the output. The input lines are D0,
D1, D2 and D3. To select any one of these input lines to pass data to the output F, the control settings A
and B are used. If A = 0 and B = 0, then the input line D0 will be selected to transmit data to the output
F. The data that would appear at output F is either a binary one (1) or a binary zero (0). This is because
binary bits are used.

72
Figure 20: A 4-1 multiplexer logic circuit

The Boolean expression for F is found by tracing the inputs Do – D3 and the control setting A and B
from the inputs of the AND gates and OR gate for example:

F  A B Do  A BD1  AB D2  ABD3 . The operation of the multiplexer is also best described by the
truth table. (See multiplexer truth table below).
Truth Table

A B F
0 0 Do
0 1 D1
1 0 D2
1 1 D3

From the truth table it is also clear that if the control setting of A and B are set to AB = 00, the Do input
line will be selected and output at F, will appear a 0 or a 1.
For example show that if the control settings A and B are set to AB =10, then the input line D2 will be
selected.

73
There are two ways to show this:

 Use the Boolean function and the input combination 10, that is substituting the 10 in the Boolean
expression, for example:
F  A B Do  A BD1  AB D2  ABD3 and substituting the values for A and B (10) in the
expression: 0.1.D0+0.0.D1+1.1.D2+1.0.D3
F = 0+0+D2+0, so F = D2.
 The second way or technique is to use the input combination 10 and propagate these two control
signals throughout the entire circuit. For example:

10.2 DE multiplexor
A DEMUX is the converse of a MUX. It has one data input line (D) and many outputs. Data
can be transferred from this single input to one of its many outputs. The application of
DEMUX is to send data from a single source to one of a number of destinations (see diagram).

Figure 21: Symbol of a 1 to 4 Demultiplexor

74
Figure 22:1 to 4 DE multiplexor logic circuit diagram

From the above logic circuit diagram, the following Boolean expressions can be derived:

F 0  ABD
F1  A BD
F 2  AB D
F 3  ABD
DE multiplexer truth table

D=1
D A B F0 F1 F2 F3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

From the truth table, it is clear that only one output of the Demultiplexer is active ant any one time.
When D is equal to zero (D =0), all the outputs of the multiplexor will be equal to zero.
This is clearly shown by the logic circuit below where the input signals have been propagated form the
input lines to the output lines. This can also be shown by substituting the input combination D = 1, A = 1
and B =1 in the Boolean output expression F0 – F3.

75
Figure 22: Demultiplexer operation

10.3 Parity Generators

A parity generator/checker is a logic circuit that is used to detect 1-bit errors in a message or during data
entry. There are two types of parity generators:

 Even parity generator

 Odd parity generator
In an even parity generator, the number of binary ones (1s) in a transmitted message must always be
even. If the number of binary ones (1s) in a transmitted message are odd then it is assumed that an error
occurred during data transmission or data entry. The even parity is generator is implemented on
Exclusive OR (XOR) gate.

Consider the example of generating an even parity logic circuit

Consider the message to be transmitted:

Pbit X Y Z
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

The Pbit (parity bit) must be calculated using the XOR logic circuit as follows:

 If the number of binary ones (1s) is even then the P` is 0.

 If the number of binary ones (1s) is odd, then the Pbit is 1

76
Note that even numbers start from: 0, 2,4,6,8,10,12,14 and so on. Odd numbers start from: 1, 3, 5, 7, 9,
11, and so on. The table below shows the message and pbit (even) calculated or filled in.
Consider the message to be transmitted:

Pbit X Y Z
0 0 0 0
1 0 0 1
1 0 1 0
0 0 1 1
1 1 0 0
0 1 0 1
0 1 1 0
1 1 1 1

To generate the logic circuit, note where pbit = 1 and write the corresponding input combination. If pbit
= 1 in more than one instance, then the input combinations are joined by the OR (+) sign.

Pbit  XY Z  XYZ  XY Z  XYZ

 X (Y Z  YZ )  X (Y Z  YZ )
For example:  X (Y  Z )  X (Y  Z )
 X Y  Z

The logic circuit can be drawn using the Boolean expression above as shown below:

The logic gate can also be drawn as three-input Exclusive OR gate

At the receiver, the Pbit must be checked for correctness. The Pbit error check logic circuit is used. The
error check bit logic circuit is implemented as shown below:

77
If there was no error during transmission Cbit will be zero. This assumption is that there were no multiple
bit changes during transmission. This is because in parity bit check codes, if two more bits change their
statuses, that is from 0 to a 1 and vice versa, the error will not be detected.

Cbit Pbit X Y Z
0 0 0 0 0
0 1 0 0 1
0 1 0 1 0
0 0 0 1 1
0 1 1 0 0
0 0 1 0 1
0 0 1 1 0
0 1 1 1 1

10.4 Generating Odd parity bit logic circuit

The same message will be used to generate the odd parity

Pbit X Y Z
1 0 0 0
0 0 0 1
0 0 1 0
1 0 1 1
0 1 0 0
1 1 0 1
1 1 1 0
0 1 1 1

Produce the pbit (odd) Boolean expression as follows:

pbit (odd )  XY Z  XYZ  XY Z  XYZ

 X (Y Z  YZ )  X (Y Z  YZ )
 X (Y  Z )  X (Y  Z )
 X Y  Z
From the Boolean expression, produce the logic circuit as shown below:

78
The odd parity checker logic circuit is generated as shown:

Just like in the even parity checker, if there are no errors during transmission, the Cbit will be zero. See
table below:

Cbit Pbit X Y Z
0 1 0 0 0
0 0 0 0 1
0 0 0 1 0
0 1 0 1 1
0 0 1 0 0
0 1 1 0 1
0 1 1 1 0
0 0 1 1 1

The Cbit value can be obtained by tracing the input combinations and observing the output or by
substituting the input combination values in the Boolean expression;

Cbit  pbit  X  Y  Z

The major disadvantage of the parity check is that if two or more errors occur during transmission, they
cannot be detected.

Exercise
Consider the diagram below:
1 Use it to generate truth table and:
(i) The Pbit
(ii) The Cbit
2 If even parity was going to be used what changes would you make to the logic circuit diagram?

79
3 What is major disadvantage of this logic circuit set up in terms of error detection and correction?

Resources for exploration

http://www.electronics-tutorials.ws/combination/comb_1.html
https://www.allaboutcircuits.com/textbook/digital/chpt-9/combinational-logic-functions/
https://www.pdx.edu/nanogroup/sites/www.pdx.edu.nanogroup/files/2013_Combinational_and_Sequent
ial_L

80
LECTURE 11 COMBINATIONAL LOGIC CIRCUIT BUILDING BLOCKS
11.1 Decoders
A decoder is a combinational logic circuit with a number of output lines one of which is active at any
one time. The active output line is dependent on the pattern of the input lines. In general a decoder has n
input lines and 2n output lines. Below is a logic circuit of a 2 to 4 decoder.

Figure 23: 2 to 4 Decoder logic circuit

The Boolean expressions for the outputs F0 – F3 are as follows:

Fo  enable. A B
F1  enable. A B
F 2  enable. AB
F 3  enable. AB
The truth table for the above decoder can be produced by tracing the input signals from input to output
noting the respective values of each output line, or can be produced by substituting the binary values of
each input combination in the above Boolean expressions.

enable = 1
A B F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Decoders have many uses in digital computers. They can be used to control other circuits. For example
if no changes are needed in other circuits, the enable line can simply be set to zero (0). The other
example where decoders are used is in memory address decoding. For example to construct a 1 KB
memory using four (4) 256 x 8 RAM chips, there is need for a single unified address space which can be
broken down as follows:

81
 \Address Chip
0000-00FF 0
0100-01FF 1
0200-02FF 2
0300-03FF 3
So each chip requires eight (8) address lines and these are supplied by the bits 0- 7 bit lines. The higher-
order 2 bits, 8 and 9 are used to select one of the four chips by using the 2 to 4 decoder. The outputs of
the decoder enable only one of the four chips at a time.
Block diagram showing address decoding

Figure 24: Address decoding

The block diagram operates as follows:

To read or store data to a particular memory location, the 2 to 4 decoder is used to select the chip. For
example if A8 = 0 and A9 = 0 then chip 0 will be selected by enable line 0 at the output of the decoder
to a 1. The address lines A0 –A7 are then used to identify the unique memory location where data can be
written to or read from. Only one chip operate at a time in the above arrangement.
11.2 Encoders
An encoder is a logic circuit that converts information or data from one form to another or from one
code to another, for example changing an octal code number to a binary number. The encoders are
exactly the opposite of decoders. In general an encoder has m inputs and n output lines. Of the m input
line only one is activated at a time. Encoders can also be used for security (data inscription) and saving
memory space (data compression). An example of a basic encoder logic circuit is shown below:

82
Basic encoder logic circuit

A3 A2 A1 A0 F1 F0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 1 0 0 1 1

The operation of the above logic is such that the active input line number is output, for example when
A0 = 1, then F0 = 0 and F1 = 0. The logic circuit below illustrate this point:

Figure 26: Basic encoder operation

Consider an 8 to 3 encoder truth table below:

X7 X6 X5 X4 X3 X2 X1 X0 Y2 Y1 Yo
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
From the truth table, it is clear that the logic expressions for Y0, Y1 and Y2 are:
YO  X 1  X 3  X 5  X 7
Y1  X 2  X 3  X 6  X 7
Y2  X4  X5  X6  X7
83
From the logic expressions, we produce the 8 to 3 binary encoder logic circuit

The xo input line is just earthed as it is insignificant here.

Figure 27: 8 to 3 encoder logic circuit

11.3 Priority encoder

A priority encoder is a combinational logic circuit that compresses multiple binary data inputs into a
small number of outputs. The output of a priority encoder is the binary representation of the ordinary
number starting from zero of the most significant input bit. Priority encoders are often used to control
interrupts requests by acting on the highest priority request. It also includes a priority function, for
example if two or more priority request input signals are equal to one (1) at the same time, the input
signal having the highest priority will take precedence. The internal hardware will check this condition
and a priority is set.
Consider the logic circuit of a priority encoder below:

Figure 28: Priority encoder logic circuit

84
 Inputs Outputs
D3 D2 D1 Do Y1 Yo V
0 0 0 0 x x 0
0 0 0 1 0 0 1
0 0 1 x 0 1 1
0 1 x x 1 0 1
1 x x x 1 1 1

The x‟s in the truth table stand for don‟t care conditions. Assume the inputs D0 – D3 (where D3 has the
highest priority and Do the least) are interrupt requests. If all the inputs have not issued any requests to
the processor (D3-D0 = 0), what appears at Y1 and Yo does not matter and V = 0, meaning no requests
have been issued by any device to the processor. If Do issues an interrupt request the outputs Yo = 0 and
Y1 = 0 indicating that input line 0 has issued an interrupt request and V =1 indicating a request has been
issued. If D1 input line issues an interrupt request, then, it does not matter whether Do also issues an
interrupt request because D0 has a lower priority than D1. The outputs at Y1 and Yo will indicate a
binary one (01) meaning D1‟s request will be serviced but both D and D3 must be zeros. The same
applies to D2 and D3. If D2 issues a request, it also does not matter whether D1 and D0 have requests,
they will simply be ignored because both have lower priorities compared to D2. But D3 must be equal to
0. If D3 issues a request then it does not matter where D2, D1, or Do also issued requests. They will be
ignored because D3 has the highest priority.
The major disadvantage of assigning priorities is that a device with higher priority may take a long time
to be serviced as long as it has requests to the processor whilst those with smaller priorities will be
ignored.
Consider the example below where D3 and D2 have both issued interrupt requests. It is clear from the
propagated signals that D3‟s request has been acknowledged whilst D2‟s has been ignored

Figure 29: Priority encoder operation

85
Exercise
1 Consider the truth table below:

D=1
D A B F0 F1 F2 F3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

(i) Use the truth table to produce the logic circuit diagram (4 marks)
(ii) Name the device and its application (2 marks)
(iii) In practice, is it true that D is always equal to 1? Explain (3 marks)
2 Two 4-bit binary numbers A and B are to be compared for equality. A=A3A2A1Ao = 1011 and
B=1101.
(i) Design (draw) a logic circuit diagram you would use to compare the two binary numbers.
Explain how your circuit diagram operates.
(ii) (ii) Produce the output logic equation
3 In practice a multiplexer and a de multiplexer are combined, what is the reason?
4 Consider the truth table below: Given that it is for a priority encoder, explain how it operates.

A3 A2 A1 A0 F1 F0
x x x 1 0 0
x x 1 x 0 1
0 1 x x 1 0
1 x x x 1 1

Materials for further reading

https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Comb/mux.html
http://www.electronicshub.org/multiplexer-and-demultiplexer/
http://www.learnabout-electronics.org/Digital/dig44.php
http://coep.vlab.co.in/?sub=28&brch=81&sim=609&cnt=1

86
LECTURE 12 SEQUENTIAL LOGIC CIRCUITS
12.1 Introduction
A sequential logic circuit is a digital circuit whose output depends on the following:

 Present inputs
 Present State
 Previous inputs
Sequential circuits have memory (storage) capabilities so they can somehow “remember” previous
inputs. See classical block diagram of a sequential logic circuit.
The D flip flop make up the storage section. From the block diagram, it is clear that a sequential circuit
is made up of two major components:

 The combinational logic block, which is used to accept inputs from the external input lines
 The storage section, which is made up of the flip flops

Figure 30: Classical block diagram of a sequential circuit

Sequential logic circuits are used to implement memory systems. For example a 1-bit memory can be
implemented using an OR logic gate whose output is feedback to its input lines. (See example below):

87
Figure 31: basic 1-bit memory implemented on OR gate
The above 1- bit memory device operates as follows:
If A and Q are initially at zero (0), then output Q remains at zero (0). If A ever becomes a binary one (1),
then Q will be binary one (1) ever after, regardless any further changes in A. The operation of this 1-bit
memory can best be described by a state table or a time diagram.

Present State Input Next State

Qn A Qn + 1
0 0 0
0 1 1
1 1 1
1 0 1
1 1 1

Figure 32: 1-bit memory time diagram

The type of 1-bit memory describe above is a Read Only Memory (ROM), which is written once but
read many times. ROMs are programmed and inserted by the manufacturer.

12.2 The SR Latch

The SR latch is the simplest 1-bit memory (see logic circuit below)

Figure 33: SR 1-bit memory neither implemented on NOR gates

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The SR flip flop has two input lines S and R. S stands for Set and the R stands for Reset. The S drives
the latch into state 1 (store) when it is equal to 1 and the R clears the latch to state 0, when it is equal to
1. The two output lines Q and (not Q) Q‟ are always complementary. The above latch is an example of
an asynchronous sequential circuit. The output Q‟ (not Q) is fed back to the upper NOR gate and the Q
output is fed back to the lower NOR gate. The not Q is also written as Q . For purposes of
standardization when propagating the signals, signals are propagated from the S input first and then the
R. If one starts propagating the signals from the R input the state tables will not be the same.
The above asynchronous latch operates as follows:

When S = 0 and R = 0, output Q = 0 and Q = 1

When S = 0 and R = 1, output Q = 0 and Q = 1

When S = 1 and R = 0, output Q = 1 and Q = 0.

The input combination S = 1 and R = 1 is not allowed and is known by several names such as „race
condition‟,‟ indeterminate‟ state and „ambiguous‟ state. This input combination gives the output Q = Q
= 0. The outputs Q and Q must never be the same. The race condition means that whichever input line
changes first determines the output. This means that one cannot predict the next state with certainty. The
operation of the SR latch is summarized by the state table below:

S R Q Q Name
0 0 0 1 No change
0 1 0 1 Reset (clear to 0)
1 0 1 0 Set to 1 (store)
1 1 x x Not allowed

The SR latch is not commercially available because of the race condition or the ambiguous state. There
were several attempts made to eliminate the race condition in the SR latch to no avail.
The SR latch can also be implemented on NAND gates only. See the SR latch logic circuit implemented
on NAND gates only below:

Figure 34: SR latch implemented on NAND gates only

The SR latch implemented on NAND gates only operates as follows:

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When S = 0 and R = 0, Q = 1 and Q = 1. This input combination is not allowed as it is also a race
condition or ambiguous case. The rest of the input combinations do not bring about ambiguous cases.
See state table below:

S R Q Q Name
0 0 x x Not allowed
0 1 0 1 Reset (clear to 0)
1 0 1 0 Set to 1 (store)
1 1 1 0 Set to 1 (store)

SR latch symbol

As can be seen from the state table above, the SR latch implemented on NAND gates only is also
affected by the ambiguous case. The attempt to eliminate this ambiguous case continued with the
introduction of the NAD gates and the clock to the SR latch.

12.3 Clocked SR flip flop

In the clocked SR flip flop, AND gates and the clock were introduced. The AND gates are usually used
for control purposes because of the operation characteristic of an AND where the output is a binary one
(1) only and only when both inputs are binary one. The clock was introduced to make sure that the latch
does not change states arbitrary but should change at regular intervals of the clock pulse. (See clocked
SR flip flop logic circuit below).

Figure 35: Clocked SR flip flop implemented on AND and NOR gates

The experimental truth table is shown below:

C S R Q Q
0 0 0 0 1
0 0 1 0 1
90
 0 1 0 0 1
0 1 1 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 x x

From the experimental truth table, it is clear that the introduction of the clock had an effect on the
operation of the flip flop. When the clock(C) = 0, the flip flop does not change its states, but changes the
states as soon as the clock is 1. However the introduction of the clock did not eliminate the ambiguous
case.

Below is the summarised standard state table of the clocked SR flip flop

C S R Q Q Name
1 0 0 0 1 No change
1 0 1 0 1 Reset (clear to 0)
1 1 0 1 0 Set to 1 (store)
1 1 1 x x Not allowed

The Clocked SR flip flop can also be implemented on NAND gates only. For example below is the
clocked SR flip flop logic implemented on NAND gates only

Figure 36: Clocked SR flip flop implemented on NAND gates only

As can be seen below, both truth tables are the same and these are standard truth tables.

C S R Q Q Name
1 0 0 0 1 No change
1 0 1 0 1 Reset (clear to 0)
1 1 0 1 0 Set to 1 (store)

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 1 1 1 x x Not allowed

12.4 Flip flop Control Signals

Control signals associated with flip flops are:

 Clock
 Pr eset
 Clear

The Clock is used to allow data from external input sources into the flip flop and it is also used for
synchronization purposes.

The Pr eset control signal is used to force the flip flop into state one (store) regardless of the clock or
the vales at the input lines. The Pr eset control signal was one of the options used to avoid the
ambiguous case in the clocked SR flip flop.

The Clear control signal is used to clear the flip flop regardless of the clock or values in the input lines.
The Pr eset and Clear are low level signals which means they operate on the falling edge of a clock
pulse, that is they are activated by a low level signal (binary 0). So as such they are not allowed to be
binary zeros at the same time.

Below is an example of a truth table of a clocked SR flip flop where the Pr eset and Clear control
signals have been added.

Pr eset Clear C S R Q Q
0 1 1 0 0 1 0
1 0 1 1 0 0 1
1 1 1 1 0 1 0
1 0 1 1 0 0 1
0 1 1 1 0 1 0

It is clear from the above state table (truth) that whenever Pr eset is equal to 0, the flip flop is forced
into state 1 (store), for example the first input combination: Pr eset = 0, Clear = 1, C = 1, S = 0 and R
=0, Q =1 and Q = 0. In the absence of the Pr eset and Clear control signals this input combination
would have been Q = 0 and Q = 1. From the above state table it is also clear that whenever Clear = 0
the flip flop is driven into state 0 (Reset or Clear to zero). In the truth table above there are two cases
when Clear = 0 and the outputs in both cases are Q = 0 and Q = 1. The above state table shows that
there are no cases where Pr eset = Clear equals to zero (0).When Pr eset = Clear = 1, the two control
signals are ignored and the conventional truth table is followed (see truth table)

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Activity
1 Complete the truth table below for the JK flip flop

Pr eset Clear C S R Q Q
1 1 1 0 0 ? ?
0 0 1 1 0 ? ?
1 1 1 1 0 ? ?
1 0 1 1 0 ? ?
0 1 1 1 0 ? ?

2 What is wrong with the above control inputs combinations?

3 Do you think the Preset and Clear control signals are only useful to the S R flip flop?

Further reading and online resources

http://www.learnabout-electronics.org/Digital/dig52.php
http://www.electronics-tutorials.ws/sequential/seq_1.html
http://www.circuitstoday.com/flip-flops

Self-assessment exercise
1 Why is it that the asynchronous SR flip flop is not commercially available?
2 Consider the clocked SR flip flop below:

Produce its truth table starting from the R input. Compare the truth table you produced from the previous
produced starting tracing the signal from the SR input. What does this tell you?

3 Control signals Pr eset and Clear are important when dealing with the SR flip flop, why?

93
LECTURE 13 SEQUENTIAL LOGIC CIRCUITS
13.1 The Clocked JK flip flop
The clocked JK flip flop is a modification of the SR clocked flip flop. This flip flop was designed to
eliminate the SR flip flop ambiguous case. (See logic circuit below). The JK flip flop was designed by
Jack Kilby and gets its name from the initials of his first and last names.

Figure 37: Clocked JK flip flop implemented on AND and NOR gates

The letters J and K do not stand for anything in particular but are used to distinguish the JK flip flop
from the SR flip flop. J = S and K = R. Note that the above flip flop is implemented using the AND and
NOR gates.

As can be seen from the above logic circuit, the outputs of Q and Q are fed back to the AND gates.
This is the only modification which is absent in the clocked SR flip flop. The J input is used to set the
flip flop into state one (store) when it is equal to one (1) and the K input is used to reset/clear to zero
when it is equal to 1.
The feedback lines are only used in cases when C = 1, J = 1 and K = 1 otherwise they are not used. From
the above statement it is clear that the JK flip flop operates like the SR flip except when C =1, J = 1 and
K =1.
The clocked JK flip flop operates as follows:

When C = 1, J = 0, K = 0, Q = 0, Q = 1

When C =1, J = 0, K = 1, Q = 0, Q = 1

When C = 1, J =1, K = 0, Q = 1, Q = 0T

When C =1, J = 1, K = 1, Q = 0 and Q = 1

The feedback complements the previous state. The operations of the JK flip flop can the summarized by
the state table as shown. The introduction of the feedback eliminated the ambiguous case since it will
always toggle (complement) the previous state whenever J = K= 1.t

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C J K Q Q Name
1 0 0 0 1 No change
1 0 1 0 1 Reset (clear to 0)
1 1 0 1 0 Set to 1 (store)
1 1 1 0 1 Toggle

Explanation of the toggle process in the JK flip flop implemented on AND and NOR gates When C
=1, J = 1 and K =1, propagate the inputs values to the outputs of the NOR gates. Take the outputs and
feed them back to the AND gates and propagate the inputs again to the outputs of the NOR gates. These
are now the correct outputs. For example consider the JK flip flop below with simulated values of the
inputs:

Figure 38: Clocked JK flip flop showing simulated signals

Simulation starts with the Upper AND gate where the JK input is connected. Take J =1, C = 1,
propagate them through the AND gates gives a 1, which is passed on to the upper NOR gate, gives a 0 at
the output of the NOR gate which is fed back to the upper AND gate. On the lower AND gate, take the
clock C =1 and K = 1, propagate them through the lower AND gate, gives a 1 at the output which is
passed on to the input of the lower NOR gate and it gives a 0 at its output. The 0 is propagated back to
the inputs of the lower AND gate. So, at the upper AND gate, we have feedback = 0, J = 1 and C =1.
These signals are passed through the AND gate and gives a 0 at its output. The 0 signal is propagated to
the NOR gate which gives a 1 at the not Q ( Q ) output. The 1 at the not Q ( Q ) output is the final output
at the upper NOR gate. On the lower AND gate, we have C =1, K = 1 and Feedback signal = 0. When
passed through the lower AND gate produces a 0 at its output. The 0 signal is passed on to the lower
NOR gate, together with a 1 from the upper NOR gate.(Note that the output of the upper NOR gate is
also connected to the input of the lower NOR gate. So a 0 and a 1 through the NOR gate produces a zero
(0). The final outputs are Q = 0 and Q = 1. This is how the ambiguous case was eliminated in the SR
flip flop.
The Clocked JK flip flop can also be implemented on NAND gates only:
For example:

95
Figure 39: Clocked JK flip flop implemented on NAND gates only.

The implementation is similar to that of the clocked JK implemented on AND and NOR gates but note
that the feedback connections. Unlike in the clocked flip flop implemented on AND and NOR gates, in
the clocked flip flop implemented on NAND gates, the output of the upper NAND gate is connected to
the inputs of the lower NAND gate and the output of the lower NAND gate is connected to the input
lines of the upper NAND gate.
Truth table

C J K Q Q Name
1 0 0 0 1 No change
1 0 1 0 1 Reset (clear to 0)
1 1 0 1 0 Set to 1 (store)
1 1 1 0 1 Toggle

Operation of the clocked JK flip flop implemented on NAND gates only

The truth table above summarizes the operation of the clocked JK flip flop implemented on NAND gates
only. Just like in the clocked JK flip flop implemented on AND and NOR gates, the feedback is only
used when C =1, J = 1, and K = 1.
In the clocked JK flip flop implemented on NAND gates only, when the input combination C = 1, J = 1
and K = 1, arises, the outputs of the previous states and present inputs are used to generate the present
state. For example consider the clocked JK flip flop below with simulated signals:

96
Figure 40: JK flip flop implemented on NAND gates showing simulated signals

Assume the previous outputs were Q = 1 and Q = 0. The 1 is from the previous output of the upper
NAND gate and is fed back to the lower NAND. The zero (0) is from the previous output of the lower
NAND gate and is propagated to the inputs of the upper NAND gate. The inputs to the upper NAND
gates are now J = 1, C = 1 and feedback (the previous state =1. These are passed on through the upper
NAND gate. The result if simulation is: Q = 0 and not Q ( Q ) = 1. Although JK flip flop is an
improvement on the clocked SR flip-flop because of the elimination of the ambiguous case (invalid
inputs), it still suffers from timing problems called “race” if the output Q changes state before the timing
pulse of the clock input has time to go “OFF”. This causes the flip flop to toggle more than once. To
avoid this (toggling more than once), the timing pulse period (T) must be kept as short as possible by
using high frequency. This is sometimes not possible with modern TTL IC‟s the much improved. The
Master-Slave JK Flip-flop was developed to eliminate the problem of toggling more than once.

13.2 The JK Master-Slave Flip Flop

The JK master- slave flip flop was developed to eliminate the problem of toggling more than once which
is associated with the JK flip flop. This flip flop is made up of two flip flop in one, the master which is
used to‟ manufacture‟ the contents and the slave which is used to store the „manufactured‟ contents. The
JK master-slave flip flop logic circuit is shown below:

Figure 41: JK Master- Slave Flip Flop implemented on NAND gates

97
The JK Master-Slave flip flop operates as follows:
On a 1 to 0 clock transition, the master flip flop is connected to the JK input lines and the slave is
inhibited from operating because of the NOT gate that complements the clock signal to the slave flip
flop. On a 0 to 1 clock transition, the master is isolated from the input lines and the slave is activated and
the contents of the master are transferred to the slave flip flop. The purpose of the slave is to hold the
output of the master whilst it is being set for the next input as determined by the J and K inputs.

JK Master-Slave flip flop Truth Table

C J K Q* Q* Q Q Meaning
1 0 0 0 1 0 1 No change
1 0 1 0 1 0 1 Clear to zero
1 1 0 1 0 1 0 Set to one (store)
1 1 1 0 1 0 1 Toggle

The JK master-slave eliminates the problem of toggling more than one but it is expensive. The edge
triggered flip flops have been developed to replace it in some instances, especially the edge triggered JK
flip flop which has become universal and most widely used flip flop. The JK flip flop, because of its
toggling nature is used to implement binary counters. The Q* and Q * are the outputs of the master JK.
Form the truth table it is clear that the master JK operates in the same way as the conventional JK flip
flop. The Feedback is only used in the input combination C = J = K =1.

Figure 45: JK master-slave with simulated signals where the previous state was Q = 1, and not Q ( Q ) =
0.

13.3 The T (Toggle) Flip Flop

The T (toggle) flip flop changes its output on each clock edge, giving an output which is half frequency
of the signal to the T input. For example:

98
It is useful for the construction of binary counters, frequency dividers, and general binary addition
devices. The T flip flop can be implemented from a special JK flip flop. The special JK flip flop is the
one where the inputs J and K are tied together. This type of flip flop operates by toggling the previous
state every time a clock pulse is applied at the input T. T = J & K.

Activity
1 Use a JK flip flop implemented on AND and NOR gates and from it show how you would implement
a T flip flop
2 Produce its truth to show how the produced T flip flop operates differently from the original JK flip
flop
3 The truth table of the produced T flip flop has how many possible input combinations?

Figure 44: T flip flop logic circuit implemented from the JK flip flop

Truth Table

C J K Q Q
1 0 0 0 1
1 1 1 1 0
1 1 1 0 1

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13.4 The D (data) Flip flop
The D flip flop is the best way to avoid the ambiguous case. This flip flop has one data input line and the
D input to the upper NAND gate is the complement to the D input of the lower NAND gate. In this way
the case of both inputs being logical ones (1s) does not arise. (See logic diagram below in figure 45.

Figure 45: D flip flop implemented on NAND gates.

The D flip flop can also be implemented on AND and NOR gates. The D flip flop operates as follows:

 When the clock C = 1 and D = 1, Q = 0 and Q = 1

 When C = 1 and D = 1, Q =1 and Q = 0

D flip flop state table

C D Q Q
1 0 0 1
1 1 1 0

The D flip flop is the simplest in terms of its operation and in this module, it is used to illustrate the
operation of most complex logic circuit diagrams.

Figure 46: D flip flop showing simulated signals propagation when C =1, D =1.

The expected output is: Q =1 and Q . So what one needs to know that when the clock(C) = 1, the value at
D is the one that will be displayed at the output.
D flip flop implemented on AND and NOR gates

100
Figure 47: D flip flop implemented on AND and NOR gates

There is no difference in the operation of the two flip flops as evidenced by their respective truth tables.
D flip flop state table

C D Q Q
1 0 0 1
1 1 1 0

101
LECTURE 14 EDGE TRIGGERED FLIP FLOPS
14.1 Positive edge transition and negative edge transition
The edge triggered flip flops were developed to eliminate the JK flip flop problem of toggling more than
once. The JK master-slave flip flop eliminates this problem but it is expensive. The edge triggered flip
flops operate either on the rising edge of a clock pulse (positive edge transition) or on the falling edge of
a clock pulse (negative edge transition). For example:

Figure 48: Positive edge transition

When the positive edge transition threshold is reached, the inputs are locked out and the flip flop
becomes irresponsive to any further inputs and will only accept inputs on the next positive edge
transition.

Positive edge triggered flip flop symbol

In some cases the not Q ( Q ) output will not be shown; this is because data or information is collected at
the Q output of flip flops. But it does not mean that it is important. In counters, it is used for down
counting where the clock is connected to it in order to complement the original clock signal. Positive
edge transition is also known as a trailing edge of the clock pulse or the rising edge of the clock pulse
transition or 0 to 1 transition.

102
14.2 Negative edge clock transition
The negative edge clock pulse transition is also known as the falling edge transition, leading edge or the
1 to 0 transition. The negative edge and positive transition principle of operation is basically the same.

Figure 49: Negative edge transition

Negative edge triggered flip flop symbol

The clock in the negative edge transition has an inversion bubble to show that it is activated by a low
level signal.
14.3 Flip flop state diagrams
Flip flop state diagrams are used in the design of state diagrams. The state diagrams show the transitions
from one state to the next as dictated by the flip flop inputs and the present states. In a state diagram, a
state is shown by a circle. The binary number inside the circle defines the present state. Transition from
one state to the next is shown by a directed line and the present inputs that cause the transitions are
labelled on the directed line. Where the present state is the same as the next state, a directed line is
drawn connecting the circle with itself and labelled the present inputs, for example in the SR state table,
S = R = 0, the next state is the same as the present state. When S = 1 and R = 0, transition is from state Q
= 0 to state Q = 1. When S = 0 and R =1, transition is from state Q = 1 to state Q = 0. (see figure 50
below).

103
The SR flip flop state diagram

Figure 50: The SR flip flop state diagram

The JK state diagram

The JK flip flop state diagram is similar to the SR flip flop state diagram but the only difference is that
the JK state diagram include the toggling combination, C = 1, J = K = 1. This combination is a
prohibited combination in the SR flip flop.

Figure 51: The JK flip flop state diagram

The toggling combination is: when J = 1 and K =1, transition can go either way depending on the
present state, for example when in state Q = 0 and the inputs J =1, K = 1 is applied to the flip flop, it will
transit into the next state Q =1. When in state Q = 1, and the inputs J =1, K = 1 are applied to the flip
flop, it will move to state Q = 0 (see figure 51).
14.5 SR and JK flip flops Excitation Tables

Excitation tables are derived from the state tables of flip flops. The state tables specify the next state
when the inputs and present states are known. During designing, the designer usually knows the required
transition from present state to next state but wishes to find out the flip flop input conditions that will
cause the required transition. So an excitation table lists the required input combinations for a given
change of state. The excitation tables can be produced from flip-flop state tables or from state diagrams.

The SR flip flop Excitation Table

Present state Next state SR flip flop inputs

104
 Q(t) Q(t+1) S R
0 0 0 x
0 1 1 0
1 0 0 1
1 1 x 0

The SR excitation table works as follows: Transition from state 0 (Q = 0) to next state Q = 0, the S input
must be zero (0), R input is a don‟t care, meaning whether a 0 or a one is used, the output remains the
same. The designer will however choose to use a 0 or a 1 or whatever is at his/her disposal during the
design stage. Transitions from state Q = 0 to state Q = 1 and from state Q =1 to state Q = 0 are straight
forward and easy to understand. Transition from State Q = 1 to next state Q = 1, R must be equal to zero
(0) and S is a don‟t care, meaning a zero or a one can be used. If a zero is chosen when in state one, it
means S = 0, R = 0, thus a no change. A no change means if you are in state 1 and S = 0, R = 0, you will
remain in state 1. The same applies if you are in state 0.

The JK flip flop Excitation Table

Present state Next state JK flip flop inputs
Q(t) Q(t+1) J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

The JK flip flop is slightly complicated by the toggling input combination. So it has don‟t care conditions
in each line of the JK inputs. The first and the last are just like in the SR excitation table. This is however
not surprising since the JK flip flop is a modification of the SR flip flop. The second and third input
combinations make use of the toggling input combination of the JK flip flop. The best way to produce the
SR and JK excitation tables is to use their state diagrams.

105
LECTURER 15 SEQUENTIAL CIRCUIT EQUATIONS
15.1 Typical sequential circuit diagram

The diagram below shows a typical example of a sequential circuit. The AND gates, OR gates and the
INVERTER (NOT gate) form the combinational logic part of the circuit. The two D flip-flops form the
storage part of the sequential circuit.

The interconnections among the gates in the combinational circuit can be specified by a set of Boolean
expressions, for example DA  Ax  Bx (A & B are the outputs of the two D flip flops and x is the
external input). DB  A x is derived from the single AND gate whose output is connected to the D input
of flip flop B. There is also an external output Y which is a function of the input variable and the state
of the flip flops, for example Y  Ax  Bx (state equation). The behavior of a sequential circuit is
derived from inputs, outputs and state of the flip flops.

Figure 52: An example of a sequential circuit

The sequential circuit state table

Present State Input Next State Output

A B X A B Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 1 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 1

106
15.2 The Sequential State Diagram

Information in a state table can be represented graphically in a state diagram. In a state diagram a circle
represents a state and the transition between states is indicated by directed lines connecting the circles.
The binary number inside the circle represents the state of the flip flops. The directed lines are labeled
with two binary numbers separated by a slash. The input value during the present state is labeled first
and the binary number after the slash gives the output. A directed line connecting a circle with itself
means that no change of state occurs.

0/0

00

0/1 10 1/0

0/1

1/0

0/1 0/1 1/0

01

0/1 1/0

Figure 52: Sequential circuit state diagram 11

15.3 Full design of a sequential circuit

The design procedure of a sequential circuit consists of the following steps:

 Translating the circuit specifications into a state diagram;

 Converting the state diagram into a state table (excitation table)
 From the excitation table obtain the logic equations of the circuit diagram.

Example: Design a clocked sequential circuit that goes through a sequence of repeated binary States 00,
01, 10, 11, 00, 01, etc when an external input x is equal to 1. The state of the sequential circuit remains
unchanged when the external input x = 0.Produce its state table showing how it functions.

107
Workings: Step 1
From the problem specifications produce state table

Present State Input Next State

A B X A B
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 1 0
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0
From the state table produce the state diagram according to the sequential circuit specification, this
circuit has no external outputs.

x0
x0

00
x 1 11

X=1

X=1

X=0

x01 1 x=1 x= 0
10

Figure 52: 2-bit binary counter state diagram

Step 2 From the state diagram, produce the excitation table. Since the sequential circuit is a binary
counter, we will use two JK flip flops to build a 2- bit binary UP counter

Present State Input Next State JK flip Flop Inputs

A B X A B JA KA JB KB
0 0 0 0 0 0 x 0 x
0 0 1 0 1 0 x 1 x
0 1 0 0 1 0 x x 0
0 1 1 1 0 1 x x 1
1 0 0 1 0 x 0 0 x
1 0 1 1 1 x 0 1 x
1 1 0 1 1 x 0 x 0
1 1 1 0 0 x 1 x 1
JA and KA are the inputs to of flip flop A and JB and KB are the inputs of flip flop B

108
Step 3
Minimize the excitation table at all positions where the output (next states of flip flops A and B) are 1s
or xs. The functions to be minimized are for the equations JA, KA, JB and KB. For JA we minimize the
function using a three variable Karnaugh map. There is no need to minimize KA since J and K inputs are
combined.
X AB 00 01 10 11
0 X
X X X

1
11 XX X

JA = BX

KA  BX
X AB 00 01 11 10
0 X X X

1 1 X X 1
1 X X 1
JB  X

KB  X
The information from the excitation table after minimization is as follows:

JA  BX ; JB  X ;

KA  BX ; KB  X .

From the logic equations it is clear that the logic diagram should consist of an AND gate and two JK flip
flops. The inputs J and K determine the next state of the counter when a clock signal occurs. When both
J and K = 0, the clock signal will have no effect.
The next step is to draw the circuit diagram from the logic equations.

109
Figure 53: Two bit binary up counter

The state table below shows the operation of the 2-bit binary UP counter

INPUT S Present State External Next State

C J K A B X A B
1 0 0 0 0 0 0 0
1 1 1 0 0 1 0 1
1 1 1 0 1 1 1 0
1 1 1 1 0 1 1 1
1 1 1 1 1 1 0 0

The binary UP counter will not count upwards whenever the external signal is equal to zero (0).
Exercise 1 Use circuit diagrams, time diagrams and state diagrams to distinguish the a JK flip flop from
an SR flip flop
2 The JK master slave was given this name to convey the way it operates. Justify this statement by using
a circuit diagram and its truth table
3 Why is a T flop with best flip flop to implement binary counters?
4 What problem is solved by edge triggered flip flops?

Resources for exploration

https://imlearner.files.wordpress.com/2010/08/computer-system-architecture-3rd-ed-morris-mano-
p98.pdf

Marshall Brain, The J-K Flip-Flop, http://computer.howstuffworks.com/boolean5.htm

William Stallings (2006) Computer Organization and Architecture p.726-730

Shankar, Kenneth and Sleight (2013) About JK and T Flip-Flop Diagrams

http://www.brighthubengineering.com/diy-electronics-devices/46610-jk-and-t-flip-flops/

110
LECTURE 16 BINARY COUNTERS
16.1 Introduction
A binary counter is a sequential circuit (device) that can go through a certain predefined number of
states. It can count up or down. Counters are used in almost all digital computers. A binary counter can
be constructed from the JK flip flop because of its toggling nature.

Applications
Counters are used to count the number of instructions in program, for example the program counter
(PC), contain the address of the next instruction to be executed.

Direct counting
Counters are used for direct counting in manufacturing, for example to count the number of products.
They are also used in digital conversions to count the number of sequences. A binary counter can be
used a frequency divider.
16.2 Counter Types
There are two types of counters namely:

 Asynchronous Up or Down counter

 Synchronous Up or Down counter
An UP counter can count from zero (0) to a predefined number. In general an Up counter counts from 0
to 2n – 1, where n is the number of flip flops used to implement the counter. For a example if a binary
counter is implemented using three (3) flip flops, then it will count from 0 to 7, that is 2n -1. A Down
counter will count from a predefined number say 2n to 0, for example if there are four flip flops in the
counter it will count from 15 to 0.
16.3 4 –bit Asynchronous binary up counter
Figure 54 shows the 4-bit asynchronous binary up counter implemented on the T flip flop (the special
JK flip flop where the J and K inputs are combined. This counter operates as follows:
Initially all the inputs, Q0, Q1, Q2, and Q3 are set to zero. The J and K inputs are tied to a high (5 volts),
so they are ready to toggle with the application of each clock pulse. The flip flops used in the above
circuit are triggered by a 1 to 0 clock transition.

When the clock is in a 1 to 0 transition, and J = K = 1, this toggles the present output at Qo to a 1. Since
each flip flop can only store 1 bit, the 1 displaces the zero (0) which is passed on to the clock of FF1,
which remains at state Q1 = 0. So the situation is Q3 = 0, Q2 = 0, Q1 = 0, Q0 = 1. Counting up always
start with flip flop FF0. So if the clock pulse is applied to FF0, since J and K are ready to toggle, the
output at Q0 is toggled to a 0, the zero (0) displaces the 1 which is passed on to the clock of FF1, this
toggles the output at Q1 from 0 to 1. The one (1) displaces the zero (0) which is passed on to FF2, which
does not change its state since clock (C) = 0. The same applies to FF3. The counter will count up from 0
to15 for example:

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Figure 54: 4- bit asynchronous binary up counter

Q3 Q2 Q1 Q0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
. . . .
1 1 1 1

A time diagram explains better the operation of the above counter. To count from 0 to 15, sixteen (16)
clock pulses are needed. All the flip flops operate on the falling edge of the clock pulse. Since they are
connected in serial, the second flip flop (FF1) cannot change its state before the first flip flop (FF0)
changes its state. The same applies to the rest of the flip flops. This asynchronous up counter is also
called a ripple counter because for the last flip flop (FF3) to change its state the signal will have rippled
from the first flip flop (FF0) to FF3.

112
Figure 55: A 4-bit binary asynchronous up counter time diagram

16.4 A 4-bit Asynchronous binary down counter

Figure 56: Down counter circuit diagram

A down counter counts from a predefined value to zero. The predefined value (2n-1) is determined by
the number of flip flops in the counter, for example if the number of flip flops (n) is four (4) then the
down counter would count from 15 to 0.
The down counter in figure 56 operates as follows:
The J and K inputs of all the flip flops are tied to a binary 1 (5v), so all the flip flops are ready to toggle
the present state as and when a clock pulse is applied. But the flip flops cannot toggle simultaneously
since the clock is connected in serial and FF1 cannot change its state before FF0 changes its present

113
state, since it is triggered by the clock connected to the Q output of FF0. The same applies to FF2 and
FF3. Initially all the flip flops are set to 1, that is FF0 = 1, FF1 = 0, FF2 = 0.
The first flip flop (FF0) operates on a 1 o 0 clock transitions (just like in the up counter) but FF1, FF2
and FF3 operate on a 0 to 1 clock transition since their clocks are connected to the Q outputs. Counting
down always starts from the first flip flop (FF0). So on a 1 to 0 transition FF0‟s present state (Q = 1) is
toggled to a 0 and at the Q output the 1 displaces the zero which is passed on to the clock and at FF1 the
situation is: J = K = 1, C = 0. This means FF1 does not change its state. The same applies to FF2 and
FF3. (See example below)

FF3 FF2 FF1 FF0

1 1 1 1 Pre-set value (15)
1 1 1 0
. . .
0 0 0 1
A time diagram explains even better the operation of a down counter. Figure 57 shows the operation of a
a4-bit asynchronous binary down counter.

Figure 57: 4-bit asynchronous binary down counter time diagram

Advantages and disadvantages of asynchronous counters

Two major advantages of asynchronous counters are:

 They are simple to design and implement

 They are less expensive

114
Disadvantages are:

 Slow operation speed. This is caused by their principle of operation, that is , the second flip flop
cannot change its state before the first flip flop has changed its state. Consider a counter with
nine flip flops. For the ninth flip flop to change, the signal has to ripple through all the other
eight flip flops.
 Erroneous counting can occur at high clocking frequencies. When using asynchronous binary
counter circuits, where the number of flip flops used in implementing the counter is large, adding the time
delay of separate stages together gives a total time delay where the difference in time between the input
signal and the counter output signal is very large. This obviously results in erroneous counting. This also
explains why asynchronous Counters are generally not used in high frequency counting circuits
were large numbers of bits are involved.

Activity
1 Why are asynchronous counters called „ripple „counters?
2 Is it possible to start counting from any digital position?
3 Is it possible to have UP/Down asynchronous counters, yes/no? Explain in each case.

Resources for exploration:

William Stallings (2006) Computer Organization and Architecture p.732-733

https://www.allaboutcircuits.com/textbook/digital/chpt-11/asynchronous-counters/

http://www.electronics-tutorials.ws/counter/count_2.html

https://imlearner.files.wordpress.com/2010/08/computer-system-architecture-3rd-ed-morris-mano-p98.pdf

https://www.allaboutcircuits.com/textbook/digital/chpt-11/synchronous-counters/

https://www.quora.com/What-is-an-asynchronous-counter

115
LECTURE 17 SYNCHRONOUS BINARY COUNTERS
17.1 Introduction
These were developed to eliminate the major problems associated with asynchronous binary counters
namely:

 Slow speed of operation

 Erroneous counting at high frequencies when the number of bits involved is large.
In synchronous counters, the external clock signal is connected to the clock input of every individual flip
flop within the counter and in this way all flip flops are clocked together simultaneously at the same
time. This gives a fixed time relationship. This means changes at the output occur in synchronization
with the clock signal. The individual output bits change state at the same time in response to a common
clock pulse. So in synchronous counters there are no ripple effects and so no propagation delays.
17.2 A 4-bit binary synchronous up counter

Figure 58: A 4-bit binary synchronous up counter

Operation
The J and K inputs of the first flip flop(FF0) are tied to a high(5v), so this flip flop is ready to toggle
whenever a clock pulse(C = 1) is applied. Initially all the flip flops are set to zero (0), that is Q0 = 0, Q1
= 0, Q2 = 0 and Q3 = 0. When a clock pulse is applied to FF0, the present state Q0 = is complemented to
1. The 1 displaces the zero which propagates to the J and K inputs of FF1 and to the inputs of the first
AND gate. With J = K = 0, C =1, FF1 does not change its state. The same applies to FF2 and FF3. In the
next count, Q0 =1 is complemented to a zero. The zero displaces the 1 which propagates to the J and K
inputs of FF1. So the inputs to FF1 are: J = K =1, C =1. The present state of FF1 (Q1 = 0) is
complemented to a 1. The 1 displaces the zero which propagates to the J and K inputs of FF2 as well as
to the inputs of the second AND gates. So the situation is Q0 = 0, Q1 = 1, Q2 and Q3 = 0.

116
The table below summarizes the operation of this synchronous counter.

Q3 Q2 Q1 Q0 J K C
0 0 0 1 1 1 1
0 0 1 0 1 1 1
0 0 1 1 1 1 1
0 1 0 0 1 1 1
. . . . 1 1 1
. . . . 1 1 1
1 1 1 . 1 1 1

The time diagram is the same as that of an asynchronous up counter, the only difference is that the
propagation delays are not there.
17.3 A 4-bit binary synchronous down counter

Figure 59: 4-bit synchronous binary down counter

The basic operation of a synchronous down counter is the same as that of a synchronous up counter. The
only difference is that initially all the flip flops are set at a predefined value, in this case 15.

Operation
Initially all the flip flops are set to 1, that is Q0 = 1, Q1 = 1, Q2 = 1 and Q3 = 1. The J and K inputs of
FF0 are tied to a high, so it is ready to toggle whenever a clock pulse (C =1) is applied to it. When a
clock pulse is applied, the present state of FF0 (Q = 1) is complemented to a zero (0). When Q was a 1,
not Q ( Q ) was a zero. When Q changed to a 0, Q changed to a 1, so the one at Q output displaces the
zero which propagates to the J and K inputs of FF1 and the inputs of the first AND gate. The situation is:
J = 0, K = 0 and C= 1. FF1 does not change its state. The same applies to FF2 and FF3. The rest of the
counting down follows the above pattern. Note that the in the synchronous down counter, the J and K
inputs as well as the AND gates control the flip flops from changing their states simultaneously. Like in
the synchronous counter, the time diagram of the asynchronous down counter and that of the
synchronous counter are the same except that in the synchronous up counter the propagation delays are
not noticeable.

117
17.3 synchronous reversible counters
In practice the up and down counters are combined into one chip to produce a reversible counter that is a
counter which is capable of counting up and down. The reversible counters are more popular than single
up or down counters.

Figure 60: Reversible counter circuit diagram

The diagram above is a simple 3-bit Up/Down synchronous binary counter implemented on JK flip flops
which operate as toggle or T flip flops. The maximum count is 111. The counter counts up in sequence
1,2,3,4,5,6,7 or in reverse sequencing. This type of counter is bidirectional and it can be made to change
the direction at any point in the counting sequence. The Up or Down input control line determines the
direction of the count (see timing diagram figure 61).

Figure 61: 3-bit reversible synchronous binary counter

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Resource for exploration
William Stallings (2006) Computer Organization and Architecture p733-735

https://www.allaboutcircuits.com/textbook/digital/chpt-11/synchronous-counters/

http://www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/counter05.html

http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol1/cwl3/article1.html

M. Morris Mano (2007) Digital Logic and Computer Design

https://imlearner.files.wordpress.com/2010/08/computer-system-architecture-3rd-ed-morris-mano-p98.pdf

http://www.learngroup.org/uploads/2014-12-26/Digital_Design_-_Fifth_Edition.pd

Exercise
1 Consider a 2-bit UP/DOWN synchronous counters that counts in the sequence 00, 01,10, 11,
00,01,11,10,01. Draw its logic circuit and the operation time diagram
2 Show the difference(s) between an up counter and a down counters by using: (i) their respective logic
circuit diagrams, (ii) their respective time diagrams
3 The counting sequences of asynchronous and synchronous counters are the same. How can you
distinguish between the two given a time diagrams of both.

119
LECTURE 18 COMPUTER REGISTERS
18.1 Introduction
A computer register is a group of flip flops used to temporarily store binary data. A computer register is
used to quickly accept, store and transfer data and instructions that are being used immediately by the
Central Processing Unit (CPU). In the computer there are various types of registers used for various
purposes. Some of the most used registers in the digital computers are:

 Accumulator (AC) – used to store intermediate results of processing

 Data register commonly known as memory data register (MDR)- this register is found in the
control unit and is used as a gateway for data from memory to CPU registers and for
results(information) from the CPU registers to main memory
 Address register also known as the memory address register (MAR) - this register has its outputs
connected to the address bus. During instruction execution, the contents of the program counter
(address of the next instruction to be executed) are transferred to this register. In this register the
binary bits are put in their corresponding order and will point to a main memory location where
the instruction or data is to be read from or stored into.
 Program counter (PC) – is used to hold the address of the next instruction to be executed. After
an instruction has been fetched from memory, the PC is updated to contain the address of the
next instruction to be executed. Depending on the address and memory organization, the PC can
be updated by adding a one, a two or a four, for example:
PC← [PC] 1 or PC← [PC]+ 4

The size of a register (the number of binary bit which it can store) is determined by the number of flip
flops used to implement that register. For a example a 16-bit register will be implemented on 16 flip
flops where each flip flop can only store 1 bit.

The most popular types of registers used for temporary data storage are implemented using the D flip
flop and the SR type of flip flops. Computer registers can be organized in serial or in parallel.

18.2 Computer register operations

The register operations include, data transfer, shift operations and register modifications.

Data transfer operation

This is the loading of data from the external sources into the computer registers or the transferring of
data or information from one register to another. The data transfer operation can be serial or parallel.
Below is a parallel load register implemented on D flip flop

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Figure 62: parallel load register implemented on D flip flops

The above parallel load register operates as follows:

All the bits of the register are loaded simultaneously with a common clock pulse
transition, for example a clock transition applied to the clock, will load all the four inputs d0 – d3.
Assume a binary word 1101 is to be loaded into the register (The leftmost bit is the MSB and the
rightmost bit is the LSB).A3 will 1, A2 will be 1, A1 will be 0 and A0 will be 1. (See figure 62). If the
contents of the register must be left unchanged then the clock should be inhibited from the circuit that is
the clocked must be zero. To reset the register the CLEAR (CLR) signal is used (uses negative logic).

Figure 62: parallel load register with simulated signals

Computer data registers can also be implemented on SR flip flops as shown below in figure 63.

121
Figure 63: Parallel load register implemented on SR flip flops

In the SR parallel load register above, do d1, d2 and d3 are input data lines and d4, d5, d6 and d7 are out
lines. The R input is tied to a reset line to avoid the ambiguous case arising. The input data strobe line
must always be a high to accept data in the register. The same applies to the output data strobe. To
parallel load the bit stream 1101, the input data strobe is set to a high, data and the bits are applied to the
respective input lines. With a high output data strobe the bits will simultaneously appear at the
respective output lines d4-d7. Figure 64 shows the simulated signals

Figure 64: SR parallel load register showing simulated signals

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Serial Load Register

In serial load, the output of each flip flop is connected to the input of the next flip-flop. For a D flip-
flop, the data on the D input is transferred to the output when a clock pulse is applied.

Figure 65: Serial load register

Example of load operation

Assume that a data word to be loaded serially in the register is 1101. In serial load, the most significant
bit is to be loaded first. If a 1 is applied to the input of the first flip-flop (FF0) and a clock pulse applied
that data will be entered and stored in flip-flop FF0. In the next clock pulse, the next binary 1 will be
applied at the D input. The 1 in the first flip flop (FF0) will be shifted to FF1 and in the next clock pulse
a 0 will be applied to FF0. FF0 will now store a 0, FF1 a 1 and FF2 a 1. In the last clock pulse FF0 will
store a 1, FF1, a 0, FF2 a, 1 and FF3 a 1. To load 4 bits serially in a register four clock pulses are
needed. The example below shows the serial load operation.
FF0 FF1 FF2 FF3
Initially 0 0 0 0

Pulse 1 1 0 0 0

Pulse 2 0 1 0 0

Pulse 3 1 0 1 0

Pulse 4 0 1 0 1

Activity

1) Given the bit stream 101, show that performing binary multiplication and binary division is
equivalent to:

(i) Shift one bit at a time to he left

(ii) Shifting one bit at a time to the right

2) Show that serial data entry is equivalent to shifting 1-bit to the right at a time

123
3) The D flip flop is used in most illustration to show the operations of logic circuit, why is it the
obvious choice

18.3 Shift Registers

These registers are designed to shift data along the register in either direction, that is
left and right. They can also do serial to parallel conversion and vice versa operations. Shift registers can
be classified as:

 Serial in Serial out (SISO)

 Serial in parallel out (SIPO)
 Parallel in Serial out (PISO)
 Parallel in parallel out (PIPO)
This classification is dependent on how input is applied to and how output is taken from the shift
register.
18.4 Serial in serial out register

Figure 66: SISO shift register

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Example of shift operation

Figure 67: serial in serial out shift register with loaded data bits 1101

Assume that a data word 1101 has been loaded in the shift register and is to be shifted out. Four clock
pulses will be needed to move all the four bits out of the register by shifting one bit at a time. To shift
the bits other data bits must be applied at the data in input line. It is encouraged to use the zero (0) bits to
shift out the bits. If a 0 is applied to the D input of the FF0, the previous bit in FF0 will be shifted to
FF1, the previous bit in FF1 will be shifted to FF2 and the previous bit in FF2 will be shifted to FF3.
The previous bit in FF3 is lost to the out or collected. Successive application of the clock pulses and
zeros will operate in a similar way until all the data word bits have been shifted out of the register. The
illustration below shows how the shifting occurs,

FF0 FF1 FF2 FF3

Initially 1 0 1 1

Pulse 1 0 1 0 1 previous bit (1) of FF3 is collected

Pulse 2 0 0 1 0 previous bit (1) of FF3 is collected

Pulse 3 0 0 0 1 previous bit (0) of FF3 is collected

Pulse 4 0 0 0 0 previous bit (1) of FF3 is collected

Figure 68: SISO shift register operation

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 18.5 Serial in parallel out (SIPO) register
The SIPO shift register allows data to be entered serially and output parallel (simultaneously). SIPO
shift register allows conversion from serial to parallel format. Data is loaded in the register serially as is
the case with SISO. Once the data is in the register, it may either be read out at each output
simultaneously, or it can be shifted out and replaced. (See figure 69). This register configuration has a
set (binary 1 control input signal) and a clear (binary 0 control signal). The Set control signal is used to
set to one of two modes of operation that is reading out at each output simultaneously or shifting the
output and replacing it

Figure 68: Serial in parallel out shift register

Assume that the data word 1101 is to be loaded as serial and output as parallel.

Figure 69: Serial in parallel out shift register operation.

Figure 689 shows one of the two modes of SIPO shift register operation. The above mode is also used
for error correction.

126
18.6 Parallel in Serial out (PISO) register

Figure 70: Parallel in serial out shift register

In the PISO shift register above, d0 – d3 are the parallel inputs. The Clear pulse is low level (binary
zero). It is initially applied to reset all the flip flops to zero (0). Assume a four bit word 1101 is to be
parallel loaded and serially output. The write enable control signal is activated with a binary 1. FF0 will
be 0, FF1 will be 1, FF3 will be 0 and FF3 will be 0. The Preset control signal is active low, so the four
bit data word 1101 will be stored in the shift register. To read the out the stored four bit word in serial
forward four clock pulses are applied to shift the stored bits to the right.

Figure 71: Parallel in serial out with simulated signals.

127
18.6 Parallel in Parallel out (PIPO) register
In the PIPO shift register above, d0 – d3 are the parallel input and Q0 – Q2 are the parallel outputs. All
the data bits at d0-d3 appear on the parallel outputs immediately following the simultaneously entry of
the data bits. The above circuit is a four- bit parallel in parallel out shift register constructed on D flip
flops. When a clock pulse is applied, all the data bits ait the D (d0-d3) inputs appear at the
corresponding Q outputs simultaneously. The clear is a low level signal used to reset the contents of the
shift register. The PIPO is a universal register can be used to output data serially. The set can be used to
select one of the modes of shifting.

Figure 72: Parallel in parallel out shift register.

Figure: 73 PIPO shift register with simulated signals

128
Activity

1) Registers can be implemented using SR flip flops. The SR flip flop is well known for the ambiguous
case. Explain two ways in which the ambiguous cases can be avoided.

2) Shift operations are very popular in digital computers. Name and explain any three cases when shift
operations are necessity.

3) SIPO is a basic operation in digital computers. Explain how this operation is used every day when
ever data is entered into the computer for processing.

Resource for exploration:

Morris Mano & Michael Ciletti, (2013) Digital Design

https://www.ee.usyd.edu.au/tutorials/digitaltutorial/part2/registers03.html

William Stallings, (2006) Computer Organization and Architecture p.731

Exercise

1 Draw a 3-bit parallel load register implemented on SR flip flops. Show how the bit stream 110 is
loaded at the input lines and how it simultaneously appear at the output lines

2 Use a 3-bit register implemented on D flip flops to show that the operation of serial load is equivalent
to shifting 1 bit to the right at a time.

3) Draw a 3- bit SIPO shift register and explain its operation using the bit stream 110

http://www.electronics-tutorials.ws/sequential/seq_5.html

https://imlearner.files.wordpress.com/2010/08/computer-system-architecture-3rd-ed-morris-mano-p98.pdf

http://www.learngroup.org/uploads/2014-12-26/Digital_Design_-_Fifth_Edition.pd

129
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