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Kalyanakumar

This document contains a professional summary and skills, as well as details of 3 projects, for an individual with 3 years of experience in RTL design and Verilog coding. The professional's responsibilities have included FPGA design, debugging, and IP integration. Project roles involved display port, DDR controller, and encryption block design. Education includes a B.E. in ECE from P.S.R Engineering College.

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44 views2 pages

Kalyanakumar

This document contains a professional summary and skills, as well as details of 3 projects, for an individual with 3 years of experience in RTL design and Verilog coding. The professional's responsibilities have included FPGA design, debugging, and IP integration. Project roles involved display port, DDR controller, and encryption block design. Education includes a B.E. in ECE from P.S.R Engineering College.

Uploaded by

kalyanakumarkg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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KALYANAKUMAR K

PROFESSIONAL SUMMARY:

 3 Yrs. of experience in RTL Design


 Very good experience in Verilog RTL Coding
 Very good experience on FPGA Hardware Boards
 Very good experience in RTL debugging
 Experience in FPGA Synthesis and Timing analysis
 Very good debugging skills
 Strong Digital and Logic Design knowledge

PROFESSIONAL SKILLS:

 HDL Languages Verilog


 VLSI EDA Tools Quartus, Xilinx Vivado, Modelsim
 Operating Systems Linux, Windows

PROJECTS:

1. LENS 4K surgical imaging system

End Client: US Client


HDL: Verilog
Team Size: 2

Project Description: The product intake lives surgical video from the visualization system
and blends surgical guidance overlays from procedure applications running on product for
display on the surgical monitor.

Description of Roles: I am part of the Display Port block design

Responsibilities:
• FPGA design creation through IP Integration (Display Port, CVO)
• Developing designer-level linear test bench
• Validating the upstream data transfer through PCIe
• Design debugging through the Signal Tap (STP) and fixing RTL issues
2. Design changes for DDR4/5 Controller IP

End Client: US Client


HDL: Verilog
Team Size: 3

Project Description: This product is Video over IP network solution of our client and it
supports real- time collaboration of video with up to 8K Ultra HD resolution.

Description of Roles: I am part of the DDR4/5 block design team

Responsibilities:
 User interface changes to accommodate back-to-back operations
 APB Slave Interface controller for register configuration
 Developing designer-side linear test bench
 Debugging and fixing RTL issues

3. Design of SHA 3 Engine block

End Client: US Client


HDL: Verilog
Team Size: 3

Project Description: This product is Video over IP network solution of our client and it
supports real- time collaboration of video with up to 8K Ultra HD resolution.

Description of Roles: I am part of the Encryption block design

Responsibilities:
 Developing RTL code from scratch, based on Client microarchitecture doc
 Developing designer-side linear test bench
 Working with DV team for IP verification closure
 Debugging and fixing RTL issues

EDUCATION:

 B. E (ECE), P.S.R Engineering College, sevalpatti, Sivakasi, in 2019, 72%


 Higher Secondary (12thGrade), VOC Government Hr. Sec. School, Kovilpatti, in 2015,
70%
 SSC (10th Grade), Lakshmi Mills Hr. Sec. School, Kovilpatti, in 2013, 79.99%

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