A B C D E

1 1

LCFC Confidential
2
S550 MB Schematic Document 2

Tiger Lake_U42 with DDR4

2020-02
REV:0.1

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-ITL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Cover Page
Date: Thursday, May 28, 2020 Sheet 1 of 61
A B C D E
 A B C D E

LCFC confidential

Memory Bus (Channel A) DDR4

DDI DDI Memory Down
HDMI CONN HDMI Reppeater Memory Bus (Channel B)
Page 34

1 1

Page 17,18
SPI ROM
W25Q80JV
PCI-Express 4x Gen3 SPI
GPU(4X) TCP
Page 19 Intel
SM Bus Retimer
Page 42,43
eDP*2 Type-C Conn
eDP Conn I2C
Page 33
I2C
USB2*1 SM Bus PD Controller Page 44
Touch Screen I2C - EC TPS65994
Page 33
Intel MCP Page 41

NGFF X2 PCI-Express 4x Gen3

SSD(4X) ITL-U42 15W
Page 37
2 USB 2.0 2

SATA 1x Gen3
HDD USB3.0x2 USB2.0x1
Page 37 SD CONN
BGA-1528 USB2.0x3
PCIe x1 Gen2
46mm*24mm C C
O O USB3.0x1
NGFF USB2.0 x1 USB2.0x1
USB3.0 CONN
N N AOU Port IO BOARD
WLAN&BT USBA*2 W/ redriver
CNVi N N SD Card reader
Page 40 USB3.0x1
USB3.0 CONN PWR BUTTON
USB2.0x1 PWR LED
Page 30
Normal Port
SPK Conn.
Page 31
Realtek HD Audio
Page 31 ALC3287
HP&Mic Page 31
I2C Touch Pad
Combo Conn.
USB x1/DMICx1 Page 46
3 3

SPI SPI ROM (16MB)

W25Q128JVSIQ_SO8
USB2.0x1 Page 3~16 Page 7

RGB Camera/DMIC SPI ROM (8MB)

SPI(Mirror Code) W25Q64JVSSIQ_SO8
Page 33 Page 7

EC
ITE IT8827
Finger Printer Page 45
(Module)
Page 38

Int.KBD Thermal Sensor Thermal Sensor

Page 46
NCT7719W NCT7718W
Page 39 Page 39
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Block Diagram
Date: Thursday, May 28, 2020 Sheet 2 of 61
A B C D E
 A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )

BOM Structure BTO Item
@ Un-stuff
Power Plane 14@ For 14" part
15@ For 15" part
+5VS BL@ For KB backlight part
+1.2V +3VS
EMC@ For EMC part
1 1
+1.8VS
+2.5V_DDR +VCCSTG EMC_14@ For EMC 14" part
+0.6VS EMC_15@ For EMC 15" part
+VCCST EMC_NS@ For EMC un-stuff part
+3VALW +1.8VALW +VCCIN ME@ For ME@
State V9B+ +5VALW +3ALW_PCH +VCCIN_AUX
MP@ For MP part
NPI@ For NPI part
CNVI@ For CNVI WLAN
DDP@ For DDP MD part
S0 O O O O O O SDP@ For SDP MD part
RF@ For RF part
RF_NS@ For RF un-stuff part
S0IX O O O O O X
S5 S4
AC Only O O O X X X
2 2
S5 S4
Battery only O O X X X X

EC SMBus1 address EC SMBus2 address EC SMBus3 address PCH SM Bus address

Device Address Device Address Device Address Device Address
Smart Battery need to update Thermal Sensor(NCT7719W) 1001_101xb PMIC 0X34 PD
Charger 0001_001xb Thermal Sensor(NCT7718W) 1001_100xb
Battery 0x34 GPU 0x9E

HSIO PORT Function

1 USB Type-C1
2 USB Type-A AOU
3 3
3 USB Type-A
USB3.0 4 USB Type-C2
5 NC
6 NC
1 USB Type-A AOU
2 USB Type-A
3 NC
4 Finger Printer
USB2.0 5 NC
6 NC
7 CAMERA
8 USB Type-C1
9 USB Type-C2
10 BT

1~4 SUB3.0
1~8
5~4 NC
9 WLAN
PCIE 10~12 NC
4 4

13~16
X4 SSD-2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Notes List
Date: Thursday, May 28, 2020 Sheet 3 of 61
A B C D E
 5 4 3 2 1

UC1A

1 OF 21

AC2 AY2 TCP0_CRX_DTX_P1

AC1 DDIA_TXP_3 TCP0_TXRX_P1
AY1 TCP0_CRX_DTX_N1 TCP0_CRX_DTX_P1 [42]
DDIA_TXN_3 TCP0_TXRX_N1 TCP0_CRX_DTX_P0 TCP0_CRX_DTX_N1 [42]
AD2 BB1
DDIA_TXP_2 TCP0_TXRX_P0 TCP0_CRX_DTX_N0 TCP0_CRX_DTX_P0 [42]
AD1 BB2
CPU_EDP_TX1+ DDIA_TXN_2 TCP0_TXRX_N0 TCP0_CTX_DRX_P1 TCP0_CRX_DTX_N0 [42]
AF1 AM5 CC406 1 2 0.22U_6.3V_K_X5R_0201
[33] CPU_EDP_TX1+ CPU_EDP_TX1- AF2 DDIA_TXP_1 TCP0_TX_P1
AM7 TCP0_CTX_DRX_N1 1 2 TCP0_CTX_C_DRX_P1 [42]
CC405 0.22U_6.3V_K_X5R_0201
[33] CPU_EDP_TX1- CPU_EDP_TX0+ DDIA_TXN_1 TCP0_TX_N1 TCP0_CTX_DRX_P0 TCP0_CTX_C_DRX_N1 [42]
AG2 AT7 CC404 1 2 0.22U_6.3V_K_X5R_0201
[33] CPU_EDP_TX0+ CPU_EDP_TX0- DDIA_TXP_0 TCP0_TX_P0 TCP0_CTX_DRX_N0 TCP0_CTX_C_DRX_P0 [42]
AG1 AT5 CC403 1 2 0.22U_6.3V_K_X5R_0201
[33] CPU_EDP_TX0- DDIA_TXN_0 TCP0_TX_N0 TCP0_AUX_P TCP0_CTX_C_DRX_N0 [42]
AP7
D CPU_EDP_AUX TCP0_AUX_P TCP0_AUX_N TCP0_AUX_P [42] D
AJ2 AP5
[33] CPU_EDP_AUX CPU_EDP_AUX# DDIA_AUX_P TCP0_AUX_N TCP0_AUX_N [42]
AJ1
[33] CPU_EDP_AUX# DDIA_AUX_N
AT2
TCP1_TXRX_P1
DN4 AT1
GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1
DT6 AU1
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0
AU2
CPU_EDP_HPD DR5 TCP1_TXRX_N0
AD5
[33] CPU_EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1
AD7
CPU_HDMI_CLKP TCP1_TX_N1
T12 AH7
[34] CPU_HDMI_CLKP CPU_HDMI_CLKN DDIB_TXP_3 TCP1_TX_P0
HDMI CLK T11 AH5
[34] CPU_HDMI_CLKN CPU_HDMI_TXP0 DDIB_TXN_3 TCP1_TX_N0
Y11 AF7
[34] CPU_HDMI_TXP0 CPU_HDMI_TXN0 Y9 DDIB_TXP_2 TCP1_AUX_P
AF5
HDMI D0 [34] CPU_HDMI_TXN0 CPU_HDMI_TXP1 T9 DDIB_TXN_2 TCP1_AUX_N
[34] CPU_HDMI_TXP1 CPU_HDMI_TXN1 DDIB_TXP_1
HDMI D1 P9 BF1
[34] CPU_HDMI_TXN1 CPU_HDMI_TXP2 DDIB_TXN_1 TCP2_TXRX_P1
V11 BF2
[34] CPU_HDMI_TXP2 CPU_HDMI_TXN2 V9 DDIB_TXP_0 TCP2_TXRX_N1
BE2
HDMI D2 [34] CPU_HDMI_TXN2 DDIB_TXN_0 TCP2_TXRX_P0
BE1
TCP2_TXRX_N0
AB9 BD7
DDIB_AUX_P TCP2_TX_P1
AD9 BD5
DDIB_AUX_N TCP2_TX_N1
AY5
PCH_HDMI_DDC_CLK DM29 TCP2_TX_P0
AY7
[34] PCH_HDMI_DDC_CLK PCH_HDMI_DDC_DATA GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0
DK27 BB5
[34] PCH_HDMI_DDC_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P
BB7
CPU_HDMI_HPD TCP2_AUX_N
DG43
[34] CPU_HDMI_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD
BK1
TCP3_TXRX_P1
DG47 BK2
GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1
DJ47 BJ2
GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0
BJ1
TBT_LSX0_TXD TCP3_TXRX_N0
[42] TBT_LSX0_TXD DU8 BM7
TBT_LSX0_RXD DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1
BM5
[42] TBT_LSX0_RXD GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1
BH5
TCP3_TX_P0
DF6 BH7
TBT_LSX1_RXD DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0
BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P
BK7
TCP3_AUX_N
DN23
GPP_D10 DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0#
AN2 TCRCOMP_P
GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P
AN1 TCRCOMP_N RC401 1 2
TC_RCOMP_N
C DK23 1/20W_150_1%_0201 C
GPP_D12 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO DSI_DE_TE_2
DN21 M8 1 @ TP401
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
DF43 AB1 EDP_COMP
GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
DF45

1
DF47 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK
CE4 DISP_UTILS
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1

1
RC402
USB_OC1# DH52 1/20W_150_1%_0201
[30] USB_OC1# USB_OC2# DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK

2
PCH_ENVDD DM8 TP402
[33] PCH_ENVDD PCH_ENBKL DN8 EDP_VDDEN
@
[33,45] PCH_ENBKL PCH_EDP_PWM EDP_BKLTEN
DG10
[33] PCH_EDP_PWM EDP_BKLTCTL

TGLLAKE-U_BGA1449
@

+3VS

RPC401
1 4 PCH_HDMI_DDC_CLK
2 3 PCH_HDMI_DDC_DATA

2.2K_0404_4P2R_5%

+3VALW_PCH

1/20W_4.7K_1%_0201 2 @ 1 RC403 TBT_LSX0_RXD

B B
1/20W_20K_5%_0201 2 1 RC404

1/20W_4.7K_5%_0201 2 @ 1 RC405 TBT_LSX1_RXD

1/20W_20K_5%_0201 2 1 RC406
@
1/20W_4.7K_5%_0201 2 @ 1 RC407 GPP_D10

1/20W_20K_5%_0201 2 @ 1 RC408

1/20W_4.7K_5%_0201 2 @ 1 RC409 GPP_D12

1/20W_20K_5%_0201 2 @ 1 RC410

An external pull-up resistor is required if the pin is GPIO Group Power Supply
used as HDMI Display I2C, instead of TBT LSx
0 = DDPx I2C / TBT LSx pins at 1.8V
1 = DDPx I2C / TBT LSx pins at 3.3V
GPP_A 1.8V

GPP_B/C/D/E 3.3V
+1.8VALW_PCH
GPP_F 1.8V(only)
RC411 1 2 10K_0201_5% USB_OC1#

RC412 1 2 10K_0201_5% USB_OC2# GPP_G/H 3.3V

GPP_R/S 1.8V
RC413 1 2 100K_0201_5%CPU_EDP_HPD GPD 3.3V(only)

A CC401 A
2 1

0.33U 10V K X5R 0402

@

RPC402
4 1 PCH_ENVDD
3 2 PCH_ENBKL

100K_0404_4P2R_5% Title
Security Classification LC Future Center Secret Data
CC402
2 1
Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
0.33U 10V K X5R 0402 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
@ DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (DDI/EDP/HDMI)
Date: Thursday, May 28, 2020 Sheet 4 of 61
5 4 3 2 1
 5 4 3 2 1

DDRA_DQ[0..63]
[17] DDRA_DQ[0..63] DDRB_DQ[0..63]
DDRA_DQS#[0..7] [18] DDRB_DQ[0..63]
[5,17] DDRA_DQS#[0..7] DDRB_DQS#[0..7]
MD DDRA_DQS[0..7] [5,18] DDRB_DQS#[0..7]
[5,17] DDRA_DQS[0..7] DDRB_DQS[0..7]
[5,18] DDRB_DQS[0..7]
UC1B
2 OF 21

DDR4/LP4/LP5/LP5 CMD Flip

LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) UC1C
DDRA_DQ7 CP53 BT42
DDRA_DQ6 CP52 DDR0_DQ0_7/DDR0_DQ0_7/DDR0_DQ0_7 DDR0_CLK_P1/DDR3_CLK_P/DDR3_CLK_P/DDR3_CLK_P
BT41
MD 3 OF 21

DDRA_DQ5 CP50 DDR0_DQ0_6/DDR0_DQ0_6/DDR0_DQ0_6 DDR0_CLK_N1/DDR3_CLK_N/DDR3_CLK_N/DDR3_CLK_N

BP52 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL) DDR4/LP4/LP5/LP5 CMD Flip
DDRA_DQ4 DDR0_DQ0_5/DDR0_DQ0_5/DDR0_DQ0_5 NC/DDR2_CLK_P/DDR2_CLK_P/DDR2_CLK_P DDRB_DQ7
CP49 BP53 AL53 R41
DDRA_DQ3 CU53 DDR0_DQ0_4/DDR0_DQ0_4/DDR0_DQ0_4 NC/DDR2_CLK_N/DDR2_CLK_N/DDR2_CLK_N
CD42 DDRB_DQ6 AL52 DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7 DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P
R42
D DDRA_DQ2 DDR0_DQ0_3/DDR0_DQ0_3/DDR0_DQ0_3 NC/DDR1_CLK_P/DDR1_CLK_P/DDR1_CLK_P DDRB_DQ5 DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6 DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK_N D
CU52 CD41 AL50 M52
DDRA_DQ1 CU50 DDR0_DQ0_2/DDR0_DQ0_2/DDR0_DQ0_2 NC/DDR1_CLK_N/DDR1_CLK_N/DDR1_CLK_N
CC52 DDRA_CLK0 DDRB_DQ4 AL49 DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5 NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P
M53
DDRA_DQ0 DDR0_DQ0_1/DDR0_DQ0_1/DDR0_DQ0_1 DDR0_CLK_P0/DDR0_CLK_P/DDR0_CLK_P/DDR0_CLK_P DDRA_CLK0# DDRA_CLK0 [17] DDRB_DQ3 DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4 NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK_N
CU49 CC53 AP53 AC42
DDRA_DQ15 DDR0_DQ0_0/DDR0_DQ0_0/DDR0_DQ0_0 DDR0_CLK_N0/DDR0_CLK_N/DDR0_CLK_N/DDR0_CLK_N DDRA_CLK0# [17] DDRB_DQ2 DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3 NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P
CH53 DDR4/LP4/LP5/LP5 CMD Flip
AP52 AC41
DDRA_DQ14 CH52 DDR0_DQ1_7/DDR0_DQ1_7/DDR0_DQ1_7
BT45 DDRB_DQ1 AP50 DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2 NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK_N
Y52 DDRB_CLK0
DDRA_DQ13 DDR0_DQ1_6/DDR0_DQ1_6/DDR0_DQ1_6 NC/DDR3_CKE0/DDR3_WCK_P/DDR3_WCK_P DDRB_DQ0 DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1 DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P DDRB_CLK0# DDRB_CLK0 [18]
CH50 BT47 AP49 Y53
DDRA_DQ12 DDR0_DQ1_5/DDR0_DQ1_5/DDR0_DQ1_5 NC/DDR3_CKE1/DDR3_WCK_N/DDR3_WCK_N DDRB_DQ15 DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0 DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK_N DDRB_CLK0# [18]
CH49 BN51 AF53 DDR4/LP4/LP5/LP5 CMD Flip
DDRA_DQ11 CL53 DDR0_DQ1_4/DDR0_DQ1_4/DDR0_DQ1_4 NC/DDR2_CKE0/DDR2_WCK_P/DDR2_WCK_P
BN53 DDRB_DQ14 AF52 DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7
R47
DDRA_DQ10 DDR0_DQ1_3/DDR0_DQ1_3/DDR0_DQ1_3 NC/DDR2_CKE1/DDR2_WCK_N/DDR2_WCK_N DDRB_DQ13 DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6 NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
CL52 CD45 AF50 R45
DDRA_DQ9 CL50 DDR0_DQ1_2/DDR0_DQ1_2/DDR0_DQ1_2 NC/DDR1_CKE0/DDR1_WCK_P/DDR1_WCK_P
CD47 DDRB_DQ12 AF49 DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5 NC/DDR7_CKE1/DDR7_WCK_N/DDR7_WCK_N
K51
DDRA_DQ8 CL49 DDR0_DQ1_1/DDR0_DQ1_1/DDR0_DQ1_1 NC/DDR1_CKE1/DDR1_WCK_N/DDR1_WCK_N
CA51 DDRB_DQ11 AH53 DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4 NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P
K53
DDRA_DQ23 CT47 DDR0_DQ1_0/DDR0_DQ1_0/DDR0_DQ1_0 NC/DDR0_CKE0/DDR0_WCK_P/DDR0_WCK_P
CA53 DDRB_DQ10 AH52 DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3 NC/DDR6_CKE1/DDR6_WCK_N/DDR6_WCK_N
AC47
DDRA_DQ22 CV47 DDR1_DQ0_7/DDR0_DQ2_7/DDR1_DQ0_7 NC/DDR0_CKE1/DDR0_WCK_N/DDR0_WCK_N DDRB_DQ9 AH50 DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2 NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P
AC45
DDR1_DQ0_6/DDR0_DQ2_6/DDR1_DQ0_6 DDR4/LP4/LP5/LP5 CMD Flip DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1 NC/DDR5_CKE1/DDR5_WCK_N/DDR5_WCK_N
DDRA_DQ21 CT45 BU52 DDRB_DQ8 AH49 W51
DDRA_DQ20 CV45 DDR1_DQ0_5/DDR0_DQ2_5/DDR1_DQ0_5 DDR0_CKE1/DDR2_CA4/DDR2_CA5/DDR2_CA1
BL50 DDRA_CKE0 DDRB_DQ23 AR41 DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0 NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
W53
DDRA_DQ19 CT42 DDR1_DQ0_4/DDR0_DQ2_4/DDR1_DQ0_4 DDR0_CKE0/DDR2_CA5/DDR2_CA6/DDR2_CA0 DDRA_CKE0 [17] DDRB_DQ22 AV42 DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7 NC/DDR4_CKE1/DDR4_WCK_N/DDR4_WCK_N
DDRA_DQ18 DDR1_DQ0_3/DDR0_DQ2_3/DDR1_DQ0_3 DDR4/LP4/LP5/LP5 CMD Flip DDRB_DQ21 DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6 DDR4/LP4/LP5/LP5 CMD Flip
CV42 CF42 AR42 P52
DDRA_DQ17 CT41 DDR1_DQ0_2/DDR0_DQ2_2/DDR1_DQ0_2 DDR0_CS1/DDR1_CA1/DDR1_CA1/DDR1_CA5
CF47 DDRA_CS0# DDRB_DQ20 AV41 DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5 DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
J50 DDRB_CKE0
DDRA_DQ16 DDR1_DQ0_1/DDR0_DQ2_1/DDR1_DQ0_1 DDR0_CS0/NC/DDR1_CS1/DDR1_CA4 DDRA_CS0# [17] DDRB_DQ19 DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4 DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0 DDRB_CKE0 [18]
CV41 DDR4/LP4/LP5/LP5 CMD Flip
AR45 DDR4/LP4/LP5/LP5 CMD Flip
DDRA_DQ31 CK47 DDR1_DQ0_0/DDR0_DQ2_0/DDR1_DQ0_0
CE53 DDRB_DQ18 AV45 DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3
AE42
DDRA_DQ30 CM47 DDR1_DQ1_7/DDR0_DQ3_7/DDR1_DQ1_7 NC/DDR0_CA0/DDR0_CA0/DDR0_CA6
CE50 DDRB_DQ17 AR47 DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2 DDR1_CS1/DDR5_CA1/DDR5_CA1/DDR5_CA5 DDRB_CS0#
DDRA_DQ29 DDR1_DQ1_6/DDR0_DQ3_6/DDR1_DQ1_6 NC/DDR0_CA1/DDR0_CA1/DDR0_CA5 DDRB_DQ16 DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1 DDR1_CS0/NC/DDR5_CS1/DDR5_CA4 AE47 DDRB_CS0# [18]
CK45 BL53 AV47 DDR4/LP4/LP5/LP5 CMD Flip
DDRA_DQ28 CM45 DDR1_DQ1_5/DDR0_DQ3_5/DDR1_DQ1_5 NC/DDR2_CS0/DDR2_CA2/DDR2_CA2
BP47 DDRB_DQ31 AJ41 DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0
N42
DDRA_DQ27 DDR1_DQ1_4/DDR0_DQ3_4/DDR1_DQ1_4 NC/DDR3_CA5/DDR3_CA6/DDR3_CA0 DDRB_DQ30 DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7 NC/DDR7_CA5/DDR7_CA6/DDR7_CA0
CK42 BP42 AJ42 N45
DDRA_DQ26 CM42 DDR1_DQ1_3/DDR0_DQ3_3/DDR1_DQ1_3 NC/DDR3_CA4/DDR3_CA5/DDR3_CA1
BP45 DDRB_DQ29 AL41 DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6 NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
N44
DDRA_DQ25 CM41 DDR1_DQ1_2/DDR0_DQ3_2/DDR1_DQ1_2 NC/DDR3_CA3/DDR3_CA4/DDR3_CS1
BP44 DDRB_DQ28 AL42 DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5 NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
N47
DDRA_DQ24 CK41 DDR1_DQ1_1/DDR0_DQ3_1/DDR1_DQ1_1 NC/DDR3_CA2/DDR3_CA3/DDR3_CS0 DDRB_DQ27 AJ45 DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4 NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
J53
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
DDRA_DQ39 BF53 DDR1_DQ1_0/DDR0_DQ3_0/DDR1_DQ1_0
BB44 DDRA_DQS7 DDRB_DQ26 AJ47 DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3 NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
AC50
DDRA_DQ38 DDR2_DQ0_7/DDR0_DQ4_7/DDR0_DQ2_7 DDR3_DQSP_1/DDR0_DQSP_7/DDR1_DQSP_3 DDRA_DQS#7 DDRA_DQS7 [5,17] DDRB_DQ25 DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2 NC/DDR4_CA1/DDR4_CA1/DDR4_CA5
BF52 BD44 AL45 AC53
DDRA_DQ37 DDR2_DQ0_6/DDR0_DQ4_6/DDR0_DQ2_6 DDR3_DQSN_1/DDR0_DQSN_7/DDR1_DQSN_3 DDRA_DQS6 DDRA_DQS#7 [5,17] DDRB_DQ24 DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1 NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
BF50 BK44 AL47 LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
DDRA_DQ36 DDR2_DQ0_5/DDR0_DQ4_5/DDR0_DQ2_5 DDR3_DQSP_0/DDR0_DQSP_6/DDR1_DQSP_2 DDRA_DQS#6 DDRA_DQS6 [5,17] DDRB_DQ39 DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0 DDRB_DQS7
BF49 BH44 A43 K36
DDRA_DQ35 DDR2_DQ0_4/DDR0_DQ4_4/DDR0_DQ2_4 DDR3_DQSN_0/DDR0_DQSN_6/DDR1_DQSN_2 DDRA_DQS5 DDRA_DQS#6 [5,17] DDRB_DQ38 DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7 DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7 DDRB_DQS#7 DDRB_DQS7 [5,18]
BH53 BA51 B43 K38
DDRA_DQ34 BH52 DDR2_DQ0_3/DDR0_DQ4_3/DDR0_DQ2_3 DDR2_DQSP_1/DDR0_DQSP_5/DDR0_DQSP_3
BA50 DDRA_DQS#5 DDRA_DQS5 [5,17] DDRB_DQ37 D43 DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6 DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7
G44 DDRB_DQS6 DDRB_DQS#7 [5,18]
DDRA_DQ33 DDR2_DQ0_2/DDR0_DQ4_2/DDR0_DQ2_2 DDR2_DQSN_1/DDR0_DQSN_5/DDR0_DQSN_3 DDRA_DQS4 DDRA_DQS#5 [5,17] DDRB_DQ36 DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5 DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6 DDRB_DQS#6 DDRB_DQS6 [5,18]
BH50 BG51 E44 J44
DDRA_DQ32 DDR2_DQ0_1/DDR0_DQ4_1/DDR0_DQ2_1 DDR2_DQSP_0/DDR0_DQSP_4/DDR0_DQSP_2 DDRA_DQS#4 DDRA_DQS4 [5,17] DDRB_DQ35 DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4 DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6 DDRB_DQS5 DDRB_DQS#6 [5,18]
BH49 BG50 A46 D39
DDRA_DQ47 DDR2_DQ0_0/DDR0_DQ4_0/DDR0_DQ2_0 DDR2_DQSN_0/DDR0_DQSN_4/DDR0_DQSN_2 DDRA_DQS3 DDRA_DQS#4 [5,17] DDRB_DQ34 DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3 DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7 DDRB_DQS#5 DDRB_DQS5 [5,18]
AY53 CK44 B46 C39
DDRA_DQ46 AY52 DDR2_DQ1_7/DDR0_DQ5_7/DDR0_DQ3_7 DDR1_DQSP_1/DDR0_DQSP_3/DDR1_DQSP_1
CM44 DDRA_DQS#3 DDRA_DQS3 [5,17] DDRB_DQ33 D46 DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2 DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7
C45 DDRB_DQS4 DDRB_DQS#5 [5,18]
DDRA_DQ45 AY50 DDR2_DQ1_6/DDR0_DQ5_6/DDR0_DQ3_6 DDR1_DQSN_1/DDR0_DQSN_3/DDR1_DQSN_1
CT44 DDRA_DQS2 DDRA_DQS#3 [5,17] DDRB_DQ32 E47 DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1 DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6
D45 DDRB_DQS#4 DDRB_DQS4 [5,18]
C C
DDRA_DQ44 DDR2_DQ1_5/DDR0_DQ5_5/DDR0_DQ3_5 DDR1_DQSP_0/DDR0_DQSP_2/DDR1_DQSP_0 DDRA_DQS#2 DDRA_DQS2 [5,17] DDRB_DQ47 DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0 DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6 DDRB_DQS3 DDRB_DQS#4 [5,18]
AY49 CV44 E38 AJ44
DDRA_DQ43 DDR2_DQ1_4/DDR0_DQ5_4/DDR0_DQ3_4 DDR1_DQSN_0/DDR0_DQSN_2/DDR1_DQSN_0 DDRA_DQS1 DDRA_DQS#2 [5,17] DDRB_DQ46 DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7 DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5 DDRB_DQS#3 DDRB_DQS3 [5,18]
BC53 CK51 D38 AL44
DDRA_DQ42 BC52 DDR2_DQ1_3/DDR0_DQ5_3/DDR0_DQ3_3 DDR0_DQSP_1/DDR0_DQSP_1/DDR0_DQSP_1
CK50 DDRA_DQS#1 DDRA_DQS1 [5,17] DDRB_DQ45 B38 DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6 DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5
AV44 DDRB_DQS2 DDRB_DQS#3 [5,18]
DDRA_DQ41 DDR2_DQ1_2/DDR0_DQ5_2/DDR0_DQ3_2 DDR0_DQSN_1/DDR0_DQSN_1/DDR0_DQSN_1 DDRA_DQS0 DDRA_DQS#1 [5,17] DDRB_DQ44 DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5 DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4 DDRB_DQS#2 DDRB_DQS2 [5,18]
BC50 CR51 A38 AR44
DDRA_DQ40 DDR2_DQ1_1/DDR0_DQ5_1/DDR0_DQ3_1 DDR0_DQSP_0/DDR0_DQSP_0/DDR0_DQSP_0 DDRA_DQS#0 DDRA_DQS0 [5,17] DDRB_DQ43 DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4 DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4 DDRB_DQS1 DDRB_DQS#2 [5,18]
BC49 CR50 E41 AG51
DDRA_DQ55 DDR2_DQ1_0/DDR0_DQ5_0/DDR0_DQ3_0 DDR0_DQSN_0/DDR0_DQSN_0/DDR0_DQSN_0 DDRA_DQS#0 [5,17] DDRB_DQ42 DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3 DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5 DDRB_DQS#1 DDRB_DQS1 [5,18]
BK47 DDR4/LP4/LP5/LP5 CMD Flip D40 AG50
DDRA_DQ54 DDR3_DQ0_7/DDR0_DQ6_7/DDR1_DQ2_7 DDRB_DQ41 DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2 DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5 DDRB_DQS0 DDRB_DQS#1 [5,18]
BK45 CF44 B40 AN51
DDRA_DQ53 BH47 DDR3_DQ0_6/DDR0_DQ6_6/DDR1_DQ2_6 DDR0_ODT1/DDR1_CA0/DDR1_CA0/DDR1_CA6
CF45 DDRA_ODT0 DDRB_DQ40 A40 DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1 DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4
AN50 DDRB_DQS#0 DDRB_DQS0 [5,18]
DDRA_DQ52 DDR3_DQ0_5/DDR0_DQ6_5/DDR1_DQ2_5 DDR0_ODT0/DDR1_CS0/DDR1_CA2/DDR1_CA2 DDRA_ODT0 [17] DDRB_DQ55 DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0 DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4 DDRB_DQS#0 [5,18]
BH45 DDR4/LP4/LP5/LP5 CMD Flip G42 DDR4/LP4/LP5/LP5 CMD Flip
DDRA_DQ51 BH42 DDR3_DQ0_4/DDR0_DQ6_4/DDR1_DQ2_4
CB47 DDRA_MA16_RAS# DDRB_DQ54 G41 DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7
AE44
DDRA_DQ50 DDR3_DQ0_3/DDR0_DQ6_3/DDR1_DQ2_3 DDR0_MA16/DDR1_CA4/DDR1_CA5/DDR1_CA1 DDRA_MA15_CAS# DDRA_MA16_RAS# [17] DDRB_DQ53 DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6 DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6 DDRB_ODT0
BK42 CB44 J41 AE45
DDRA_DQ49 DDR3_DQ0_2/DDR0_DQ6_2/DDR1_DQ2_2 DDR0_MA15/DDR1_CA3/DDR1_CA4/DDR1_CS1 DDRA_MA14_WE# DDRA_MA15_CAS# [17] DDRB_DQ52 DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5 DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2 DDRB_ODT0 [18]
BK41 CB45 J42 DDR4/LP4/LP5/LP5 CMD Flip
DDRA_DQ48 DDR3_DQ0_1/DDR0_DQ6_1/DDR1_DQ2_1 DDR0_MA14/DDR1_CA2/DDR1_CA3/DDR1_CS0 DDRA_MA13 DDRA_MA14_WE# [17] DDRB_DQ51 DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4 DDRB_MA16_RAS#
BH41 CF41 G45 AA47
DDRA_DQ63 DDR3_DQ0_0/DDR0_DQ6_0/DDR1_DQ2_0 DDR0_MA13/DDR1_CS1/DDR1_CS0/DDR1_CA3 DDRA_MA12 DDRA_MA13 [17] DDRB_DQ50 DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3 DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1 DDRB_MA15_CAS# DDRB_MA16_RAS# [18]
BD47 BU53 J45 AA44
DDRA_DQ62 DDR3_DQ1_7/DDR0_DQ7_7/DDR1_DQ3_7 DDR0_MA12/DDR2_CA1/DDR2_CA1/DDR2_CA5 DDRA_MA11 DDRA_MA12 [17] DDRB_DQ49 DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2 DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1 DDRB_MA14_WE# DDRB_MA15_CAS# [18]
BB47 BT51 G47 AA45
DDRA_DQ61 DDR3_DQ1_6/DDR0_DQ7_6/DDR1_DQ3_6 DDR0_MA11/NC/DDR2_CS1/DDR2_CA4 DDRA_MA10 DDRA_MA11 [17] DDRB_DQ48 DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1 DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0 DDRB_MA13 DDRB_MA14_WE# [18]
BD45 BV42 J47 AE41
DDRA_DQ60 DDR3_DQ1_5/DDR0_DQ7_5/DDR1_DQ3_5 DDR0_MA10/DDR3_CA1/DDR3_CA1/DDR3_CA5 DDRA_MA9 DDRA_MA10 [17] DDRB_DQ63 DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0 DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3 DDRB_MA12 DDRB_MA13 [18]
BB45 BU50 G38 P53
DDRA_DQ59 DDR3_DQ1_4/DDR0_DQ7_4/DDR1_DQ3_4 DDR0_MA9/DDR2_CA0/DDR2_CA0/DDR2_CA6 DDRA_MA8 DDRA_MA9 [17] DDRB_DQ62 DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7 DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5 DDRB_MA11 DDRB_MA12 [18]
BB42 BY53 G36 N51
DDRA_DQ58 DDR3_DQ1_3/DDR0_DQ7_3/DDR1_DQ3_3 DDR0_MA8/DDR0_CA2/DDR0_CA3/DDR0_CS0 DDRA_MA7 DDRA_MA8 [17] DDRB_DQ61 DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6 DDR1_MA11/NC/DDR6_CS1/DDR6_CA4 DDRB_MA10 DDRB_MA11 [18]
BB41 CA50 H36 U42
DDRA_DQ57 BD42 DDR3_DQ1_2/DDR0_DQ7_2/DDR1_DQ3_2 DDR0_MA7/DDR0_CA4/DDR0_CA5/DDR0_CA1
BY52 DDRA_MA6 DDRA_MA7 [17] DDRB_DQ60 H38 DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5 DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5
P50 DDRB_MA9 DDRB_MA10 [18]
DDRA_DQ56 DDR3_DQ1_1/DDR0_DQ7_1/DDR1_DQ3_1 DDR0_MA6/DDR0_CA3/DDR0_CA4/DDR0_CS1 DDRA_MA5 DDRA_MA6 [17] DDRB_DQ59 DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4 DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6 DDRB_MA8 DDRB_MA9 [18]
BD41 BY50 N36 U53
DDR3_DQ1_0/DDR0_DQ7_0/DDR1_DQ3_0 DDR0_MA5/DDR0_CA5/DDR0_CA6/DDR0_CA0 DDRA_MA4 DDRA_MA5 [17] DDRB_DQ58 DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3 DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0 DDRB_MA7 DDRB_MA8 [18]
CD51 L36 W50
DDR0_MA4/DDR0_CS0/DDR0_CA2/DDR0_CA2 DDRA_MA3 DDRA_MA4 [17] DDRB_DQ57 DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2 DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1 DDRB_MA6 DDRB_MA7 [18]
CD53 L38 U52
DDR0_MA3/DDR0_CS1/DDR0_CS0/DDR0_CA3 DDRA_MA2 DDRA_MA3 [17] DDRB_DQ56 DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1 DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1 DDRB_MA5 DDRB_MA6 [18]
BV47 N38 U50
DDR0_MA2/DDR3_CS0/DDR3_CA2/DDR3_CA2
CE52 DDRA_MA1 DDRA_MA2 [17] DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0 DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0
AA51 DDRB_MA4 DDRB_MA5 [18]
DDR0_MA1/NC/DDR0_CS1/DDR0_CA4 DDRA_MA0 DDRA_MA1 [17] DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2 DDRB_MA3 DDRB_MA4 [18]
BV41 AA53
DDR0_MA0/NC/DDR3_CS1/DDR3_CA4 DDRA_MA0 [17] DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3 DDRB_MA2 DDRB_MA3 [18]
DDR4/LP4/LP5/LP5 CMD Flip U47
BN50 DDRA_BG1 DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2
AC52 DDRB_MA1 DDRB_MA2 [18]
DDR0_BG1/DDR2_CA2/DDR2_CA3/DDR2_CS0 DDRA_BG0 DDRA_BG1 [17] DDR1_MA1/NC/DDR4_CS1/DDR4_CA4 DDRB_MA0 DDRB_MA1 [18]
BL52 U41
DDR0_BG0/DDR2_CA3/DDR2_CA4/DDR2_CS1 DDRA_BG0 [17] DDR1_MA0/NC/DDR7_CS1/DDR7_CA4 DDRB_MA0 [18]
DDR4/LP4/LP5/LP5 CMD Flip DDR4/LP4/LP5/LP5 CMD Flip
CB42 DDRA_BA1 K50 DDRB_BG1
DDR0_BA1/DDR1_CA5/DDR1_CA6/DDR1_CA0 DDRA_BA0 DDRA_BA1 [17] DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0 DDRB_BG0 DDRB_BG1 [18]
BV44 J52
DDR0_BA0/DDR3_CA0/DDR3_CA0/DDR3_CA6 DDRA_BA0 [17] DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1 DDRB_BG0 [18]
DDR4/LP4/LP5/LP5 CMD Flip DDR4/LP4/LP5/LP5 CMD Flip
BT53 DDRA_ACT# AA42 DDRB_BA1
DDR0_ACT#/DDR2_CS1/DDR2_CS0/DDR2_CA3 DDRA_ACT# [17] DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0
U44 DDRB_BA0 DDRB_BA1 [18]
DDR4/LP4/LP5/LP5 CMD Flip DDRB_BA0 [18]
DDRA_PAR DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
BV45
DDR0_PAR/DDR3_CS1/DDR3_CS0/DDR3_CA3 DDRA_PAR [17] DDRB_ACT#
N53
B
AU50 DDRA_ALERT# DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3 DDRB_ACT# [18] B
DDR0_ALERT# DDR_SA_VREFCA DDRA_ALERT# [17] DDRB_PAR
AU49 U45
DDR0_VREF_CA DDR_SA_VREFCA [17] DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3 DDRB_PAR [18]
E52 DDR_VTT_CNTL AU53 DDRB_ALERT#
DDR_VTT_CTL
DV47 CPU_DRAMRST#_R DDR1_ALERT#
AU52 DDR_SB_VREFCA DDRB_ALERT# [18]
DDR_SB_VREFCA [18]
DRAM_RESET#
C49 DDR_RCOMP_0 RC501 1 2 1/20W_100_1%_0201 DDR1_VREF_CA
DDR_RCOMP

TGLLAKE-U_BGA1449
TGLLAKE-U_BGA1449 @
@

+3VALW_PCH

+VDDQ_CPU

1
RC504
1

100K_0402_5%
RC505
1/16W_470_1%_0402

2
CPU_DRAMPG_CNTL [55]
2

@
CPU_DRAMRST#_R RC507 2 1 0_0402_5% +VDDQ_CPU
CPU_DRAMRST# [17,18]

1
RC506 C
1 1 2 2 QC501
CC501 1K_0402_5% B MMBT3904WH_SOT323-3
0.1U_6.3V_K_X5R_0201 E

3
@
2

DDR_VTT_CNTL

A A

2
RC508
10K_0402_5%
@

1
Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (DDR4)
Date: Thursday, July 30, 2020 Sheet 5 of 61
5 4 3 2 1
 5 4 3 2 1

+VCCSTG_TERM

RC601 1 2 51_0402_5% PCH_JTAG_TDO_CPU +VCCSTG_CPU

RC602 1 @ 2 51_0402_5% PCH_JTAG_TDI_CPU

1
RC603 1 @ 2 51_0402_5% PCH_JTAG_TMS_CPU
RC30
1 2 1K_0402_5% H_PROCHOT#
RC604 EAR 1K_0201_5%

PCH_TCK_JTAGX_CPU
Stall CPU reset sequence
RC2019 1 2 51_0402_5% until de-asserted:

2
XDP_TRST_CPU_N - 1 = (Default) Normal CPU_EAR
RC605 1 2 51_0402_5% Operation; No stall.
@ UC1U
PCH_TCK_JTAGX - 0 = Stall
RC2020 1 2 51_0402_5%
21 OF 21

1
@
RC34
D XDP_TRST_CPU_N D
CATERR# M7 K4 @ 1K_0201_5%
BK9 CATERR# PROC_TRST#
B9 PCH_JTAG_TMS_CPU
[45] H_PECI
RC606 1 2 499_0402_1% H_PROCHOT#_R E2 PECI PROC_TMS
D12 PCH_JTAG_TDO_CPU
[13,45,55] H_PROCHOT#

2
H_THRMTRIP# PROCHOT# PROC_TDO PCH_JTAG_TDI_CPU
M5 A12
THRMTRIP# PROC_TDI
B6 PCH_TCK_JTAGX_CPU
RC608 1 2 1/20W_49.9_1%_0201 PROC_OPI_RCOMP CT39 PROC_TCK

RC610 1 2 1/20W_49.9_1%_0201 PCH_OPI_RCOMP CB9 PROC_POPIRCOMP

D8 PCH_TCK_JTAGX_CPU
CW12 PCH_OPIRCOMP PCH_JTAGX
A9 PCH_JTAG_TMS_CPU
TP_1 PCH_TMS PCH_JTAG_TDO_CPU
CM39 E12
TP_2 PCH_TDO
B12 PCH_JTAG_TDI_CPU
DBG_PMODE DF4 PCH_TDI
A7 PCH_TCK_JTAGX
C750@ need check DBG_PMODE PCH_TCK
H4 XDP_TRST_CPU_N GPP_F7 RC50 1 @ 2 1/20W_20K_5%_0201
RC628 1 @ 2 0_0201_5% PCH_TBT_FORCE_PWR DB42 PCH_TRST#
[41,42] TBT_FORCE_PWR GPP_B4/CPU_GP3 PROC_PRDQ_N GPP_F10
DB41 C11 1 TP603 @ RC49 1 @ 2 1/20W_20K_5%_0201
DF8 GPP_B3/CPU_GP2 PROC_PREQ#
D11 PROC_PREY_N 1 TP604 @
EC_SCI# DU5 GPP_E7/CPU_GP1 PROC_PRDY#
[45] EC_SCI# GPP_E3/CPU_GP0 CPU_EAR
G1 GPP_F7 and GPP_F10:
GPP_H2 DF31 EAR_N/EAR_N_TEST_NCTF
20191214 GPP_H2 Reserved, Rising edge of RSMRST#
GPP_H1 DV32 DT15 GPP_F7
GPP_H0 GPP_H1 GPP_F7 This strap has a 20 kohm ¡À 30% internal pull-down.
DW32 DR15 This strap should sample LOW. There should NOT be any onboard
+3VALW_PCH GPP_H0 GPP_F9
DT14 GPP_F10
GPP_F10 device driving it to opposite direction during strap sampling.
DJ27
GPP_H19/TIME_SYNC0 Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

2. This signal is in the primary well.

1

GPP_H0: Boot Strap 1 TGLLAKE-U_BGA1449

RC637

RC638

RC639

GPP_H1: Boot Strap 2 @

GPP_H2: Boot Strap 3
Boot Strap, Rising edge of RSMRST#
@ @ @
These straps has a 20 kohm ¡À 30% internal
2

GPP_H0 pull-down.
GPP_H1 They are bit [3:1] of a total of 4-bit encoded pin straps
GPP_H2 for boot configuration.
Refer to Boot Strap 0 (on GPP_C5) for the encoding.
1/20W_20K_5%_0201

1/20W_20K_5%_0201

1/20W_20K_5%_0201

Notes: 1. The internal pull-down is disabled after

RSMRST# de-asserts.
1

1
RC640

2. This signal is in the primary well.

RC641

RC642

C C

@ @ @
2

0000 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is enabled
0010 = Master Attached Flash Configuration (BIOS / CSME on SPI). eSPI is disabled
0100 = BIOS on eSPI Peripheral Channel; CSME on master attached SPI
1000 = Slave Attached Flash Configuration (BIOS / CSME on eSPI attached device).
UC1G
1100 = BIOS on eSPI peripheral Channel; CSME on slave attached SPI.
7 OF 21

RC618 1 2 1/20W_33_5%_0201 HDA_BCLK_R DR38 DW15

[31] HDA_BITCLK_AUDIO HDA_SYNC_R GPP_R0/HDA_BCLK/I2S0_SCLK GPP_F8/I2S_MCLK2_INOUT
+VCCST_CPU RC619 1 2 1/20W_33_5%_0201 DU37 DW24
[31] HDA_SYNC_AUDIO HDA_SDO_R GPP_R1/HDA_SYNC/I2S0_SFRM GPP_D19/I2S_MCLK1
RC620 1 2 1/20W_33_5%_0201 DT37
H_THRMTRIP# [31] HDA_SDOUT_AUDIO HDA_SDI GPP_R2/HDA_SDO/I2S0_TXD
RC615 1 2 1K_0402_5% DV37 DG41
[31] HDA_SDI GPP_R3/HDA_SDI0/I2S0_RXD GPP_A23/I2S1_SCLK
RC616 1 2 1K_0402_5% CATERR# DT38
GPP_R7/I2S1_SFRM
this signal should have an exposed test point for easy debug access DV41 DV38
GPP_R4/HDA_RST# GPP_R6/I2S1_TXD
and have a 1K ohm pull-up to VCCST DL53 DW38
CNVI_RF_RESET#_PCH GPP_A7/I2S2_SCLK/DMIC_CLK_A0 GPP_R5/HDA_SDI1/I2S1_RXD
RC624 1 2 1/20W_33_5%_0201 DG51
[40] CNVI_RF_RESET#_R GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0 DMIC_CLK0_PCH RC635
+3VS DG50 DN31 1 @ 2 0_0201_5%
GPP_A10/I2S2_RXD/DMIC_DATA1 GPP_S6/SNDW3_CLK/DMIC_CLK_A0 DMIC_DAT0_PCH RC636 DMIC_CLK [31,33]
DM31 1 @ 2 0_0201_5%
1 2 10K_0402_5% EC_SCI# 1 2 1/20W_33_5%_0201 CNVI_MODEM_CLKREQ_PCH DL49 GPP_S7/SNDW3_DATA/DMIC_DATA0 DMIC_DATA [31,33]
RC617 RC626
[40] CNVI_MODEM_CLKREQ_R GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1
DL52 DK33
GPP_A11/PMC_I2C_SDA/I2S3_SCLK GPP_S4/SNDW2_CLK/DMIC_CLK_A1
DK31
PCH_BT_OFF# GPP_S5/SNDW2_DATA/DMIC_DATA1
RC3912 1 @ 2 0_0201_5% DH49
[8,23,26] PCH_BT_OFF# GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0
DW35
RC627 1 2 1/20W_200_1%_0201 SNDW_RCOMP DF33 GPP_S2/SNDW1_CLK/DMIC_CLK_B0
DV35
SNDW_RCOMP GPP_S3/SNDW1_DATA/DMIC_CLK_B1

DT32
GPP_S0/SNDW0_CLK
DR35
GPP_S1/SNDW0_DATA

TGLLAKE-U_BGA1449
B @ B

33P_0201_50V8-J 2 1 CC605 HDA_BCLK_R +1.8VALW_PCH

33P_0201_50V8-J 2 1 CC607 @ HDA_SDO_R

1

UC1D
33P_0201_50V8-J 2 1 CC606 @ HDA_SDI RC622
1/20W_4.7K_5%_0201 4 OF 21

1/20W_75K_5%_0201 2 1 RC631 CNVI_RF_RESET#_PCH

2

HDA_SDO_R RC625 1 @ 2 0_0201_5% DV24

ME_FLASH [45] RSVD_2
DW47 RSVD_3
GPP_R2(HDA_SDO_R): DW49 RSVD_4
Glitch Free Requirements: This signal has a 20K ¡À30% internal pull-down. A48 RSVD_5
Pull-down resistor to ensure the stability of the signal 0 = Enable security measures defined in the Flash Descriptor. (Default)
during platform bootup 1 = Disable Flash Descriptor Security (override). This strap should only
be asserted high using external Pull-up in manufacturing/debug TGLLAKE-U_BGA1449
Option 1:Cap Implementation environments ONLY. @
NA for 3.3v Ramp Rate from 5-50ms Notes:
NA for 3.3V Ramp Rate Less than 5ms 1. The internal pull-down is disabled after PCH_PWROK is high.
2. This signal is in the primary well.
Option 2:Pull-down Resistor Implementation
NA for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

CNVI_MODEM_CLKREQ_PCH
DMIC_CLK0_PCH DMIC_DAT0_PCH
CC604 EMC_NS@
33P_0201_50V8-J

+VCC1.05_OUT_FET 1
CC601
33P_0201_50V8-J

CC602
33P_0201_50V8-J

1 1
@
RC632 1 2 1K_0201_5% DBG_PMODE
@ 2
2 2
EMC_NS@

EMC_NS@

A RC633 1 2 1K_0201_5% A

DBG_PMODE(Reserved): Rising edge of RSMRST#

This strap has a 20 kohm internal pull-up.
This strap should sample high. There should NOT be
any on-board device driving it to opposite direction
during strap sampling.
Notes:
1. The internal pull-up is disabled after RSMRST# deasserts.
2. This signal is in the primary well. Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (JTAG/AUDIO/SDIO/GPIO)
Date: Sunday, August 02, 2020 Sheet 6 of 61
5 4 3 2 1
 5 4 3 2 1

UC1E
5 OF 21
+3VALW_PCH

RPC701
SPI_CLK RC734 1 @ 2 0_0201_5% PCH_SPI0_CLK DJ37 DK21 PCH_SMB_CLK PCH_SML0_CLK 1 4
[45] SPI_CLK SPI_IO3 PCH_SPI0_IO3 SPI0_CLK GPP_C0/SMBCLK PCH_SMB_DATA PCH_SML0_DATA
RC731 1 @ 2 0_0201_5% DG35 DM19 2 3
SPI_IO2 RC730 1 @ 2 0_0201_5% PCH_SPI0_IO2 DJ39 SPI0_IO3 GPP_C1/SMBDATA
DN19 PCH_SMB_ALERT#
SPI_SO RC732 1 @ 2 0_0201_5% PCH_SPI0_SO DJ33 SPI0_IO2 GPP_C2/SMBALERT#
2.2K_0404_4P2R_5%
[45] SPI_SO SPI_SI PCH_SPI0_SI SPI0_MISO PCH_SML0_CLK PCH_SML0_ALERT# RC701
RC729 1 @ 2 0_0201_5% DJ35 DK19 Retimer 2 @ 1 4.7K_0402_5%
[45] SPI_SI PCH_SPI0_CS1# SPI0_MOSI GPP_C3/SML0CLK PCH_SML0_DATA PCH_SML0_CLK [42]
DF35 DM17
PCH_SPI0_CS0# SPI0_CS1# GPP_C4/SML0DATA PCH_SML0_ALERT# PCH_SML0_DATA [42]
DG37 DN17 GPP_C5(PCH_SML0_ALERT#):
SPI0_CS0# GPP_C5/SML0ALERT#
DF39 Rising edge of RSMRST#
SPI0_CS2#
DK17 PCH_SML1_CLK
BOARD_ID4 GPP_C6/SML1CLK PCH_SML1_DATA This signal has a 20K+/-30% internal pull-down.
DJ6 DJ17 0 = Enable eSPI. (Default)
[8] BOARD_ID4 BOARD_ID2 GPP_E11/SPI1_CLK/THC0_SPI1_CLK GPP_C7/SML1DATA PCH_SML1_ALERT#
[8] BOARD_ID2
DN5 CY50 PD
1 = Disable eSPI.
BOARD_ID1 DR9 GPP_E2/SPI1_IO3/THC0_SPI1_IO3 GPP_B23/SML1ALERT#/PCHHOT#/GSPI1_CS1#
D [8] BOARD_ID1 BOARD_ID5 DM6 GPP_E1/SPI1_IO2/THC0_SPI1_IO2
DN53 ESPI_CLK_R Notes: D
RC702 1 2 1/20W_49.9_1%_0201
[8] BOARD_ID5 BOARD_ID6 DK6 GPP_E12/SPI1_MISO_IO1/THC0_SPI1_IO1 GPP_A5/ESPI_CLK
DJ53 ESPI_IO3_R RC706 1 2 1/20W_15_5%_0201
ESPI_CLK [45] 1. The internal pull-down is disabled after RSMRST# de-asserts.
[8] BOARD_ID6 BOARD_ID3 DK8 GPP_E13/SPI1_MOSI_IO0/THC0_SPI1_IO0 GPP_A3/ESPI_IO3/SUSACK#
DH50 ESPI_IO2_R RC705 1 2 1/20W_15_5%_0201
ESPI_IO3 [45] 2. This signal is in the primary well
EC_SMI [8] BOARD_ID3 GPP_E10/SPI1_CS#/THC0_SPI1_CS# GPP_A2/ESPI_IO2/SUSWARN#_SUSPWRDNACK ESPI_IO1_R ESPI_IO2 [45]
DV11 DP50 RC704 1 2 1/20W_15_5%_0201
[45] EC_SMI BOARD_ID7 GPP_E8/SPI1_CS1#/SATA_LED# GPP_A1/ESPI_IO1 ESPI_IO0_R ESPI_IO1 [45]
[8] BOARD_ID7
DW9 DP52 RC703 1 2 1/20W_15_5%_0201
GPP_E6 GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS#_R ESPI_IO0 [45]
DT8 DK52 RC707 1 @ 2 0_0201_5%
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_CS# [45] +3VALW_PCH
DL50
BOARD_ID8 GPP_A6/ESPI_RESET# ESPI_RST# [45]
DN15
[8] BOARD_ID8 BOARD_ID12 GPP_F11/THC1_SPI2_CLK 2.2K_0404_4P2R_5%
[8] BOARD_ID12
DK13
BOARD_ID11 DM13 GPP_F15/GSXSRESET#/THC1_SPI2_IO3 PCH_SMB_CLK 4 1
[8] BOARD_ID11 BOARD_ID10 GPP_F14/GSXDIN/THC1_SPI2_IO2 PCH_SMB_DATA
[8] BOARD_ID10
DN13 3 2
BOARD_ID9 DJ15 GPP_F13/GSXSLOAD/THC1_SPI2_IO1
[8] BOARD_ID9 BOARD_ID13 GPP_F12/GSXDOUT/THC1_SPI2_IO0
DK15 RPC702
[8] BOARD_ID13 GPP_F16/GSXCLK/THC1_SPI2_CS#
DN10
GPP_F18/THC1_SPI2_INT#
DV14
GPP_F17/THC1_SPI2_RST#

DH3 PCH_SMB_ALERT# RC708 1 2 1/20W_4.7K_5%_0201

CL_CLK
DH4
+3VALW_PCH CL_DATA
DF2 GPP_C2(PCH_SMB_ALERT#):
CL_RST#
GPP_E6
This signal is used to wake the system or generate SMI#.
RC754 1 2 100K_0201_5% External Pull-up resistor is required.Rising edge of RSMRST#
TGLLAKE-U_BGA1449 This signal has a 20K+/-30% internal pull-down.
RC753 1 @ 2 1/20W_4.7K_5%_0201 @ 0 = Disable Intel ME Crypto Transport Layer Security (TLS)
cipher suite (no confidentiality). (Default)
1 = Enable Intel ME Crypto Transport Layer Security (TLS)
GPP_E6: cipher suite (with confidentiality). Must be
JTAG ODT Disable pulled up to support Intel AMT with TLS.
Rising edge of RSMRST# +3VALW_PCH +3V_SPI Notes:
This strap does not have an internal pull-up or pull-down. 1. The internal pull-down is disabled after RSMRST# de-asserts.
External pull-up is recommended 2. This signal is in the primary well.
RC728 1 MP@ 2 0_0402_5%
0=> JTAG ODT is disabled
1=> JTAG ODT is enabled
+3VALW_PCH
DC11 2 1
+3V_SPI RC711 1 @ 2 1/20W_150K_5%_0201 PCH_SML1_ALERT#
2 1
C RC714 1 2 1/20W_20K_5%_0201 C
RB521CM-30T2R_VMN2M-2
+1.8VALW_PCH 1
NPI@
CC702 GPP_B23 /SML1_ALERT# /PCHHOT#:
0.1U_6.3V_K_X5R_0201 CPUNSSC Clock Frequency
1K_0201_5% 1 @ 2 RC709 ESPI_CS# 0_0201_5% UC702 2
SPI_CS1# SPI_8M_CS1#
Rising edge of RSMRST#
RC746 1 @ 2 1 8 This strap has a 20 kohm ¡À 30% internal pull-down.
/CS VCC
1/20W_75K_5%_0201 2 @ 1 RC710 0 = 38.4 MHz clock (direct from crystal) (default)
SPI_SO 1/20W_15_5%_0201 1 2 RC741 SPI_16M_SO 2 7 SPI_16M_IO3 RC743 1 2 1/20W_15_5%_0201 SPI_IO3
DO(IO1) /HOLD(IO3) 1 = 19.2 MHz clock (derived from 38.4 MHz crystal)
SPI_IO2 1/20W_15_5%_0201 1 2 RC742 SPI_16M_IO2 3 6 SPI_16M_CLK RC744 1 2 1/20W_15_5%_0201 SPI_CLK Notes: 1. The internal pull-down is disabled after RSMRST# de-asserts.
/WP(IO2) CLK 2. When used as PCHHOT# and strap low, a 150K pull-up is needed
4 5 SPI_16M_SI RC745 1 2 1/20W_15_5%_0201 SPI_SI +3VALW_PCH to ensure it does not override the internal pull-down strap sampling.
GND DI(IO0) 3. This signal is in the primary well.
Glitch Free Requirements Site for cap or pull-down resistor only.
W25Q128JVSIQ_SO8 +3VALW_PCH
ESPI_RST# RC712 1 2 1/20W_75K_5%_0201

4
3
CC701 @1 2 0.033UC_10VC_KC_X5RC_0201
RPC703

2
2.2K_0404_4P2R_5%

G
PCH_SPI0_CLK RC713 1 2 100K_0402_5%
QC701A

1
2
PCH_SML1_CLK 1 6 PD_I2C2_SCL

S
PD_I2C2_SCL [41]

D
2N7002KDWH_SOT363-6

+3VALW_PCH RC725 1 2
0520
0_0402_5%
@
1/20W_4.7K_5%_0201 2 1 RC755 PCH_SPI0_CS0#

5
G
1/20W_150K_5%_0201 2 1 RC759 PCH_SPI0_CS1#
QC701B
+3V_SPI
1/20W_4.7K_5%_0201 1 2 RC756 PCH_SPI0_SI PCH_SML1_DATA 4 3 PD_I2C2_SDA

S
B PD_I2C2_SDA [41] B

D
100K_0201_5% 2 1 RC757 PCH_SPI0_IO2 2N7002KDWH_SOT363-6
1
100K_0201_5% 2 1 RC758 PCH_SPI0_IO3 CC703
0.1U_6.3V_K_X5R_0201
SPI0_MOSI(PCH_SPI_SI ): 0_0201_5% UC703 2 RC726 1 2
PCH_SPI0_CS0# RC740 1 @ 2 SPI_16M_CS0# 1 8 0_0402_5%
Rising edge of RSMRST# /CS VCC
External pull-up is required. Recommend 4.7 kohm pull up. SPI_SO @
This strap should sample HIGH. There should NOT be any onboard 1/20W_15_5%_0201 1 2 RC747 SPI_8M_SO 2 7 SPI_8M_IO3 RC748 1 2 1/20W_15_5%_0201 SPI_IO3
DO (IO1) IO3
device driving it to opposite direction during strap sampling. SPI_IO2 1/20W_15_5%_0201 1 2 RC749 SPI_8M_IO2 3 6 SPI_8M_CLK RC750 1 2 1/20W_15_5%_0201 SPI_CLK
IO2 CLK
SPI0_IO2 and SPI0_IO3: SPI_8M_SI SPI_SI
Rising edge of RSMRST# 4 5 RC751 1 2 1/20W_15_5%_0201
GND DI (IO0)
External pull-up is required.
Recommend 100K if pulled up to 3.3V or 75K if pulled up to 1.8V.
This strap should sample HIGH. There should NOT be any onboard W25Q64JVSSIQ_SO8
device driving it to opposite direction during strap sampling. 8M_ROM@

UC704
1 8
/CS VCC
0520 2 7
IO1 IO3
3 6
IO2 CLK
4 5
GND IO0

RC739 1 @ 2 0_0201_5% PCH_SPI0_CS0# W25R64JVSSIQ_SO8

[7,45] EC_SPI_CS0#

RC752 1 @ 2 0_0201_5%
[7,45] EC_SPI_CS0#
0526 Co-lay
PCH_SPI0_CS1# RC735 1 @ 2 0_0201_5% SPI_CS1#

SPI_SO RC733 1 @ 2 100K_0201_5%

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (SPI/SMB/SML/ESPI)
Date: Saturday, August 01, 2020 Sheet 7 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS
RPC801
UC1F PCH_I2C1_SDA_TP 1 4
TP PCH_I2C1_SCL_TP 2 3
6 OF 21

2.2K_0404_4P2R_5%
PCH_TP_INT# DC53 DR27 PCH_TP_INT# RC801 2 1 10K_0201_5%
[46] PCH_TP_INT# GPP_B18 DA51 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD
DW27
GPP_B18/GSPI0_MOSI GPP_D13/ISH_UART0_RXD ECLPM_BREAK [45]
DC49 DV25
PCH_BEEP DC50 GPP_B17/GSPI0_MISO GPP_D16/ISH_UART0_CTS#
DT25 FPR_RESET_R RC852 1 @ 2 0_0201_5% FPR_RESET +3VS
[31,45] PCH_BEEP PCH_WLAN_OFF# GPP_B14/SPKR/TIME_SYNC1/GSPI0_CS1# GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/IMGCLKOUT5 FPR_RESET [38]
DC52
[40] PCH_WLAN_OFF# GPP_B15/GSPI0_CS0#
DB45 1 @ 2 0_0201_5% FB_GC6_EN_R UART2_TXD 1 2 1/20W_49.9K_1%_0201
RC854 RC802
PCH_TS_INT#_R GPP_B6/ISH_I2C0_SCL GPU_EVENT# FB_GC6_EN_R [6,23,26] UART2_RXD
RC849 1 @ 2 0_0201_5% CY49 DB44 RC803 1 2 1/20W_49.9K_1%_0201
[33] PCH_TS_INT# PCH_TS_STOP_R GPP_B20/GSPI1_CLK GPP_B5/ISH_I2C0_SDA GPU_EVENT# [26]
RC848 1 @ 2 0_0201_5% CY53
[33] PCH_TS_STOP PCH_TS_RST_R GPP_B22/GSPI1_MOSI PXS_PWREN_R RC804
RC851 1 @ 2 0_0201_5% CY52 CY39 1 @ 2 0_0201_5%
D [33] PCH_TS_RST VCC_TS_ON GPP_B21/GSPI1_MISO GPP_B8/ISH_I2C1_SCL PXS_RST#_R RC805 PXS_PWREN [23] D
DA50 DB47 1 @ 2 0_0201_5%
[33] VCC_TS_ON GPP_B19/GSPI1_CS0# GPP_B7/ISH_I2C1_SDA PXS_RST# [26]
+3VS
DV21 DD47 DGPU_PWROK_R RC806 1 @ 2 0_0201_5%
DGPU_PWROK [23,58] RPC802
GPP_C9/UART0_TXD GPP_B10/I2C5_SCL/ISH_I2C2_SCL
DT21 DD44 RC814 1 @ 2 0_0201_5% 1.0VGS_1.25VGSPG PCH_I2C0_SDA 1 4
GPP_C8/UART0_RXD GPP_B9/I2C5_SDA/ISH_I2C2_SDA 1.0VGS_1.25VGSPG [57] PCH_I2C0_SCL
DR21 TS 2 3
GPP_C11/UART0_CTS#
DW21 DJ8
GPP_C10/UART0_RTS# GPP_E16/ISH_GP7
DR7 2.2K_0404_4P2R_5%
DV19 GPP_E15/ISH_GP6
DR24 PCH_TS_INT# RC850 2 1 10K_0201_5%
PCH_CAPS_LED# GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_D18/ISH_GP5
RC856 1 @ 2 0_0201_5% DT19 DU25
[46] CAPS_LED# PCH_Fnlk_LED# GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_D17/ISH_GP4
RC853 1 @ 2 0_0201_5% DR18 DV31
[46] Fnlk_LED# GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_D3/ISH_GP3/BK3/SBK3
RC855 1 @ 2 0_0201_5% DU19 DU31
[45,46] NUM_LED# GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_D2/ISH_GP2/BK2/SBK2
DT27
UART2_TXD DJ21 GPP_D1/ISH_GP1/BK1/SBK1
DV27 +3VS
UART2_RXD GPP_C21/UART2_TXD GPP_D0/ISH_GP0/BK0/SBK0
DG23
PCIE_WAKE#_WLAN_R DJ19 GPP_C20/UART2_RXD
DR51 GPP_RCOMP
[40] PCIE_WAKE#_WLAN_R

1
DF21 GPP_C23/UART2_CTS# GPP_RCOMP CAPS_LED# RC857 1 2 100K_0201_5%
GPP_C22/UART2_RTS#
DN33 RC811
PCH_I2C0_SCL DV18 GPP_T3
DT35
[33] PCH_I2C0_SCL GPP_C17/I2C0_SCL GPP_T2
1/20W_200_1%_0201
PCH_I2C0_SDA DW18 Fnlk_LED# 1 2 100K_0201_5%
TS [33] PCH_I2C0_SDA GPP_C16/I2C0_SDA
RC858
DG17

2
PCH_I2C1_SCL_TP DJ23 GPP_U5
DG19
[46] PCH_I2C1_SCL_TP PCH_I2C1_SDA_TP GPP_C19/I2C1_SCL GPP_U4 NUM_LED#
TP DT18 RC859 1 2 100K_0201_5%
[46] PCH_I2C1_SDA_TP GPP_C18/I2C1_SDA

DJ29
GPP_H5/I2C2_SCL
DJ31
GPP_H4/I2C2_SDA

DF29
GPP_H7/I2C3_SCL
DG29
GPP_H6/I2C3_SDA

DF25
GPP_H9/I2C4_SCL/CNV_MFUART2_TXD
DF27
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD
FPR_RESET_R RC891 1 @ 2 10K_0201_5%
TGLLAKE-U_BGA1449
require always floting, High>10ms reset active
@

C C

+3VS

PXS_PWREN_R RC807 1 OPT@ 2 10K_0201_5%

RC808 1 @ 2 10K_0201_5%

+3VS
+3VALW_PCH +3VS +3VS
PXS_RST#_R RC809 1 @ 2 10K_0201_5%
RC847 1 2 100K_0201_5% ECLPM_BREAK RC815 1 @ 2 1/20W_4.7K_5%_0201 PCH_BEEP RC816 1 @ 2 1/20W_4.7K_5%_0201 GPP_B18
RC810 1 OPT@ 2 10K_0201_5%
GPP_B14(PCH_BEEP): RC819 1 @ 2 1/20W_20K_5%_0201
Rising edge of PCH_PWROK
The strap has a 20 kohm ¡À 30% internal pull-down.
0 = Disable Top Swap mode. (Default) FB_GC6_EN_R
1 = Enable Top Swap mode. This inverts an address on access to SPI GPP_B18:Rising edge of PCH_PWROK RC812 1 @ 2 10K_0201_5%
and firmware hub, so the processor believes it fetches the alternate The signal has a weak internal pull-down.
boot block instead of the original boot-block. PCH will invert A16 0 = Disable No Reboot mode. (Default)
(default) for cycles going to the upper two 64-KB blocks in the FWH 1 = Enable No Reboot mode (PCH will disable the
or the appropriate address lines (A16, A17, or A18) as selected TCO Timer system reboot feature). This function is
BOARD ID in Top Swap Block size soft strap.
Notes:
useful when running ITP/XDP.
Notes:
+3VS

+1.8VALW_PCH 1. The internal pull-down is disabled after PCH_PWROK is high. 1. The internal pull-down is disabled after GPU_EVENT# RC813 1 OPT@ 2 10K_0201_5%
2. Software will not be able to clear the Top Swap bit until the system PCH_PWROK is high.
is rebooted. 2. This signal is in the primary well. RC817 1 @ 2 10K_0201_5%
3. The status of this strap is readable using the Top Swap bit
1

(Bus0, Device31, Function0, offset DCh, bit4).

100K_0201_5%
1

4. This signal is in the primary well.

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%
RC821

RC824

RC825

RC826

@
RC822

RC823

@ @ @ @ UMA@ PXS_RST# CC801 1 2 0.01U_6.3V_K_X7R_0201

2

B B
OPT@
2

BOARD_ID8 [7]
BOARD_ID9 [7] DGPU_PWROK_R
BOARD_ID10 [7] RC820 1 UMA@ 2 10K_0201_5%
BOARD_ID11 [7] Board ID Table 1: 3.3V Level Board ID Table 1: 1.8V Level
BOARD_ID12 [7]
BOARD_ID13 [7] 0 Non-FPR 00 Samsung ***
Board ID1 GPP_E1 No Use Board ID8 GPP_F11
1 FPR H 01 Micro ***
1
100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%
1

0 Non-TS 10 Hynix ***

RC837

Board ID2 GPP_E2 No Use Board ID9 GPP_F12

RC834

RC835

RC836

RC838

RC839

@ @ 1 TS L 11 No Use
@ @ OPT@
2

00 FHD *** 00 4G No Use

2

Board ID3 GPP_E10 Board ID10 GPP_F13

H 01 UHD No Use H 01 8G ***
BOARD ID
10 FHD HDR *** 10 12G ***
Board ID4 GPP_E11 Board ID11 GPP_F14
L 11 Reserved No Use L 11 16G ***
+3VALW_PCH
00 13" No Use 0 OPT
Board ID5 GPP_E12 Board ID12 GPP_F15 No Use
H 01 14" *** 1 UMA
Reserved
1

10 15" *** 10
100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

for
Board ID6 GPP_E13 Board ID13 GPP_F16
RC827

RC828

RC829

RC830

RC831

RC832

RC833

dGPU
@ @ @ 15@ @ @ L 11 17" No Use 11
@
0 Non-TPM
2

Board ID7 GPP_E17 No Use No Use

BOARD_ID1 [7] 1 TPM
BOARD_ID2 [7] Reserved
BOARD_ID3 [7] for
BOARD_ID4 [7] Project
A A
BOARD_ID5 [7]
BOARD_ID6 [7]
BOARD_ID7 [7]
100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%

100K_0201_5%
1

1
RC840

RC841

RC842

RC843

RC844

RC845

RC846

@ @ @ @ @ 15@ @
2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (UART/I2C/ISH/GSPI)
Date: Saturday, August 01, 2020 Sheet 8 of 61
5 4 3 2 1
 5 4 3 2 1

UC1I
9 OF 21

BT7 CV4 USB20_P10

BT8 PCIE12_TXP/SATA1_TXP USB2P_10
CY3 USB20_N10 USB20_P10 [40]
CE2 PCIE12_TXN/SATA1_TXN
PCIE12_RXP/SATA1_RXP
USB2N_10 USB20_N10 [40] BT
CE1 DD5
PCIE12_RXN/SATA1_RXN USB2P_9
DD4
SATA_PTX_DRX_P0 USB2N_9
BT9
[37] SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 PCIE11_TXP/SATA0_TXP
BV9 CW9
[37] SATA_PTX_DRX_N0 SATA_PRX_DTX_P0 PCIE11_TXN/SATA0_TXN USB2P_8
CF4 DA9
HDD [37]
[37]
SATA_PRX_DTX_P0
SATA_PRX_DTX_N0
SATA_PRX_DTX_N0 CF3 PCIE11_RXP/SATA0_RXP
PCIE11_RXN/SATA0_RXN
USB2N_8

DD1
BV7
PCIE10_TXP
USB2P_7
USB2N_7
DD2
USB20_P7
USB20_N7
[38]
[38]
FPR
BV8
D PCIE10_TXN USB20_P6 D
CG2 DA1
CG1 PCIE10_RXP
PCIE10_RXN
USB2P_6
USB2N_6
DA2 USB20_N6 USB20_P6
USB20_N6
[30]
[30]
Card reader
CC906 1 20.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_P9 BY7 DA12 USB20_P5
[40] PCIE_PTX_C_DRX_P9
CC905 1 20.1U_6.3V_K_X5R_0201 PCIE_PTX_DRX_N9 BY8 PCIE9_TXP USB2P_5
DA11 USB20_N5 USB20_P5 [33] Camera
WLAN [40]
[40]
PCIE_PTX_C_DRX_N9
PCIE_PRX_DTX_P9
PCIE_PRX_DTX_P9 CG5 PCIE9_TXN USB2N_5 USB20_N5 [33]
PCIE_PRX_DTX_N9 CG4 PCIE9_RXP
DC8 USB20_P4
[40] PCIE_PRX_DTX_N9 PCIE9_RXN USB2P_4
USB2N_4
DC7 USB20_N4 USB20_P4
USB20_N4
[30]
[30]
USB3.0 Normal
PCIE_PTX_DRX_P8 CB8
[37] PCIE_PTX_DRX_P8 PCIE_PTX_DRX_N8 PCIE8_TXP
CB7 DB4
[37] PCIE_PTX_DRX_N8 PCIE_PRX_DTX_P8 PCIE8_TXN USB2P_3
[37] PCIE_PRX_DTX_P8
CK5 DB3
PCIE_PRX_DTX_N8 CK4 PCIE8_RXP USB2N_3
[37] PCIE_PRX_DTX_N8 PCIE8_RXN
DA5
[37] PCIE_PTX_DRX_P7
PCIE_PTX_DRX_P7 CD9 USB2P_2
DA4
TBT_PCH_USB20_P2
TBT_PCH_USB20_N2
[44]
[44]
TBT
PCIE_PTX_DRX_N7 CD8 PCIE7_TXP USB2N_2
[37] PCIE_PTX_DRX_N7 PCIE_PRX_DTX_P7 CK1 PCIE7_TXN
DC11 USB20_P1
[37] PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 CK2 PCIE7_RXP USB2P_1
DC9 USB20_N1 USB20_P1 [30] USB3.0 AOU
SSD [37] PCIE_PRX_DTX_N7 PCIE7_RXN USB2N_1 USB20_N1 [30]
PCIE_PTX_DRX_P6 CG8 DP4
[37] PCIE_PTX_DRX_P6 PCIE_PTX_DRX_N6 CG7 PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0
DF41 SSD_PCIE_DET#
[37] PCIE_PTX_DRX_N6 PCIE_PRX_DTX_P6 CL4 PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM SSD_PCIE_DET# [37]
[37] PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 CL3 PCIE6_RXP
DD8 USB_OC0#
[37] PCIE_PRX_DTX_N6 PCIE6_RXN GPP_E9/USB_OC0# USB_OC3# USB_OC0# [30]
DJ45
PCIE_PTX_DRX_P5 GPP_A16/USB_OC3#/I2S4_SFRM USB_OC3# [41]
CJ8
[37] PCIE_PTX_DRX_P5 PCIE_PTX_DRX_N5 CJ7 PCIE5_TXP
DN6
[37] PCIE_PTX_DRX_N5 PCIE_PRX_DTX_P5 CN2 PCIE5_TXN GPP_E5/DEVSLP1
DG8
[37] PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 CN1 PCIE5_RXP GPP_E4/DEVSLP0
[37] PCIE_PRX_DTX_N5 PCIE5_RXN
DN29
GPP_H15/M2_SKT2_CFG3
CR8 DK29
PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2
CR7 DT31
PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1
CN5 DR32
PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0
CN4
PCIE4_RXN/USB31_4_RXN
DV9 PCIE_RCOMPN 1/20W_100_1%_0201 2 1 RC905
PCIE_RCOMP_P PCIE_RCOMPP
CU8 DT9
PCIE3_TXP/USB31_3_TXP PCIE_RCOMP_N
CU7
CT2 PCIE3_TXN/USB31_3_TXN
DC12 USB2_VBUSSENSE RC902 1 2 10K_0201_5%
CT1 PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE
DF1 USB2_ID RC901 1 2 10K_0201_5%
C
PCIE3_RXN/USB31_3_RXN USB_ID
DE1 USB2_COMP RC903 1 2 1/16W_113_1%_0402 C
USB30_TX_P2 USB2_COMP
CW8
[30] USB30_TX_P2 USB30_TX_N2 PCIE2_TXP/USB31_2_TXP
CW7 E3
[30] USB30_TX_N2 USB30_RX_P2 CU3 PCIE2_TXN/USB31_2_TXN RSVD_BSCAN
USB3.1 Normal PORT [30] USB30_RX_P2 USB30_RX_N2 CT4 PCIE2_RXP/USB31_2_RXP
[30] USB30_RX_N2 PCIE2_RXN/USB31_2_RXN
USB30_TX_P1 DA8
[30] USB30_TX_P1 USB30_TX_N1 PCIE1_TXP/USB31_1_TXP
DA7
[30] USB30_TX_N1 USB30_RX_P1 CV2 PCIE1_TXN/USB31_1_TXN
USB3.1 PORT [30] USB30_RX_P1 USB30_RX_N1 CV1 PCIE1_RXP/USB31_1_RXP
AOU [30] USB30_RX_N1 PCIE1_RXN/USB31_1_RXN

TGLLAKE-U_BGA1449
@

UC1H
8 OF 21

PCIE4_CTX_C_GRX_P3 OPT@ 0.22U_0201_6.3V6-K 1 2 CC904 PCIE4_CTX_GRX_P3 P5 V5 PCIE4_CTX_GRX_P1 CC910 2 1 0.22U_0201_6.3V6-K OPT@ PCIE4_CTX_C_GRX_P1
PCIE4_CTX_C_GRX_N3 PCIE4_CTX_GRX_N3 PCIE4_TX_P_3 PCIE4_TX_P_1 PCIE4_CTX_GRX_N1 PCIE4_CTX_C_GRX_N1
OPT@ 0.22U_0201_6.3V6-K 1 2 CC903 P7 V7 CC909 2 1 0.22U_0201_6.3V6-K OPT@
PCIE4_CRX_GTX_P3 N1 PCIE4_TX_N_3 PCIE4_TX_N_1
T1 PCIE4_CRX_GTX_P1
PCIE4_CRX_GTX_N3 N2 PCIE4_RX_P_3 PCIE4_RX_P_1
T2 PCIE4_CRX_GTX_N1
GPU PCIE4_RX_N_3 PCIE4_RX_N_1
PCIE4_CTX_C_GRX_P2 OPT@ 0.22U_0201_6.3V6-K 1 2 CC902 PCIE4_CTX_GRX_P2 T5 Y5 PCIE4_CTX_GRX_P0 CC908 2 1 0.22U_0201_6.3V6-K OPT@ PCIE4_CTX_C_GRX_P0
PCIE4_CTX_C_GRX_N2 PCIE4_CTX_GRX_N2 PCIE4_TX_P_2 PCIE4_TX_P_0 PCIE4_CTX_GRX_N0 PCIE4_CTX_C_GRX_N0
OPT@ 0.22U_0201_6.3V6-K 1 2 CC901 T7 Y7 CC907 2 1 0.22U_0201_6.3V6-K OPT@
PCIE4_CRX_GTX_P2 R1 PCIE4_TX_N_2 PCIE4_TX_N_0
V1 PCIE4_CRX_GTX_P0
PCIE4_CRX_GTX_N2 R2 PCIE4_RX_P_2 PCIE4_RX_P_0
V2 PCIE4_CRX_GTX_N0
PCIE4_RX_N_2 PCIE4_RX_N_0
Y12 PCIE4_RCOMP_P
PCIE4_RCOMP_P PCIE4_RCOMP_N RC908
V12 1 2
PCIE4_RCOMP_N
2.2K_0402_1%
B B

TGLLAKE-U_BGA1449
@

[20] PCIE4_CRX_GTX_N[0..3]

[20] PCIE4_CRX_GTX_P[0..3]

[20] PCIE4_CTX_C_GRX_N[0..3]

[20] PCIE4_CTX_C_GRX_P[0..3]

+3VALW_PCH
A A
RC904 1 2 10K_0201_5% USB_OC0#

+1.8VALW_PCH

RC906 1 2 10K_0201_5% USB_OC3#

RC907 1 2 10K_0201_5% SSD_PCIE_DET#

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (PCIE/SATA/USB3/USB2)
Date: Thursday, May 28, 2020 Sheet 9 of 61
5 4 3 2 1
 5 4 3 2 1

UC1J +1.8VALW_PCH
10 OF 21
CNVI_RGI_RSP RC1000 1 @ 2 1/20W_20K_5%_0201

D22 DK47 CNV_WT_D1P CNVI_BRI_RSP RC1001 1 @ 2 1/20W_20K_5%_0201

B22 CSI_F_DP_1 CNVI_WT_D1P
DM47 CNV_WT_D1N CNV_WT_D1P [40]
CSI_F_DN_1 CNVI_WT_D1N CNV_WT_D0P CNV_WT_D1N [40]
E22 DN49
CSI_F_DP_0 CNVI_WT_D0P CNV_WT_D0N CNV_WT_D0P [40]
D20 DR49
CSI_F_DN_0 CNVI_WT_D0N CNV_WT_CLKP CNV_WT_D0N [40]
A20 DN45
B20 CSI_F_CLK_P CNVI_WT_CLKP
DN47 CNV_WT_CLKN CNV_WT_CLKP [40]
CSI_F_CLK_N CNVI_WT_CLKN CNV_WT_CLKN [40] +1.8VALW_PCH
B18 DU43 CNV_WR_D1P
CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P CNV_WR_D1N CNV_WR_D1P [40]
A18 DV43 RC1002 1 @ 2 1/20W_4.7K_1%_0201
D CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_WR_D0P CNV_WR_D1N [40] D
D18 DR44
CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P CNV_WR_D0N CNV_WR_D0P [40] CNVI_BRI_DT_R
E18 DT43 RC1004 1 @ 2 1/20W_20K_5%_0201
CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N CNV_WR_CLKP CNV_WR_D0N [40]
C16 DV44
CSI_E_CLK_P CNVI_WR_CLKP CNV_WR_CLKN CNV_WR_CLKP [40]
D16 DW44
CSI_E_CLK_N CNVI_WR_CLKN CNV_WR_CLKN [40]
D15 DN51 CNV_WT_RCOMP RC1005 1 2 150_0402_1%
CSI_C_DP_2 CNVI_WT_RCOMP
GPP_F0 /CNV_BRI_DT /UART0_RTS#
E15 XTAL Frequency Selection, Rising edge of RSMRST#
A15 CSI_C_DN_2
DJ13 CNVI_RGI_RSP
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNVI_RGI_DT_R CNVI_RGI_RSP [40] This strap has a 20 kohm ¡À 30% internal pull-down.
B15 DG13 RC1006 1 @ 2 0_0201_5% This strap should not be pulled high since 24 MHz crystal is not
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD CNVI_BRI_RSP CNVI_RGI_DT [40]
DF15 supported on the PCH.
GPP_F1/CNV_BRI_RSP/UART0_RXD CNVI_BRI_DT_R CNVI_BRI_RSP [40]
L18 DF17 RC1007 1 @ 2 0_0201_5%
N18 CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS# CNVI_BRI_DT [40] 0 = 38.4 MHz (default)
L20 CSI_C_DN_1
DJ10 1 = 24 MHz
N20 CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ
DV15 Notes:
G20 CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING
DK10 1. The internal pull-down is disabled after RSMRST# de-asserts.
H20 CSI_C_CLK_P GPP_F4/CNV_RF_RESET# 2. This signal is in the primary well.
CSI_C_CLK_N

H16
CSI_B_DP_1
G16
CSI_B_DN_1
G18
CSI_B_DP_0
H18
CSI_B_DN_0
L16
CSI_B_CLK_P +1.8VALW_PCH
N16 Pull up at CONN
CSI_B_CLK_N

G14 CNVI_RGI_DT_R RC1009 2 @ 1 100K_0201_5%

CSI_B_DP_2
H14
CSI_B_DN_2
L14 RC1011 1 @ 2 1/20W_4.7K_5%_0201
CSI_B_DP_3
N14
CSI_B_DN_3

RC1008 1 2 150_0402_1% CSI_COMP K14

CSI_RCOMP
GPP_F2 /CNV_RGI_DT /UART0_TXD:
DK25 M.2 CNVI MODES, Rising edge of RSMRST#
GPP_H23/IMGCLKOUT4
DM25 A weak external pull-up is required.
GPP_H22/IMGCLKOUT3
DN25 0 = Integrated CNVi enabled.
GPP_H21/IMGCLKOUT2
DJ25 1 = Integrated CNVi disabled.
GPP_H20/IMGCLKOUT1
DR30
GPP_D4/IMGCLKOUT_0/BK4/SBK4 Note:
C
When a RF companion chip is connected to the PCH CNVi interface, C
the device internal pulldown resistor will pull the strap low to
TGLLAKE-U_BGA1449
enable CNVi interface.
@

CLKOUT_PCIE_P /N [6,5,4, 2,1] = Support up to PCIe Gen3

CLKOUT_PCIE_P /N [3, 0] = Support up to PCIe Gen4
UC1K
11 OF 21
TP4505
BW1 DU14 GPU_CLKREQ#_N 1 @
CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6#
BW2 DF23
CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5#
DG25
GPP_H10/SRCCLKREQ4# +3VS
CB2 DT24
CB1 CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3#
DT30 WLAN_CLKREQ#
CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2# SSD_CLKREQ# WLAN_CLKREQ# [40] WLAN_CLKREQ#
DV30 RC1012 1 @ 2 10K_0201_5%
GPP_D6/SRCCLKREQ1# GPU_CLKREQ# SSD_CLKREQ# [37]
DW30
GPP_D5/SRCCLKREQ0# GPU_CLKREQ# [20] SSD_CLKREQ#
BW4 RC1013 1 2 10K_0201_5%
BW5 CLKOUT_PCIE_P4
DM1 XTAL_PCH_38P4M_OUT
CLKOUT_PCIE_N4 XTAL_OUT
DL1 XTAL_PCH_38P4M_IN GPU_CLKREQ# RC1014 1 2 10K_0201_5%
XTAL_IN
CL7
CLKOUT_PCIE_P3
CL8 DW41 SUSCLK
CLKOUT_PCIE_N3 GPD8/SUSCLK SUSCLK [40]
CLK_PCIE_WLAN CB4 DT47 RTC_X2
[40] CLK_PCIE_WLAN CLK_PCIE_WLAN# CLKOUT_PCIE_P2 RTCX2 RTC_X1
CB5 DR47
[40] CLK_PCIE_WLAN# CLKOUT_PCIE_N2 RTCX1
CLK_PCIE_SSD BY4 DN37 RTC_RST# SUSCLK RC1015 1 @ 2 1K_0201_5%
[37] CLK_PCIE_SSD CLK_PCIE_SSD# CLKOUT_PCIE_P1 RTCRST# SRTC_RST#
[37] CLK_PCIE_SSD# BY3 DK37
CLKOUT_PCIE_N1 SRTCRST#
CLK_PCIE_GPU CN7
[20] CLK_PCIE_GPU CLK_PCIE_GPU# CLKOUT_PCIE_P0
CN8
[20] CLK_PCIE_GPU# CLKOUT_PCIE_N0
B B
1/20W_60.4_1%_02012 1 RC1016 XCLK_BIASREF DJ5
XCLK_BIASREF

TGLLAKE-U_BGA1449
@

XTAL_PCH_38P4M_IN RC1017 2 @ 1 0_0402_5% XTAL_PCH_38P4M_IN_R

EXC24CH500U_4P VCCRTC
4 3 1
4 3

CC1000
1 2 1U_6.3V_K_X5R_0201
1 2
RC1018 1 2 20K_0402_1% 2 RTC_RST# RC1019 2 @ 1 0_0402_5%
LC1000EMC_NS@ EC_RTC_RST# [45]
RTC_X1 RC1020 1 2 20K_0402_1% SRTC_RST#
XTAL_PCH_38P4M_OUT RC1021 2 @ 1 0_0402_5% XTAL_PCH_38P4M_OUT_R
RTC_X2 1
10M_0402_5% CC1001
RC1022 1 2 1U_6.3V_K_X5R_0201
2 CMOS RESET
YC1000
XTAL_PCH_38P4M_IN_R RC1023 1 2 200K_0402_1% XTAL_PCH_38P4M_OUT_R 1 2 SAVE CMOS = PU (Default)
32.768KHZ 9PF 202934-PG14
CLEAR CMOS = PD
YC1001
1 1

A
4
NC1 OSC2
3 CC1002
9P_50V_C_COG_0402
CC1003
9P_50V_C_COG_0402
ME RESET A
1
OSC1 NC2
2 2 2 SAVE ME = PU (Default)
1 1
CLEAR ME = PD
CC1004 CC1005
38.4MHZ_10PF_7R38400001
10P_0402_50V8J 10P_0402_50V8J
2 2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (CSI/EMMC/CNVI/CLK)
Date: Saturday, August 01, 2020 Sheet 10 of 61
5 4 3 2 1
 5 4 3 2 1

UC1L
12 OF 21

PM_SLP_SUS# DV49 BM9

[45] PM_SLP_SUS# SLP_SUS# PROCPWRGD PBTN_OUT#_R
DK41
1PM_SLP_S5# DM43 GPD3/PWRBTN#
DN41 PBTN_OUT#_R [45]
TP1103
@ BATLOW#
PM_SLP_S4# DJ41 GPD10/SLP_S5# GPD0/BATLOW#
DK43 AC_PRESENT_R
[41,45,47] PM_SLP_S4# PM_SLP_S3# GPD5/SLP_S4# GPD1/ACPRESENT AC_PRESENT_R [45]
DJ43
[45] PM_SLP_S3# 1PM_SLP_A# DR41 GPD4/SLP_S3#
CW40 PCH_PD_INT#_R
TP1101 @ RC1135 1 @ 2 0_0201_5%
PM_SLP_WLAN# GPD6/SLP_A# GPP_B11/PMCALERT# CPU_C10_GATE# PCH_PD_INT# [41]
TP1102 @ 1 DT44 DN27
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# [47]
DG31
PM_SLP_S0# DD42 GPP_H3/SX_EXIT_HOLDOFF#
[45,47] PM_SLP_S0# DN39 GPP_B12/SLP_S0#
DK39
SLP_LAN# WAKE# PCIE_WAKE# [40]
PCH_RSMRST#_R DM35 DM41 PCH_LAN_WAKE#
SYS_RESET# DD10 RSMRST# GPD2/LAN_WAKE#
DT41 PCH_CNVI_EN# 1
D PLT_RST#_R SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON D
RC1101 1 @ 2 0_0201_5% DD41 TP4503 @
[26,37,40,42,45] PLT_RST# GPP_B13/PLTRST# BB_TBT_PERST#
DN43
PCH_DPWROK_R GPD7 BB_TBT_PERST# [42]
DK35
SYS_PWROK_R DSW_PWROK VCCST_OVERRIDE_R
RC1106 1 @ 2 0_0201_5% DF10 CE5 RC1102 1 @ 2 0_0201_5%
[45] SYS_PWROK PCH_PWROK_R SYS_PWROK VCCSTPWRGOOD_TCSS VCCST_PWRGD_R VCCST_OVERRIDE [47]
RC1105 1 @ 2 0_0201_5% DN35 BP8 RC1103 1 2 1/20W_60.4_1%_0201
[45] PCH_PWROK PCH_PWROK VCCST_PWRGD VCCSTPWRGOOD_TCSS EC_VCCST_PWRGD [45]
BP9 RC1104 1 @ 2 0_0201_5%
VCCST_OVERRIDE
INTRUDER# DM37
SPI VCCIOSEL DT49 INTRUDER#
DR12 VCCST_OVERRIDE
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE#
DW12
GPP_F21/EXT_PWR_GATE2#

TGLLAKE-U_BGA1449
@

DSW_PWROK and RSMRST# are always separate power good signals

+VCCPDSW_3P3
PCH_DPWROK RC1107 1 @ 2 0_0201_5% PCH_DPWROK_R
[45] PCH_DPWROK
RC1108 2 1 100K_0201_5% PCIE_WAKE# RC1116 1 2 1K_0201_5%
AC_PRESENT_R RC1122 1 2 100K_0402_5%
EC_RSMRST# RC1109 1 @ 2 0_0201_5% PCH_RSMRST#_R BATLOW# RC1120 1 2 100K_0201_5%
[45] EC_RSMRST#
RC1110 2 1 100K_0201_5% PBTN_OUT#_R RC1119 1 @ 2 100K_0201_5%
PCH_LAN_WAKE# RC1117 1 2 10K_0201_5%

C +3VALW C

RC1111 2 @ 1 4.7K_0402_5% SPI VCCIOSEL +VCCST_CPU

RC1112 2 1 4.7K_0402_5% EC_VCCST_PWRGD RC1113 1 2 1K_0402_5%

Glitch Free Requirements:

CAD NOTE: Pull-up resistor is required if a device is monitoring SLP_S0#
INPUT3VSEL: 3V SELECT STRAP before RSMRST# de-assertion +3VS
LOW-> 3.3V +/-5% 100K for 3.3V Signaling Mode SYS_RESET#
HIGH->3.0V +/-5% 75K for 1.8V Signaling Mode RC1114 1 2 10K_0201_5%
+3VALW_PCH
+3VALW_PCH

PM_SLP_S0# RC1115 1 2 100K_0201_5%

PCH_PD_INT# RC1137 1 2 10K_0201_5%

CPU_C10_GATE# RC1123 1 @ 2 1/20W_20K_5%_0201

VCCRTC
Glitch Free Requirements:
RC1118 1 2 1M_0402_5% INTRUDER# Cap or pull-down resistor is required

Option 1:Cap Implementation

330 nF for 3.3v Ramp Rate from 5-50ms
RC1121 1 @ 2 1M_0402_5%
33 nF for 3.3V Ramp Rate Less than 5ms

CC1100 2 1 0.1U_6.3V_K_X5R_0201 Option 2:Pull-down Resistor Implementation

100K for 3.3V Signaling Mode
75K for 1.8V Signaling Mode

SPI Voltage Configuration: PM_SLP_SUS#

The VCCSPI voltage (3.3V or 1.8V) is selected via a hard strap RC1126 1 2 100K_0201_5%
on the INTRUDER#.
B This strap sets the SPI interface signaling voltage at the rising edge PCH_PWROK B
of RTCRST#. Designers should strap this pin to match the expected RC1124 1 2 100K_0402_5%
PM_SLP_S3# RC1128 1 2 100K_0201_5%
interface operational voltage for their target SPI device as follows. SYS_PWROK RC1125 1 2 100K_0402_5%
0 = SPI interface operation voltage is 3.3V
(ground through a 10kohm resistor) PM_SLP_S4# RC1129 1 2 100K_0201_5% VCCST_OVERRIDE RC1127 1 2 100K_0402_5%
1 = SPI interface operation voltage is 1.8V
(pulled up with 1 Mohm to VCCRTC)
@
PCH_PWROK_R CC1111 2 1 0.1U_6.3V_K_X5R_0201

@
SYS_PWROK_R CC1110 2 1 0.1U_6.3V_K_X5R_0201

PLT_RST# RC1134 1 2 100K_0201_5% BB_TBT_PERST# RC1132 1 2 1/20W_20K_5%_0201

GPD7(BB_TBT_PERST#): Rising edge of DSW_PWROK

PM_SLP_WLAN# RC1138 1 2 100K_0201_5% This signal has a 20K+-30% internal pull-down.
This strap should sample LOW. There should NOT be
any on-board device driving it to opposite direction
during strap sampling
Notes:
1. The internal pull-down is disabled after DSW_PWROK is high.
2. This signal is in the DSW well

1000P_0201_50V7-K 1 2 CC1107 EMC_NS@ PCH_RSMRST#_R

1000P_0201_50V7-K 1 2 CC1109 EMC_NS@ PCH_DPWROK_R

FOR EMC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (MANAGEMENT-CFG)
Date: Saturday, August 01, 2020 Sheet 11 of 61
5 4 3 2 1
 5 4 3 2 1

UC1M
13 OF 21
+VCCIN +VCCIN

A24 G32
VCCIN_1 VCCIN_66
A26 H24
VCCIN_2 VCCIN_67
A29 H26
VCCIN_3 VCCIN_68
+VCCST_CPU A30 H30
VCCIN_4 VCCIN_69
A33 H32
RC1201 1 2 100_0402_1% VR_SVID_DATA A35 VCCIN_5 VCCIN_70
J1
VCCIN_6 VCCIN_71
AY39 J2
RC1202 1 2 56_0402_5% VR_SVID_ALERT_N B24 VCCIN_7 VCCIN_72
K1
VCCIN_8 VCCIN_73
B26 K2
RC1203 1 @ 2 1/16W_45.3_1%_0402 VR_SVID_CLK B29 VCCIN_9 VCCIN_74
K24
VCCIN_10 VCCIN_75
B30 K26
VCCIN_11 VCCIN_76
CAD NOTE: B33 K30
VCCIN_12 VCCIN_77
Alert signal must be routed between Clk and Data signals B35 K32
D VCCIN_13 VCCIN_78 D
to minimize Cross-Talk. BA10 L24
VCCIN_14 VCCIN_79
BA40 L26
VCCIN_15 VCCIN_80
BB39 L30
VCCIN_16 VCCIN_81
BB9 L32
VCCIN_17 VCCIN_82
BC10 N24
VCCIN_18 VCCIN_83
BC40 N26
VCCIN_19 VCCIN_84
BD39 N30
VCCIN_20 VCCIN_85
BD9 N32
VCCIN_21 VCCIN_86
BE10 P24
VCCIN_22 VCCIN_87
BE40 P26
VCCIN_23 VCCIN_88
BF9 P28
VCCIN_24 VCCIN_89
BG10 P30
VCCIN_25 VCCIN_90
+VCCSTG_OUT_LGC CAD NOTE: +VCCSTG_TERM BG40 P32
FOR SIDEBAND TERMINATION. VCCIN_26 VCCIN_91
BH12 T21
VCCIN_27 VCCIN_92
@ BH39 T23
VCCIN_28 VCCIN_93
RC1206 2 1 0_0402_5% BH9 T25
VCCIN_29 VCCIN_94
BJ10 T27
VCCIN_30 VCCIN_95
BJ40 T31
VCCIN_31 VCCIN_96
BK39 U23
+1.2V +VDDQ_CPU VCCIN_32 VCCIN_97
BL10 U27
VCCIN_33 VCCIN_98
BL40 U29
VCCIN_34 VCCIN_99
0.16A BM39 U31
VCCIN_35 VCCIN_100
BN40 U33
VCCIN_36 VCCIN_101
BP12 V23
VCCIN_37 VCCIN_102
BP39 V25
VCCIN_38 VCCIN_103
BR10 V27
VCCIN_39 VCCIN_104
BR40 V29 +VCCIN
VCCIN_40 VCCIN_105
BT12 V31
VCCIN_41 VCCIN_106
BT39 V33

2
VCCIN_42 VCCIN_107
BU10 W22
VCCIN_43 VCCIN_108
+VCCSTG_OUT_R +VCCSTG_OUT1 BU40 W24 RC1204
VCCIN_44 VCCIN_109
BV12 W28 1/20W_100_1%_0201
VCCIN_45 VCCIN_110
BY12 W32
VCCIN_46 VCCIN_111
RC1210 1 @ 2 0_0201_5% CA10

1
CB12 VCCIN_47
R38 VCCIN_SENSE
VCCIN_48 VCCIN_SENSE VSSIN_SENSE VCCIN_SENSE [56]
D24 R37
D26 VCCIN_49 VSSIN_SENSE VSSIN_SENSE [56]
Place as close to BGA as possible VCCIN_50 VR_SVID_DATA
C D29 M12 C
VCCIN_51 VIDSOUT VR_SVID_DATA [56]

2
D30 M11 VR_SVID_CLK
VCCIN_52 VIDSCK VR_SVID_ALRT_N VR_SVID_CLK [56]
D33 P12 RC1205
D35 VCCIN_53 VIDALERT# VR_SVID_ALERT_N [56]
VCCIN_54
1/20W_100_1%_0201
E24
VCCIN_55
E26

1
VCCIN_56
E27
VCCIN_57
E29
VCCIN_58
E30
VCCIN_59
+VCCSTG_OUT_R +VCCSTG_OUT2 E32
VCCIN_60
E33
VCCIN_61
G2
VCCIN_62
RC1207 1 @ 2 0_0201_5% G24
VCCIN_63
G26
VCCIN_64
G30
VCCIN_65
Place as close to BGA as possible
TGLLAKE-U_BGA1449
@

Short VCCSTG BGA pins AF12 and AD12 with the

UC1O VCCSTG_OUT BGA pins AN10,AM9, AG10 and AF9
together on the board.
15 OF 21
+VDDQ_CPU
+VCCST_CPU +VCCSTG_CPU
AA39 AF9 +VCCSTG_OUT_R
VDD2_1 VCCSTG_OUT_1
AB40 AF12
VDD2_2 VCCSTG_1 +VCCSTG_OUT2
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

AC39 AD12
VDD2_3 VCCSTG_2
1 1 1 1 AD40 +VCCSTG_OUT1
VDD2_4
CC1212

CC1213

CC1214

CC1215

AD51 AN10
VDD2_5 VCCSTG_OUT_2
AD52 AM9
VDD2_6 VCCSTG_OUT_3
AE39 AG10 1 TP1201 @
2 2 2 2 VDD2_7 VCCSTG_OUT_4
AF40
VDD2_8
@ @ AG39 V15 INTERNAL RAIL. +VCCIO_OUT
B VDD2_9 VCCIO_OUT B
AH40
VDD2_10
AJ39 M9 +VCCSTG_OUT_LGC
VDD2_11 VCCSTG_OUT_LGC
AK40
VDD2_12
AK51 BT2 +VCCST_CPU
VDD2_13 VCCST_1
AK52 BT1
VDD2_14 VCCST_2
AL39 BT4
VDD2_15 VCCST_3
AM40
VDD2_16
AN39 BP2
VDD2_17 VCCSTG_3 +VCCSTG_CPU
AP40 BP1
VDD2_18 VCCSTG_4
AR39 BP4
VDD2_19 VCCSTG_5
AT52
VDD2_20
+VCCIN +VCCIN +1.8VALW +1.8VALW AU40
VDD2_21
AW40
VDD2_22
AW51
VDD2_23
AW52
VDD2_24
BD51
VDD2_25
0.1U_6.3V_K_X5R_0201

BD52
CC1200
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

1 1 1 VDD2_26
CC1216 EMC@
100P_0402_50V8J

CC1217 EMC@
12P_50V_F_COG_0402

CC1218

BK51
CC1201

CC1202

CC1204

VDD2_27
BK52
1

VDD2_28
@ BV51
2 2 2 VDD2_29
BV52
VDD2_30
CA40
2

VDD2_31
EMC@

CC40
@ @ @ VDD2_32
CC49
VDD2_33
CC50
VDD2_34
CE40
VDD2_35
CG40
VDD2_36
CH39
VDD2_37
+VCCIN_AUX +VCCIN_AUX +3VALW CJ40
VDD2_38
CL40
VDD2_39
Place as close as possible to the CN40
VDD2_40
package (less than 5mm). CP47
VDD2_41
CR40
VDD2_42
D50
VDD2_43
E51
VDD2_44
F49
VDD2_45
T51
VDD2_46
A T52 A
VDD2_47

TGLLAKE-U_BGA1449
@

S550-IIL Title
Security Classification LC Future Center Secret Data
Issued Date 2018/12/04 Deciphered Date 2018/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (CPU PWR1)
Date: Saturday, August 01, 2020 Sheet 12 of 61
5 4 3 2 1
 5 4 3 2 1

+1.8VALW +1.8VALW_PCH

+VCCIN_AUX UC1N
RC1310 1 @ 2 0_5%_0603
14 OF 21
+VCCPRIM_1P8

AB12 CY18
VCCIN_AUX_1 VCCPRIM_1P8_1
+VCCPDSW_3P3 AC10 CY20
+3VALW VCCIN_AUX_2 VCCPRIM_1P8_2
0.003A AE10 CY24
VCCIN_AUX_3 VCCPRIM_1P8_3
AK2 CY26
VCCIN_AUX_4 VCCPRIM_1P8_4
@ AR10 DA18
VCCIN_AUX_5 VCCPRIM_1P8_5
RC1302 2 1 0_0402_5% AT12 DA20
D VCCIN_AUX_6 VCCPRIM_1P8_6 D
AU10 DA22
VCCIN_AUX_7 VCCPRIM_1P8_7
AW10 DA24
VCCIN_AUX_8 VCCPRIM_1P8_8
BV1 DA26
VCCIN_AUX_9 VCCPRIM_1P8_9
RC1318 1 2 0_0402_5% BV39 DC18
+3VALW_PCH VCCIN_AUX_10 VCCPRIM_1P8_10

1U_6.3V_M_X5R_0201
1 BW40 DC20
VCCIN_AUX_11 VCCPRIM_1P8_11

CC1301
@ BY39 DC22
VCCIN_AUX_12 VCCPRIM_1P8_12
CC1 DC24
VCCIN_AUX_13 VCCPRIM_1P8_13
@ CD12 DC26
2 VCCIN_AUX_14 VCCPRIM_1P8_14
CF10 DD20
VCCIN_AUX_15 VCCPRIM_1P8_15
CG12 DD22
VCCIN_AUX_16 VCCPRIM_1P8_16
CH10 DV22
VCCIN_AUX_17 VCCPRIM_1P8_17
CJ1
VCCIN_AUX_18
CJ12 DA35
VCCIN_AUX_19 VCCPRIM_3P3_1 +VCCPRIM_3P3
CK10 DC28
VCCIN_AUX_20 VCCPRIM_3P3_2
CL12 DC30
VCCIN_AUX_21 VCCPRIM_3P3_3
CM10 DD30
VCCIN_AUX_22 VCCPRIM_3P3_4
CP1
VCCIN_AUX_23
CP10 DV34
+3VALW_PCH VCCIN_AUX_24 DCPRTC +VCCRTCEXT
+VCCPRIM_3P3 0.202A CR12
VCCIN_AUX_25
@ CT10 DV46 INTERNAL RAIL. +VCCLDOSTD_OUT_0P85
VCCIN_AUX_26 VCCLDOSTD_0P85
RC1317 2 1 0_0402_5% CU12
VCCIN_AUX_27
CY1 DV16
VCCIN_AUX_28 VCCA_CLKLDO_1P8_1
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
1 1 AK1 DC15 0.165A
VCCIN_AUX_29 VCCA_CLKLDO_1P8_2 +VCCA_CLKLDO_1P8
CC1302

CC1303
VCCIN_AUX_VSSSENSE AV9 DV28 INTERNAL RAIL. SHORT TO CPU SIDE VCCPLL.
VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE VCCDPHY_1P24 +VCCDPHY_1P24
@ @ AT9
2 2 VCCIN_AUX_VCCSENSE
DD38 INTERNAL RAIL. +VCCDSW_1P05
VCCDSW_1P05
1.05V / 0.76V 0.2A DD17
+VNN_BYPASS VCC_VNNEXT_1P05_1
DD18 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET_1
BR4 FET TO VCCST_CPU & VCCSTG_CPU
VCC1P05_OUT_FET_2
+V1.05A_BYPASS 1.05V 0.2A DA15 BT5 +VCC1.05_OUT_FET
VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET_3
DA17
VCC_V1P05EXT_1P05_2
DA31 INTERNAL RAIL.
GPPC_B2_VRALERT_N DB39 VCCPRIM1P05_OUT_PCH_1
DC33
[41] GPPC_B2_VRALERT_N GPP_B2/VRALERT# VCCPRIM1P05_OUT_PCH_2 +VCC1.05_OUT_PCH
DV12 DC31 +VCC1.05_OUT_PCH
GPP_F22/VNN_CTRL VCCPRIM1P05_OUT_PCH_3
+VCCPGPPR_3P3_1P8 DT12
+1.8VALW_PCH GPP_F23/V1P05_CTRL
DC35 VCCRTC
C @ VCCIN_AUX_VID0 DB37 VCCRTC
DD37 C
[47,55] VCCIN_AUX_VID0 VCCIN_AUX_VID1 GPP_B0/CORE_VID0 VCCDSW_3P3 +VCCPDSW_3P3
RC1307 2 1 0_0402_5% DB38 DA28 +VCCPGPPR_3P3_1P8
[47,55] VCCIN_AUX_VID1 GPP_B1/CORE_VID1 VCCPGPPR
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1 1 CY31 +VCCPRIM_3P3
VCCPRIM_3P3_5
CC1306

CC1307

CY33
VCCPRIM_3P3_6
CV39
VCCPRIM_1P8_18 +VCCPRIM_1P8
@ @
2 2 AP12
RSVD_1

TGLLAKE-U_BGA1449
@

+VCCIN_AUX

+VCCPRIM_1P8 VCCPRIM_1P8A:1.3A

1
+1.8VALW_PCH
RC1304
1.3A 100_0402_1%
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1 1 1
CC1308

CC1309

CC1310

VCCIN_AUX_VCCSENSE
[55] VCCIN_AUX_VCCSENSE VCCIN_AUX_VSSSENSE
@ @ @
2 2 2 [55] VCCIN_AUX_VSSSENSE
1

RC1306
100_0402_1%
2

+1.8VALW_PCH +VCCA_CLKLDO_1P8

@
RC1315 2 1 0_0402_5% 0.165A
B B
1

RC1313
0_0402_5%
2

@
47U_6.3V_M_X5R_0805_H1.25

1U_6.3V_M_X5R_0201

1 1 +VCCLDOSTD_OUT_0P85 +VCCDSW_1P05 +VCCDPHY_1P24 +V1.05A_BYPASS +VNN_BYPASS

+3VALW_PCH
CC1314

CC1315

1U_6.3V_M_X5R_0201

@ 1 1 1
1

1
2 2
CC1311
2.2U_0402_6.3V6M

CC1312

CC1313
4.7U_0402_6.3V6M

100K_0201_5%

1K_0402_5%
RC1309

RC1311
RC1312
RB521CM-30T2R_VMN2M-2 20K_0201_5%
2 2 2
2

2
@ DC1301 2 1 GPPC_B2_VRALERT_N
[6,45,55] H_PROCHOT#
@
2 1

RC1314 1 @ 2 0_0402_5%

VCCRTC
+VCCRTCEXT
0.1U_0402_10V7K

PDG: VCCRTCEXT
1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201

1 1 1 0.1u_0402 *1
CC1316

CC1317

CC1318

Place on Primary/Secondary Side

as close as possible to the package
A A
2 2 2 edge (less than 3mm).

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (CPU PWR2)
Date: Sunday, August 02, 2020 Sheet 13 of 61
5 4 3 2 1
 5 4 3 2 1

VDDQ_CPU :

PDG:1 , 2x47uF 0603, 8x10uF 0402, 8x1uF 0402,

vs
C750 ITL: 6x10uF 0402, 3x1uF 0402,10x1uF 0201,Reserve 8x10uF 0402,7x1uF 0201
S550 ITL 6x10uF 0402, 9x1uF 0201 Reserve 11x10uF 0402, 7x1uF 0201

D D

+VDDQ_CPU +VDDQ_CPU +VDDQ_CPU

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CC1402

CC1406

CC1407

CC1413

CC1415

CC1419

CC1421

CC1422

CC1423

CC1426

CC1427

CC1405

CC1414

CC1418

CC1420

CC1424

CC1425

CC1428

CC1429

CC1430

CC1432

CC1433

CC1434
@
@ @ @ @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

@ @ @

@ @ @ @ @ @ @

Place on the back side of the SoC

C C
+VDDQ_CPU
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 1 1 1 1 1 1 1 1
CC1401

CC1408

CC1409

CC1410

CC1411

CC1412

CC1435

CC1436

CC1437

2 2 2 2 @2 2 2 2 2 2 CC1438
@

Place on the same side of the SoC

B B

EMC CAPS refer CRB

+VCCIN +VCCIN_AUX
0.1U_6.3V_K_X5R_0201

1 1 1 1 1
CC1403 EMC@
100P_0402_50V8J

CC1416 EMC@
12P_50V_F_COG_0402

CC1417

CC1439 EMC@
100P_0402_50V8J

CC1440 EMC@
12P_50V_F_COG_0402

0.1U_6.3V_K_X5R_0201
1
CC1404

2 2 2 2 2

2
EMC@

EMC@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (PCH PWR)
Date: Monday, June 01, 2020 Sheet 14 of 61
5 4 3 2 1
 5 4 3 2 1

UC1R
UC1P UC1Q 18 OF 21
16 OF 21 17 OF 21

TP4509@ 1 DP53 K34

VSS_2 VSS_46
A27 B19 BY44 CY44 DR11 K48
VSS_223 VSS_289 VSS_109 VSS_169 VSS_3 VSS_47
A32 B2 1 BY45 CY45 DR16 K5
VSS_224 VSS_290 VSS_110 VSS_170 VSS_4 VSS_48
A45 B23 @TP4514 BY47 CY47 DR22 L22
VSS_225 VSS_291 VSS_111 VSS_171 VSS_5 VSS_49
1 A49 B27 BY49 CY5 DR28 L28
VSS_226 VSS_292 VSS_112 VSS_172 VSS_6 VSS_50
TP4513@ AA41 B32 BY9 D27 DR34 L34
VSS_227 VSS_293 VSS_113 VSS_173 VSS_7 VSS_51
AA48 B36 C13 D32 DR40 L39
D VSS_228 VSS_294 VSS_114 VSS_174 VSS_8 VSS_52 D
AB5 B39 C19 D36 DR46 L41
VSS_229 VSS_295 VSS_115 VSS_175 VSS_9 VSS_53
AB7 B42 C23 D42 DT4 L42
VSS_230 VSS_296 VSS_116 VSS_176 VSS_10 VSS_54
AB8 B48 CA48 D49 DT50 L44
VSS_231 VSS_297 VSS_117 VSS_177 VSS_11 VSS_55
AC44 B52 1 CB41 D5 DU11 L45
VSS_232 VSS_298 VSS_118 VSS_178 VSS_12 VSS_56
AC49 B8 @ TP4512 CC10 DA30 DU16 L47
VSS_233 VSS_299 VSS_119 VSS_179 VSS_13 VSS_57
AD4 BA48 CC3 DA33 DU22 L49
VSS_234 VSS_300 VSS_120 VSS_180 VSS_14 VSS_58
AD48 BA53 CC5 DA53 DU28 M1
VSS_235 VSS_301 VSS_121 VSS_181 VSS_15 VSS_59
AD8 BB4 CD44 DC17 DU34 M2
VSS_236 VSS_302 VSS_122 VSS_182 VSS_16 VSS_60
AF4 BB8 CD48 DD15 DU40 M50
VSS_237 VSS_303 VSS_123 VSS_183 VSS_17 VSS_61
AF8 BC1 CD7 DD24 DU46 N22
VSS_238 VSS_304 VSS_124 VSS_184 VSS_18 VSS_62
AG41 BC2 CE49 DD26 TP4510@ 1 DV1 N28
VSS_239 VSS_305 VSS_125 VSS_185 VSS_19 VSS_63
AG42 BD12 CG48 DD28 DV40 N34
VSS_240 VSS_306 VSS_126 VSS_186 VSS_20 VSS_64
AG44 BD4 CG51 DD31 TP4508@ 1 DV52 N39
VSS_241 VSS_307 VSS_127 VSS_187 VSS_21 VSS_65
AG45 BD48 CG52 DD33 DW51 N41
VSS_242 VSS_308 VSS_128 VSS_188 VSS_22 VSS_66
AG47 BD8 CG9 DD35 E13 N48
VSS_243 VSS_309 VSS_129 VSS_189 VSS_23 VSS_67
AG48 BF39 CH41 DD39 E19 P11
VSS_244 VSS_310 VSS_130 VSS_190 VSS_24 VSS_68
AG53 BF4 CH42 DD45 E35 P14
VSS_245 VSS_311 VSS_131 VSS_191 VSS_25 VSS_69
AH4 BF41 CH44 DD51 E48 P16
VSS_246 VSS_312 VSS_132 VSS_192 VSS_26 VSS_70
AH8 BF42 CH45 DD52 G22 P18
VSS_247 VSS_313 VSS_133 VSS_193 VSS_27 VSS_71
AK12 BF44 CH47 DE3 G28 P20
VSS_248 VSS_314 VSS_134 VSS_194 VSS_28 VSS_72
AK4 BF45 CJ3 DE5 G34 P22
VSS_249 VSS_315 VSS_135 VSS_195 VSS_29 VSS_73
AK48 BF47 CJ5 DF19 G39 P33
VSS_250 VSS_316 VSS_136 VSS_196 VSS_30 VSS_74
AK5 BF5 CJ9 DF37 G48 P35
VSS_251 VSS_317 VSS_137 VSS_197 VSS_31 VSS_75
AK7 BF7 CK39 DG15 G51 P4
VSS_252 VSS_318 VSS_138 VSS_198 VSS_32 VSS_76
AK8 BF8 CK48 DG21 G52 P49
VSS_253 VSS_319 VSS_139 VSS_199 VSS_33 VSS_77
AM1 BG48 CK53 DG27 H12 P8
VSS_254 VSS_320 VSS_140 VSS_200 VSS_34 VSS_78
AM2 BG53 CL9 DG33 H22 R39
VSS_255 VSS_321 VSS_141 VSS_201 VSS_35 VSS_79
AM4 BH1 CN12 DG39 H28 R44
VSS_256 VSS_322 VSS_142 VSS_202 VSS_36 VSS_80
AM8 BH2 CN48 DG45 H34 T19
VSS_257 VSS_323 VSS_143 VSS_203 VSS_37 VSS_81
AN41 BH4 CN51 DG5 H8 T29
VSS_258 VSS_324 VSS_144 VSS_204 VSS_38 VSS_82
AN42 BH8 CN52 DG53 J39 T33
VSS_259 VSS_325 VSS_145 VSS_205 VSS_39 VSS_83
AN44 BK12 CN9 DG6 J49 T4
VSS_260 VSS_326 VSS_146 VSS_206 VSS_40 VSS_84
AN45 BK4 CP3 DJ1 K16 T48
VSS_261 VSS_327 VSS_147 VSS_207 VSS_41 VSS_85
AN47 BK48 CP41 DJ2 K18 T8
VSS_262 VSS_328 VSS_148 VSS_208 VSS_42 VSS_86
AN48 BK8 CP42 DJ4 K20 U19
VSS_263 VSS_329 VSS_149 VSS_209 VSS_43 VSS_87
AN53 BL49 CP44 DK51 K22 U25
VSS_264 VSS_330 VSS_150 VSS_210 VSS_44 VSS_88
AP4 BM1 CP45 DL3 K28 U39
VSS_265 VSS_331 VSS_151 VSS_211 VSS_45 VSS_89
C AP8 BM4 CP5 DL5 U49 C
VSS_266 VSS_332 VSS_152 VSS_212 VSS_90
AT4 BM41 CR48 DM10 V19
VSS_267 VSS_333 VSS_153 VSS_213 VSS_91
AT48 BM42 CR53 DM15 V4
VSS_268 VSS_334 VSS_154 VSS_214 VSS_92
AT51 BM44 CR9 DM21 V8
VSS_269 VSS_335 VSS_155 VSS_215 VSS_93
AT8 BM45 CT5 DM27 W1
VSS_270 VSS_336 VSS_156 VSS_216 VSS_94
AV12 BM47 CU4 DM33 W16
VSS_271 VSS_337 VSS_157 VSS_217 VSS_95
AV39 BM8 CU9 DM39 W26
VSS_272 VSS_338 VSS_158 VSS_218 VSS_96
AV4 BN48 CV10 DM4 W30
VSS_273 VSS_339 VSS_159 VSS_219 VSS_97
AV5 BP41 CV48 DM45 W39
VSS_274 VSS_340 VSS_160 VSS_220 VSS_98
AV7 BP49 CV5 DN1 W41
VSS_275 VSS_341 VSS_161 VSS_221 VSS_99
AV8 BP5 CV51 DN2 W42
VSS_276 VSS_342 VSS_162 VSS_222 VSS_100
AW1 BP50 CV52 W44
VSS_277 VSS_343 VSS_163 VSS_101
AW2 BP7 CY17 W45
VSS_278 VSS_344 VSS_164 VSS_102
AW48 BT44 CY22 W47
VSS_279 VSS_345 VSS_165 VSS_103
AY4 BT48 CY35 W48
VSS_280 VSS_346 VSS_166 VSS_104
AY41 BU49 CY41 Y4
VSS_281 VSS_347 VSS_167 VSS_105
AY42 BV3 CY42 Y49
VSS_282 VSS_348 VSS_168 VSS_106
AY44 BV48 Y50
VSS_283 VSS_349 VSS_107
AY45 BV5 Y8
VSS_284 VSS_350 VSS_108
AY47 BW10 TGLLAKE-U_BGA1449
VSS_285 VSS_351
AY8 BY41 @
VSS_286 VSS_352
AY9 BY42 TGLLAKE-U_BGA1449
VSS_287 VSS_353
B13 @
VSS_288

TGLLAKE-U_BGA1449
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. MCP (VSS)
Date: Thursday, May 28, 2020 Sheet 15 of 61
5 4 3 2 1
 5 4 3 2 1

+VCCIO_OUT

UC1S

RC212

RC213

RC214

RC219

RC218

RC215

RC216

RC217

RC220
19 OF 21

DF53 C53

2
RSVD_19 RSVD_23
T35
RSVD_24
DF52 E53
RSVD_20 RSVD_25
@ CF39
RSVD_26
DT52 U35
PCH_IST_TP_1 RSVD_27
DU53 F53

1
PCH_IST_TP_0 RSVD_28
B53
RSVD_29
1K_0201_5% DF50 AP9

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%

1K_0201_5%
RSVD_21 RSVD_30
DF49 A52
D RSVD_22 RSVD_31 D
CY30 BF12
RSVD_TP_25 RSVD_TP_28
CY15 V21
RSVD_TP_26 RSVD_TP_29
W20
RSVD_TP_30
D4 U37
CPU_CFG14 RSVD_TP_27 RSVD_TP_31
CD39
CPU_CFG11 A6 RSVD_TP_32
U21
CPU_CFG10 A4 IST_TP_1 RSVD_TP_33
CB39
CPU_CFG9 IST_TP_0 RSVD_32
BB12
CPU_CFG7 RSVD_TP_34
W37
CPU_CFG4 RSVD_TP_35
AY12
CPU_CFG3 RSVD_TP_36
W38
CPU_CFG2 RSVD_TP_37
U38
CPU_CFG1 RSVD_TP_38
CY28
RSVD_TP_39
RC222

RC223

RC224

RC229

RC228

RC225

RC226

RC227

RC230
TGLLAKE-U_BGA1449
@
2

2
@ @ @ @ @ @ @ @
1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

1K_0201_5%1

C UC1T C
20 OF 21

T15 A51
CPU_CFG14 V17 CFG_15 RSVD_TP_7
B51
CFG_14 RSVD_TP_8
U15
CFG_13
K11 C1
CPU_CFG11 K12 CFG_12 RSVD_TP_9
D2
CPU_CFG10 K9 CFG_11 RSVD_TP_10
CPU_CFG9 T17 CFG_10
CP39
CFG_9 RSVD_TP_11
K7 CU40
CPU_CFG7 H7 CFG_8 RSVD_TP_12
AK9
CFG_7 RSVD_12
************************************** K8
CFG_6
Change CFG Follow PDG_V1.0---Xukun1220 H9 AH9
CPU_CFG4 E6 CFG_5 RSVD_13
************************************** CPU_CFG3 CFG_4
H5 DW6
CPU_CFG2 E9 CFG_3 RSVD_14
DV6
CPU_CFG1 D9 CFG_2 RSVD_15
Pin Name Strap Description Configuration Default Value CFG_1
E7 DV4
CFG_0 RSVD_TP_13
DW3
RSVD_TP_14
CFG[0] RSVD None RC1603 2 1 1/20W_49.9_1%_0201 B5
CFG_RCOMP
DU1
RSVD_TP_15
U17 DT2
CFG_17 RSVD_TP_16
CFG[3:1] RSVD Pull-up to VCCIO 1Kohm H11
CFG_16
DW2
RSVD_TP_17
Y1 DV2
BPM#_3 RSVD_TP_18
eDP enable strap Pull-up to VCCIO / Pull-down M4
BPM#_2
CFG[4] 1 = Disabled Platform design dependent 1Kohm AB4 E1
BPM#_1 RSVD_TP_19
0 = Enabled Y2 F1
BPM#_0 RSVD_TP_20

A3 AB2
RSVD_6 RSVD_16
CFG[6:5] RSVD None B3
RSVD_7
DR1
RSVD_TP_21
RC1604 1 2 2.2K_0402_1% AR2 DR2
TCP0_MBIAS_RCOMP RSVD_TP_22
PEG deferred link training Pull-up to VCCIO / Pull-down AL10
RSVD_TP_2
CFG[7] 1 = (default) PEG Trainimmediately Platform design dependent 1Kohm AM12 DR53
RSVD_TP_3 RSVD_TP_23
following RESET# de-assertion. AH12 DW5
B RSVD_TP_4 RSVD_TP_24 B
0 = PEG Wait for BIOS for training. AJ10
RSVD_TP_5
AR1 DV51
RSVD_TP_6 VSS_1
DW52
TP_3
CFG[8] RSVD None BN10 DV53
RSVD_8 TP_4
BM12 W34
RSVD_9 RSVD_17
DD13 V35
RSVD_10 RSVD_18
CFG[11:9] RSVD Pull-up to VCCIO 1Kohm DF13
RSVD_11
D52
SKTOCC#

CFG[13:12] RSVD None

TGLLAKE-U_BGA1449
PEG60 Lane Reversal Pull-up to VCCIO / Pull-down @
CFG[14] 1 = Normal(Default) Platform design dependent 1Kohm
0 = Reversed

CFG[17:15] RSVD None

CPU PCIe Gen4 Bifurcation and Lane Reversal Mapping

CFG Signals Lanes

Bifurcation
CFG [14] 0 1 2 3
1x4 1 0 1 2 3
1x4(Reversed) 0 3 2 1 0
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Debug
Date: Thursday, May 28, 2020 Sheet 16 of 61
5 4 3 2 1
 5 4 3 2 1

+0.6VS

8Gb SDP DDRA_DQ[0..63] CHANNELA@

RPD2
[5] DDRA_DQ[0..63]
16Gb DDP DDRA_MA0
UD1
DDRA_DQ5 [5] DDRA_DQS#[0..7]
DDRA_DQS#[0..7]
DDRA_MA0
UD2
DDRA_DQ41 CHANNELA@
+1.2V DDRA_MA16_RAS#
DDRA_ODT0
1 8
P3 G2 P3 G2 2 7
[5] DDRA_MA0 DDRA_MA1 A0 DQL0 DDRA_DQ0 DDRA_DQS[0..7] DDRA_MA1 A0 DQL0 DDRA_DQ46 DDRA_CKE0
P7 F7 P7 F7 1 1/16W_36_5%_4P2R_0404 3 6
[5] DDRA_MA1 DDRA_MA2 A1 DQL1 DDRA_DQ7 [5] DDRA_DQS[0..7] DDRA_MA2 A1 DQL1 DDRA_DQ43 DDRA_CLK0# DDRA_CLK0_R DDRA_CS0#
R3 H3 R3 H3 2 3 1 2 CD1766 4 5
[5] DDRA_MA2 DDRA_MA3 A2 DQL2 DDRA_DQ3 DDRA_MA3 A2 DQL2 DDRA_DQ44 DDRA_CLK0
N7 H7 N7 H7 CD1767 1 4 0.01U_25V_K_X5R_0201
[5] DDRA_MA3 DDRA_MA4 N3 A3 DQL3 H2 DDRA_DQ6 DDRA_MA4 N3 A3 DQL3 H2 DDRA_DQ42 Byte 5 3.3P_50V_C_NPO_0201 1/16W_36_5%_8P4R_0804
[5] DDRA_MA4 DDRA_MA5 P8 A4 DQL4
H8 DDRA_DQ2 Byte 0 DDRA_MA5 P8 A4 DQL4
H8 DDRA_DQ45 2 RPD12
CHANNELA@
[5] DDRA_MA5 DDRA_MA6 A5 DQL5 DDRA_DQ4 DDRA_MA6 A5 DQL5 DDRA_DQ40 @
P2 J3 P2 J3
[5] DDRA_MA6 DDRA_MA7 A6 DQL6 DDRA_DQ1 DDRA_MA7 A6 DQL6 DDRA_DQ47
R8 J7 R8 J7 CHANNELA@
[5] DDRA_MA7 DDRA_MA8 A7 DQL7 DDRA_DQ16 DDRA_MA8 A7 DQL7 DDRA_DQ57
R2 A3 R2 A3 RPD4
[5] DDRA_MA8 DDRA_MA9 A8 DQU0 DDRA_DQ21 DDRA_MA9 A8 DQU0 DDRA_DQ62 +1.2V
R7 B8 R7 B8
[5] DDRA_MA9 DDRA_MA10 A9 DQU1 DDRA_DQ22 DDRA_MA10 A9 DQU1 DDRA_DQ61 DDRA_MA11
[5] DDRA_MA10
M3 C3 M3 C3 1 8
DDRA_MA11 T2 A10/AP DQU2
C7 DDRA_DQ23 DDRA_MA11 T2 A10/AP DQU2
C7 DDRA_DQ58 DDRA_PAR 2 7
[5] DDRA_MA11 DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ18 Byte 2 DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ56 Byte 7 DDRA_ALERT#
RD1703 1 21/20W_49.9_1%_0201 DDRA_MA2 3 6
[5] DDRA_MA12 DDRA_MA13 A12/BC_N DQU4 DDRA_DQ19 DDRA_MA13 A12/BC_N DQU4 DDRA_DQ60 DDRA_MA0
T8 C8 T8 C8 CHANNELA@ 4 5
[5] DDRA_MA13 A13 DQU5 DDRA_DQ20 A13 DQU5 DDRA_DQ63 +0.6VS
D3 D3
D DDRA_MA14_WE# L2 DQU6
D7 DDRA_DQ17 DDRA_MA14_WE# L2 DQU6
D7 DDRA_DQ59 D
[5] DDRA_MA14_WE# CHANNELA@ 1/16W_36_5%_8P4R_0804
DDRA_MA15_CAS# M8 WE_N/A14 DQU7 DDRA_MA15_CAS# M8 WE_N/A14 DQU7
RPD1
[5] DDRA_MA15_CAS# DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V RPD6
[5] DDRA_MA16_RAS# RAS_N/A16
D1 RAS_N/A16
D1 DDRA_MA14_WE# 1 8 CHANNELA@
DDRA_CLK0# K8 VDD1
J1 DDRA_CLK0# K8 VDD1
J1 DDRA_ACT# 2 7 DDRA_BG0 1 8
[5] DDRA_CLK0# DDRA_CLK0 CK_C VDD2 DDRA_CLK0 CK_C VDD2 DDRA_MA12 DDRA_BA0
[5] DDRA_CLK0
K7 L1 K7 L1 3 6 2 7
CK_T VDD3 R1 CK_T VDD3 R1 DDRA_MA10 4 5 DDRA_MA6 3 6
DDRA_CKE0 K2 VDD4 B3 DDRA_CKE0 K2 VDD4 B3 DDRA_MA8 4 5
[5] DDRA_CKE0 CKE VDD5 CKE VDD5
G7 G7 1/16W_36_5%_8P4R_0804
DDRA_DQS#0 F3 VDD6 B9 DDRA_DQS#5 F3 VDD6 B9 1/16W_36_5%_8P4R_0804
DDRA_DQS0 G3 DQSL_C VDD7
J9 DDRA_DQS5 G3 DQSL_C VDD7
J9 DDRA_BG1_R DDRA_MA9
RD1754 1 DDPA@ 2 0_0201_5% DDRA_BG1 [5] RD1721 1CHANNELA@
21/20W_36_1%_0201
DDRA_DQS#2 A7 DQSL_T VDD8
L9 DDRA_DQS#7 A7 DQSL_T VDD8
L9
+1.2V DDRA_DQS2 B7 DQSU_C VDD9 T9 +1.2V DDRA_DQS7 B7 DQSU_C VDD9 T9 DDRA_BG1_R
RD1755 1 SDPA@ 2 0_0201_5% RD1734 1 21/20W_36_1%_0201 RPD8
DQSU_T VDD10 DQSU_T VDD10 DDRA_MA1 1 4
DDPA@
DDRA_DM1 DDRA_DM3 DDRA_MA4
RD1709 1 @ 2 0_0201_5% E2 A1 RD1710 1 @ 2 0_0201_5% E2 A1 2 3
DDRA_DM0 NF/UDM_N/UDBI_N VDDQ1 DDRA_DM2 NF/UDM_N/UDBI_N VDDQ1
RD1712 1 @ 2 0_0201_5% E7 C1 RD1713 1 @ 2 0_0201_5% E7 C1
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 RPD11 1/16W_36_5%_4P2R_0404
DDRA_BA0 N2 VDDQ3 F2 DDRA_BA0 N2 VDDQ3 F2 DDRA_MA15_CAS# 1 4
[5] DDRA_BA0 DDRA_BA1 BA0 VDDQ4 DDRA_BA1 BA0 VDDQ4 UD1_DDRA_UZQ DDRA_MA5 CHANNELA@
N8 J2 N8 J2 RD1756 1 SDPA@ 2 0_0201_5% 2 3 RPD9
[5] DDRA_BA1 BA1 VDDQ5 BA1 VDDQ5
F8 F8 CHANNELA@
DDRA_ACT# VDDQ6 DDRA_ACT# VDDQ6 DDRA_MA3
[5] DDRA_ACT#
L3 J8 L3 J8 RD1718 1 DDPA@ 2 1/20W_240_1%_0201 1/16W_36_5%_4P2R_0404 1 8
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_MA7 2 7
[5] DDRA_CS0# DDRA_ALERT# CS_N VDDQ8 DDRA_ALERT# CS_N VDDQ8 CHANNELA@ DDRA_MA13
P9 D9 P9 D9 3 6
[5] DDRA_ALERT# ALERT_N VDDQ9 G9 +2.5V_DDR ALERT_N VDDQ9 G9 +2.5V_DDR UD2_DDRA_UZQ DDRA_BA1
RD1757 1 SDPA@ 2 0_0201_5% 4 5
DDRA_BG0 M2 VDDQ10 DDRA_BG0 M2 VDDQ10
[5] DDRA_BG0 BG0 BG0
B1 B1 RD1723 1 DDPA@ 2 1/20W_240_1%_0201 1/16W_36_5%_8P4R_0804
DDRA_ODT0 K3 VPP1
R9 DDRA_ODT0 K3 VPP1
R9
[5] DDRA_ODT0 ODT VPP2 ODT VPP2
DDRA_PAR +VREF_CA_SA DDRA_PAR +VREF_CA_SA UD3_DDRA_UZQ

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
T3 M1 T3 M1 RD1758 1 SDPA@ 2 0_0201_5%
[5] DDRA_PAR PAR VREFCA PAR VREFCA
1 1 1 1 CHANNELA@ 1 1
TEN_UD1 2 10K_0201_5% TEN_UD2

CD1703

CD1704

CD1707

CD1708
1
RD1728 2 10K_0201_5% N9 E1 CD1701 CD1702
1
RD1730 N9 E1 RD1731 1 DDPA@ 2 1/20W_240_1%_0201
TEN VSS1 K1 TEN VSS1 K1
CHANNELA@ 1 1

0.047U_0402_25V7K
CPU_DRAMRST# P1 VSS2 N1 CPU_DRAMRST# P1 VSS2 N1

0.1U_25V_K_X5R_0201
@ CD1705 CD1706
[5,18] CPU_DRAMRST# RESET_N VSS3
T1 2 2 2 2 RESET_N VSS3
T1 2 2 UD4_DDRA_UZQ
RD1759 1 SDPA@ 2 0_0201_5%

CHANNELA@

CHANNELA@

CHANNELA@

0.047U_0402_25V7K

0.1U_25V_K_X5R_0201
F1 VSS4 B2 F1 VSS4 B2 @

CHANNELA@

CHANNELA@

CHANNELA@
H1 VSSQ1 VSS5 G8 H1 VSSQ1 VSS5 G8 2 2 RD1735 1 DDPA@ 2 1/20W_240_1%_0201
VSSQ2 VSS6 VSSQ2 VSS6
1 A2 K9 A2 K9
D2 VSSQ3 VSS8 D2 VSSQ3 VSS8
CD1775 1
0.1U_6.3V_K_X5R_0201

E3 VSSQ4 T7 1 DDPA@ 2 E3 VSSQ4 T7 1 2

@ CD1776

0.1U_6.3V_K_X5R_0201
A8 VSSQ5 VSS7 A8 VSSQ5 VSS7
RD1760 0_0201_5% @ RD1761 DDPA@0_0201_5%
2 D8 VSSQ6 D8 VSSQ6
E8 VSSQ7 M9 DDRA_BG1_R 2 E8 VSSQ7 M9 DDRA_BG1_R
C9 VSSQ8 VSS9 C9 VSSQ8 VSS9
H9 VSSQ9
E9 UD1_DDRA_UZQ H9 VSSQ9
E9 UD2_DDRA_UZQ
VSSQ10 VSS10 F9 VSSQ10 VSS10 F9
ZQ ZQ
1

1
+1.2V
CHANNELA@

RD1740 RD1741

CHANNELA@
K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201 K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201
@ @
C C
2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD1709

CD1710

CD1711

CD1712

CD1713

CD1714

CD1715

CD1716

CD1717

CD1718

CD1719

CD1720

CD1721

CD1722

CD1723

CD1724

CD1777

CD1778

CD1779

CD1780
CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
@

@ @ @ @

UD3
UD4
DDRA_MA0 P3 G2 DDRA_DQ11 +1.2V
DDRA_MA1 P7 A0 DQL0 F7 DDRA_DQ15 DDRA_MA0 P3 G2 DDRA_DQ34
DDRA_MA2 R3 A1 DQL1
H3 DDRA_DQ9 DDRA_MA1 P7 A0 DQL0
F7 DDRA_DQ39
DDRA_MA3 N7 A2 DQL2 H7 DDRA_DQ13 DDRA_MA2 R3 A1 DQL1 H3 DDRA_DQ32
DDRA_MA4 N3 A3 DQL3 H2 DDRA_DQ10 DDRA_MA3 N7 A2 DQL2 H7 DDRA_DQ37
DDRA_MA5 P8 A4 DQL4
H8 DDRA_DQ14 Byte 1 DDRA_MA4 N3 A3 DQL3
H2 DDRA_DQ35
DDRA_MA6 A5 DQL5 DDRA_DQ8 DDRA_MA5 A4 DQL4 DDRA_DQ38 Byte 4

CD1725

10U 6.3V M X5R 0402

CD1726

10U 6.3V M X5R 0402

CD1727

10U 6.3V M X5R 0402

CD1728

10U 6.3V M X5R 0402

CD1729

10U 6.3V M X5R 0402

CD1730

10U 6.3V M X5R 0402

CD1731

10U 6.3V M X5R 0402

CD1732

10U 6.3V M X5R 0402

P2 J3 P8 H8
DDRA_MA7 R8 A6 DQL6 J7 DDRA_DQ12 DDRA_MA6 P2 A5 DQL5 J3 DDRA_DQ33
DDRA_MA8 R2 A7 DQL7 A3 DDRA_DQ25 DDRA_MA7 R8 A6 DQL6 J7 DDRA_DQ36
DDRA_MA9 A8 DQU0 DDRA_DQ31 DDRA_MA8 A7 DQL7 DDRA_DQ55 1 1 1 1 1 1 1 1
R7 B8 R2 A3
DDRA_MA10 M3 A9 DQU1 C3 DDRA_DQ26 DDRA_MA9 R7 A8 DQU0 B8 DDRA_DQ53
DDRA_MA11 T2 A10/AP DQU2 C7 DDRA_DQ27 DDRA_MA10 M3 A9 DQU1 C3 DDRA_DQ54

@
@
Byte 3

CHANNELA@

CHANNELA@

CHANNELA@
DDRA_MA12 M7 A11 DQU3
C2 DDRA_DQ28 DDRA_MA11 T2 A10/AP DQU2
C7 DDRA_DQ52 2 2 2 2 2 2 2 2
DDRA_MA13 T8 A12/BC_N DQU4 C8 DDRA_DQ29 DDRA_MA12 M7 A11 DQU3 C2 DDRA_DQ50
A13 DQU5 D3 DDRA_DQ30 DDRA_MA13 T8 A12/BC_N DQU4 C8 DDRA_DQ51 Byte 6
DDRA_MA14_WE# L2 DQU6 D7 DDRA_DQ24 A13 DQU5 D3 DDRA_DQ49
DDRA_MA15_CAS# WE_N/A14 DQU7 DDRA_MA14_WE# DQU6 DDRA_DQ48 @ @ @
M8 L2 D7
DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V DDRA_MA15_CAS# M8 WE_N/A14 DQU7
RAS_N/A16
D1 DDRA_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRA_CLK0# K8 VDD1 J1 RAS_N/A16 D1
DDRA_CLK0 K7 CK_C VDD2 L1 DDRA_CLK0# K8 VDD1 J1
CK_T VDD3
R1 DDRA_CLK0 K7 CK_C VDD2
L1
DDRA_CKE0 K2 VDD4 B3 CK_T VDD3 R1 +0.6VS
CKE VDD5
G7 DDRA_CKE0 K2 VDD4
B3
DDRA_DQS#1 F3 VDD6 B9 CKE VDD5 G7 +0.6VS
DDRA_DQS1 G3 DQSL_C VDD7
J9 DDRA_DQS#4 F3 VDD6
B9 +1.2V
DDRA_DQS#3 A7 DQSL_T VDD8 L9 DDRA_DQS4 G3 DQSL_C VDD7 J9
DDRA_DQS3 B7 DQSU_C VDD9 T9 DDRA_DQS#6 A7 DQSL_T VDD8 L9
+1.2V DQSU_T VDD10 +1.2V DDRA_DQS6 B7 DQSU_C VDD9 T9
DDRA_DM5 DQSU_T VDD10
RD1742 1 @ 2 0_0201_5% E2 A1
DDRA_DM4 NF/UDM_N/UDBI_N VDDQ1 DDRA_DM7

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
RD1743 1 @ 2 0_0201_5% E7 C1 RD1744 1 @ 2 0_0201_5% E2 A1
NF/LDM_N/LDBI_N VDDQ2
G1 DDRA_DM6 NF/UDM_N/UDBI_N VDDQ1
RD1745 1 @ 2 0_0201_5% E7 C1 1 1 1 1 1 1 1 1
DDRA_BA0 VDDQ3 NF/LDM_N/LDBI_N VDDQ2

CD1733

CD1734

CD1735

CD1736

CD1737

CD1738

CD1739

CD1740
B N2 F2 G1 B
DDRA_BA1 N8 BA0 VDDQ4 J2 DDRA_BA0 N2 VDDQ3 F2
BA1 VDDQ5 DDRA_BA1 BA0 VDDQ4
1 1 1 1
F8 N8 J2

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@

CHANNELA@
DDRA_ACT# L3 VDDQ6 J8 BA1 VDDQ5 F8 2 2 2 2 2 2 2 2 CD1741 CD1742 CD1743 CD1744
DDRA_CS0# L7 ACT_N VDDQ7 A9 DDRA_ACT# L3 VDDQ6 J8 22P_0201_258J 22P_0201_258J 22P_0201_258J 22P_0201_258J
DDRA_ALERT# P9 CS_N VDDQ8 D9 DDRA_CS0# L7 ACT_N VDDQ7 A9 2 2 2 2
RF_NS@ RF_NS@ RF_NS@ RF_NS@
ALERT_N VDDQ9
G9 +2.5V_DDR DDRA_ALERT# P9 CS_N VDDQ8
D9
DDRA_BG0 M2 VDDQ10 ALERT_N VDDQ9 G9 +2.5V_DDR
BG0
B1 DDRA_BG0 M2 VDDQ10
DDRA_ODT0 K3 VPP1
R9 BG0
B1
ODT VPP2 DDRA_ODT0 K3 VPP1 R9
DDRA_PAR +VREF_CA_SA ODT VPP2
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

T3 M1
PAR VREFCA DDRA_PAR T3 M1 +VREF_CA_SA +0.6VS

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
CHANNELA@ 1 1
CHANNELA@

2 10K_0201_5% TEN_UD3 PAR VREFCA

CD1749

CD1750

RD1746 1 N9 E1 CHANNELA@ 1 1 (1OuF_0603_6.3V) *2

TEN VSS1
2 10K_0201_5% TEN_UD4

CD1753

CD1754
K1 1 1 RD1747 1 N9 E1 Place around the DRAMs
CPU_DRAMRST# P1 VSS2
N1 TEN VSS1
K1
CD1747 CD1748 1 1
RESET_N VSS3
T1 2 2 CPU_DRAMRST# P1 VSS2
N1 CD1751
Memory :
0.047U_0402_25V7K

0.1U_25V_K_X5R_0201

VSS4 RESET_N VSS3 CD1752 @

1 F1 B2 @ T1 2 2
CHANNELA@

CHANNELA@

0.047U_0402_25V7K

0.1U_25V_K_X5R_0201
H1 VSSQ1 VSS5 G8 2 2 F1 VSS4 B2
1 @

CHANNELA@
CD1773 VSSQ2 VSS6 VSSQ1 VSS5 2 2

CD1755

10U 6.3V M X5R 0402

CD1756

10U 6.3V M X5R 0402

CD1757

10U 6.3V M X5R 0402

CD1758

10U 6.3V M X5R 0402

A2 K9 H1 G8
VSSQ3 VSS8 CD1774 VSSQ2 VSS6 PDG: 1.2V,16x1uF 0402, 5x10uF 0603,
0.1U_25V_K_X5R_0201

@ D2 A2 K9
2 VSSQ4 VSSQ3 VSS8
0.1U_25V_K_X5R_0201

E3 T7 1 2 @ D2 1 1 1 1 2.5V ,8x1uF 0402,3x10uF 0603

CHANNELA@
A8 VSSQ5 VSS7 2 E3 VSSQ4 T7 1 2
RD1762 DDPA@ 0_0201_5%
D8 VSSQ6
VSSQ7 DDRA_BG1_R
A8 VSSQ5
VSSQ6
VSS7
RD1763 DDPA@0_0201_5% 0.6V,8x1uF 0402,2x10uF 0603
E8 M9 D8

@
@
C750 ITL: 1.2V 16x1uF 0201,3x10uF 0402

CHANNELA@

CHANNELA@
C9 VSSQ8 VSS9 E8 VSSQ7 M9 DDRA_BG1_R 2 2 2 2
VSSQ9 UD3_DDRA_UZQ VSSQ8 VSS9
H9
VSSQ10 VSS10
E9 C9
VSSQ9 UD4_DDRA_UZQ
2.5V 8x1uF 0201 2x10uF 0402
F9 H9 E9
ZQ VSSQ10 VSS10
F9 0.6V 3x1uF 0201 2x10uF 0402
1

ZQ
S550 ITL 1.2V,20x1uF 0402, 8x10uF 0603,

1
RD1748
K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201 RD1749 2.5V ,8x1uF 0201,4x10uF 0402
@ CHANNELA@ K4AAG165WA-BCWE_FBGA96 1/20W_240_1%_0201
CHANNELA@
0.6V,8x1uF 0201,4x10uF 0402
@
2

+2.5V_DDR

+2.5V_DDR
(1OuF_0603_6.3V) *2
Place around the DRAMs
+1.2V

CD1762

10U 6.3V M X5R 0402

CD1763

10U 6.3V M X5R 0402

CD1760

10U 6.3V M X5R 0402

CD1761

10U 6.3V M X5R 0402

0.1u_0201_10V6K

0.1u_0201_10V6K
0.1u_0201_10V6K

0.1u_0201_10V6K
1 1 1 1
CD17681 1
CD1770 CD1771
1 1 CD1769
CHANNELA@ 1
1

EMC_NS@
CD1759 @

CHANNELA@
EMC_NS@

EMC_NS@
0.1U_6.3V_K_X5R_0201 RD1750 2 2 2 2 2 2

CHANNELA@

CHANNELA@
A 1/20W_1.8K_1%_0201 2 2 A
2 CHANNELA@
2

1 2 +VREF_CA_SA
RD1751
[5] DDR_SA_VREFCA
1/20W_2.7_1%_0201
1 CHANNELA@
1

1
CHANNELA@

CD1764 RD1572
0.022U_0402_25V7K 1/20W_1.8K_1%_0201 CD1765
2 CHANNELA@ @ 0.1U_25V_K_X5R_0201
2
1

RD1753
CHANNELA@

24.9_0201_1%
Security Classification LC Future Center Secret Data Title
2

Issued Date 2018/08/20 Deciphered Date 2017/12/13 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Memory Channel A
Date: Sunday, August 02, 2020 Sheet 17 of 61
5 4 3 2 1
 5 4 3 2 1

DDRB_DQ[0..63] +0.6VS
[5] DDRB_DQ[0..63]
DDRB_DQS#[0..7]
[5] DDRB_DQS#[0..7]
DDRB_DQS[0..7]
[5] DDRB_DQS[0..7]
RPD13
+1.2V
1
8Gb SDP UD5 UD6 CD1867 DDRB_CLK0# 1
RPD23
4 DDRB_CLK0_R 1 2 CD1866
DDRB_MA12
DDRB_CS0#
1
2
8
7
DDRB_CLK0 DDRB_ODT0
16Gb DDP [5] DDRB_MA0
DDRB_MA0
DDRB_MA1
P3
A0 DQL0
G2 DDRB_DQ0
DDRB_DQ7
DDRB_MA0
DDRB_MA1
P3
A0 DQL0
G2 DDRB_DQ48
DDRB_DQ55
3.3P_50V_C_NPO_0201 @
2
2 3 0.01U_25V_K_X5R_0201
DDRB_CKE0
3
4
6
5
P7 F7 P7 F7 1/16W_36_5%_4P2R_0404
[5] DDRB_MA1 DDRB_MA2 A1 DQL1 DDRB_DQ1 DDRB_MA2 A1 DQL1 DDRB_DQ52
R3 H3 R3 H3 1/16W_36_5%_8P4R_0804
[5] DDRB_MA2 DDRB_MA3 A2 DQL2 DDRB_DQ5 DDRB_MA3 A2 DQL2 DDRB_DQ51
N7 H7 N7 H7
[5] DDRB_MA3 DDRB_MA4 N3 A3 DQL3 H2 DDRB_DQ2 DDRB_MA4 N3 A3 DQL3 H2 DDRB_DQ50 Byte 6
[5] DDRB_MA4 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ6 Byte 0 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ54 DDRB_ACT#
RD1804 1 21/20W_36_5%_0201
[5] DDRB_MA5 DDRB_MA6 A5 DQL5 DDRB_DQ3 DDRB_MA6 A5 DQL5 DDRB_DQ53 +1.2V DDRB_MA10
P2 J3 P2 J3 RD1805 1 21/20W_36_5%_0201
[5] DDRB_MA6 DDRB_MA7 A6 DQL6 DDRB_DQ4 DDRB_MA7 A6 DQL6 DDRB_DQ49
[5] DDRB_MA7
R8 J7 R8 J7
DDRB_MA8 R2 A7 DQL7
A3 DDRB_DQ16 DDRB_MA8 R2 A7 DQL7
A3 DDRB_DQ33
[5] DDRB_MA8 DDRB_MA9 A8 DQU0 DDRB_DQ23 DDRB_MA9 A8 DQU0 DDRB_DQ37
R7 B8 R7 B8
[5] DDRB_MA9 DDRB_MA10 A9 DQU1 DDRB_DQ18 DDRB_MA10 A9 DQU1 DDRB_DQ35 DDRB_ALERT# DDRB_MA15_CAS#
M3 C3 M3 C3 RD1803 1 21/20W_49.9_1%_0201 RD1806 1 21/20W_36_5%_0201
[5] DDRB_MA10 DDRB_MA11 A10/AP DQU2 DDRB_DQ19 DDRB_MA11 A10/AP DQU2 DDRB_DQ36 DDRB_BA1
T2 C7 T2 C7 RD1807 1 21/20W_36_5%_0201
D [5] DDRB_MA11 DDRB_MA12 M7 A11 DQU3
C2 DDRB_DQ22 Byte 2 DDRB_MA12 M7 A11 DQU3
C2 DDRB_DQ34 D
[5] DDRB_MA12 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ21 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ38 Byte 4
[5] DDRB_MA13 A13 DQU5 DDRB_DQ20 A13 DQU5 DDRB_DQ32
D3 D3 RPD18
DDRB_MA14_WE# L2 DQU6
D7 DDRB_DQ17 DDRB_MA14_WE# L2 DQU6
D7 DDRB_DQ39
[5] DDRB_MA14_WE# DDRB_MA15_CAS# WE_N/A14 DQU7 DDRB_MA15_CAS# WE_N/A14 DQU7 DDRB_BG0
M8 M8 1 8
[5] DDRB_MA15_CAS# DDRB_MA16_RAS# L8 CAS_N/A15 DDRB_MA16_RAS# L8 CAS_N/A15 DDRB_BA0 2 7
[5] DDRB_MA16_RAS# RAS_N/A16 +1.2V RAS_N/A16 +1.2V DDRB_MA11
D1 D1 3 6
DDRB_CLK0# K8 VDD1 J1 DDRB_CLK0# K8 VDD1 J1 DDRB_MA14_WE# 4 5
[5] DDRB_CLK0# DDRB_CLK0 CK_C VDD2 DDRB_CLK0 CK_C VDD2 +0.6VS
K7 L1 K7 L1
[5] DDRB_CLK0 CK_T VDD3 CK_T VDD3
R1 R1 1/16W_36_5%_8P4R_0804
DDRB_CKE0 K2 VDD4
B3 DDRB_CKE0 K2 VDD4
B3
[5] DDRB_CKE0 CKE VDD5 CKE VDD5
G7 G7 RPD20
DDRB_DQS#0 F3 VDD6 B9 DDRB_DQS#6 F3 VDD6 B9 RD1854 1 DDPB@ 2 0_0201_5% DDRB_BG1 [5]
DDRB_DQS0 G3 DQSL_C VDD7 J9 DDRB_DQS6 G3 DQSL_C VDD7 J9 DDRB_BG1_R DDRB_MA8 1 8
DDRB_DQS#2 A7 DQSL_T VDD8 L9 DDRB_DQS#4 A7 DQSL_T VDD8 L9 DDRB_MA6 2 7
RPD25
DDRB_DQS2 B7 DQSU_C VDD9 T9 DDRB_DQS4 B7 DQSU_C VDD9 T9 DDRB_PAR
RD1855 1 SDPB@ 2 0_0201_5% 3 6
+1.2V DQSU_T VDD10 +1.2V DQSU_T VDD10 DDRB_MA9 1 8 DDRB_MA2 4 5
DDRB_DM1 DDRB_DM3 DDRB_MA13
RD1810 1 @ 2 0_0201_5% E2 A1 RD1811 1 @ 2 0_0201_5% E2 A1 2 7
DDRB_DM0 NF/UDM_N/UDBI_N VDDQ1 DDRB_DM2 NF/UDM_N/UDBI_N VDDQ1 DDRB_MA7
RD1813 1 @ 2 0_0201_5% E7 C1 RD1814 1 @ 2 0_0201_5% E7 C1 3 6 1/16W_36_5%_8P4R_0804
NF/LDM_N/LDBI_N VDDQ2 G1 NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_MA5 4 5
DDRB_BA0 N2 VDDQ3 F2 DDRB_BA0 N2 VDDQ3 F2
[5] DDRB_BA0 DDRB_BA1 BA0 VDDQ4 DDRB_BA1 BA0 VDDQ4
[5] DDRB_BA1
N8 J2 N8 J2 RD1856 1 SDPB@ 2 0_0201_5% 1/16W_36_5%_8P4R_0804 RPD17
BA1 VDDQ5 F8 BA1 VDDQ5 F8 UD5_DDRB_UZQ
DDRB_ACT# L3 VDDQ6 J8 DDRB_ACT# L3 VDDQ6 J8 RD1819 1 DDPB@ 2 1/20W_240_1%_0201 DDRB_MA4 1 8
[5] DDRB_ACT# DDRB_CS0# ACT_N VDDQ7 DDRB_CS0# ACT_N VDDQ7 +2.5V_DDR DDRB_MA0
L7 A9 L7 A9 2 7
[5] DDRB_CS0# DDRB_ALERT# P9 CS_N VDDQ8 D9 DDRB_ALERT# P9 CS_N VDDQ8 D9 DDRB_MA1 3 6
[5] DDRB_ALERT# ALERT_N VDDQ9 ALERT_N VDDQ9 DDRB_MA16_RAS# DDRB_MA3
G9 G9 RD1857 1 SDPB@ 2 0_0201_5% RD1832 1 21/20W_36_1%_0201 4 5
DDRB_BG0 M2 VDDQ10 +2.5V_DDR DDRB_BG0 M2 VDDQ10 UD6_DDRB_UZQ
[5] DDRB_BG0 BG0 BG0 DDRB_BG1_R
B1 B1 RD1824 1 DDPB@ 2 1/20W_240_1%_0201 RD1834 1 21/20W_36_1%_0201 1/16W_36_5%_8P4R_0804
DDRB_ODT0 K3 VPP1
R9 DDRB_ODT0 K3 VPP1
R9 DDPB@
[5] DDRB_ODT0 ODT VPP2 ODT VPP2
DDRB_PAR T3 M1 +VREF_CA_SB DDRB_PAR T3 M1 +VREF_CA_SB
RD1858 1 SDPB@ 2 0_0201_5%
[5] DDRB_PAR PAR VREFCA PAR VREFCA UD7_DDRB_UZQ

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 @
2 10K_0201_5% TEN_UD5 2 10K_0201_5% TEN_UD6

1U_6.3V_M_X5R_0201
RD1829 1 N9 E1 1 1 RD1830 1 N9 E1 1 1 RD1831 1 DDPB@ 2 1/20W_240_1%_0201
TEN VSS1 CD1802 TEN VSS1

CD1804

CD1807

CD1808
K1 CD1801 1 K1

0.1U_25V_K_X5R_0201
CPU_DRAMRST# VSS2 CPU_DRAMRST# VSS2

CD1803

0.1U_25V_K_X5R_0201
P1 N1 @ P1 N1 1 1

0.047U_0402_25V7K
[5,17] CPU_DRAMRST# RESET_N VSS3 2 RESET_N VSS3
T1 T1 CD1805 RD1859 1 SDPB@ 2 0_0201_5%

CD1806
F1 VSS4 B2 2 2 F1 VSS4 B2 2 2 UD8_DDRB_UZQ

0.047U_0402_25V7K
H1 VSSQ1 VSS5 G8 2 H1 VSSQ1 VSS5 G8 RD1835 1 DDPB@ 2 1/20W_240_1%_0201
@ @
A2 VSSQ2 VSS6 K9 A2 VSSQ2 VSS6 K9 2 2
1 VSSQ3 VSS8 VSSQ3 VSS8
CD1873 D2 1 D2
E3 VSSQ4 T7 1 2 E3 VSSQ4 T7 1 2
0.1U_6.3V_K_X5R_0201 CD1874
A8 VSSQ5 VSS7 A8 VSSQ5 VSS7
RD1860 DDPB@ 0_0201_5% 0.1U_6.3V_K_X5R_0201 RD1861 DDPB@ 0_0201_5%
VSSQ6 VSSQ6
2 D8 D8
@ E8 VSSQ7 M9 DDRB_BG1_R 2 E8 VSSQ7 M9 DDRB_BG1_R
C9 VSSQ8 VSS9 @ C9 VSSQ8 VSS9
H9 VSSQ9 E9 UD5_DDRB_UZQ H9 VSSQ9 E9 UD6_DDRB_UZQ
VSSQ10 VSS10 F9 VSSQ10 VSS10 F9
ZQ ZQ
1/20W_240_1%_0201

1
C C
K4AAG165WA-BCWE_FBGA96 K4AAG165WA-BCWE_FBGA96
RD1840

RD1841
1/20W_240_1%_0201
+1.2V
@ @ (1uF_0402_6.3V) *16
Place around DRAM
chip
2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD1809

CD1810

CD1811

CD1812

CD1813

CD1814

CD1815

CD1816

CD1817

CD1818

CD1819

CD1820

CD1821

CD1822

CD1823

CD1824

CD1877

CD1878

CD1879
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

UD7 @ @ @ @ @

DDRB_MA0 P3 G2 DDRB_DQ11
UD8
DDRB_MA1 P7 A0 DQL0 F7 DDRB_DQ14
DDRB_MA2 R3 A1 DQL1 H3 DDRB_DQ10 DDRB_MA0 P3 G2 DDRB_DQ63
DDRB_MA3 N7 A2 DQL2
H7 DDRB_DQ13 DDRB_MA1 P7 A0 DQL0
F7 DDRB_DQ58 +1.2V (1OuF_0603_6.3V) *4
DDRB_MA4 N3 A3 DQL3
H2 DDRB_DQ9 DDRB_MA2 R3 A1 DQL1
H3 DDRB_DQ57 Place around the DRAMs Memory :
DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ12 Byte 1 DDRB_MA3 N7 A2 DQL2 H7 DDRB_DQ62
DDRB_MA6 P2 A5 DQL5 J3 DDRB_DQ8 DDRB_MA4 N3 A3 DQL3 H2 DDRB_DQ60 Byte 7
DDRB_MA7 R8 A6 DQL6 J7 DDRB_DQ15 DDRB_MA5 P8 A4 DQL4 H8 DDRB_DQ59 PDG: 1.2V,16x1uF 0402, 5x10uF 0603,
DDRB_MA8 R2 A7 DQL7 A3 DDRB_DQ29 DDRB_MA6 P2 A5 DQL5 J3 DDRB_DQ56
DDRB_MA9 A8 DQU0 DDRB_DQ31 DDRB_MA7 A6 DQL6 DDRB_DQ61 2.5V ,8x1uF 0402,3x10uF 0603

CD1825

10U 6.3V M X5R 0402

CD1826

10U 6.3V M X5R 0402

CD1827

10U 6.3V M X5R 0402

CD1828

10U 6.3V M X5R 0402

CD1829

10U 6.3V M X5R 0402

CD1830

10U 6.3V M X5R 0402

CD1831

10U 6.3V M X5R 0402

CD1832

10U 6.3V M X5R 0402

R7 B8 R8 J7
DDRB_MA10
DDRB_MA11
M3 A9
A10/AP
DQU1
DQU2
C3 DDRB_DQ25
DDRB_DQ26
DDRB_MA8
DDRB_MA9
R2 A7
A8
DQL7
DQU0
A3 DDRB_DQ41
DDRB_DQ46
0.6V,8x1uF 0402,2x10uF 0603
T2 C7 R7 B8
DDRB_MA12 M7 A11 DQU3 C2 DDRB_DQ28 Byte 3 DDRB_MA10 M3 A9 DQU1 C3 DDRB_DQ42 1 1 1 1 1 1 1 1 C750 ITL: 1.2V 16x1uF 0201,3x10uF 0402
DDRB_MA13 A12/BC_N DQU4 DDRB_DQ30 DDRB_MA11 A10/AP DQU2 DDRB_DQ44
T8
A13 DQU5
C8
DDRB_DQ24 DDRB_MA12
T2
A11 DQU3
C7
DDRB_DQ40
2.5V 8x1uF 0201 2x10uF 0402
D3 M7 C2 @ @ @
DDRB_MA14_WE# L2 DQU6 D7 DDRB_DQ27 DDRB_MA13 T8 A12/BC_N DQU4 C8 DDRB_DQ45 Byte 5 2 2 2 2 2 2 2 @ 2
0.6V 3x1uF 0201 2x10uF 0402
DDRB_MA15_CAS# WE_N/A14 DQU7 A13 DQU5 DDRB_DQ43
DDRB_MA16_RAS#
M8
L8 CAS_N/A15 DDRB_MA14_WE# L2 DQU6
D3
D7 DDRB_DQ47 S550 ITL 1.2V,20x1uF 0402, 8x10uF 0603,
RAS_N/A16 D1 +1.2V DDRB_MA15_CAS# M8 WE_N/A14 DQU7
@
2.5V ,8x1uF 0201,4x10uF 0402
DDRB_CLK0# K8 VDD1
J1 DDRB_MA16_RAS# L8 CAS_N/A15 +1.2V
DDRB_CLK0 K7 CK_C VDD2 L1 RAS_N/A16 D1
0.6V,8x1uF 0201,4x10uF 0402
CK_T VDD3
R1 DDRB_CLK0# K8 VDD1
J1
DDRB_CKE0 K2 VDD4 B3 DDRB_CLK0 K7 CK_C VDD2 L1
CKE VDD5 CK_T VDD3
G7 R1
DDRB_DQS#1 F3 VDD6 B9 DDRB_CKE0 K2 VDD4 B3 +0.6VS
DDRB_DQS1 G3 DQSL_C VDD7 J9 CKE VDD5 G7
DDRB_DQS#3 A7 DQSL_T VDD8 L9 DDRB_DQS#7 F3 VDD6 B9
+1.2V DDRB_DQS3 B7 DQSU_C VDD9 T9 DDRB_DQS7 G3 DQSL_C VDD7 J9
(1uF_0402_6.3V) *8
DQSU_T VDD10 DDRB_DQS#5 A7 DQSL_T VDD8
L9
Place around DRAM chip
DDRB_DM5 DDRB_DQS5 DQSU_C VDD9 +1.2V
RD1842 1 @ 2 0_0201_5% E2 A1 B7 T9
DDRB_DM4 NF/UDM_N/UDBI_N VDDQ1 +1.2V DQSU_T VDD10
B RD1843 1 @ 2 0_0201_5% E7 C1 B
NF/LDM_N/LDBI_N VDDQ2 G1 DDRB_DM7
RD1844 1 @ 2 0_0201_5% E2 A1
DDRB_BA0 N2 VDDQ3 F2 DDRB_DM6 NF/UDM_N/UDBI_N VDDQ1
RD1845 1 @ 2 0_0201_5% E7 C1

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
DDRB_BA1 N8 BA0 VDDQ4 J2 NF/LDM_N/LDBI_N VDDQ2 G1
BA1 VDDQ5 DDRB_BA0 VDDQ3
1 1 1 1 1 1 1 1

CD1833

CD1834

CD1835

CD1836

CD1837

CD1838

CD1839

CD1840
F8 N2 F2
DDRB_ACT# L3 VDDQ6 J8 DDRB_BA1 N8 BA0 VDDQ4 J2
DDRB_CS0# L7 ACT_N VDDQ7
A9 BA1 VDDQ5
F8
DDRB_ALERT# P9 CS_N VDDQ8 D9 DDRB_ACT# L3 VDDQ6 J8 2 2 2 2 2 2 2 2
ALERT_N VDDQ9 DDRB_CS0# ACT_N VDDQ7 1
G9 L7 A9 1
DDRB_BG0 M2 VDDQ10 +2.5V_DDR DDRB_ALERT# P9 CS_N VDDQ8
D9 CD1842
BG0 B1 ALERT_N VDDQ9 G9 22P_0201_258J
CD1841
DDRB_ODT0 K3 VPP1 R9 DDRB_BG0 M2 VDDQ10 +2.5V_DDR 22P_0201_258J 2 RF_NS@
ODT VPP2 BG0 B1 @ @ 2 RF_NS@
DDRB_PAR T3 M1 +VREF_CA_SB DDRB_ODT0 K3 VPP1
R9
PAR VREFCA ODT VPP2
1U_6.3V_M_X5R_0201

2 10K_0201_5% TEN_UD7 DDRB_PAR +VREF_CA_SB

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
RD1846 1 N9 E1 1 T3 M1
TEN VSS1 PAR VREFCA
CD1845

1U_6.3V_M_X5R_0201
K1 1 1
CPU_DRAMRST# P1 VSS2 N1 2 10K_0201_5% TEN_UD8
RD1847 1 N9 E1
CD1846

CD1850
RESET_N VSS3
1 TEN VSS1
1

CD1849
T1 CD1843 1 K1 +0.6VS
F1 VSS4 B2 2 CPU_DRAMRST# P1 VSS2 N1 1 1
0.047U_0402_25V7K

CD1844

H1 VSSQ1 VSS5 G8 2 RESET_N VSS3 T1 2

CD1847 CD1848 (1OuF_0603_6.3V) *2
0.1U_25V_K_X5R_0201

VSSQ2 VSS6 2 VSS4 2 +0.6VS

A2 K9 @ F1 B2

0.047U_0402_25V7K
Place around the DRAMs

0.1U_25V_K_X5R_0201
VSSQ3 VSS8 VSSQ1 VSS5
D2
VSSQ4
2 H1
VSSQ2 VSS6
G8 @

RF & EMC

CD1852

10U 6.3V M X5R 0402

CD1853

10U 6.3V M X5R 0402

CD1854

10U 6.3V M X5R 0402

1 E3 T7 1 2 A2 K9 2 2
VSSQ5 VSS7 VSSQ3 VSS8

CD1851

10U 6.3V M X5R 0402

CD1875 A8 RD1862 DDPB@ 0_0201_5% 1 D2
D8 VSSQ6 E3 VSSQ4 T7 1 2
0.1U_6.3V_K_X5R_0201 CD1876 1 1 1
E8 VSSQ7 M9 DDRB_BG1_R A8 VSSQ5 VSS7
0.1U_6.3V_K_X5R_0201 RD1863 DDPB@ 0_0201_5% 1
2 C9 VSSQ8 VSS9 D8 VSSQ6
@ VSSQ9 UD7_DDRB_UZQ VSSQ7 DDRB_BG1_R 1 1
H9 E9 2 E8 M9
VSSQ10 VSS10
F9 @ C9 VSSQ8 VSS9 2 2 2
@ CD1855 CD1856
ZQ
H9 VSSQ9
E9 UD8_DDRB_UZQ 2 22P_0201_258J 22P_0201_258J
VSSQ10 VSS10 F9 2 2
ZQ
@
1

K4AAG165WA-BCWE_FBGA96

1
@ RD1848
1/20W_240_1%_0201 K4AAG165WA-BCWE_FBGA96 RD1849
@ 1/20W_240_1%_0201
2

+1.2V +2.5V_DDR

1 (1OuF_0603_6.3V) *2
1

CD1857 +2.5V_DDR
Place around the DRAMs
0.1U_6.3V_K_X5R_0201 RD1850
1/20W_1.8K_1%_0201

CD1872

CD1869

CD1870
CD1868
2

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
CD1859

10U 6.3V M X5R 0402

CD1858

10U 6.3V M X5R 0402

CD1860

10U 6.3V M X5R 0402

A A
2

CD1863

10U 6.3V M X5R 0402

1 1 1 1
+VREF_CA_SB 1 1 1
1
RD1851 2 1
[5] DDR_SB_VREFCA
1/20W_2.7_1%_0201

EMC_NS@
EMC_NS@
1 @ 2 2 2 2
1

1 2 2 2
CD1864 RD1864 2
0.022U_0402_25V7K 1/20W_1.8K_1%_0201 CD1865
2 @ 0.1U_25V_K_X5R_0201
2
@
2
1

RD1853
24.9_0201_1%
2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Memory Channel B
Date: Tuesday, August 11, 2020 Sheet 18 of 61
5 4 3 2 1
 5 4 3 2 1

GDDR6 Mapping table

DRAM1(0...31) DRAM2(32...63)
GPIOs
CHA(Bytes 0,1) CHB(Bytes 2,3) CHA(Bytes 4,5) CHB(Bytes 4,5) Remark
GPIO I/O ACTIVE Function Description
CMD0 CA0_A

GPIO0 OUT - GPU Core VDD PWM control signal CMD9 CA1_A

CMD8 CA2_A
GPIO1 OUT N/A FB Enable for GC6 2.0
CMD32 CA3_A

D GPIO2 OUT N/A GPU EVENT CMD4 CA0_B D

CMD12 CA1_B
GPIO3 OUT N/A
CMD5 CA2_B

GPIO4 OUT N/A 1.8VGS_PWR_EN_R FOR 1.8VGS&1.0VGS&NVDD CMD13 CA3_B

CMD7 CA4_A CA4_B

GPIO5 OUT N/A
CMD11 CA5_A CA5_B

GPIO6 OUT - PSI_VGA CMD15 CA6_A CA6_B

CMD14 CA7_A CA7_B

GPIO7 OUT N/A
CMD3 CA8_A CA8_B

GPIO8 OUT - VRAM_VDDQ_ADJ control the power voltage CMD1 CA9_A CA9_B

CMD6 CABI_A CABI_B

GPIO9 I/O N/A 10K Pull-up
CMD10 CKE_A CKE_B 10K Pull 1.25VGS

GPIO10 OUT FBVREF_ALTV for GDDR6 CMD2 REST REST 10K Pull GND

CMD20 CA0_A
GPIO11 OUT -
CMD28 CA1_A

GPIO12 IN AC Power Detect Input (10K pull High) CMD21 CA2_A

CMD29 CA3_A
GPIO13 OUT -
CMD16 CA0_B

GPIO14 IN N/A CMD25 CA1_B

C CMD24 CA2_B C
GPIO15 IN N/A
CMD33 CA3_B

GPIO16 N/A CMD23 CA4_A CA4_B

CMD27 CA5_A CA5_B

GPIO17 IN N/A
CMD30 CA6_A CA6_B

GPIO18 OUT N/A GPIO18_FP_FUSE CMD31 CA7_A CA7_B

CMD19 CA8_A CA8_B

GPIO19 IN N/A
CMD17 CA9_A CA9_B

GPIO20 N/A CMD22 CABI_A CABI_B

CMD26 CKE_A CKE_B 10K Pull 1.25VGS

GPIO21 OUT
CMD18 REST REST 10K Pull GND

OVERT OUT Active Low Thermal Catastrophic Over Temperature CMD35 NC

Performance Mode P0 TDP and EDP-Continuous current (GDDR5) POWER RAIL

FB_PLL_AVDD Frame Buffer PLL analog Power Rail 1.8V
TDP Min
EDP GPCPLL_AVDD Core PLL analog Power Rails 1.8V
Core Clk FB Total 1.0V Total 1.8V/3.3V Total SP_PLLVDD Core Clock PLL Analog Power Rail 1.8V
GPU Mem NVVDD GPU FBIO (GPU+Mem) (1.0V@N17s)
Product (1.35V) (1.35V) (1.05V@N16s) 1.8V 3.3V VDD,VDDS Primary Core Power Rail NVVDD
B N17s N16s B
Cont. Peak Cont. Peak Cont. Peak Cont. Peak Cont. Cont. VDD_SENSE
(W) (W) (MHz) (A) (A) (A) (A) (A) (A) (A) (A) (A) (A) GND_SENSE

N16S-GMR 16 1.6 849 19 34 2.0 2.9 4.2 6.8 0.8 2.1 --- 0.06 VDDS_SENSE
GNDS_SENSE
N16S-GTR 18 1.7 965 26.5 53 2.0 2.9 4.2 6.8 0.8 2.1 --- 0.06
VDD18 or 1V8_MAIN 1.8V Power Rail 1.8V
1V8_AON
N17S-LG(0x1D12) 10 1.6 936 15.4 48.3 2.5 2.8 5.0 5.8 0.1 0.2 0.2 ---
VID_PLLVDD Thermal Controller and Video Pixel Clock PLL 1.8V
N17S-LG(0x1D52) 10.5 1.7 936 15.6 48.6 2.7 3.0 5.3 6.2 0.1 0.2 0.2 --- Analog Power Rail

N17S-G1 25 1.9 1468 30.0 60.1 3.0 3.4 5.6 6.9 0.1 0.2 0.3 --- XS_PLLVDD Core PLL analog Power Rails 1.8V

N17S-G0 25 1.9 1518 27.8 42.0 3.2 3.9 5.8 7.4 0.2 0.3 0.5 ---

N17S-G2 25 1.9 1518 28.6 60.3 3.2 3.9 5.8 7.4 0.2 0.3 0.5 ---

Product TDP

A N18S-G5/GDDR6 A

25W

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. VGA Notes List
Date: Thursday, May 28, 2020 Sheet 19 of 61
5 4 3 2 1
 5 4 3 2 1

+1.8VGS
Under GPU
+1.8V_AON GPU and PS +1.0VGS
PEX_DVDD 1 @ 2 0_5%_0603

2
RV2007

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
RV2002 @ RV2003

OPT_NS@

OPT@

OPT@
4.7U_0402_6.3V6M

OPT@

OPT@
0_0201_5% 10K_0402_5%

CV2006

CV2005

22U_0603_6.3V6-M

22U_0603_6.3V6-M
CV2035

CV2034

CV2033

CV2032

CV2031

CV2004
OPT@

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1 1 1 1 1 1

1
UV1A

CV2010

CV2030
CV2029

CV2008

CV2009
OPT@

OPT_NS@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
1/14 PCI_EXPRESS
1 2 2 2 2 2 2 2 2 2 2 2 2 2
CV2003 GP107S TU117S
@ PEX_WAKE#:N18,Leave unconnected and folating
TU117S GP107S AA22
0.1U_6.3V_K_X5R_0201 PEX_CVDD
2 AA14 NC
PEX_DVDD
PEX_WAKE_N

2
PLT_RST_VGA# AC7 AB23
D [26] PLT_RST_VGA# PEX_RST_N PEX_DVDD_2 D
OPT@ QV2001 AC24
1 3 CLK_REQ_GPU# AC6 PEX_DVDD_3
AD25
[10] GPU_CLKREQ# PEX_CLKREQ_N PEX_DVDD_4
AE26
CLK_PCIE_GPU PEX_DVDD_5 +1.8VGS
AE8 AE27
[10] CLK_PCIE_GPU CLK_PCIE_GPU# PEX_REFCLK PEX_DVDD_6 PEX_HVDD
LSI1012XT1G_SC-89-3 AD8 Under GPU
[10] CLK_PCIE_GPU# PEX_REFCLK_N
PCIE4_CRX_GTX_P0 GPU and PS
OPT@ CV2001 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P0 AC9
PCIE4_CRX_GTX_N0 OPT@ CV2011 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N0 AB9 PEX_TX0
PEX_TX0_N
PCIE4_CTX_C_GRX_P0 AG6 PEX_HVDD 1 @ 2 0_5%_0603

1U_6.3V_K_X5R_0201
PCIE4_CTX_C_GRX_N0 PEX_RX0

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AG7 AA10

CV2037
RV2006
PEX_RX0_N PEX_HVDD_1

10U 6.3V M X5R 0402

AA12

OPT@

OPT@

OPT@
CV2019
RV2005

OPT@

22U_0603_6.3V6-M

22U_0603_6.3V6-M
4.7U_0402_6.3V6M
10U 6.3V M X5R 0402
CV2041

CV2040

CV2014

CV2015

CV2016

CV2017

CV2039
10K_0201_5% PCIE4_CRX_GTX_P1 OPT@ CV2012 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P1 AB10 PEX_HVDD_2
AA13

OPT@ CV2018

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

PCIE4_CRX_GTX_N1 PEX_TX1 PEX_HVDD_3 1 1
@ OPT@ CV2013 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N1 AC10 AA16 1 1 1 1 1 1 1 1 1 1 1 1
PEX_TX1_N PEX_HVDD_4
AA18

1
PCIE4_CTX_C_GRX_P1 AF7 PEX_HVDD_5
AA19

OPT@
PCIE4_CTX_C_GRX_N1 AE7 PEX_RX1 PEX_HVDD_6
AA20 2 2

CV2020
OPT@

CV2021

CV2022

CV2036
OPT@

OPT@

OPT@

OPT@
OPT_NS@

OPT_NS@

OPT_NS@
PEX_RX1_N PEX_HVDD_7 2 2 2 2 2 2 2 2 2 2 2 2
AA21
PCIE4_CRX_GTX_P2 PEX_HVDD_8
OPT@ CV2002 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P2 AD11 AB22
PCIE4_CRX_GTX_N2 OPT@ CV2024 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N2 AC11 PEX_TX2 PEX_HVDD_9
AC23
PEX_TX2_N PEX_HVDD_10
AD24
PCIE4_CTX_C_GRX_P2 AE9 PEX_HVDD_11
AE25
PCIE4_CTX_C_GRX_N2 AF9 PEX_RX2 PEX_HVDD_12
AF26
PEX_RX2_N PEX_HVDD_13
AF27
PCIE4_CRX_GTX_P3 OPT@ CV2025 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_P3 AC12 PEX_HVDD_14
PCIE4_CRX_GTX_N3 OPT@ CV2026 1 2 0.22U_0201_6.3V6-K PCIE4_CRX_C_GTX_N3 AB12 PEX_TX3
PEX_TX3_N
PCIE4_CTX_C_GRX_P3 AG9
PCIE4_CTX_C_GRX_N3 PEX_RX3
AG10
PEX_RX3_N

AB13
PEX_TX4
AC13
PEX_TX4_N

[9] PCIE4_CRX_GTX_N[0..3]
AF10
PEX_RX4
AE10
PEX_RX4_N
[9] PCIE4_CRX_GTX_P[0..3]
AD14
C AC14 PEX_TX5
AA8 PEX_PLL_HVDD C
[9] PCIE4_CTX_C_GRX_N[0..3] PEX_TX5_N PEX_PLL_HVDD_1
AA9

0.1U_6.3V_K_X5R_0201
PEX_PLL_HVDD_2 +1.8VGS
AE12
[9] PCIE4_CTX_C_GRX_P[0..3] AF12 PEX_RX5
1 @
PEX_RX5_N
RV2009 2 1 0_0402_5%

OPT@
CV2027
AC15
PEX_TX6
AB15
PEX_TX6_N 2
AG12
PEX_RX6
AG13
PEX_RX6_N
Under GPU
AB16
AC16 PEX_TX7 (below 150mils)
PEX_TX7_N

AF13
PEX_RX7
AE13
PEX_RX7_N

AD17
PEX_TX8
AC17
PEX_TX8_N
AE15
PEX_RX8
AF15
PEX_RX8_N

AC18
PEX_TX9
AB18

PEX LANES 15 - 4 ARE DEFEATURED

PEX_TX9_N

AG15
PEX_RX9
AG16
PEX_RX9_N
AB19
PEX_TX10
AC19
PEX_TX10_N

AF16
PEX_RX10
AE16
PEX_RX10_N
AD20
PEX_TX11
AC20
PEX_TX11_N
B B
AE18
PEX_RX11
AF18
PEX_RX11_N

AC21
PEX_TX12
AB21
PEX_TX12_N

AG18
PEX_RX12
AG19
PEX_RX12_N

AD23
PEX_TX13
AE23
PEX_TX13_N

AF19
PEX_RX13
AE19
PEX_RX13_N

AF24
PEX_TX14
AE24
PEX_TX14_N

AE21
PEX_RX14
AF21
PEX_RX14_N
AG24
PEX_TX15
AG25
PEX_TX15_N

AG21
PEX_RX15
AG22
PEX_RX15_N

AF25 PEX_TERMP 2.49K_0402_1% 2 OPT@ 1 RV2010

PEX_TERMP

@
N18S-G5-A1_BGA603

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_PCIE Interface
Date: Monday, August 03, 2020 Sheet 20 of 61
5 4 3 2 1
 5 4 3 2 1

UV1B
2/14 FBA
FBA_D0 E18
FBA_D1 F18 FBA_D0
FBA_D2 E16 FBA_D1
FBA_D3 F17 FBA_D2
FBA_D4 FBA_D3
D20
FBA_D5 D21 FBA_D4
FBA_D6 F20 FBA_D5
FBA_D7 E21 FBA_D6
FBA_D8 E15 FBA_D7
FBA_D9 FBA_D8
D15
FBA_D10 F15 FBA_D9
D FBA_D11 FBA_D10 D
F13
FBA_D12 C13 FBA_D11
FBA_D13 B13 FBA_D12
FBA_D14 FBA_D13 FBA_CMD0
E13 C27
FBA_D15 D13 FBA_D14 FBA_CMD0
C26 FBA_CMD1 +1.25VGS
FBA_D16 B15 FBA_D15 FBA_CMD1
E24 FBA_CMD2
FBA_D17 C16 FBA_D16 FBA_CMD2
F24 FBA_CMD3
FBA_D18 A13 FBA_D17 FBA_CMD3
D27 FBA_CMD4
FBA_D19 FBA_D18 FBA_CMD4 FBA_CMD5
A15 D26
FBA_D20 B18 FBA_D19 FBA_CMD5
F25 FBA_CMD6

1
FBA_D21 A18 FBA_D20 FBA_CMD6
F26 FBA_CMD7
FBA_D22 A19 FBA_D21 FBA_CMD7
F23 FBA_CMD8 RV2101 RV2102
FBA_D23
FBA_D24
C19
B24
FBA_D22
FBA_D23
FBA_CMD8
FBA_CMD9
G22
G23
FBA_CMD9
FBA_CMD10
CKE_A 10K_0402_1%
OPT@
10K_0402_1%
OPT@
FBA_D25 C23 FBA_D24 FBA_CMD10
G24 FBA_CMD11

2
FBA_D26 A25 FBA_D25 FBA_CMD11
F27 FBA_CMD12
FBA_D27 A24 FBA_D26 FBA_CMD12
G25 FBA_CMD13 FBA_CMD10
FBA_D28 A21 FBA_D27 FBA_CMD13
G27 FBA_CMD14
FBA_D29 FBA_D28 FBA_CMD14 FBA_CMD15 FBA_CMD26
B21 G26
[27,28] FBA_D[0..63] FBA_D30 C20 FBA_D29 FBA_CMD15
M24 FBA_CMD16
FBA_D31 C21 FBA_D30 FBA_CMD16
M23 FBA_CMD17
[27,28] FBA_CMD[33..0] FBA_D32 FBA_D31 FBA_CMD17 FBA_CMD18
R22 K24
FBA_D33 R24 FBA_D32 FBA_CMD18
K23 FBA_CMD19 FBA_CMD2
[27,28] FBA_EDC[7..0] FBA_D34 FBA_D33 FBA_CMD19 FBA_CMD20
T22 M27
FBA_D35 R23 FBA_D34 FBA_CMD20
M26 FBA_CMD21 FBA_CMD18
[27,28] FBA_DBI[7..0] FBA_D36 FBA_D35 FBA_CMD21 FBA_CMD22
N25 M25
FBA_D37 N26 FBA_D36 FBA_CMD22
K26 FBA_CMD23
RESET

1
FBA_D38 N23 FBA_D37 FBA_CMD23
K22 FBA_CMD24
FBA_D39 FBA_D38 FBA_CMD24 FBA_CMD25
N24 J23 RV2103 RV2104
FBA_D40 V23 FBA_D39 FBA_CMD25
J25 FBA_CMD26 10K_0402_1% 10K_0402_1%
FBA_D41 V22 FBA_D40 FBA_CMD26
J24 FBA_CMD27 OPT@ OPT@
FBA_D42 T23 FBA_D41 FBA_CMD27
K27 FBA_CMD28

2
FBA_D43 U22 FBA_D42 FBA_CMD28
K25 FBA_CMD29
FBA_D44 FBA_D43 FBA_CMD29 FBA_CMD30 +1.25VGS
Y24 J27
FBA_D45 AA24 FBA_D44 FBA_CMD30
J26 FBA_CMD31
FBA_D46 Y22 FBA_D45 FBA_CMD31
B19 FBA_CMD32
FBA_D47 AA23 FBA_D46 GP107S FBA_CMD32
F22 FBA_CMD33
C FBA_D48 AD27 FBA_D47 FBA_CMD34 FBA_CMD33
J22 RV2105 1 2 C
FBA_D49 FBA_D48 FBA_CMD35
AB25 1/20W_60.4_1%_0201
FBA_D50 AD26 FBA_D49
@
FBA_D51 AC25 FBA_D50
FBA_D52 AA27 FBA_D51
FBA_D53 AA26 FBA_D52
FBA_D54 FBA_D53
W26
FBA_D55 Y25 FBA_D54
FBA_D56 R26 FBA_D55
FBA_D57 T25 FBA_D56
FBA_D58 N27 FBA_D57
FBA_D59 FBA_D58 FBA_CLK0
R27 D24
FBA_D60 FBA_D59 FBA_CLK0 FBA_CLK0# FBA_CLK0 [27]
V26 D25
FBA_D61 FBA_D60 FBA_CLK0_N FBA_CLK1 FBA_CLK0# [27]
V27 N22
FBA_D62 FBA_D61 FBA_CLK1 FBA_CLK1# FBA_CLK1 [28]
W27 M22
FBA_D63 FBA_D62 FBA_CLK1_N FBA_CLK1# [28]
W25
FBA_D63

FBA_DBI0 D19
FBA_DBI1 D14 FBA_DQM0
D18 FBA_WCK01
FBA_DBI2 C17 FBA_DQM1 FBA_WCK01
C18 FBA_WCK01# FBA_WCK01 [27]
FBA_DBI3 FBA_DQM2 GP107S FBA_WCK01_N FBA_WCKB01 FBA_WCK01# [27]
C22 A17
FBA_DBI4 FBA_DQM3 N/A FBA_WCKB01 FBA_WCKB01# FBA_WCKB01 [27]
P24 A14
FBA_DBI5 FBA_DQM4 N/A FBA_WCKB01_N FBA_WCKB01# [27]
W24
FBA_DBI6 AA25 FBA_DQM5
D17 FBA_WCK23
FBA_DBI7 U25 FBA_DQM6 FBA_WCK23
D16 FBA_WCK23# FBA_WCK23 [27]
FBA_DQM7 FBA_WCK23_N FBA_WCKB23 FBA_WCK23# [27]
A23
N/A FBA_WCKB23 FBA_WCKB23# FBA_WCKB23 [27]
A20
FBA_EDC0 E19 N/A FBA_WCKB23_N FBA_WCKB23# [27]
FBA_EDC1 C15 FBA_DQS_WP0
FBA_EDC2 B16 FBA_DQS_WP1
T24 FBA_WCK45
FBA_EDC3 FBA_DQS_WP2 FBA_WCK45 FBA_WCK45# FBA_WCK45 [28]
B22 U24
FBA_EDC4 FBA_DQS_WP3 FBA_WCK45_N FBA_WCKB45 FBA_WCK45# [28]
R25 AC27
FBA_EDC5 FBA_DQS_WP4 N/A FBA_WCKB45 FBA_WCKB45# FBA_WCKB45 [28]
W23 Y27
FBA_EDC6 FBA_DQS_WP5 N/A FBA_WCKB45_N FBA_WCKB45# [28]
AB26
FBA_EDC7 T26 FBA_DQS_WP6
FBA_DQS_WP7 FBA_WCK67
V24
FBA_WCK67 FBA_WCK67# FBA_WCK67 [28]
TU117S GP107S V25
B
F19 FBA_WCK67_N
U27 FBA_WCKB67 FBA_WCK67# [28] B
OPT_GND_0 FBA_DQS_RN0 N/A FBA_WCKB67 FBA_WCKB67# FBA_WCKB67 [28]
C14 P27
OPT_GND_1 N/A FBA_WCKB67_N FBA_WCKB67# [28]
A16 FBA_DQS_RN1
OPT_GND_2 FBA_DQS_RN2
A22
OPT_GND_3 FBA_DQS_RN3
P25
OPT_GND_4 FBA_DQS_RN4
W22
OPT_GND_5 FBA_DQS_RN5
AB27 Place close to BGA
OPT_GND_6
T27 FBA_DQS_RN6
OPT_GND_7 FBA_DQS_RN7 +FB_PLLAVDD +1.8VGS
200mA
LV2101
F16 Under GPU Near GPU 1 2

10U 6.3V M X5R 0402

FB_PLL_AVDD_1
HCB1608KF-300T60_2P

CV2103
1U_6.3V_K_X5R_0201
CV2101

CV2102
P22 +FB_PLLAVDD

1U_6.3V_K_X5R_0201
FB_PLL_AVDD_2 OPT@

OPT@

22U_0603_6.3V6-M
1 1 1
H22 Place close to ball 1
FB_REFPLL_AVDD
30ohms (ESR=0.01) 0603 Bead

OPT@

OPT@
2 2 2
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

CV2107

OPT@
2

CV2105
CV2108

1U_6.3V_K_X5R_0201

1 1
OPT@
CV2106

1
RV2106 OPT@ 49.9_0402_1%
OPT@

1 2 D23 2 2
OPT@

FB_VREF 2
CV2110 1 23.9P_50V_B_NPO_0402
@
OPT@ N18S-G5-A1_BGA603

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_MEM Interface
Date: Thursday, May 28, 2020 Sheet 21 of 61
5 4 3 2 1
 5 4 3 2 1

+VGA_CORE
+VGA_CORE
5x1uF Under GPU 14x10uF

OPT_RF_NS@
Under GPU For RF

OPT@

OPT@
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
+VGA_CORE

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402

OPT_NS@
UV1C

CV2257 OPT@

CV2258 OPT@

CV2256 @

CV2201 OPT@

CV2202 @

CV2203 @

CV2204 OPT@

1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
UV1H

330U_B2_2.5VM_R9M

33P_0402_50V8J
CV2205 OPT@

33P_0402_50V8J
6/14 XVDD 11/14 VDD 1 of 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
K10 1

OPT_RF@
VDD_01
K12 +
VDD_02
G1 N4 K14

CV2259

CV2239

CV2240

CV2206

CV2207

CV2208

CV2209

CV2210

CV2211

CV2212

CV2213

CV2214

CV2215

CV2216

CV2217

CV2228

CV2229

CV2230

CV2231

CV2232

CV2233
G2 XVDD_1 XVDD_36
N5 K16 VDD_03 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CV2274
XVDD_2 XVDD_37 VDD_04 2 2
G3 N7 K18

CV2218
XVDD_3 XVDD_38 VDD_05
G4 P3 L13
XVDD_4 XVDD_39 VDD_07
G5 P4 L15
XVDD_5 XVDD_40 VDD_08
G6 P6 M10
XVDD_6 XVDD_41 VDD_10
G7 R1 M12
D XVDD_7 XVDD_42 VDD_11 D
H3 R2 M16
XVDD_8 XVDD_43 VDD_13
H4 R3 M18
XVDD_9 XVDD_44 VDD_14
H6 R4 N11 Near GPU 10x22uF
XVDD_10 XVDD_45 VDD_15
J1 R5 N13 Near Vram
XVDD_11 XVDD_46 VDD_16
J2 R6 N15
XVDD_12 XVDD_47 VDD_17
J3 R7 N17
XVDD_13 XVDD_48 VDD_18

10U 6.3V M X5R 0402

J4 T1 P14

OPT@
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
XVDD_14 XVDD_49 VDD_21
J5 T2 R11 1
XVDD_15 XVDD_50 VDD_24

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
J6 T3 R13

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
XVDD_16 XVDD_51 VDD_25

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

J7 T4 R15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
XVDD_17 XVDD_52 VDD_26

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

K1 T5 R17

CV2238
XVDD_18 XVDD_53 VDD_27 1 1 2
K2 T6 T10 1 1 1 1 1 1 1 1 1
XVDD_19 XVDD_54 VDD_28
K3 T7 T12

CV2268

CV2269

CV2270

CV2271

CV2264

CV2265

CV2266

CV2267

CV2260

CV2261

CV2262

CV2263

CV2234

CV2235

CV2236

CV2237
XVDD_20 XVDD_55 VDD_29 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
K4 U3 T16

CV2272

CV2273
K5 XVDD_21 XVDD_56
U4 T18 VDD_31 2 2

CV2219

CV2220

CV2221

CV2222

CV2223

CV2224

CV2225

CV2226

CV2227
XVDD_22 XVDD_57 VDD_32 2 2 2 2 2 2 2 2 2
K6 U6 U13
XVDD_23 XVDD_58 VDD_34
K7 V1 U15
XVDD_24 XVDD_59 VDD_35
L3 V2 V10
XVDD_25 XVDD_60 VDD_37
L4 V3 V12
XVDD_26 XVDD_61 VDD_38
M1 V4 V14
XVDD_27 XVDD_62 VDD_39
M2 V5 V16 For RF
XVDD_28 XVDD_63 VDD_40
M3 V6 V18
XVDD_29 XVDD_64 VDD_41
M4 V7
M5 XVDD_30
XVDD_31
XVDD_65
XVDD_66
W1 NVVDD Decouling
M7 W2
N1 XVDD_32 XVDD_67
W3 F2 NVVDD_VCC_SENSE
NVVDD_VCC_SENSE [58]
N2 XVDD_33
XVDD_34
XVDD_68
XVDD_69
W4 VDD_SENSE
GND_SENSE
F1 NVVDD_VSS_SENSE
NVVDD_VSS_SENSE [58] MLCC N18/GB2E-64 location
N3
XVDD_35

trace width: 16mils 10uF X6S 0603 TBD

differential voltage sensing. NVVDD/Q Decouling
differential signal routing.
4.7uF X6S 0603 0 Under
@ @
N18S-G5-A1_BGA603 N18S-G5-A1_BGA603 1.0uF X6S 0201/0402 TBD
C C

0.47uF X6S 0201/0402 0

10uF X6S 0603 0
22uF X6S 0805 TBD Near

4.7uF X6S 0603 0

+1.25VGS

UV1E Near GPU 470uF POS 7343 TBD

12/14 FBVDDQ 1x10uF 3x22uF
+1.25VGS
B26 Under GPU(below 150mils) 8x1uF 2x10uF
FBVDDQ_01
C25
FBVDDQ_02 +VGA_CORE
E23
FBVDDQ_03
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

E26
FBVDDQ_04
CV2251

1U_6.3V_M_X5R_0201

CV2255

1U_6.3V_M_X5R_0201

CV2250

1U_6.3V_M_X5R_0201

CV2243

1U_6.3V_M_X5R_0201

CV2244

CV2248

CV2245

CV2249

CV2241

CV2242

22UC_6.3VC_MC_X5RC_0603
F14 UV1G
FBVDDQ_05

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

10U 6.3V M X5R 0402

F21

CV2252

CV2253

CV2254

OPT@ CV2246
FBVDDQ_06 1 1 1 1 1 1 1 1 2 2 7/14 VDD 2 of 2
G13 1 1 1 1
FBVDDQ_07
G14
FBVDDQ_08
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

G15 L11
FBVDDQ_09 2 2 2 2 2 2 2 2 1 1 VDD_06

OPT@

OPT_NS@

OPT_NS@
G16 L17
G18 FBVDDQ_10 2 2 2 2 M14 VDD_09
FBVDDQ_11 VDD_12
G19 P10
FBVDDQ_12 VDD_19
G20 P12
FBVDDQ_13 VDD_20
G21 P16
FBVDDQ_14 VDD_22
L22 P18
FBVDDQ_19 VDD_23
L24 T14
FBVDDQ_20 VDD_30
L26 U11
FBVDDQ_21 VDD_33
M21 U17
FBVDDQ_22 VDD_36
N21 CV32 CV686 Use virtual Symbol for diff value
FBVDDQ_23
R21
FBVDDQ_24
T21
B FBVDDQ_25 B
V21 +1.25VGS
FBVDDQ_26
W21
FBVDDQ_27
H24
FBVDDQ_15
H26
FBVDDQ_16
J21
FBVDDQ_17
K21
FBVDDQ_18
CV4788
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
CV4785

CV4786

CV4787

CV4789

CV4790

1 1 1 1 1 1 @
N18S-G5-A1_BGA603
OPT_NS@

OPT_NS@

OPT@

OPT@

OPT_NS@

OPT_NS@

2 2 2 2 2 2

FBVDDQ Decouling

MLCC N18/GB2E-64 location

+1.25VGS 0.47uF X6S 0201 24

1.0uF X6S 0201/0402 0 Under

D22 RV2204 1 OPT@ 2 40.2_0402_1% CALIBRATION PIN GDDR6 10uF X6S 0603 4
FB_CAL_PD_VDDQ

10uF X6S 0603 2

FB_CAL_PU_GND
C24 RV2205 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PD_VDDQ 40.2Ohm
Near
A B25 RV2206 1 OPT@ 2 40.2_0402_1% FB_CAL_x_PU_GND 40.2Ohm 22uF X6S 0603 5 A
FB_CAL_TERM_GND

Place near balls

FB_CAL_xTERM_GND 40.2Ohm

@
Security Classification LC Future Center Secret Data Title
N18S-G5-A1_BGA603
Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_+VGA_CORE,FBVDDQ
Date: Thursday, May 28, 2020 Sheet 22 of 61
5 4 3 2 1
 5 4 3 2 1

+1.8VGS

Under GPU Near GPU RV4784

+VDD18 1 2 1/10W_0_5%_0603 Discharge +1.25VGS
@

CV2304

CV2330
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
+5VALW

CV2301

CV2302

CV2303

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1/20W_47K_5%_0201
UV1F 1 1 1 1 1

1
14/14 VDD18

1
RV2303

OPT_NS@
GP107S TU117S

RV2302
G8 470_0402_5%

OPT_NS@

OPT_NS@
OPT_NS@

OPT_NS@

OPT_NS@
VDD18
VDD18
VDD18_1
G9 2 2 2 2 2 OPT_NS@
VDD18_2
G10

2
1V8_AON_1
G12

2
1V8_AON_2

3
D
FBVDDQ_PWR_EN# 5 QV2301B
FP_FUSE_GPU +1.8V_AON
D G D
LBSS138DW1T1G_SOT363-6

6
D
GP107S TU117S S

4
FBVDDQ_PWR_EN 2
NC AB6 FP_FUSE_GPU QV2301A OPT_NS@
FP_FUSE_SRC G
S LBSS138DW1T1G_SOT363-6

RV1200
1/16W_2.21K_1%_0402

1
Under GPU Near GPU OPTNS@

1
1 VDD_AON

CV2316
2.2U_6.3V_M_X5R_0201
RV2301 1 @ 2 0_5%_0603

OPT@

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
CV2305

CV2306

CV2317

CV2318

CV2307
2 +1.8V_AON FP_FUSE_GPU

10U 6.3V M X5R 0402

OPT@ CV2308

OPT@ CV2319
4.7U_0402_6.3V6M
2
OPT@
1 1 1 1 1 1 1 UV11
@ A2 A1 FP_FUSE_GPU
VIN Vout
N18S-G5-A1_BGA603 1 GPIO18_FP_FUSE

2.2U_6.3V_M_X5R_0201
CV2315
OPT@
B1 B2

OPT@

OPT@

OPT@

OPT@

OPT@
2 2 2 2 2 2 2 GND ON GPIO18_FP_FUSE [26]

2
2 AP22913CN4-7_X1-WLB0909-4 RV2336
OPT@ 10K_0402_5%
OPT@

1
PXE_VDD & +1.8V_AON&1.0VGS

PXS_PWREN RV2307 1 @ 2 0_0201_5% PXS_PWR_EN_R

[8] PXS_PWREN PXS_PWR_EN_R [57]
1

RV2309
100K_0201_5%
@
C C
2

DV2301 OPT@ +3VS +1.8V_AON

DGPU_PWROK 1 2 Notice the Virtual Symbol
N17:10K
2

1 2 N16:30.9K
2

RB521CM-30T2R_VMN2M-2 RV2311
RV2310 1 @ 2 1.0VGS_EN
10K_0201_5% [8,23,58] DGPU_PWROK 1.0VGS_EN [57]
10K_0201_5% @ RV2334 0_0201_5%
DV2302 OPT@
1

1
PXS_PWREN 2 @ +5VALW +1.0VGS
1

1 @ CV2314
1.8VGS_PWR_EN RV2312 1 @ 2 3 PXE_VDD_EN RV2313 2 1 0_0402_5% PXE_VDD_EN_R RV2335 1 @ 2 0_0201_5% 0.1U_0201_25V6-K

2
0_0201_5%
LBAT54AWT1G_SOT323-3
2

OPT@ 2

1
RV2314

1
10K_0201_5% D2301 @ CV2310 RV2317
RV2315 RV2316
@ 0.22U_6.3V_K_X5R_0402 5.11_0805_1%
1 47K_0402_5% 5.11_0805_1%
1 2 @ OPT_NS@
1

OPT_NS@ OPT_NS@

2
1 2

2
RB521CM-30T2R_VMN2M-2

1
+VGA_CORE&+1.25VGS

D
+1.0VGS_PWR_EN# 2 QV2306
G
AO3402_SOT-23-3
OPT_NS@

S
+3VS

3
1
D
B B
1

PXE_VDD_EN_R 2 QV2307
RV2318 G LBSS139WT1G_SC70-3
10K_0402_5% OPT_NS@ S

3
OPT@
OPT@
DV2303
2

PXS_PWREN RV2321 1 @ 2 0_0201_5% 2

1
1.8VGS_PWR_EN RV2323 1 @ 2 0_0201_5% 3 NVVDD_EN
[26,47] 1.8VGS_PWR_EN NVVDD_EN [58]

+1.8VGS RV2324 1 2 0_0201_5% LBAT54AWT1G_SOT323-3

1

@
RV2325
100K_0201_5%
RV4785 1 @ 2 0_0201_5% @
2

+5VALW +VGA_CORE

1
RV2327
47K_0402_5% RV2328
OPT_NS@ 10_0603_5%
OPT_NS@

3 2
D
@ DV2304 NVVDD_EN# 5 QV2303B
FB_GC6_EN_R RV2329 2 1 0_0402_5% GC6_EN 2 G LBSS138DW1T1G_SOT363-6
[6,8,26] FB_GC6_EN_R

6
1 FBVDDQ_PWR_EN D OPT_NS@
FBVDDQ_PWR_EN [57] S

4
3 NVVDD_EN 2 QV2303A
GC6@
G
DGPU_PWROK RV2330 1 @ 2 10K_0402_5% BAV70W-7-F_SOT323-3
LBSS138DW1T1G_SOT363-6
S

1
[8,23,58] DGPU_PWROK
OPT_NS@

A 1.0VGS_PG RV2331 1 @ 2 0_0201_5% A

[57] 1.0VGS_PG
1

RV2333
1

200K_0402_5%
OPT_NS@ CV2313 GC6@
0.1u_0201_10V6K
2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_AON/MAIN PWR/SEQUENCE
Date: Monday, August 03, 2020 Sheet 23 of 61
5 4 3 2 1
 5 4 3 2 1

UV1I
13/14 GND

D D
A2 K11
GND_001 GND_059
AB17 K13
GND_006 GND_060
AB20 K15
GND_007 GND_061
AB24 K17
GND_008 GND_062
AC2 L10
GND_010 GND_063
AC22 L12
GND_011 GND_064
AC26 L14
GND_012 GND_065
AC5 L16
GND_013 GND_066
AC8 L18
GND_014 GND_067
AD12 L5
GND_015 GND_071
AD13 M11
GND_016 GND_072
A26 M13
GND_002 GND_073
AD15 M15
GND_017 GND_074
AD16 M17
GND_018 GND_075
AD18 N10
GND_019 GND_076
AD19 N12
GND_020 GND_077
AD21 N14
GND_021 GND_078
AD22 N16
GND_022 GND_079
AE11 N18
GND_023 GND_080
AE14 P11
GND_024 GND_081
AE17 P13
GND_025 GND_082
AE20 P15
GND_026 GND_083
AB11 P17
GND_004 GND_084
AF1 P23
GND_027 GND_086
AF11 P26
GND_028 GND_087
AF14 R10
GND_029 GND_089
AF17 R12
GND_030 GND_090
AF20 R14
GND_031 GND_091
AF23 R16
GND_032 GND_092
AF5 R18
GND_033 GND_093
AF8 T11
GND_034 GND_094
AG2 T13
GND_035 GND_095
AG26 T15
GND_036 GND_096
AB14 T17
GND_005 GND_097
B1 U10
GND_037 GND_098
B11 U12
GND_038 GND_099
B14 U14
GND_039 GND_100
C B17 U16 C
GND_040 GND_101
B20 U18
GND_041 GND_102
B23 U23
GND_042 GND_104
B27 U26
GND_043 GND_105
B5 V11
GND_044 GND_107
B8 V13
GND_045 GND_108
E11 V15
GND_046 GND_109
E14 V17
GND_047 GND_110
E17 Y2
GND_048 GND_111
E2 Y23
GND_049 GND_112
E20 Y26
GND_050 GND_113
E22 Y5
GND_051 GND_114
E25 AA7
GND_052 GND_003
E5 AB7
GND_053 GND_009
E8
GND_054

OPTIONAL GND:

XVDD AREA
H2 P2
GND_055 GND_085
H5 P5
GND_058 GND_088
L2 U2
GND_068 GND_103
U5
GND_106
PCB
ADR/CMD

PWR
H23 REFERENCE L23
GND_056 GND_069
H25 L25
GND_057 GND_070

@
N18S-G5-A1_BGA603
B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_GND
Date: Thursday, May 28, 2020 Sheet 24 of 61
5 4 3 2 1
 5 4 3 2 1

UV1J
4/14 IFPAB

UV1D DVI HDMI DP

5/14 NC SL/DL

AC4 UV1K
IFPA_L3_N
TXC/TXC AC3 10/14 MISC2
IFPA_L3
AA15 AA6
NC_2 IFPAB_RSET
AB8 TXD0/0 Y3
NC_4 IFPA_L2_N
AD10 Y4
AD7 NC_5 IFPA_L2
D12 ROM_CS0#
D NC_6 ROM_CS_N D
AE22
AE3 NC_7
AA2 B12 ROM_SI
TXD1/1 ROM_SI [29]
AE4 NC_8
W7 IFPA_L1_N
AA3 ROM_SI
A12 ROM_SO
NC_9 IFPAB_PLLVDD IFPA_L1 ROM_SO ROM_SCLK ROM_SO [29]
AF2 STRAP0 D1 C12
NC_10 [29] STRAP0 STRAP0 ROM_SCLK ROM_SCLK [29]
AF22 STRAP1 D2
NC_11 [29] STRAP1 STRAP1
AF3 TXD2/2 AA1 STRAP2 E4
NC_12 IFPA_L0_N [29] STRAP2 STRAP2
AF4 AB1 STRAP3 E3
NC_13 IFPA_L0 [29] STRAP3 STRAP3
AG3 STRAP4 D3
NC_14 [29] STRAP4 STRAP4
D10 STRAP5 C1
NC_15 [29] STRAP5 STRAP5
E10 AA5
NC_16 IFPA_AUX_SDA_N
F6 AA4
NC_21 IFPA_AUX_SCL
W5
NC_22
F5 D11 RV2506 1 @ 2 10K_0201_5%
NC_20 BUFRST_N
AB4
IFPB_L3_N
TXC AB5
IFPB_L3

W6 TXD0/3 AB2
IFP_IOVDD_1 IFPB_L2_N
AB3
IFPB_L2
@ Y6
IFP_IOVDD_2
N18S-G5-A1_BGA603
TXD1/4 AD2
IFPB_L1_N
AD3
IFPB_L1

@
TXD2/5 AD1
IFPB_L0_N
AE1
IFPB_L0

AD5
IFPB_AUX_SDA_N
AD4
IFPB_AUX_SCL

IFPAB
@
C +1.8V_AON C
N18S-G5-A1_BGA603
CORE_PLLVDD UV1L
9/14 XTAL_PLL

1
L6
XS_PLLVDD
M6 RV2507
SP_PLLVDD
F11 100K_0201_5%
GPCPLL_AVDD
N6 @
VID_PLLVDD

2
+1.8VGS Under GPU 150mA
LV2501
1 2 CORE_PLLVDD
TU117S GP107S
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
HCB1608KF-300T60_2P
OPT@ XTALSSIN A10 C10 XTALOUT
CV2507

CV2506

CV2510

CV2511

CV2512

2
EXT_REFCLK_FL XTAL_SSIN XTAL_OUTBUFF
30ohms (ESR=0.05) Bead RV2508
1 1 1 1 1 XTAL_IN XTAL_OUT
10U 6.3V M X5R 0402

10K_0201_5% C11 B10

10U 6.3V M X5R 0402
OPT@

XTAL_IN XTAL_OUT
OPT@

OPT@
OPT@

4.7U_0402_6.3V6M

1 @
OPT@

OPT@

OPT@

OPT@

OPT@

1
1 1 2 2 2 2 2
N18S-G5-A1_BGA603

1
RV2509
CV2515

2
CV2509

2 2 100K_0201_5%
CV2508

RV2511 1 OPT@ 2 10M_0402_5% XTAL_OUT OPT@

2
2
RV2514
0_0402_5%
YV2501 OPT@

1
XTAL_IN 1 4
OSC1 GND2

2 3 XTAL_OUT_R
GND1 OSC2

1
27MHZ_10PF_7V27000050
B B
CV2513 OPT@ CV2514
10P_0402_50V8J 10P_0402_50V8J

2
OPT@ OPT@

+1.8V_AON

+1.8V_AON

CV2518
10U 6.3V M X5R 0402
1
1
2

RV2501 @ CV2517
10K_0402_5%
2 0.1U_6.3V_K_X5R_0201
OPT@ 2 OPT@
1

UV3
ROM_CS0# RV25161 OPT@ 2 33_0402_5% ROM_CS#_R 1 8
ROM_SO ROM_SO_R CS# VCC
RV2517 2 1 0_0402_5% 2 7
@ 3 DO HOLD#
6 ROM_SCLK_R RV25191 OPT@ 2 33_0402_5% ROM_SCLK
4 WP# CLK
5 ROM_SI_R RV25181 2 33_0402_5% ROM_SI
GND DI
OPT@
W25Q80EWSNIG_SO8
OPT@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_STRAP/DP/HDMI
Date: Saturday, August 01, 2020 Sheet 25 of 61
5 4 3 2 1
 5 4 3 2 1

+1.8V_AON +1.8V_AON
+1.8V_AON UV1M GPU Address 0x9E
8/14 MISC1

2
2
RV2602
RV2601
2.2K_0402_5% QV2601A

2
TU117S GP107S 2.2K_0402_5% OPT@
TS_AVDD OPT@
RV2634 1 @ 2 F10

G1
TS_AVDD Internal Thermal Sensor OPT@ PJT7838_SOT363-6
NC D9 VGA_SMB_CLK

1
0_0201_5% 2

1
I2CS_SCL
D8 VGA_SMB_DATA VGA_SMB_CLK 1 6
I2CS_SDA S1 D1 EC_SMB_CK0 [39,45]
CV2610 OVERT# A6
1U_6.3V_K_X5R_0201 AE2 OVERT
A9 I2CC_SCL
OPT@ 1 TS_VREF I2CC_SCL
B9 I2CC_SDA
I2CC_SDA

CV2601
D D

1
@ E12
THERMDN
C9 I2CB_SCL

5
QV2601B OPT@
0.1u_0201_10V6K F12 I2CB_SCL
C8 I2CB_SDA

G2
THERMDP I2CB_SDA
PJT7838_SOT363-6
VGA_SMB_DATA 4 3
S2 D2 EC_SMB_DA0 [39,45]

TU117S GP107S
F3
F4 ADC_IN NC
C6 NVVDD_PWM_VID PU AT EC SIDE, +3VS AND 4.7K
ADC_IN_N NC GPIO0 FB_GC6_EN NVVDD_PWM_VID [58]
B2
PLT_RST_VGA# @ GPIO1 GPU_EVENT#_R
RV2605 1 2 56_0402_5% D6
GPIO2
C7 TEST_1 1
GPIO3 1.8VGS_PWR_EN_R RV2632 1 TV2601
1 F9 2 0_0402_5% 1.8VGS_PWR_EN
GPIO4 1.8VGS_PWR_EN [23,26,47]
CV2602 A3 @
220P_0201_25V7-K GPIO5
A4 PSI_VGA
GPIO6 TEST_2 PSI_VGA [58]
@ B6 1
TV2606
2

2 GPIO7
E9 VRAM_VDDQ_ADJ
GPIO8 VGA_ALERT# VRAM_VDDQ_ADJ [57] +1.8V_AON +3VALW +3VS
F8
GPIO9
C5 GPIO10_FBVREF_ALTV
3 1 GPIO10
E7 GPIO10_FBVREF_ALTV [27]

2
OVERT#
WRST# [45] GPIO11 VGA_AC_DET_R DV2601 2
D7 1 RV2606
GPIO12 VGA_AC_DET [45]
1 B4

2
CV2603 GPIO13
B3 OPT@RB521CM-30T2R_VMN2M-2 RV2609 10K_0201_5%
QV2604 GPIO14
C3 RV2608 10K_0402_5%
0.01U_0201_10V6K GC6@
GPIO15 FB_GC6_EN_R

1
@ LSI1012XT1G_SC-89-3 D5 10K_0201_5% GC6@
2 GPIO16 FB_GC6_EN_R [6,8,23]
@ D4
GPIO17
C2 GPIO18_FP_FUSE

1
GPIO18 GPIO18_FP_FUSE [23]
F7

3
GPIO19 @ GC6@ QV2602B
E6

D2
GPIO20
C4 5
GPIO21 PJT7838_SOT363-6
A7 G2
GPIO22 +3VS
B7
GPIO23

S2
6

4
@ +3VALW QV2602A

D1
FB_GC6_EN 2
N18S-G5-A1_BGA603 G1
PJT7838_SOT363-6

2
C RV2636 C
10K_0402_5%

S1
2
2
RV2635 OPT@
10K_0402_5% RV2612 GC6@

1
OPT@ 10K_0402_5%

1
UV1N GC6@
1.8VGS_PWR_EN
3/14 JTAG

1
1
1.8VGS_PWR_EN [23,26,47]

1 AE5
TV2602 JTAG_TCK
1 AE6
TV2603 JTAG_TDI

3
1 AF6 GC6@ QV2607B
TV2604 JTAG_TDO
1 AD6

D2
TV2605 JTAG_TMS
10K_0402_5% 2 OPT@ 1 RV2614 AG4 5 PJT7838_SOT363-6
JTAG_TRST_N G2
10K_0402_5% 2 OPT@ 1 RV2615 TESTMODE AD9
NVJTAG_SEL FB_GC6_EN RV2607 1 2 0_0201_5% FB_GC6_EN_R

S2
@

4
6
QV2607A

D1
1.8VGS_PWR_EN_R 2
G1
PJT7838_SOT363-6

S1
GC6@

1
@
N18S-G5-A1_BGA603 +1.8V_AON
+1.8V_AON
+1.8V_AON

0.1U_6.3V_K_X5R_0201
2
RV2616 1
2.2K_0404_4P2R_5%

@
10K_0402_5%

CV2604
I2CB_SCL 2 3 GC6@
B I2CB_SDA B
1 4

1
OPT@ 2

2
RPV2

2.2K_0404_4P2R_5%
I2CC_SCL 2 3 GPU_EVENT#_R 3 1 GPU_EVENT#
I2CC_SDA GPU_EVENT# [8]
1 4
OPT@
RPV3 GC6@
QV2606
LSI1012XT1G_SC-89-3
+3VS VRAM_VDDQ_ADJ RV26171 @ 2 10K_0402_5%

RV2621 1 2 0_0201_5%
+1.8V_AON RV47831 OPT@ 2 10K_0402_5% @

GPIO10_FBVREF_ALTV RV2603 1 OPT@ 2 10K_0201_5%

2

RV2629
10K_0402_5%
0.1U_6.3V_K_X5R_0201

OPT@
1

1
OPT@

+1.8V_AON
CV2605
5

UV2603 2 1.8VGS_PWR_EN_R RV26181 OPT@ 2 10K_0402_5%

PLT_RST# 1
P

[11,37,40,42,45] PLT_RST# B SYS_PEX_RST_MON#

4 RV2631 2 1 0_0402_5% OVERT# RV26191 OPT@ 2 10K_0402_5%
Y PLT_RST_VGA# [20]
2 @
[8] PXS_RST# A VGA_ALERT#
G

RV26201 OPT@ 2 10K_0402_5%

MC74VHC1G09DFT2G_SC70-5
3

OPT@ VGA_AC_DET_R RV26221 OPT@ 2 100K_0402_5%

1

PSI_VGA RV26231 @ 2 10K_0402_5%

RV2633 RV2630
100K_0402_5% 100K_0402_5%
A @ A
OPT@
2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_GPIO/JTAG
Date: Saturday, August 01, 2020 Sheet 26 of 61
5 4 3 2 1
 5 4 3 2 1

UV4D
N18S_GDDR6_A_[31_0] UV4C
COMMON

+1.25VGS COMMON

[21,28] FBA_CMD[0..33]
A11 A1 UV4B FBA_CMD0 H3 K1 +FBA_VREFC
VSS_1 VDD_1 FBA_CMD9 CA0_A VREFC
A13 A14 UV4A G11
A2 VSS_2 VDD_2
E10 NORMAL FBA_CMD8 G4 CA1_A

A4 VSS_3 VDD_3
E5 FBA_CMD32 H12 CA2_A
VSS_4 VDD_4 [21] FBA_D[0..15] NORMAL [21] FBA_D[16..31] FBA_CMD7 CA3_A
B1 H13 x16 x8 H5
B14 VSS_5 VDD_5
H2 FBA_D6 G2 FBA_D31 N2 FBA_CMD11 H10 CA4_A
VSS_6 VDD_6 FBA_D1 DQ7_A FBA_D30 DQ6_B FBA_CMD15 CA5_A
C10 L13 B3 P3 J12
C12 VSS_7 VDD_7
L2 FBA_D7 F2 DQ2_A FBA_D28 M2 DQ4_B FBA_CMD14 J11 CA6_A
D VSS_8 VDD_8 FBA_D3 DQ6_A BYTE3 FBA_D29 DQ7_B FBA_CMD3 CA7_A D
C3 P10 E3 P2 J4
C5 VSS_9 VDD_9
P5 FBA_D2 B4 DQ4_A FBA_D26 U3 DQ5_B FBA_CMD1 J3 CA8_A
VSS_10 VDD_10 BYTE0 FBA_D4 DQ0_A FBA_D25 DQ2_B FBA_CMD6 CA9_A
D1 V1 B2 V3 J5
VSS_11 VDD_11 FBA_D5 DQ3_A FBA_D24 DQ1_B FBA_CMD10 CABI_n_A
D12 V14 E2 U4 G10
D14 VSS_12 VDD_12 FBA_D0 A3 DQ5_A FBA_D27 U2 DQ0_B CKE_n_A
VSS_13 DQ1_A DQ3_B
D3 N5
E11 VSS_14 FBA_EDC0 C2 FBA_EDC3 T2 TCK
VSS_15 +1.25VGS [21] FBA_EDC0 FBA_DBI0 EDC0_A [21] FBA_EDC3 FBA_DBI3 EDC0_B
E4 D2 R2 F10
VSS_16 [21] FBA_DBI0 DBI0_n_A [21] FBA_DBI3 DBI0_n_B TDI
F1 N10
F12 VSS_17 FBA_WCK01 D4 FBA_WCKB23 R4 TDO
VSS_18 [21] FBA_WCK01 FBA_WCK01# WCK_t_A [21] FBA_WCKB23 FBA_WCKB23# NC3
F14 B10 D5 R5 F5
F3 VSS_19 VDDQ_1
B5 [21] FBA_WCK01# WCK_c_A [21] FBA_WCKB23# NC4 FBA_CMD4 L3 TMS
G1 VSS_20 VDDQ_2
C1 FBA_D19 P13 FBA_CMD12 M11 CA0_B
VSS_21 VDDQ_3 FBA_D18 DQ13_B FBA_CMD5 CA1_B
G12 C11 x16 x8 U13 M4
G14 VSS_22 VDDQ_4
C14 FBA_D8 B11 FBA_D16 M13 DQ11_B FBA_CMD13 L12 CA2_B
VSS_23 VDDQ_5 FBA_D11 DQ8_A
NC BYTE2 FBA_D17 DQ15_B FBA_CMD7 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6
E1 FBA_D14 E13 DQ15_A FBA_D21 U12 DQ14_B FBA_CMD11 L10 CA4_B
NC
H4 VSS_25 VDDQ_7
E14 FBA_D10 F13 DQ13_A FBA_D20 P12 DQ10_B FBA_CMD15 K12 CA5_B
VSS_26 VDDQ_8 BYTE1 FBA_D9 DQ14_A NC
FBA_D22 DQ12_B FBA_CMD14 CA6_B
L11 F11 E12 NC V12 K11
L4 VSS_27 VDDQ_9
F4 FBA_D12 B12 DQ12_A FBA_D23 U11 DQ9_B FBA_CMD3 K4 CA7_B
NC
M1 VSS_28 VDDQ_10
H1 FBA_D15 B13 DQ10_A
NC
DQ8_B FBA_CMD1 K3 CA8_B

M12 VSS_29 VDDQ_11

H14 FBA_D13 A12 DQ11_A
NC
FBA_EDC2 T13 FBA_CMD6 K5 CA9_B
J14 FBA_ZQ_1_A RV1290 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 DQ9_A [21] FBA_EDC2 FBA_DBI2 EDC1_B FBA_CMD10 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBA_EDC1 [21] FBA_DBI2 DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBA_ZQ_1_B RV1122 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 [21] FBA_EDC1 FBA_DBI1 EDC1_A FBA_WCK23 ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 [21] FBA_DBI1 DBI1_n_A NC [21] FBA_WCK23 FBA_WCK23# WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBA_WCKB01 [21] FBA_WCK23# WCK_c_B
N14 L1 D11 NC
VSS_35 VDDQ_17 [21] FBA_WCKB01 FBA_WCKB01# NC1
N3 L14 D10 NC
VSS_36 VDDQ_18 [21] FBA_WCKB01# NC2 FBA_CMD2
P11 N11 J1 RESET_n
VSS_37 VDDQ_19
P4 N4 MT61K256M32JE-14-A_FBGA180
VSS_38 VDDQ_20
R1 P1 MT61K256M32JE-14-A_FBGA180 @
VSS_39 VDDQ_21
R12 P14 @
R14 VSS_40 VDDQ_22
T1 FBA_CLK0# K10
[21] FBA_CLK0# CK_c
VSS_41 VDDQ_23 FBA_CLK0
R3 T11 J10
VSS_42 VDDQ_24 [21] FBA_CLK0 CK_t
T10 T14 G5
VSS_43 VDDQ_25 NC5
T12 T4
VSS_44 VDDQ_26
T3 U10 M5
VSS_45 VDDQ_27 NC6
C T5 U5 C
U1 VSS_46 VDDQ_28 NV:4x1uF
VSS_47
U14
VSS_48
V11
VSS_49
V13
VSS_50 +1.8V_AON
V2 +1.8V_AON
VSS_51
V4 CLOSE TO DRAM
VSS_52
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VPP_1
A5 @
VPP_2
V10 1 1 1 1 1 1
VPP_3
CV588
4.7U_0402_6.3V6M

V5
VPP_4
OPT@

OPT@

OPT@

OPT@
CV589

CV592

CV1523

CV1524

CV1525
OPT_NS@

MT61K256M32JE-14-A_FBGA180
2 2 2 2 2 2
@

OPT@
+1.25VGS

NV:6x10uF 0402 18x1uF 0201 6x22uF,Reserve 2x220uF 5x22uF 0805

1
RV97
549_0402_1%
@
4x10uF 18x1uF

2
+1.25VGS 6x22uF,2x10uF +1.25VGS 1 @ 2 +FBA_VREFC
RV1291 +FBA_VREFC [28]
AROUND DRAM CLOSE TO DRAM 16 mil

1
931_0402_1% 1
RV99 CV1521
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

CV587

CV576

CV577

CV578

CV582

CV579

CV580

CV581

CV585

CV583

CV584
1K_0402_1% 820P_0402_25V7
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
CV238 OPT_NS@

CV220 OPT_NS@

CV221 OPT_NS@

CV228 OPT_NS@

CV491 OPT_NS@

CV586 OPT_NS@

1
OPT@

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
1

2
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
2 QV48
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
[26] GPIO10_FBVREF_ALTV
2

B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 B
CV234

CV235

CV236

CV237

CV563

CV178

CV490

LSI1012XT1G_SC-89-3
@

3
Vgs(th)¡Ü0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
+1.25VGS +1.25VGS
1K OHM PULL-DOWN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLACE OF THE 1.33K
FOR RV99
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV564

CV565

CV566

CV567

CV571

CV568

CV569

CV570

CV575

CV572

CV573

CV574

CV494OPT_NS@

CV242OPT_NS@

CV243OPT_NS@
1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

CV492

CV493

CV239

CV240

CV241
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV245

CV244

CV246

CV247

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18S_GDDR6_A_[31_0]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-ITL
Date: Thursday, May 28, 2020 Sheet 27 of 73
5 4 3 2 1
 5 4 3 2 1

UV5D
N18S_GDDR6_A_[63_32] UV5C
COMMON

+1.25VGS COMMON
UV5A
[21,27] FBA_CMD[0..33]
UV5B
A11 A1 FBA_CMD20 H3 K1 +FBA_VREFC
VSS_1 VDD_1 [21] FBA_D[32..47] NORMAL FBA_CMD28 CA0_A VREFC +FBA_VREFC [27]
A13 A14 NORMAL G11
A2 VSS_2 VDD_2
E10 FBA_D37 G2 FBA_CMD21 G4 CA1_A
VSS_3 VDD_3 FBA_D32 DQ7_A [21] FBA_D[48..63] FBA_CMD29 CA2_A 1
A4 E5 B3 x16 x8 H12 CV172
B1 VSS_4 VDD_4
H13 FBA_D36 F2 DQ2_A FBA_D56 N2 FBA_CMD23 H5 CA3_A
820P_0402_25V7
B14 VSS_5 VDD_5
H2 FBA_D33 E3 DQ6_A FBA_D62 P3 DQ6_B FBA_CMD27 H10 CA4_A
@
VSS_6 VDD_6 BYTE4 FBA_D38 DQ4_A FBA_D57 DQ4_B FBA_CMD30 CA5_A 2
C10 L13 B4 M2 J12
C12 VSS_7 VDD_7
L2 FBA_D39 B2 DQ0_A FBA_D59 P2 DQ7_B FBA_CMD31 J11 CA6_A
D VSS_8 VDD_8 FBA_D35 DQ3_A BYTE7 FBA_D63 DQ5_B FBA_CMD19 CA7_A D
C3 P10 E2 U3 J4
C5 VSS_9 VDD_9
P5 FBA_D34 A3 DQ5_A FBA_D60 V3 DQ2_B FBA_CMD17 J3 CA8_A
D1 VSS_10 VDD_10
V1 DQ1_A FBA_D61 U4 DQ1_B FBA_CMD22 J5 CA9_A
VSS_11 VDD_11 FBA_EDC4 FBA_D58 DQ0_B FBA_CMD26 CABI_n_A
D12 V14 C2 U2 G10
VSS_12 VDD_12 [21] FBA_EDC4 FBA_DBI4 EDC0_A DQ3_B CKE_n_A
D14 D2
VSS_13 [21] FBA_DBI4 DBI0_n_A FBA_EDC7
D3 T2 N5
VSS_14 FBA_WCK45 [21] FBA_EDC7 FBA_DBI7 EDC0_B TCK
E11 D4 R2
VSS_15 +1.25VGS [21] FBA_WCK45 FBA_WCK45# WCK_t_A [21] FBA_DBI7 DBI0_n_B
E4 D5 F10
VSS_16 [21] FBA_WCK45# WCK_c_A FBA_WCKB67 TDI
F1 R4 N10
VSS_17 [21] FBA_WCKB67 FBA_WCKB67# NC3 TDO
F12 R5
VSS_18 [21] FBA_WCKB67# NC4
F14 B10 x16 x8 F5
F3 VSS_19 VDDQ_1
B5 FBA_D43 B11 NC
FBA_D51 P13 FBA_CMD16 L3 TMS
G1 VSS_20 VDDQ_2
C1 FBA_D47 G13 DQ8_A FBA_D49 U13 DQ13_B FBA_CMD25 M11 CA0_B
NC
VSS_21 VDDQ_3 FBA_D44 DQ15_A FBA_D50 DQ11_B FBA_CMD24 CA1_B
G12 C11 E13 NC M13 M4
G14 VSS_22 VDDQ_4
C14 FBA_D45 F13 DQ13_A FBA_D48 N13 DQ15_B FBA_CMD33 L12 CA2_B
VSS_23 VDDQ_5 BYTE5 FBA_D40 DQ14_A NC
FBA_D52 DQ14_B FBA_CMD23 CA3_B
G3 C4 E12 NC BYTE6 U12 L5
H11 VSS_24 VDDQ_6
E1 FBA_D41 B12 DQ12_A FBA_D55 P12 DQ10_B FBA_CMD27 L10 CA4_B
NC
H4 VSS_25 VDDQ_7
E14 FBA_D46 B13 DQ10_A FBA_D53 V12 DQ12_B FBA_CMD30 K12 CA5_B
NC
VSS_26 VDDQ_8 FBA_D42 DQ11_A FBA_D54 DQ9_B FBA_CMD31 CA6_B
L11 F11 A12 NC U11 K11
L4 VSS_27 VDDQ_9
F4 DQ9_A DQ8_B FBA_CMD19 K4 CA7_B
M1 VSS_28 VDDQ_10
H1 FBA_EDC5 C13 GND
FBA_EDC6 T13 FBA_CMD17 K3 CA8_B
[21] FBA_EDC5 FBA_DBI5 [21] FBA_EDC6 FBA_DBI6 FBA_CMD22
M12 VSS_29 VDDQ_11
H14 D13 EDC1_A
R13 EDC1_B
K5 CA9_B
J14 FBA_ZQ_2_A RV1177 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 [21] FBA_DBI5 DBI1_n_A [21] FBA_DBI6 DBI1_n_B FBA_CMD26 CABI_n_B ZQ_A
M14 J13 NC M10
VSS_31 VDDQ_13 FBA_WCKB45 FBA_WCK67 CKE_n_B
M3 J2 D11 NC R11 K14FBA_ZQ_2_B RV1178 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 [21] FBA_WCKB45 FBA_WCKB45# NC1 [21] FBA_WCK67 FBA_WCK67# WCK_t_B ZQ_B
N1 K13 D10 NC R10
VSS_33 VDDQ_15 [21] FBA_WCKB45# NC2 [21] FBA_WCK67# WCK_c_B
N12 K2
VSS_34 VDDQ_16
N14 L1
VSS_35 VDDQ_17
N3 L14 MT61K256M32JE-14-A_FBGA180
VSS_36 VDDQ_18 FBA_CMD18
P11 N11 @ MT61K256M32JE-14-A_FBGA180 J1 RESET_n
VSS_37 VDDQ_19
P4 N4 @
VSS_38 VDDQ_20
R1 P1
VSS_39 VDDQ_21
R12 P14
R14 VSS_40 VDDQ_22
T1 FBA_CLK1# K10
[21] FBA_CLK1# CK_c
VSS_41 VDDQ_23 FBA_CLK1
R3 T11 J10
VSS_42 VDDQ_24 [21] FBA_CLK1 CK_t
T10 T14 G5
VSS_43 VDDQ_25 NC5
T12 T4
VSS_44 VDDQ_26
T3 U10 M5
VSS_45 VDDQ_27 NC6
C T5 U5 C
VSS_46 VDDQ_28
U1
VSS_47
U14
VSS_48
V11
V13 VSS_49 NV:4x1uF 0402
VSS_50 +1.8V_AON
V2 +1.8V_AON
VSS_51
V4 CLOSE TO DRAM
VSS_52
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VPP_1
A5 @
CV597

CV598

CV600

CV1526

CV1527

OPT@ CV1528
VPP_2
V10 1 1 1 1 1 1 1
VPP_3
CV599
4.7U_0402_6.3V6M

V5
VPP_4
OPT@

OPT@

OPT@
OPT_NS@

OPT_NS@

MT61K256M32JE-14-A_FBGA180
2 2 2 2 2 2 2
OPT@
@

6x22uF,2x10uF 4x10uF 18x1uF

+1.25VGS +1.25VGS
AROUND DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

OPT@

OPT@

OPT@

OPT@

OPT@
CV617

CV620

CV616

CV619

CV618

CV621

CV636

CV623

CV624

CV625

CV628

CV627

CV626

CV629

CV632

CV630

CV631
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

CV609 OPT_NS@

CV635 OPT_NS@
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@
2

B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 B
CV633

CV634

CV611

CV610

CV608

+1.25VGS +1.25VGS
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

OPT@

OPT@
CV622

CV601

CV602

CV603

CV607

CV604

CV605

CV606

CV614

CV612

CV613

CV615

CV595

CV638

CV637

CV639

CV642

CV641

CV640

CV643

CV593

CV644 OPT_NS@
1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

OPT_NS@

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CV645

CV594

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 N18S_GDDR6_A_[63_32]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 2.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550-ITL
Date: Thursday, May 28, 2020 Sheet 28 of 73
5 4 3 2 1
 5 4 3 2 1

+1.8V_AON
X76

2
RV2901 RV2902 RV2903
100K_0402_5% 100K_0402_5% 100K_0402_5% VRAMCFG
@ @ @
GPU VRAM FB Memory (GDDR6) Starp STRAP2 STRAP1 STRAP0

1
D D
[25] STRAP0 STRAP0
[25] STRAP1 STRAP1
STRAP2 Samsung 8Gb K4Z80325BC-HC14 0x0 L L L
[25] STRAP2
2GB
Micron 8Gb MT61K256M32JE-14:A 0x1 L L H

2
RV2904 RV2905 RV2906
100K_0402_5% 100K_0402_5% 100K_0402_5%
@ @ @

1
+1.8V_AON

STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

2

2
RV2907 RV2908 RV2909
100K_0402_5% 100K_0402_5% 100K_0402_5% L L L 0 0 0 0
@ @ @
1

1
1: SMB_ALT_ADDR ENABLE SMB_ALT_ADDR DEVID_SEL
C STRAP3 C
[25] STRAP3
[25] STRAP4 STRAP4 0: SMB_ALT_ADDR DISABLE
[25] STRAP5 STRAP5 0 Single GPU configurations 0 Original PCIE DEVID
1: DEVID_SEL REBRAND
1 Dual GPU configurations 1 Alternate "re-band"DEVID
0: DEVID_SEL ORIGNAL
2

RV2910 RV2911 RV2912

100K_0402_5% 100K_0402_5% 100K_0402_5% 1: PCIE_CFG LOW POWER
OPT@ OPT@ OPT@ VGA_DEVICE
0: PCIE_CFG HIGH POWER
PCIE_CFG
1

0 3D Device (Class Code 302)

0 (Default)
1: VGA_DEVICE ENABLE
1 3D Device (Class Code 300)
0: VGA_DEVICE DISABLE 1

B B
+1.8V_AON
1

RV2914
0_0402_5%
@
2
2

ROM_SO ROM_SI ROM_SCLK FS_OVERT*Function

RV2915 RV2916 RV2917
100K_0402_5% 10K_0402_1% 100K_0402_5%
@ @ @ FS_OVERT*function ENABLE
N18S-G5 L L L
1

ROM_SI
[25] ROM_SI ROM_SO
[25] ROM_SO ROM_SCLK
[25] ROM_SCLK
2

RV2918 RV2919 RV2920

100K_0402_5% 10K_0402_1% 100K_0402_5%
OPT@ OPT@ OPT@
1

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. GPU_Strap
Date: Saturday, August 01, 2020 Sheet 29 of 61
5 4 3 2 1
 5 4 3 2 1

+3VL
+3VL

RTC

1
RI3002 RI3001
100K_0402_5% 0_0402_5%
@

2
VCCRTC 3.2V
@

1
NOV_BTN# RI3005 2 1 0_0402_5%
NOVO# [45]
RI3004
+3VL DI3001 @ 45.3K_0402_1% RTC_VCC
D D
BAT54CW_SOT323-3

2
2

1
RI3003 1
100K_0402_5%
3 2 RI3007 1

2
ON/OFF RI30061 2 ON/OFFBTN# 1 1K_0603_5%
[45] ON/OFF
2.2K_0402_5%
CI3003
@ 1U_6.3V_M_X5R_0201
2

1
TP4504
@

+3VALW +3VALW_IO

@ Redriver
RI3008 2 1 0_0402_5%

BUTTON

+USB_VCCB

C +USB_VCCA C
+5VALW

UI3001
5 1 +USB_VCCB
IN OUT
1
2 JPIO
GND
CI3004 1
RI3009 1 @ 2 0_0201_5% USB_ON#_R 4 3 0.1u_0201_10V6K 2 1
[45] USB_ON# ENB OCB USB_OC1# [4] 2 2
3
3
SY6288D20AAC_SOT23-5 4
4
1 5
5
6
6
CI3001 7
USB POWER SW @
2
0.1u_0201_10V6K 8
9
7
8
USB30_RX_N2 10 9
[9] USB30_RX_N2 USB30_RX_P2 10
edward@0624 11
[9] USB30_RX_P2 12 11
USB30_TX_N2 12
13
[9] USB30_TX_N2 USB30_TX_P2 13
14
[9] USB30_TX_P2 14
15
USB30_TX_P1 16 15
[9] USB30_TX_P1 USB30_TX_N1 17 16
[9] USB30_TX_N1 17
18
USB Charger [9] USB30_RX_P1
USB30_RX_P1
USB30_RX_N1
19
20
18
19
[9] USB30_RX_N1 20
21
+5VALW 2.2A USB20_P1_C
USB20_N1_C
22
23
21
22
23
24
USB20_N4 25 24
UI3002 [9] USB20_N4 USB20_P4 25
26
SN1702001RTER_WQFN16_3X3 [9] USB20_P4 27 26
27
28
ILIM_HI [9] USB20_N6 28
1 16 RI3010 1 2 1/20W_20K_5%_0201 29
B IN ILIM_HI [9] USB20_P6 30 29 B
USB20_N1 2 15 ILIM_LO RI3011 1 @ 2 1/20W_20K_5%_0201 31 30
[9] USB20_N1 DM_OUT ILIM_LO 31
220_0402_1% 32
USB20_P1 FPR_LED_AMBER# 1 32
3 14 [45] FPR_LED_AMBER#
2 33
[9] USB20_P1 DP_OUT GND
34 33
+USB_VCCA ON/OFFBTN# RI3016
ILIM_SEL 4 13 NOV_BTN# 35 34
ILIM_SEL FAULT USB_OC0# [9] 35
[45] PWR_LED_WIT#
36
USB_CHG_EN 5 12 37 36
[45] USB_CHG_EN EN OUT RTC_VCC 37
@ 1 +3VALW_IO 38
CHG_MOD1 2 1 0_0402_5% CLT1 6 11 USB20_N1_C 39 38
41
[45] CHG_MOD1 CLT1 DM_IN +3VS 39 GND1
RI4618 CI3005 40 42
7 10 USB20_P1_C 0.1u_0201_10V6K 40 GND2

@
CLT2 DP_IN 2
CHG_MOD3 2 1 0_0402_5% 8 9 AOU_DET#
E_PAD

[45] CHG_MOD3 CLT3

CLT3 STATUS
RI4619 ELCO_046809640410846+
1 ME@
17

CI3002
@ 0.1u_0201_10V6K
2

CLT1 CLT2 CLT3 ILIM_SEL MOD

+3VALW
* 0 0 0 X DCH OUT held low

* 1 1 1 1 CDP Data Connected and Load Detect Active

+5VALW
RI3012 1 2 10K_0201_5% AOU_DET#
AOU_DET# [45]

1 1 1 0 SDP2 Data Connected

* RI3013 2
@
1 0_0402_5% ILIM_SEL

A
* 1 1 0 X SDP1 Data Connected RI3014 1 @ 2 100K_0201_5% USB_CHG_EN A

* 0 1 0 X SDP1 Data Connected RI3015 1 @ 2 100K_0201_5% ILIM_SEL

* 1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

* 1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode

Title
Security Classification LC Future Center Secret Data
* 0 1 1 X DCP_Auto Data Disconnected and Load Detect Active
Issued Date 2018/03/15 Deciphered Date 2019/03/14 S550-IIL
* 0 0 1 X DCP_Auto Data Disconnected and Load Detect Active THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
Size Document Number Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. IO CONN
Date: Saturday, August 01, 2020 Sheet 30 of 61
5 4 3 2 1
 5 4 3 2 1

+1.8V_AUDIO
DVDD_IO DVDD_IO +5VD
+1.8VALW
+5VA
Analog power for DACs, ADCs
+3VS DVDD +1.8V_AUDIO DVDD
+1.8VS

+5VD
RA6 1 @ 2 0_5%_0603

+5VA

0.1U_0201_6.3V6-K

2.2U_0402_6.3V6M
2 2

2.2U_0402_6.3V6M

0.1U_0201_6.3V6-K

CA2
RA1 1 @ 2 0_5%_0603 RA2 1 @ 2 0_5%_0603

CA1
1 2

CA3

0.1U_0201_6.3V6-K
1 1

CA6

10U_0402_6.3V6M

18

46

41

40

20
2 1

3
CA4

CA5
UA3101
2 1

PVDD2

PVDD1

AVDD1

CPVDD/AVDD2
DVDD

DVDD-IO
1 2

@
2 SPKR_MUTE#
D PDB D
14 HDA_BITCLK_AUDIO
HPOUT_L BCLK HDA_BITCLK_AUDIO [6]
27
HPOUT-L HDA_SYNC_AUDIO
Close to Pin7 15
HPOUT_R SYNC HDA_SYNC_AUDIO [6]
26
HPOUT-R @
47 RA7 2 1 100K_0402_1% +3VS
MIC2_VREFOL 28 JD2
+5VS +5VA MIC2-VREFO-L
48 JSENSE RA8 1 @ 2 0_0402_5% PLUG_IN
+5VS +5VD MIC2_VREFOR JD1
29
MIC2-VREFO-R CA7
EMC_NS@ @2 1 0.22U_6.3V_K_X5R_0201
LA1 1 2 1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
RA11 1 @ 2 0_5%_0603 BLM15PD600SN1D_2P
4 DMIC_DATA_R 0_0201_5% 2 1 RA9
@ DMIC_DATA [6,33]

1U_10V_M_X5R_0201
RING2_CONN GPIO0/DMIC-DATA12
30

CA9
1
0.1u_0201_10V6K
1

MIC2-L/RING2 DMIC_CLK_R
CA8

RA13 1 @ 2 0_5%_0603 5 0_0201_5% 2 1 RA10

0.1u_0201_10V6K
CA12

CA13
DMIC_CLK [6,33]

0.1u_0201_10V6K
CA11
RING3_CONN GPIO1/DMIC-CLK

CA10
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

1 1 31 @

1
MIC2-R/SLEEVE
@ 6
2

2 PC_BEEP 34 I2C-DATA
PCBEEP
7

2
2 2 I2C-CLK

+5VA
8
RA121 2 10K_0402_5% VDD_STB 33 NC1
5VSTB
9
NC2
LINE2-R 35
LINE2-R
10
NC3
LINE2-L 36
LINE2-L
DA1 11
EC_MUTE# NC4
1 2 @
[45] EC_MUTE# SPKR_MUTE# 12

1
NC5
LRB751V-40T1G_SOD323-2
RA15
10K_0402_5% CA14 1 1U_6.3V_K_X5R_0201
2 23 45 SPK_R+
CBP SPK-OUT-R+
RA16 1 @ 2 0_0402_5% @
24 44 SPK_R-

2
CBN SPK-OUT-R-
43 SPK_L-
SPK-OUT-L-
C C
42 SPK_L+
SPK-OUT-L+
2.2U_0402_6.3V6M 2 1 CA15 32
MIC2-CAP
13
DC DET/EAPD
2.2U_0402_6.3V6M 2 1 CA16 38
VREF

2.2U_0402_6.3V6M 1 2 CA17 19 16 SDATA_IN 33_0402_5% 2 1 RA14

LDO3-CAP SDATA-IN HDA_SDI [6]
2.2U_0402_6.3V6M 1 2 CA18 21 17 HDA_SDOUT_AUDIO
LDO2-CAP SDATA-OUT HDA_SDOUT_AUDIO [6]
DA2
@ 2.2U_0402_6.3V6M 1 2 CA19 39 CAP NEED CONFIR
PC_BEEP1 RA18 PC_BEEP LDO1-CAP
[8,45] PCH_BEEP
2 1 1 2 1 2 CA22 25
CPVEE
1K_0402_5% 0.1U_6.3V_K_X5R_0201
LRB751V-40T1G_SOD323-2 2

Thermal Pad
CAP NEED CONFIR
1

1 @ 2 0_0402_5%

AVSS1

AVSS2
RA19 CA20
RA20 10K_0402_5% 1U_6.3V_K_X5R_0201
1
ALC3287-CG_MQFN48_6X6
2

37

22

49
pin define TBD

JSPK
SPK_R+ LA2 1 EMC@ 2 BLM15PX800SN1D_2P SPK_R+_CONN
SPK_R-
SPK_L+
LA3
LA4
1 EMC@
1 EMC@
2
2
BLM15PX800SN1D_2P
BLM15PX800SN1D_2P
SPK_R-_CONN
SPK_L+_CONN 1
Speaker
1
2
HDA_SYNC_AUDIO SPK_L- SPK_L-_CONN 2
LA5 1 EMC@ 2BLM15PX800SN1D_2P 3 5
3 GND1
4 6
HDA_SDOUT_AUDIO 4 GND2

2200P_25V_K_X7R_0201

2200P_25V_K_X7R_0201
2200P_25V_K_X7R_0201
EMC_NS@

2200P_25V_K_X7R_0201
CA24

CA25
27_0402_5%HDA_BITCLK_AUDIO

CA23
RA28 1 2

CA26
HIGHS_WS33041-S0191-HF
2 2 2 2 ME@
HDA_SDI
B SPK_R+ B
RA38 1 @ 2 0_0402_5%
SPK_R-
22P_0201_258J

22P_0201_258J

33P_0201_50V8-J

33P_0201_50V8-J

RA39 1 @ 2 0_0402_5%
SPK_L+ 1 1 1 1
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

RA40 1 @ 2 0_0402_5%

EMC@

EMC@

EMC@

EMC@
1 1 1 1 SPK_L-
CA33

CA34

CA35

CA36

RA41 1 @ 2 0_0402_5%
220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
220P_25V_K_X7R_0201

2 2 2 2
CA28

CA29

220P_25V_K_X7R_0201
CA27

CA30
2 2
2
2

1 1 Audio Jack
@

1
@

DMIC_CLK_R 1
@

JHP
DMIC_DATA_R
MIC2_VREFOL RA31 2 1 2.2K_0402_5% RING2_CONN 3 G/M
HPOUT_L A_HP_OUTL_R
100P_0201_25V8J

100P_0201_25V8J

RA32 1 2 56_0402_5% 1 L
EMC@

EMC_NS@

1 1 CA38 @ 1U_6.3V_M_X5R_0201 PLUG_IN

CA31

CA32

RA21 1 @ 2 0_0402_5% LINE2-L 1 2 5

5

CA40 @ 1U_6.3V_M_X5R_0201
6
2 2 6
RA26 1 @ 2 0_0402_5% LINE2-R 1 2
A_HP_OUTR_R 2
HPOUT_R R
RA34 1 2 56_0402_5%
RA27 1 @ 2 0_0402_5% 4
MIC2_VREFOR RA36 2 1 2.2K_0402_5% RING3_CONN M/G
7
MS

100P 25V J NPO 0201

100P_0201_25V8J
RA29 1 @ 2 0_0402_5%

CA43

CA44
100P 25V J NPO 0201

100P_0201_25V8J
2 1

CA42

CA45
ATOB_063-RT04-0601
RING3_CONN 1 1
ME@
RING2_CONN
GND GNDA

EMC@
A_HP_OUTL_R 1@ 2

EMC@
A_HP_OUTR_R 2@ 2
PLUG_IN
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

RA30 CA37
A 0_0402_5% 470P_0201_50V7-K A
1

1 @ 2 1 2 @ A_HP_OUTL_R
47P_0201_25V8-J

DA7 DA3 DA4 DA5 DA6

1

1
EMC_NS@

1
CA39

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC@

@
RA33 1 2 100K_0402_1%
2
2

RA35 CA41
0_0402_5% 470P_0201_50V7-K
2

1 @ 2 1 2 @ A_HP_OUTR_R

Security Classification LC Future Center Secret Data Title

RA37
10K_0402_5%
1 @ 2
Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. ALC-3287
Date: Sunday, August 02, 2020 Sheet 31 of 61
5 4 3 2 1
 A B C D E

1 1

2 2

3 3

4 4

ALC-3287 Title
Security Classification LC Future Center Secret Data
Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, May 28, 2020 Sheet 32 of 61
A B C D E
 5 4 3 2 1

TOUCH SCREEN +3VS_TS

+3VS +LCDVDD +3VS

LCD POWER CIRCUIT Ton=5.5ns @5V +3VS_TS +3VS_TS

Toff=35ns @5V
UG3301 400K spec=300ns
5 1 RG3301 1 @ 2
IN OUT
1/2W_0.01_+-1%_0603_50PPM/C

4
3
2 MS@ +3VALW_PCH
GND
1 RPG1
4 3 2.2K_0404_4P2R_5% QG3303
[4] PCH_ENVDD EN OCB
@ CG3301 MS@

2
3 1

D
0.1U_6.3V_K_X5R_0201 SY6288C20AAC_SOT23-5 QG3301

1
2

1
2
RG3325 LP2301ALT1G_SOT-23-3
PCH_I2C0_SDA 1 3 Touch_I2C0_SDA MS@ 100K_0201_5%

G
2
D D

@ @

2
SSM3K15AMFV_2-1L1B RG3322 2 1 0_0402_5% RG3327 2 1 0_0402_5% VCC_TS_ON
+LCDVDD +LCDVDD_CON
1
MS@
CG3321
0.1U_6.3V_K_X5R_0201

2
RG3302 1 @ 2 0_5%_0603 QG3302 2

1 CG3303 1 CG3304 1 CG3305 1

1
PCH_I2C0_SCL Touch_I2C0_SCL

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201

33P_50V_J_NPO_0201
1 3 QG3304 @
CG3320
@ 0.1U_6.3V_K_X5R_0201

RF_NS@
2 2 2 SSM3K15AMFV_2-1L1B 2 2 MS@
[8] VCC_TS_ON
MS@
SSM3K15AMFV_2-1L1B

3
1
PCH_I2C0_SDA RG3312 1 2 0_0402_5% Touch_I2C0_SDA
[8] PCH_I2C0_SDA
@ RG3323
@ 100K_0402_5%
PCH_I2C0_SCL RG3321 1 2 0_0402_5% Touch_I2C0_SCL
[8] PCH_I2C0_SCL

2
@

Footprint is SP04000520J, it's no AVL, change PN SP040006N00

LED POWER +1.8VS

V9B+ +LEDVDD +3VS confirm touch module pin define,I2C or USB?

FG3301

2
RG3305 1 @ 2 0_5%_0603 1 2

2
10K_0201_5%

10K_0201_5%
RG336

2
10K_0201_5%

10K_0201_5%
RG3330

RG3331
3A_32V_ERBRD3R00X 0_0201_5%

RG3335

RG3332
2 1 @
C CG3309 C

1
@ CG3307 10U_0805_25V6K JEDP

MIC_OE
1

1
0.1U_25V_K_X5R_0201 +LEDVDD
1

1
1 2 UG3302 2 1
2
1 8 3
VCCA VCCB 3
4
DMIC_CLK DMIC_CLK_C 4
[6,31] DMIC_CLK 2 7 5
A0 B0 5
DISPOFF# 6
DMIC_DATA 3 6 DMIC_DATA_C 7 6
[6,31] DMIC_DATA A1 B1 +LCDVDD_CON 7
8
4 5 MIC_OE INVT_PWM 9 8
GND OE CPU_EDP_HPD 9
10
[4] CPU_EDP_HPD 10
11

1
CG3306 1 20.1U_6.3V_K_X5R_0201 EDP_AUX 12 11
FXMA2102UMX_U-MLP8_1P2X1P4 [4] CPU_EDP_AUX EDP_AUX# 12
RG3333 CG3308 1 20.1U_6.3V_K_X5R_0201 13
[4] CPU_EDP_AUX# 13
100K_0201_5% 14
EDP_TX0+ 14
CG3310 1 20.1U_6.3V_K_X5R_0201 15
DICM BOARD POWER [4]
[4]
CPU_EDP_TX0+
CPU_EDP_TX0-
CG3311 1 20.1U_6.3V_K_X5R_0201 EDP_TX0- 16 15

2
16
+3VS +3VS_CAMERA 17
CG3312 1 20.1U_6.3V_K_X5R_0201 EDP_TX1+ 18 17
FG3302 [4] CPU_EDP_TX1+ 1 20.1U_6.3V_K_X5R_0201 EDP_TX1- 19 18
W=40mils CG3313
[4] CPU_EDP_TX1- 19
RG3307 1 @ 2 0_5%_0603 1 2 20
USB20_N_CAMERA 21 20

1A_32V_ERBRD1R00X USB20_P_CAMERA 22 21
1 1 22
23
@ CG3314 CG3315 24 23
DMIC_CLK_C 24
0.1U_6.3V_K_X5R_0201 10U 6.3V M X5R 0402 25
2 2 DMIC_DATA_C 26 25
26
+DMIC_PWR
27
27
28
28
29 31
+3VS_CAMERA 29 GND1
30 32
30 GND2

+3VS RG3320 1 @ 2 0_0201_5% +DMIC_PWR

HIGHS_FC5AF301-3181H
@ ME@
RG3306 2 1 0_0402_5%
B
Camera B

LG3302 EMC_NS@
USB20_N5 4 3 USB20_N_CAMERA
[9] USB20_N5 4 3

USB20_P5 1 2 USB20_P_CAMERA
[9] USB20_P5 1 2

EXC24CH900U_4P

@
RG3308 2 1 0_0402_5%

TS DISCHARGER
+3VS_TS

+3VS_TS

JTS
pd?

1
1
+3VS +3VS 1
need confirm£¿ RG3326 2
100_0402_5% PCH_TS_RST 3 2
[8] PCH_TS_RST
1

PCH_TS_INT# 4 3
[8] PCH_TS_INT#
2

PCH_TS_STOP 5 4
RG3314 1 2
[8] PCH_TS_STOP 5
1/20W_4.7K_5%_0201 RG3316 6
PCH_ENBKL @ Touch_I2C0_SDA 6
RG33151 2 @ 1K_0402_5% QG3305 MS@ 7
[4,45] PCH_ENBKL Touch_I2C0_SCL 7
0_0201_5% @ 8
2

8
@ 9
1

@ RG3317 2 1 0_0402_5% INVT_PWM VCC_TS_ON 2 10 9

[4] PCH_EDP_PWM 10
BKOFF# RG3318 2 1 DISPOFF# 11
[45] BKOFF#
1

GND1
0_0402_5% SSM3K15AMFV_2-1L1B 12
3

GND2
RG3309
MS@
100K_0402_5% HIGHS_WS83100-S0171-HF
A A
ME@
2

DMIC_CLK INVT_PWM DISPOFF# DMIC_DATA DMIC_CLK_C

DMIC_DATA_C DMIC_CLK_C
100P 25V J NPO 0201
470P_50V_K_X7R_0201

470P_50V_K_X7R_0201

1
100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

EMC_NS@
1 1 1 1 1
100P 25V J NPO 0201
EMC_NS@

EMC_NS@

EMC_NS@ EMC_NS@ EMC_NS@

1
CG3319

EMC@ Title
2 Security Classification LC Future Center Secret Data
CG3316

CG3302

CG3322
CG3317

CG3318

2 2 2 2 2
CG3421

2 Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EDP/CAMERA/TS
Date: Sunday, August 02, 2020 Sheet 33 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS +3VS +3VS

+3VS
+3VS

1
RG3453 2 1 0_0402_5% 1 VDDIO_PS8203
1 1

1
CG3412
1U_6.3V_M_X5R_0201

CG3413

CG3414
RG3401 RG3403

0.1u_0201_10V6K

0.1u_0201_10V6K
RG3452 1 @ 2 0_5%_0603 VDD_PS8203 RG3406
1 1 1 4.7K_0402_5% 4.7K_0402_5%

CG3411
1U_6.3V_M_X5R_0201

CG3409

CG3410
@

0.1u_0201_10V6K

0.1u_0201_10V6K
4.7K_0402_5%
+1.8VS 2 2 2

2
@

2
2 2 2 @
RG3457 2 1 0_0402_5%
HDMI_EQ HDMI_PRE
HDMI_DCIN

1
D D
RG3402 RG3404
@ 4.7K_0402_5% @ 4.7K_0402_5%

2
PS8203TQFN32GTR-A3_TQFN32_3X6 UG1
+1.8VS
30 VDDIO_PS8203
CPU_HDMI_TXP2 HDMI_TX2_DP_C VDDIO
CG3401 1 2 0.1u_0201_10V6K 1
[4] CPU_HDMI_TXP2 CPU_HDMI_TXN2 HDMI_TX2_DN_C IN_D2P PCH_HDMI_DDC_DATA
CG3402 1 2 0.1u_0201_10V6K 2 32
[4] CPU_HDMI_TXN2 CPU_HDMI_HPD CPU_HDMI_HPD_R IN_D2N SDA_SRC PCH_HDMI_DDC_CLK PCH_HDMI_DDC_DATA [4]
RG3455 2 @ 1 0_0402_5% 3 31 RG3454 1 @ 2 0_0201_5%
CPU_HDMI_TXP1 HDMI_TX1_DP_C HPD_SRC SCL_SRC PCH_HDMI_DDC_CLK [4]
CG3403 1 2 0.1u_0201_10V6K 4
[4] CPU_HDMI_TXP1 CPU_HDMI_TXN1 HDMI_TX1_DN_C IN_D1P DDPB_DATA_U
CG3404 1 2 0.1u_0201_10V6K 5 29
[4] CPU_HDMI_TXN1 IN_D1N SDA_SNK

2
CPU_HDMI_TXP0 CG3405 1 2 0.1u_0201_10V6K HDMI_TX0_DP_C 6 28 DDPB_CLK_U
[4] CPU_HDMI_TXP0 CPU_HDMI_TXN0 1 2 0.1u_0201_10V6K HDMI_TX0_DN_C 7 IN_D0P SCL_SNK
CG3406 RG3408
[4] CPU_HDMI_TXN0 HDMI_DCIN 8 IN_D0N
27 HDMI_TX2_DP_U
1M_0402_5%

2
CPU_HDMI_CLKP CG3407 1 2 0.1u_0201_10V6K HDMI_CLK_DP_C 9 DCIN_EN OUT_D2P
26 HDMI_TX2_DN_U
[4] CPU_HDMI_CLKP CPU_HDMI_CLKN HDMI_CLK_DN_C IN_CKp OUT_D2N HDMI_DET
CG3408 1 2 0.1u_0201_10V6K 10 25 QG3403
[4] CPU_HDMI_CLKN

1
IN_CKn HPD_SNK HDMI_TX1_DP_U
24
VDD_PS8203 11 OUT_D1P
23 HDMI_TX1_DN_U CPU_HDMI_HPD 3 1 HDMI_DET
VDD OUT_D1N HDMI_TX0_DP_U [4] CPU_HDMI_HPD
22
@ 1 PAD 12 OUT_D0P
21 HDMI_TX0_DN_U
TG1 HDMI_EQ PD# OUT_D0N
13 20 1
TG2 @ PAD LSI1012XT1G_SC-89-3
EQ CFG HDMI_CLK_DP_U
19
HDMI_PRE 15 OUT_CKp
18 HDMI_CLK_DN_U
PRE OUT_CKn
16 Maybe 2N7002 is ok?
REXT
17

EPAD
CEXT

GND

CG3415
1 1

0.1u_0201_10V6K
14

33
RG3405 F1 use 1.1A
5.9K_0402_1% 2 +5VS_HDMI_F +5VS_HDMI
C C
+5VS
2

FG3401
1 3 1 2

S
QG3402
1.1A_8V_1206L110THYR

2
LP2301ALT1G_SOT23-3

G
2
CG3420
SUSP 0.1u_0201_10V6K

1
[47] SUSP

@
RG3413 2 1 0_0402_5% HDMI_TX0_DP_CON
1

EMC_HDMI_NC@ DG3401
HDMI_TX0_DP_U 1 2 RG3414 HDMI_CLK_DN_CON 1 1 10 9 HDMI_CLK_DN_CON
1 2 +5VS_HDMI
270_0402_1%
EMC_HDMI_R@ HDMI_CLK_DP_CON 2 2 9 8 HDMI_CLK_DP_CON
HDMI_TX0_DN_U 4 3
2

4 3 HDMI_TX0_DN_CON HDMI_TX0_DN_CON
4 4 7 7

2
1
EXC24CH900U_4P
HDMI_TX0_DP_CON 5 5 6 HDMI_TX0_DP_CON RP3401
LG3401 6
@ 2.2K_0404_4P2R_5%
RG3415 2 1 0_0402_5% HDMI_TX0_DN_CON 3 3 +5VS_HDMI
JHDMI

3
4
8
18 15 DDPB_CLK_U
+5V_Pow er SCL
16 DDPB_DATA_U
SDA
AZ1045-04F_DFN2510P10E-10-9
@ HDMI_TX0_DP_CON 7
EMC_NS@
RG3416 2 1 0_0402_5% HDMI_TX1_DP_CON HDMI_TX0_DN_CON 9 TMDS_Data0+
13
B HDMI_TX1_DP_CON TMDS_Data0- CEC B
4 17
EMC_HDMI_NC@ HDMI_TX1_DN_CON 6 TMDS_Data1+ DDC/CEC_Ground
19 HDMI_DET
HDMI_TX2_DP_CON 1 TMDS_Data1- Hot_Plug_Detect
DG3402 TMDS_Data2+
2

HDMI_TX1_DP_U 1 2 HDMI_TX2_DN_CON 3
HDMI_TX1_DN_CON 1 1 HDMI_TX1_DN_CON
10 9

2
1 2 TMDS_Data2-
RG3417
270_0402_1% HDMI_TX1_DP_CON HDMI_TX1_DP_CON 8 14
HDMI_TX1_DN_U 2 2 9 8 TMDS_Data0_Shield Utility RG3411
4 3 EMC_HDMI_R@ 5
4 3
2 TMDS_Data1_Shield 20K_0402_5%
HDMI_TX2_DN_CON 4 4 7 HDMI_TX2_DN_CON
1

EXC24CH900U_4P LG3402 7 TMDS_Data2_Shield

1
HDMI_TX2_DP_CON HDMI_TX2_DP_CON 20
5 5 6 6 GND1
@ 11 21
RG3418 2 1 0_0402_5% HDMI_TX1_DN_CON HDMI_CLK_DP_CON 10 TMDS_Clock_Shield GND2
22
3 3 HDMI_CLK_DN_CON TMDS_Clock+ GND3
12 23
TMDS_Clock- GND4
8
@
RG3419 2 1 0_0402_5% HDMI_TX2_DP_CON
AZ1045-04F_DFN2510P10E-10-9 ALLTO_C128AF-K1935-L
EMC_HDMI_NC@ EMC_NS@ ME@
change symbol to SP011703273 by amy 0622
2

HDMI_TX2_DP_U 1 2 HDMI_DET
1 2
RG3420 DDPB_CLK_U
DDPB_DATA_U
270_0402_1%
HDMI_TX2_DN_U 4 3 EMC_HDMI_R@ +5VS_HDMI
4 3
1

LG3403 EXC24CH900U_4P
2

2
PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2

PESD5V0H1BSF_SOD962-2

@
2

2
RG3421 2 1 0_0402_5% HDMI_TX2_DN_CON
DG3403

DG3404

DG3405

DG3406

For EMC
1

@
1

RG3422 2 1 0_0402_5% HDMI_CLK_DP_CON

EMC_NS@ EMC_NS@ EMC_NS@ EMC_NS@
A A
EMC_HDMI_NC@
2

HDMI_CLK_DP_U 1 2
1 2
RG3423
270_0402_1%
HDMI_CLK_DN_U 4 3 EMC_HDMI_R@
4 3
1

EXC24CH900U_4P
LG3404
@
RG3424 2 1 0_0402_5% HDMI_CLK_DN_CON
Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 S550-ITL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
For EMC MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. HDMI_CONN
Date: Sunday, August 02, 2020 Sheet 34 of 61
5 4 3 2 1
 A B C D E

20190813
Page 45: UE4501,change 128K

1 1

2 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, May 28, 2020 Sheet 35 of 61
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, May 28, 2020 Sheet 36 of 61
5 4 3 2 1
 5 4 3 2 1

+3VS_SSD

0.1U_6.3V_K_X5R_0201

4.7U_6.3V_K_X5R_0402
CF3703

CF3707
10U 6.3V M X5R 0402
CF3701
1 1 1

2 2 2
@

JSSD
D D
1 2
GND_1 3.3V_1
3 4
GND_2 3.3V_2
5 6
+3VS +3VS_SSD [9] PCIE_PRX_DTX_N5 PERN3 N/C_2
7 8
[9] PCIE_PRX_DTX_P5 PERP3 N/C_3
Min 3A 9 10
0.22U_0402_10V6K 1 2 CF3702 PCIE_PTX_C_DRX_N5 11 GND_3 DAS/DSS#
12
RF3701 [9] PCIE_PTX_DRX_N5 PCIE_PTX_C_DRX_P5 PETN3 3.3V_3
0.22U_0402_10V6K 1 2 CF3704 13 14
[9] PCIE_PTX_DRX_P5 PETP3 3.3V_4
1 2 1/10W_0_5%_0603 15 16
GND_4 3.3V_5
17 18
[9] PCIE_PRX_DTX_N6 PERN2 3.3V_6
19 20
[9] PCIE_PRX_DTX_P6 21 PERP2 N/C_4
22
0.22U_0402_10V6K 1 2 CF3709 PCIE_PTX_C_DRX_N6 23 GND_5 N/C_5
24
[9] PCIE_PTX_DRX_N6 PCIE_PTX_C_DRX_P6 PETN2 N/C_6
[9] PCIE_PTX_DRX_P6 0.22U_0402_10V6K 1 2 CF3710 25 26
PETP2 N/C_7
27 28
GND_6 N/C_8
29 30
[9] PCIE_PRX_DTX_N7 PERN1 N/C_9
31 32
[9] PCIE_PRX_DTX_P7 PERP1 N/C_10
33 34
PCIE_PTX_C_DRX_N7 GND_7 N/C_11
[9] PCIE_PTX_DRX_N7 0.22U_0402_10V6K 1 2 CF3711 35 36
0.22U_0402_10V6K 1 2 CF3712 PCIE_PTX_C_DRX_P7 37 PETN1 N/C_12
38
[9] PCIE_PTX_DRX_P7 PETP1 DEVSLP
39 40
GND_8 N/C_13
41 42
[9] PCIE_PRX_DTX_P8 PERN0/SATA-B+ N/C_14
43 44
[9] PCIE_PRX_DTX_N8 PERP0/SATA-B- N/C_15
45 46
0.22U_0402_10V6K 1 2 CF3713 PCIE_PTX_C_DRX_N8 47 GND_9 N/C_16
48
[9] PCIE_PTX_DRX_N8 PCIE_PTX_C_DRX_P8 PETN0/SATA-A- N/C_17 PLT_RST#
[9] PCIE_PTX_DRX_P8 0.22U_0402_10V6K 1 2 CF3714 49 50
PETP0/SATA-A+ PERST# SSD_CLKREQ_Q# PLT_RST# [11,26,40,42,45]
51 52 RF3703 2 @ 1 0_0402_5% SSD_CLKREQ# [10]
GND_10 CLKREQ#
53 54
[10] CLK_PCIE_SSD# REFCLKN PEWAKE#
55 56
[10] CLK_PCIE_SSD REFCLKP N/C_18
57 58
GND_11 N/C_19

59 NC NC 60 +3VS_SSD
61 NC NC 62
63 NC NC 64
65 NC NC 66
67 68
SSD_PCIE_DET# RF3707 2 1 0_0402_5% SSD_DET 69 N/C_1 SUSCLK
70

0.1U_6.3V_K_X5R_0201
@
[9] SSD_PCIE_DET# 71 PEDET 3.3V_7
72
C C

4.7U_6.3V_K_X5R_0402
GND_12 3.3V_8

CF3706
73 74

10U 6.3V M X5R 0402

SSD_DET#

CF3716
CF3715
GND_13 3.3V_9
75 1 1 1
SATA-->GND 77
GND_14
76
PCIE-->NC PEG1 PEG2
@
2 2 2
ARGOS_NASM0-S6701-TS40
ME@

Change Symbol to SP070013X00 amy 0614

B B

+5VS +5VS_HDD

RF3708 1 @ 2 0_5%_0603
0.1u_0201_10V6K
CF3717

CF3718

CF3719

CF3720
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

ME@
CF3722RF_NS@
33P_0402_50V8J

CF3723 RF_NS@
33P_0402_50V8J

1 1 1 1 1 1
1

HIGHS_FC5AF101-2931H
CF3721

@ @ @
1
SATA_PTX_DRX_P0 CF3725 1 2 0.01U_0201_10V6K SATA_PTX_C_DRX_P0 2 1
[9] SATA_PTX_DRX_P0
2

2 2 2 2 2 2 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 2
CF3724 1 2 0.01U_0201_10V6K 3
[9] SATA_PTX_DRX_N0 3
4
SATA_PRX_DTX_N0 CF3726 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_N0 5 4
[9] SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 CF3727 1 2 0.01U_0201_10V6K SATA_PRX_C_DTX_P0 6 5
[9] SATA_PRX_DTX_P0 7 6
7
8 12
8 GND2
9
9
10 11
+5VS_HDD 10 GND1

JHDD

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. NGFF_SSD/HDD
Date: Tuesday, August 11, 2020 Sheet 37 of 61
5 4 3 2 1
 5 4 3 2 1

FPR POWER DISCHAGER

FPR POWER +3V_FPR
+3V_FPR
+3VL +3VL

1
RI4622 1 @ 2 0_0402_5% RI4624

1
330_0402_1%
D D
RI4623

1
200K_0402_5%
RI4621

2
0_0402_5%

2
@
@

2
QI3801

1
S

D
1 3 1 QI3803

LP2301ALT1G_SOT-23-3
1 FPR_PWR_EN# 2

G
RI3803 1 CI3805

2
100K_0201_5%
CI4610 0.1U_6.3V_K_X5R_0201 SSM3K15AMFV_2-1L1B

3
0.047U_0402_25V_X7R_0402 2
2 FPR_PWR_EN @
2

RI3804 2 1 RI3805 1 @ 2 0_0402_5%

10K_0402_5%
FPR_PWR_EN#
1

QI3802 1
CI3802
2 0.1U_6.3V_K_X5R_0201
[45] FPR_PWR_EN 2
@
SSM3K15AMFV_2-1L1B
3
2

RI3806
100K_0402_5%
1

C C
+3V_FPR

FP CONN
JFP
1
USB20_N7_CONN 1
2
USB20_P7_CONN 3 2
3
4
RI3807 FPR_DELINK_E 5 4
[45] FPR_DELINK_E FPR_AL0 FPR_AL0_C 5
1 2 RI3821 1 @ 2 0_0201_5% 6
[45] FPR_AL0 FPR_RESET FPR_RESET_C 6
0_0402_5% RI3822 1 @ 2 0_0201_5% 7
[8] FPR_RESET FPR_SCL 7
@ LI3801 8
USB20_N7 USB20_N7_CONN [45] FPR_SCL 8
1 2
[9] USB20_N7 1 2
9
GND1
10
USB20_P7 USB20_P7_CONN GND2
4 3
[9] USB20_P7

1
4 3
HIGHS_FC5AF081-2931H
EXC24CH900U_4P RI3814 ME@
EMC@ 1/20W_47K_5%_0201
RI3808
1 2

2
0_0402_5%
@ +3V_FPR
USB20_N7_CONN

USB20_P7_CONN

1
DI3801

EMC_NS@
AZ5725-01F.R7GR_DFN1006P2X2

1
AZ5425-01F.R7GR DFN1006P2E
1

1
AZ5425-01F.R7GR DFN1006P2E

EMC@
B B

EMC@

DI3802
DI3803

2
2
2

2
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date Deciphered Date 2019/06/01 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. FPR
Date: Saturday, August 01, 2020 Sheet 38 of 61
5 4 3 2 1
 5 4 3 2 1

REMOTE1+_R RS3901 1 @ 2 0_0201_5% REMOTE1+

REMOTE1+ Near CHARGER REMOTE2+
1 1

1
REMOTE1-_R RS3902 1 @ 2 0_0201_5% REMOTE1- CS3901
2
C CS3902
2
C Near CPU
100P 25V J NPO 0201 QS3901 100P 25V J NPO 0201 QS3902
B MMBT3904WH_SOT323-3 B MMBT3904WH_SOT323-3
REMOTE2+_R RS3903 1 @ 2 0_0201_5% REMOTE2+ 2 E 2 E

3
REMOTE1- REMOTE2-
REMOTE2-_R RS3904 1 @ 2 0_0201_5% REMOTE2-

D D

Close to U1
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: REMOTE1+_R
Trace width/space:10/10 mil 1
CS3903
+3VS Trace length:<8" 2200P_25V_K_X7R_0201
US3901
2 REMOTE1-_R

1 10 EC_SMB_CK0
VDD SCLK EC_SMB_CK0 [26,39,45]
REMOTE1+_R 2 9 EC_SMB_DA0
D1+ SDA EC_SMB_DA0 [26,39,45]
1 REMOTE1-_R
CS3904 3 8
0.1U_6.3V_K_X5R_0201 D1- ALERT# Close to U1
REMOTE2+_R 4 7 RS3905 1 2 100K_0201_5% REMOTE2+_R
2 D2+ TCRIT# +3VS
REMOTE2-_R 1
5 6 CS3905
D2- GND
2200P_25V_K_X7R_0201

NCT7719W_MSOP10 2 REMOTE2-_R

C C
REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-: Confirm need???
Trace width/space:10/10 mil @
Near GPU
+3VS REMOTE+_R RS3906 2 1 0_0402_5% REMOTE+
Trace length:<8" 1

1
CS3906 C
100P_0201_25V8J 2 QS3903
US3902 OPT@ B MMBT3904WH_SOT323-3
1 8 @ 2 E OPT@
EC_SMB_CK0 [26,39,45]

3
VDD SCL REMOTE-_R RS3907 2 1 0_0402_5% REMOTE-
REMOTE+_R 2 7
1 D+ SDA EC_SMB_DA0 [26,39,45]
CS3907 REMOTE-_R 3 6
0.1U_6.3V_K_X5R_0201 D- ALERT#
OPT@
2 RS3908 1 2 100K_0201_5%
4 5
+3VS T_CRIT# GND
OPT@
NCT7718W_MSOP8
OPT@
Address 1001_100xb

Close to U3
REMOTE+_R
1
CS3908
2200P_0201_25V7-K
OPT@
2 REMOTE-_R

B B

FAN CONN HALL Sensor CONN

+5VS +5VS_FAN

RC3911
FAN
1 2 1/10W_0_5%_0603
0.1u_0201_10V6K

1 @ 1
CS3910

CS3909
10U_0603_10V6K
2 2 +3VL

RS3920 1 @ 2 0_0201_5% LID_0D_SW#

LID_0D_SW# [45]
U3903
2
1 CS3919
OUTPUT
2
100P_0201_25V8J
+5VS_FAN
FAN Conn 3
4
GND
NC 1
JFAN 1 VDD
5
EC_FAN_PWM 1 CS3915 EP
[45] EC_FAN_PWM EC_FAN_SPEED 1
2 0.1U_6.3V_K_X5R_0201 AH1912-FA-7 X1-DFN1216
[45] EC_FAN_SPEED 2 2
3
3
A 4 A
4

5
GND1
6
GND2

HIGHS_WS33040-S0351-HF
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2017/08/15 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Thermal Sensor/LID
Date: Tuesday, August 11, 2020 Sheet 39 of 61
5 4 3 2 1
 A B C D E

Mini-Express Card(WLAN/WiMAX)
+3VALW_PCH +3V_WLAN

RN4001 1 @ 2 0_5%_0603

1 1

47U_6.3V_M_X5R_0805_H1.25
0.01U_0402_25V7K
1 1

CN4001

CN4002
@
2@ 2

+3V_WLAN

0.1U_6.3V_K_X5R_0201

CN4005
CN4004
0.01U_0402_25V7K

10U 6.3V M X5R 0402

1 1 1

CN4003
2 2 2
@
JWLAN

1 2
USB20_P10 3 GND1 3.3VAUX1
4
+3V_WLAN [9] USB20_P10 USB20_N10 USB_D+ 3.3VAUX2
5 6
[9] USB20_N10 7 USB_D- LED1#
8
CNV_WR_D1N GND2 PCM_CLK/I2S_SCK CNVI_RF_RESET# CNVI_RF_RESET#_R
9 10 RN4010 2 @ 1 0_0402_5%
[10] CNV_WR_D1N CNV_WR_D1P SDIO_CLK PCM_SYNC/I2S_WS CNVI_RF_RESET#_R [6]
11 12
@ PCH_WLAN_OFF# [10] CNV_WR_D1P SDIO_CMD PCM_IN/I2S_SD_IN CNVI_MODEM_CLKREQ
RN4011 1 2 10K_0402_5% 13 14 RN4012 2 @ 1 0_0402_5%
BT_OFF_N CNV_WR_D0N SDIO_DATA0 PCM_OUT/I2S_SD_OUT CNVI_MODEM_CLKREQ_R [6]
RN4009 1 2 10K_0402_5% 15 16
[10] CNV_WR_D0N CNV_WR_D0P 17 SDIO_DATA1 LED#2
18
2 2
[10] CNV_WR_D0P SDIO_DATA2 GND11
19 20
+1.8VALW CNV_WR_CLKN 21 SDIO_DATA3 UART_WAKE#
22 CNVI_BRI_RSP_R RN4013 1 CNVI@ 2 1/20W_49.9_1%_0201
[10] CNV_WR_CLKN CNV_WR_CLKP 23 SDIO_WAKE# UART_RXD CNVI_BRI_RSP [10]
CNVI_BRI_DT [10] CNV_WR_CLKP SDIO_RESET#
RN4014 1 @ 2 20K_0402_5%

RN4015 1 2 100K_0402_5% CNVI_RGI_DT

KEY E
25 PIN24~PIN31 NC PIN 24
27 26
29 28
31 30

33 32 CNVI_RGI_DT
PCIE_PTX_C_DRX_P9 GND3 UART_TXD CNVI_RGI_RSP_R RN4016 1 CNVI@ CNVI_RGI_DT [10]
35 34 2 1/20W_49.9_1%_0201
[9] PCIE_PTX_C_DRX_P9 PCIE_PTX_C_DRX_N9 PETP0 UART_CTS CNVI_BRI_DT CNVI_RGI_RSP [10]
37 36
[9] PCIE_PTX_C_DRX_N9 PETN0 UART_RTS EC_TX_RSVD CNVI_BRI_DT [10]
39 38 RN4017 1 @ 2 0_0402_5% EC_TX
PCIE_PRX_DTX_P9 41 GND4 VENDOR_DEFINED1
40 EC_RX_RSVD RN4018 1 @ 2 0_0402_5% EC_RX
[9] PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 PERP0 VENDOR_DEFINED2
PCIE 43 42
[9] PCIE_PRX_DTX_N9 PERN0 VENDOR_DEFINED3
45 44
CLK_PCIE_WLAN 47 GND5 COEX3
46
+3V_WLAN [10] CLK_PCIE_WLAN CLK_PCIE_WLAN# REFCLKP0 COEX2
49 48
+3VS [10] CLK_PCIE_WLAN# REFCLKN0 COEX1 SUSCLK_R
51 50 RN4019 2 @ 1 0_0402_5%
WLAN_CLKREQ_Q# GND6 SUSCLK WLAN_PERST# SUSCLK [10]
53 52 RN4030 2 @ 1 0_0402_5%
PLT_RST# [11,26,37,42,45]
2

PCIE_WAKE#_WLAN 55 CLKREQ0# PERST0#

54 BT_OFF# RN4020 2 @ 1 0_0402_5% BT_OFF_N
2

RN4021 57 PEWAKE0# W_DISABLE2#

56 WLAN_OFF# RN4022 2 @ 1 0_0402_5%
G

GND7 W_DISABLE1# PCH_WLAN_OFF# [8]

QN4002 10K_0402_5%
@
@ CNV_WT_D1N 59 58 WLAN_SMB_DATA RN4023 2 @ 1 0_0402_5%
[10] CNV_WT_D1N EC_RX [45]
1

3 1 WLAN_CLKREQ_Q# CNV_WT_D1P 61 RSRVD/PETP1 I2C_DATA

60 WLAN_SMB_CLK RN4024 2 1 0_0402_5%
[10] WLAN_CLKREQ# [10] CNV_WT_D1P RSRVD/PETN1 I2C_CLK EC_TX [45]
S

63 62
CNV_WT_D0N GND8 ALERT#
L2N7002KWT1G_SOT323-3 65 64
[10] CNV_WT_D0N

1
@ CNV_WT_D0P 67 RSRVD/PERP1 RSRVD
66
[10] CNV_WT_D0P RERVD/PERN1 UIM_SWP/PERST1#
RN4025 2 1 0_0402_5% 69 68 RN4026
CNV_WT_CLKN 71 GND9 UIM_POWER_SNK/CLKREQ1#
70 100K_0402_5%
[10] CNV_WT_CLKN CNV_WT_CLKP 73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1#
72
[10] CNV_WT_CLKP RSRVD/REFCLKN1 3.3VAUX3
75 74

2
GND10 3.3VAUX4
3 3
77 76
GND15 GND14

+3V_WLAN ARGOS_NASE0-S6701-TS40
PCIE_WAKE#_WLAN_R(GPP_H2) +3V_WLAN
ME@
strap pin at PCH side, default internal 20K PD
1

R3506 request by CNVi check list

0.1U_6.3V_K_X5R_0201
RN4027
200K is to make sure GPP_H2 strap low at RSMRST#

10U 6.3V M X5R 0402

200K_0402_5%
GPP_H2 internal PD disabled after RSMRST#

0.01U_0402_25V7K
CNVI@ 1 1 1

CN4006

CN4007
2

RN4028 1 @ 2 0_0402_5% PCIE_WAKE#_WLAN +1.8VALW

[11] PCIE_WAKE# 2 2 2

CN4008
@ @

2
RN4029 2 1 0_0402_5%
[8] PCIE_WAKE#_WLAN_R
RN30
0_0201_5%
@

1
2
RN29
100K_0201_5%

1
2
QN3
BT_OFF_N 1 3
PCH_BT_OFF# [12,13]

LSI1012XT1G_SC-89-3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2016/12/14 Deciphered Date 2017/12/13 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. NGFF_WLAN
Date: Sunday, August 02, 2020 Sheet 40 of 61
A B C D E
 5 4 3 2 1

+5VALW RB4101
+5VTBTA
1 2 1/10W_0_5%_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1
1 1 1 1 1

CB4118

CB4117

CB4103

CB4104

CB4105

CB4101
2
2 2 2 2 2 VCC3_LDO_PD

1
D D
RB4137

1/20W_100K_1%_0201
VBUS_TBTA

2
+3VALW VIN_3V3 VCC3_LDO_PD PD_ADCIN1
PD_ADCIN2
RB4109

1/20W_12.1K_1%_0201
1 2 1/10W_0_5%_0603

1
VIN_3V3

1
4.7U_25V_M_X5R_0603

NSR20F30NXT5G_DSN2-2

RB4135
1 1

1
2

10U_0402_6.3V6M

CB4108

DB4101
10U_0402_6.3V6M

10U_0402_6.3V6M
RB4104

2
0_5%_0603 1 1 2 2

CB4122

CB4123
@

CB4111

2
1
2 2

2
G2

G8
H4

H1

H3

H8

C8
A3

A8
B8
F8
UU1

VIN_3V3

LDO_1V5_1
LDO_1V5_2

LDO_3V3

PA_VBUS_1
PA_VBUS_2
PA_VBUS_3

PB_VBUS_1
PB_VBUS_2
PB_VBUS_3
VSYS
A7
+5VTBTA B7 PP5V_1

C7 PP5V_2 TBTA_CC1 CB4114 1 2 220P_25V_K_X7R_0201

PP5V_3
D7
E7 PP5V_4
G4 PD_ADCIN1 TBTA_CC2 CB4113 1 2 220P_25V_K_X7R_0201
PP5V_5 ADCIN1
F7
G7 PP5V_6 TBTB_CC1 @ CB4112 1 2220P_25V_K_X7R_0201
H7 PP5V_7
G3 PD_ADCIN2
PP5V_8 ADCIN2 TBTB_CC2 @ CB4115 1 2220P_25V_K_X7R_0201
C C

RB4126 1 @ 2 0_0201_5% A4
[52] TBTA_GATE_VSYS 1 TBTA_GATE_VBUS E8 PA_GATE_VSYS
G5 TBTA_CC1
@ PA_GATE_VBUS PA_CC1 TBTA_CC2
H5 TBTA_CC1 [44]
PA_CC2 TBTA_CC2 [44]
TP4101
B5 TBTB_CC1
B4 PB_CC1
A5 TBTB_CC2
PB_GATE_VSYS PB_CC2
D8
PB_GATE_VBUS

TBTB_CC1 RB4118 1 @ 2 0_0201_5%

TBTA_RESET# C1 D1 PD_I2C1_IRQ RB4124 1 @ 2 0_0201_5% TBTB_CC2 RB4117 1 @ 2 0_0201_5%
[42] TBTA_RESET# GPIO0 I2C_EC_IRQ# EC_PD_INT# [45]
RB4102 1 @ 2 0_0201_5% G1 E1 PD_I2C1_SCL RB4122 1 @ 2 0_0201_5%
[11,45,47] PM_SLP_S4# GPIO1 I2C_EC_SCL PD_I2C1_SDA EC_SMB_CK4 [45]
F1 RB4123 1 @ 2 0_0201_5% EC_SMB_DA4 [45]
TBTA_PWR_EN A6 I2C_EC_SDA
[43] TBTA_PWR_EN GPIO2

RB4439 1 @ 2 0_0201_5% H6
[52] PD_ACK_SNK1 GPIO3
F2 PD_I2C2_IRQ RB4125 1 @ 2 0_0201_5%
PD_GPIO13 I2C2S_IRQ# PCH_PD_INT# [11]
RB4119 1 @ 2 0_0201_5% B3 only slave
[9] USB_OC3# GPIO4 PD_I2C2_SCL
E2
I2C2S_SCL PD_I2C2_SDA PD_I2C2_SCL [7]
C2 D2
GPIO5 I2C2S_SDA PD_I2C2_SDA [7]
RB4121 1 @ PD_GPIO6
2 0_0201_5% F6 VCC3_LDO_PD
[13] GPPC_B2_VRALERT_N GPIO6

G6 B1 PD_I2C3_IRQ# RB4437 1 @ 2 0_0201_5% TBT_I2C_INT#

GPIO7 I2C3M_IRQ# TBT_I2C_INT# [42] PD_I2C3_SCL RP4103 1 4 2.2K_0404_4P2R_5%
RB4127 1 @ 2 0_0201_5% B6 A2 PD_I2C3_SCL RB4435 1 @ 2 0_0201_5% TBT_I2C_SCL PD_I2C3_SDA 2 3
[52] PD_VBUS_C_CTRL1 GPIO8 I2C3M_SCL PD_I2C3_SDA RB4436 1 @ TBT_I2C_SDA TBT_I2C_SCL [42]
A1 2 0_0201_5% TBT
I2C3M_SDA_1 TBT_I2C_SDA [42]
RB4434 1 @ 2 0_0201_5% PD_GPIO9 C6 B2 PD_I2C3_IRQ# RB4438 1 2 10K_0201_5%
[6,42] TBT_FORCE_PWR GPIO9 I2C3M_SDA_2
GND

SN2001024ADYBGR PD_I2C2_SCL RB4103 1 2 1/20W_2.2K_5%_0201

H2

PD_I2C2_SDA RB4106 1 2 1/20W_2.2K_5%_0201

PCH
B B
PD_I2C2_IRQ RB4107 1 @ 2 10K_0201_5%

PD_I2C1_SCL RP4102 1 4 2.2K_0404_4P2R_5%

PD_I2C1_SDA 2 3
EC
@
PD_I2C1_IRQ RB4108 1 2 10K_0201_5%
@

A A

USBC 0111 111xb

For the I2C2 interface, the unique I2C address is a fixed
value

Security Classification LC Future Center Secret Data Title

Issued Date Deciphered Date 2019/06/01 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PD
Date: Tuesday, August 11, 2020 Sheet 41 of 61
5 4 3 2 1
 5 4 3 2 1

Burnside Bridge Re-Timer UB1D Y

3VALW_TBTA

[4] TCP0_CTX_C_DRX_P0
TCP0_CTX_C_DRX_P0 J1
TBT PORTS J12 TBTA_RX_P0
TBTA_RX_P0 [44]
TBT_FLASH_BUSY# RB4202 1 2 10K_0201_5% FLASH_BUSY# should be shared between BBR#1 and
TCP0_CTX_C_DRX_N0 J2 ASSRXp1 BSSRXp1
J11 TBTA_RX_N0 RB4205 1 @ 2 10K_0201_5%
[4] TCP0_CTX_C_DRX_N0 TBTA_RX_N0 [44] BBR#2 with PU to PW_VCC3v3_SX_SYS

Port B - TypeC Side

ASSRXn1 BSSRXn1

Port A - Host Side

TCP0_CRX_DTX_P0 CB4206 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX_P0 G1 G12 TBTA_TX_P0
[4] TCP0_CRX_DTX_P0 TCP0_CRX_DTX_N0 TCP0_CRX_C_DTX_N0 ASSTXp1 BSSTXp1 TBTA_TX_N0 TBTA_TX_P0 [44]
CB4200 1 2 0.22U_6.3V_K_X5R_0201 G2 G11
[4] TCP0_CRX_DTX_N0 ASSTXn1 BSSTXn1 TBTA_TX_N0 [44]
TCP0_CTX_C_DRX_P1 C1 C12 TBTA_RX_P1 +3VS
[4] TCP0_CTX_C_DRX_P1 TCP0_CTX_C_DRX_N1 ASSRXp2 BSSRXp2 TBTA_RX_N1 TBTA_RX_P1 [44]
C2 C11 POC_GPIO6:
[4] TCP0_CTX_C_DRX_N1 ASSRXn2 BSSRXn2 TBTA_RX_N1 [44] BB_TBTA_GPIO_6 RB4224 1 2 10K_0201_5% Indication to S0 state for Re-timer
TCP0_CRX_DTX_P1 CB4201 1 2 0.22U_6.3V_K_X5R_0201 TCP0_CRX_C_DTX_P1 E1 E12 TBTA_TX_P1 RB4204 1 @ 2 10K_0201_5%
[4] TCP0_CRX_DTX_P1 TCP0_CRX_DTX_N1 TCP0_CRX_C_DTX_N1 ASSTXp2 BSSTXp2 TBTA_TX_N1 TBTA_TX_P1 [44]
CB4202 1 2 0.22U_6.3V_K_X5R_0201 E2 E11
[4] TCP0_CRX_DTX_N1 ASSTXn2 BSSTXn2 TBTA_TX_N1 [44]
TBT_LSX0_TXD M7 M10 TBTA_SBU1
[4] TBT_LSX0_TXD TBT_LSX0_RXD PA_LSTX_SBU1 B_SBU1 TBTA_SBU2 TBTA_SBU1 [44]
L7 L10
D [4] TBT_LSX0_RXD PA_LSRX_SBU2 B_SBU2 TBTA_SBU2 [44] 3VALW_TBTA D
TCP0_AUX_P RB4225 1 @ 2 0_0201_5% TCP0_AUX_P_R L8
[4] TCP0_AUX_P TCP0_AUX_N TCP0_AUX_N_R PA_AUX_P TBT_FORCE_PWR
BB_FORCE_PWR:
RB4226 1 @ 2 0_0201_5% M8 RB4203 1 @ 2 10K_0201_5% Connect to EC/PCH for FW update
[4] TCP0_AUX_N PA_AUX_N
RB4206 1 2 10K_0201_5% '0' - by default
AC coupling caps and PU/PD on AUX lines '1' - for debug only/FW update

1
1M_0402_1%

1M_0402_1%
are implemented inside Burnside Bridge.

RB4219

RB4222
@ @

3VALW_TBTA

2
BB_TBTA_FLSH_SHARE_EN RB4207 1 @ 2 10K_0201_5% FLSH_SHARE_EN (iPU):
RB4223 1 2 10K_0201_5% '0' - Flash isn't shared, 1 Flash per Re-timer.
'1' - Flash is shared between 2 Re-timers
INTEL-RETIMER_BGA105

3VALW_TBTA FLSH_MSTR_SLV (iPU):

BB_TBTA_FLSH_MSTR_SLV
Should be used only when DG_FLSH_SHARE_EN is High.
RB4208 1 @ 2 10K_0201_5% '0' - Set Re-timer to be Slave on shared flash SPI I/F.
RB4221 1 @ 2 10K_0201_5% '1' - Set Re-timer to be Master on shared flash SPI I/F
FLSH_MSTR_SLV of BBR#1 (set as Master) should be PU
UB1A and PD for BBR#2 (set as Slave)
TBT_SPI_MOSI RB4227 1 @ 2 0_0201_5% BB_SPI_DI C6 C9 TBTA_I2C_SCL RB4231 1 @ 2 0_0201_5%
TBT_SPI_MISO BB_SPI_DO EE_DI I2C_SCL TBTA_I2C_SDA TBT_I2C_SCL [41]
RB4228 1 @ 2 0_0201_5% B4 E7 RB4232 1 @ 2 0_0201_5%

FLASH
TBT_SPI_CS# BB_SPI_CS# TBT_I2C_SDA [41]
RB4229 1 @ 2 0_0201_5% B6 EE_DO I2C_SDA
A10 TBTA_I2C_INT RB4233 1 @ 2 0_0201_5% 3VALW_TBTA
TBT_SPI_CLK BB_SPI_CLK TBT_I2C_INT# [41]
RB4330 1 @ 2 0_0201_5% C7 EE_CS_N I2C_INT
B10 TBTA_FORCE_PWR RB4234 1 @ 2 0_0201_5%
EE_CLK FORCE_PWR TBT_FLASH_BUSY# TBT_FORCE_PWR [6,41] TBTA_RESET#_R
A9 RB4212 1 @ 2 100K_0201_5%

POC GPIO
+VCC3V3_LC_TBTA FLASH_BUSY_N BB_TBTA_GPIO_5
RPB1 B9 RB4211 1 @ 2 100K_0201_5%

DEBUG
MISC &
POC_GPIO_5
A8 BB_TBTA_GPIO_6
1 8 TBTA_TDI A3 POC_GPIO_6
B8 BB_TBTA_PERST#
2 7 TBTA_TMS C3 TDI PERST_N
A7 TBTA_SMBUS_SCL
3 6 TBTA_TCK B5 TMS SMBUS_SCL
B7 TBTA_SMBUS_SDA
RESET# should be output from PD.

JTAG
TBTA_TDO TCK SMBUS_SDA BB_TBTA_FLSH_SHARE_EN
4 5 C5 A4 Pull up or Pull down based on USB PD Controller GPIO design.
TDO POC_GPIO_10
A5 BB_TBTA_FLSH_MSTR_SLV
POC_GPIO_11 BB_TBTA_POC_GPIO12
Note: If the USB PD Controller has a weak pull up present during its
10K_0804_8P4R_5% A6 boot, a 10K to 100K Ohm pull down resistor is required to keep the
POC_GPIO_12
L3 POC_GPIO_12 have iPU Burnside Bridge RESET_N low during the VCC_3P3_SX power supply
C @ TP3701 1 TBTA_THERMDA M11 NC_L3
C
THERMDA ramp. The USB PD controller must drive RESET_N meeting the Burnside
M12
Bridge datasheet timing requirements to take it out of reset. If the USB
B2 TEST_EDM PD Controller can hold RESET_N low during the Burnside Bridge
FUSE_VQPS_64
Main power reset signal
TBTA_RESET#_R VCC_3P3_SX power supply ramp, a 10K to 100K Ohm pull up and
L11 RB4235 1 @ 2 0_0201_5%
A11 RESET_N TBTA_RESET# [41] push/pull GPIO on the USB PD controller is recommended.
MONDC TBTA_XTAL_25M_IN
A12 L9

DEBUG

Main
L12 NC_A12 XTAL_25_IN
M9 TBTA_XTAL_25M_OUT
MONDC_SVR XTAL_25_OUT
RB4220 1 @ 2 0_0201_5%
TBTA_TEST_PWRGD TBTA_RSENSE PLT_RST# [11,26,37,40,45]
B3 L5
B11 TEST_PWR_GOOD RSENSE
L4 TBTA_RBIAS RB4241 1 2
TEST_EN RBIAS BB_TBTA_PERST#
1/20W_4.75K_0.5%_0201 RB4236 1 2 0_0201_5%
BB_TBT_PERST# [11]
A1 Place as close as @
ATEST_P
A2 possible to pins
ATEST_N

INTEL-RETIMER_BGA105 Y

UB1C Y

B1 F12
VSS_ANA_1 VSS_ANA_12
B12 G7
VSS_ANA_2 VSS_ANA_13
D1 H1
VSS_ANA_3 VSS_ANA_14 3VALW_TBTA
D2 H2
VSS_ANA_4 VSS_ANA_15 3VALW_TBTA
D11 H11
D12
F1
VSS_ANA_5
VSS_ANA_6 GND VSS_ANA_16
VSS_ANA_17
H12
J9 RB4213 1 @ 2 10K_0201_5%
F2 VSS_ANA_7 VSS_ANA_18
K1 RPB3 1 4 2.2K_0404_4P2R_5% TBTA_I2C_SCL BB_TBTA_PERST# RB4214 1 @ 2 10K_0201_5%
VSS_ANA_8 VSS_ANA_19 TBTA_I2C_SDA
F7 K2 2 3
VSS_ANA_9 VSS_ANA_20
F9 K11
VSS_ANA_10 VSS_ANA_21
F11 K12 @
VSS_ANA_11 VSS_ANA_22
RB4240 1 2 10K_0201_5% TBTA_I2C_INT
VSS_1
VSS_2
VSS_3

@ 3VALW_TBTA

BB_TBTA_POC_GPIO12 RB4201 1 @ 2 10K_0201_5%

F3
F5
G5

B B
INTEL-RETIMER_BGA105
+3VALW_PCH RB4209 1 @ 2 10K_0201_5%
3VALW_TBTA BB_TBTA_GPIO_5 RB4243 1 2 100K_0201_5%
TBTA_TEST_PWRGD RB4210 1 2 1/20W_100_1%_0201
4
3

RPB2
2.2K_0404_4P2R_5%
XTAL
3VALW_TBTA VCC3_BB_SPI
TBTA_XTAL_25M_IN_R RB4238 1 @ 2 0_0402_5% TBTA_XTAL_25M_IN
1
2

RB4237 1 @ 2 0_0402_5% 0.1U_6.3V_K_X5R_0201 1 2 CB4205

UB3 LB4200 EMC_NS@
8 1 4 3
VCCB VCCA 4 3
8

UB2 TBTA_SMBUS_SCL 7 2 PCH_SML0_CLK

B0 A0 PCH_SML0_CLK [7]
1 2
VCC

TBTA_SMBUS_SDA PCH_SML0_DATA 1 2
6 3
B1 A1 PCH_SML0_DATA [7]
EXC24CH500U_4P
TBT_SPI_CS# 1 5 TBT_SPI_MOSI 5 4
/CS DI(IO0) OE GND TBTA_XTAL_25M_OUT_R RB4239 1 @ 2 0_0402_5% TBTA_XTAL_25M_OUT

TBT_SPI_MISO 2 6 TBT_SPI_CLK RB4331 1 @ 2

DO(IO1) CLK +3VALW_PCH FXMA2102UMX_U-MLP8_1P2X1P4
0_0201_5%
TBTA_XTAL_25M_IN_R
1

TBT_SPI_WP# 3 7 TBT_SPI_HOLD#
/WP(IO2) /HOLD(IO3) YB1
RB4244
100K_0201_5%
1 4
OSC1 GND2
2

TBTA_SMBUS_SCL 2 0_0402_5% PCH_SML0_CLK TBTA_XTAL_25M_OUT_R

GND

RB4200 1 1 2 3
GND1 OSC2
A CB4203 A
W25Q80DVSSIG_SO8 @ 1
4

TBTA_SMBUS_SDA RB4242 1 2 0_0402_5% PCH_SML0_DATA 8.2P_50V_J_NPO_0402 CB4204

2 25MHZ_10PF_7V25000014
@ 8.2P_50V_J_NPO_0402
2

VCC3_BB_SPI

TBT_SPI_MISO RB4215 1 2 1/20W_2.2K_5%_0201

TBT_SPI_CS# Security Classification LC Future Center Secret Data Title
RB4216 1 2 1/20W_2.2K_5%_0201
TBT_SPI_WP# RB4217 1 2 1/20W_3.3K_5%_0201
S550-IIL
TBT_SPI_HOLD# Issued Date 2018/12/04 Deciphered Date 2018/08/20
RB4218 1 2 1/20W_3.3K_5%_0201
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TBT_BB_PORTA
Date: Sunday, August 02, 2020 Sheet 42 of 61
5 4 3 2 1
 5 4 3 2 1

PW_VCC3v3_SX(=3VALW_TBTA) Tolerance (+ 5%/-7.5%):

+3VALW 3VALW_TBTA
Burnside Bridge power pins which connected to PW_VCC3v3_SX
should be 3.465v maximum and 3.07v minimum for normal operation.
PW_VCC3v3_SX ripple: 40mVp-p
1

10U 6.3V M X5R 0402

0.1U_6.3V_K_X5R_0201
1 1
CB4323
UB4

CB4321

CB4322
1U_10V_M_X5R_0201
2 1 14 3VALW_TBTA
2 IN1_1 OUT1_2
13 2 2
IN1_2 OUT1_1

RB4301 1 @ 2 0_0201_5% 3VTBTON 3 12 CB4319 1 2 1000P_50V_K_X7R_0201

[41] TBTA_PWR_EN EN1 CT1

+3VALW
4 11
VBIAS GND
D D
3VTBTON 5 10 CB4320 1 2 1000P_50V_K_X7R_0201
EN2 CT2
6 9
IN2_1 OUT2_2 3VALW_TBTA

1/20W_47K_5%_0201
7 8
IN2_2 OUT2_1

0.01U_0402_25V7K
CB4326
1

1
+3VALW 15
Thermal Pad

RB4300
2 TPS22976DPUR_WSON_2X3
1
@

2
CB4327
1U_10V_M_X5R_0201
2

0.9v @850mA
C For BBR, C
3VALW_TBTA C3718 +VCC0V9_SVR_TBTA_IND +VCC0V9_SVR_TBTA
PL4300
can be
removed. 1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 0.68UH_HMLQ25201B-R68MSR_4.4A_20% 1 1 1 1 1 1 1

1
CB4309
2.2U_6.3V_M_X5R_0201

CB4310
2.2U_6.3V_M_X5R_0201

CB4301
18P_50V_J_NPO_0201

CB4302
2.2U_6.3V_M_X5R_0201

CB4303
2.2U_6.3V_M_X5R_0201

CB4304
2.2U_6.3V_M_X5R_0201

CB4305
2.2U_6.3V_M_X5R_0201

CB4306
2.2U_6.3V_M_X5R_0201

CB4307
2.2U_6.3V_M_X5R_0201
Pin E6
Inductor must be placed on the

Pin M4

Pin M5

Pin J5
CB4308

CB4324

CB4300

CB4325
UB1B same side as BB. No vias allowed

Pin E3

Pin E9

Pin G6

Pin G3

Pin G9
3.3V@ 230mA

Pin F6
on VCC0v9_SVR_IND

2
L2 E6 2 2 2@ 2 2 2 2 2 2
+VCC3V3_ANA_TBTA VCC3P3_ANA VCC3P3_SX 3VALW_TBTA IN
+VCC3V3_LC_TBTA
E5 M4
VCC3P3_LC VCC3P3_SVR_1
M5
VCC3P3_SVR_2
+VCC0V9_SVR_TBTA
F6 3.3V@ 50mA
VCC0P9_SVR_ANA_1
G6 J7 3VA_TBTA IN
VCC0P9_SVR_ANA_2 VCC3P3A
Power

E3 L1 +VCC0V9_SVR_TBTA_IND Share Same GND plane and connect to M2 & M3 pins (SVR_VSS) of BB
VCC0P9_SVR_1 SVR_IND_1
G3 M1 OUT
VCC0P9_SVR_2 SVR_IND_2

E9 M2
VCC0P9_SVR_PB_ANA_1 SVR_VSS_1
G9 M3
VCC0P9_SVR_PB_ANA_2 SVR_VSS_2

+VCC0V9_LC_TBTA
J3
VCC0P9_LC

+VCC0V9_LVR_TBTA
L6 J5 3VALW_TBTA
VCC0P9_LVR NC_J5 3VALW_TBTA 3VA_TBTA +VCC3V3_ANA_TBTA +VCC3V3_LC_TBTA +VCC0V9_LC_TBTA +VCC0V9_LVR_TBTA
M6 J6
VCC0P9_LVR_SENSE NC_J6
@
RB4303 2 @ 1 0_0402_5%

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

INTEL-RETIMER_BGA105 Y RB4304 2 1 0_0402_5% 1 1 1 1 1 1 1 1

CB4311

CB4312
2.2U_6.3V_M_X5R_0201

CB4313
18P_50V_J_NPO_0201

CB4314
2.2U_6.3V_M_X5R_0201

CB4315
2.2U_6.3V_M_X5R_0201

CB4316
2.2U_6.3V_M_X5R_0201

CB4317

CB4318
2.2U_6.3V_M_X5R_0201
Pin L2

Pin E5

Pin L6
Pin J5 should be connected to

Pin J7

Pin J7

Pin J3
PW_VCC3v3_SX for DBR
compatibility. for BBR this pin is NC in
2 2 2 2 2 2 2 2
the package.
@

Place holder for RC filter to reduce

ripple to VCC3v3A pin
B B

A A

Security Classification LC Future Center Secret Data Title

S550-IIL
Issued Date 2018/12/04 Deciphered Date 2018/08/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TBT_BB_PWR
Date: Saturday, August 01, 2020 Sheet 43 of 61
5 4 3 2 1
 5 4 3 2 1

VCC3_LDO_PD

TBTA_SBU1 RB4407 1 2 0_0201_5% TBTA_SBU1_CONN VCC3_LDO_PD

[42,44] TBTA_SBU1 TBTA_SBU2 TBTA_SBU2_CONN
RB4409 1 2 0_0201_5%
[42,44] TBTA_SBU2
@
TBTA_CC1 RB4411 1 @ 2 0_0402_5% TBTA_CC1_CONN @
[41,44] TBTA_CC1 TBTA_CC2 TBTA_CC2_CONN
RB4412 1 2 0_0402_5% VPWR RB4430 2 1 0_0402_5%
[41,44] TBTA_CC2
@

2
@
1 RB4431
10K_0201_5%
CB4421
0.1U_6.3V_K_X5R_0201

1
2
D D
U3904

C4 B4 -FLT_REPORT_TYPEC1
VPWR FLT
TBTA_SBU1 D1 B1 TBTA_SBU1_CONN
[42,44] TBTA_SBU1 TBTA_SBU2 SBU1 C_SBU1 TBTA_SBU2_CONN
D2 A1
[42,44] TBTA_SBU2 SBU2 C_SBU2
TBTA_CC1 D3 A2 TBTA_CC1_CONN
[41,44] TBTA_CC1 TBTA_CC2 CC1 C_CC1
D4 B2
[41,44] TBTA_CC2 CC2 RPD_G1
A3 TBTA_CC2_CONN
C_CC2
B3 DB4401EMC_NS@ DB4402EMC_NS@
RPD_G2

C1 TBTA_CC1_CONN 1 2 1 2 TBTA_CC2_CONN
GND1 1 2 1 2
C2
GND2
A4 C3
VBIAS GND3
PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
TBTA_RX_P0 RB4433 1 2 1/20W_2.2_1%_0201 TBTA_RX_P0_U

0.1U_50V_K_X5R_0402
DB4403EMC_NS@ DB4404EMC_NS@
1 SN1904020YBFR_DSBGA16
TBTA_RX_N0 RB4405 1 2 1/20W_2.2_1%_0201 TBTA_RX_N0_U TBTA_SBU1_CONN 1 2 1 2 TBTA_SBU2_CONN

CB4420
1 2 1 2

2 PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

DB4405EMC_NS@ DB4406EMC_NS@
TBTA_USB2P_CONN 1 2 1 2 TBTA_USB2N_CONN
1 2 1 2

RB4401 1 2 221K_0402_1% TBTA_RX_P0_C PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

RB4402 1 2 221K_0402_1% TBTA_RX_N0_C DB4407EMC_NS@ DB4408EMC_NS@

TBTA_TX_P0 RB4410 1 2 1/20W_2.2_1%_0201TBTA_TX_P0_U RB4403 1 2 221K_0402_1% TBTA_RX_P1_C TBTA_TX_P0_U 1 2 2 1 TBTA_TX_N0_U

1 2 2 1

RB4404 1 2 221K_0402_1% TBTA_RX_N1_C

C TBTA_TX_N0 RB4416 1 2 1/20W_2.2_1%_0201TBTA_TX_N0_U PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2 C

DB4409EMC_NS@ DB4410EMC_NS@
TBTA_RX_N1_U 1 2 2 1 TBTA_RX_P1_U
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2

DB4411EMC_NS@ DB4412EMC_NS@
TBTA_RX_P0_U 1 2 2 1 TBTA_RX_N0_U
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
TBTA_RX_P1 RB4417 1 2 1/20W_2.2_1%_0201 TBTA_RX_P1_U
DB4413EMC_NS@ DB4414EMC_NS@
TBTA_RX_N1 RB4413 1 2 1/20W_2.2_1%_0201 TBTA_RX_N1_U TBTA_TX_N1_U 1 2 2 1 TBTA_TX_P1_U
1 2 2 1

PESD5V0H1BSF_SOD962-2 PESD5V0H1BSF_SOD962-2
VBUS_TBTA

DB4415
EMC@

VBUS_TBTA 1 2
1 2

0.1U_25V_K_X5R_0201

0.1U_25V_K_X5R_0201

0.1U_25V_K_X5R_0201

0.1U_25V_K_X5R_0201
1 1 1 1

CB4401

CB4402

CB4403

CB4404
Near Near Near Near SPHV24-01ETG-C_SOD882-2
PinB9 PinB4 PinA9 PinA4
TBTA_TX_P1 RB4414 1 2 1/20W_2.2_1%_0201 TBTA_TX_P1_U 2 2 2 2

TBTA_TX_N1 RB4415 1 2 1/20W_2.2_1%_0201 TBTA_TX_N1_U

B B
VBUS_TBTA VBUS_TBTA

JTC ME@

A1 B12
GND1 GND4
AC coupling is recommended for TBTA_TX_P0_C TBTA_RX_P0_C
VBUS-short protection on SSRX lines. If A2 B11
SSTXp1 SSRXp1
not needed, place 0Ohm resistor instead. TBTA_TX_N0_C TBTA_RX_N0_C
A3 B10
TBTA_RX_P0 TBTA_RX_P0_U CB4405 1 2 0.33U_25V_K_X5R_0402 TBTA_RX_P0_C SSTXn1 SSRXn1
[42] TBTA_RX_P0 TBTA_RX_N0 TBTA_RX_N0_U TBTA_RX_N0_C
CB4406 1 2 0.33U_25V_K_X5R_0402 A4 B9
[42] TBTA_RX_N0 Vbus1 Vbus4
TBTA_TX_P0 TBTA_TX_P0_U CB4407 1 2 0.22U_25V_K_X5R_0402 TBTA_TX_P0_C TBTA_CC1_CONN A5 B8 TBTA_SBU2_CONN
[42] TBTA_TX_P0 TBTA_TX_N0 TBTA_TX_N0_U TBTA_TX_N0_C CC1 SBU2
CB4408 1 2 0.22U_25V_K_X5R_0402
[42] TBTA_TX_N0 TBTA_USB2P_CONN TBTA_USB2N_CONN
A6 B7
TBTA_RX_P1 TBTA_RX_P1_U CB4409 1 2 0.33U_25V_K_X5R_0402 TBTA_RX_P1_C Dp1 Dn2
[42] TBTA_RX_P1 TBTA_RX_N1 TBTA_RX_N1_U TBTA_RX_N1_C TBTA_USB2N_CONN TBTA_USB2P_CONN
CB4410 1 2 0.33U_25V_K_X5R_0402 A7 B6
[42] TBTA_RX_N1 Dn1 Dp2
TBTA_TX_P1 TBTA_TX_P1_U CB4411 1 2 0.22U_25V_K_X5R_0402 TBTA_TX_P1_C TBTA_SBU1_CONN A8 B5 TBTA_CC2_CONN
[42] TBTA_TX_P1 TBTA_TX_N1 TBTA_TX_N1_U TBTA_TX_N1_C SBU1 CC2
CB4412 1 2 0.22U_25V_K_X5R_0402
[42] TBTA_TX_N1 A9 B4
Vbus2 Vbus3
TBTA_RX_N1_C A10 B3 TBTA_TX_N1_C
SSRXn2 SSTXn2
TBTA_RX_P1_C A11 B2 TBTA_TX_P1_C
SSRXp2 SSTXp2

A12 B1
GND2 GND3

+3VALW 28 25
UB4401 29 GND8 GND5
26
GND9 GND6
CB4413 30 27
TBTA_USB2P_CONN RB4422 1 @ 2 0_0402_5% TBTA_USB2P_RE 0.1U_6.3V_K_X5R_0201 1 2 8 7 GND10 GND7
VCC NC
CB4414
TBTA_USB2N_CONN RB4421 1 @ 2 0_0402_5% TBTA_USB2N_RE 1U_6.3V_M_X5R_0201 1 2 HIGHS_UB11245-B200W-1H
2 3
TBTA_USB2P_RE HSD+ D+ TBT_PCH_USB20_P2 [9]
A A
LB4401 +3VALW TBTA_USB2N_RE 6 5
HSD- D- TBT_PCH_USB20_N2 [9]
2 1
2 1
RB4423
1 2 1 4
OE# GND
3 4
3 4
100K_0402_5%
1

EMC@ EXC24CH900U_4P tbd QB4401 TS3USB31ERSER_UQFN8_1P5X1P5

SSM3K35MFV_2-1L1B

2 Title
[45,47] EC_ON_PCH Security Classification LC Future Center Secret Data
Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL
3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. TBT CONN
Date: Thursday, July 30, 2020 Sheet 44 of 61
5 4 3 2 1
 5 4 3 2 1

+3VL
RE4501
+1.8VALW VCC_LPC_ESPI 1 2 1/10W_0_5%_0603
@ +3VL +3VALW VCC_FSPI
RE4502 2 1 0_0402_5%
@ +3VL_EC +3VL_EC_R
RE4503 2 1 0_0402_5% +3VS
RE4505
RE4504 1 2 0_0201_5% All capacitors close to EC 1 2 1/10W_0_5%_0603
EC_FAN_SPEED

CE4502
0.1U_6.3V_K_X5R_0201
@ RE45071 2 100K_0402_5%

1000P_50V_K_X7R_0201
1

0.1U_6.3V_K_X5R_0201
+3VL_EC

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
VCC_LPC_ESPI 1 1 1 1 1 1 1 1

CE4509
CE4501
1 CE4503 CE4504 CE4505 CE4506 CE4507 CE4508
VCC_FSPI EC_TP_ON

0.1U_6.3V_K_X5R_0201
1
DE4501 2 RB751V-40_SOD323-2 RE45081 @ 2 100K_0201_5%
2 @ @

CE4510
@ @
2 2 2 2 2 2 2 2
2 +3VL_EC +3VL_EC_R CPU_VR_READY RE45091 2 100K_0402_5%
1 2 RE4510 WRST#
WRST# [26]
D 100K_0402_5% 1 RE4511 D
+3VL_EC
CE4511 1 2
1/10W_0_5%_0603 EC_AGND
1U_6.3V_M_X5R_0201
2 USB_ON# RE4512 1 2 100K_0402_5%
EC_AGND
UE1

D10

K10
IT8227VG-192-CX_VFBGA128 +3VL_EC

D4
D5

K4

E6
E9

E4
J5
RE4564 1 @ 2 0_0201_5% EC_ESPI_IO0 K1 A10 RE4513 1 @ 2 0_0201_5% EC_SMB_CK0

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VCC

AVCC
VFSPI

VSTBY(PLL)
[7] ESPI_IO0 EC_SMB_CK0 [26,39]
0_0201_5% EC_ESPI_IO1 EC_SMB_DA0 LID_0D_SW#
EIO0/LAD0/GPM0(3) SMCLK0/GPF2
RE4565 1 @ 2 J2 B10 RE4514 1 @ 2 0_0201_5% RE45151 2 100K_0402_5%
[7] ESPI_IO1 EC_SMB_DA0 [26,39]
0_0201_5% EC_ESPI_IO2 EC_SMB_CK1
EIO1/LAD1/GPM1(3) SMDAT0/GPF3
RE4566 1 @ 2 J1 SM BUS B3
[7] ESPI_IO2 EC_SMB_CK1 [53]
RE4567 1 @ 2 0_0201_5% EC_ESPI_IO3 H2 EIO2/LAD2/GPM2(3) SMCLK1/GPC1
B2 EC_SMB_DA1
@ +3VALW
[7] ESPI_IO3 EC_ESPI_RST# EIO3/LAD3/GPM3(3) SMDAT1/GPC2 PECI_EC EC_SMB_DA1 [53]
M4 B1 1/20W_43_5%_0201 2 1 RE4517
ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3) H_PECI [6]
RE4572 1 @ 2 0_0201_5% EC_ESPI_CLK K2 C1
[7] ESPI_CLK ME_FLASH [6]
RE4573 1 @ 2 0_0201_5% EC_ESPI_CS# H1 ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3)
[7] ESPI_CS# ECS#/LFRAME#/GPM5(3)
EC_ON_PCH RE45161 2 100K_0201_5%

RE4524 1 @ 2 0_0201_5% ENBKL F1

[4,33] PCH_ENBKL 1 @ TP4506 G2 GA20/GPB5(3)
A11 EC_ON_PCH_R 1 @ 2 +3VL_EC
RE4518 0_0201_5%
PLT_RST# L2 ALERT#/SERIRQ/GPM6(3) PS2CLK0/CEC/TMB0/GPF0
B11 PBTN_OUT# 1 @ 2 EC_ON_PCH [44,47]
LPC RE4519 0_0201_5% Battery/Charge
[11,26,37,40,42,45] PLT_RST# PLTRST#/ECSMI#/GPD4(3) PS2DAT0/TMB1/GPF1 EC_TP_INT# PBTN_OUT#_R [11]
0_0201_5% RB4501 1 @ 2 N4 PS/2 D9 RE4590 1 @ 2 0_0201_5% PCH_TP_INT# [46] RE4520
[6] EC_SCI# ECSCI#/GPD3 PS2CLK2/GPF4 EC_NUM_LED# EC_SMB_DA1
WRST# L1 B9 RE4552 1 2 0_0201_5% 2 3 2.2K_0404_4P2R_5%
VGA_AC_DET_EC WRST# PS2DAT2/GPF5 NUM_LED# [8,46] EC_SMB_CK1
0_0201_5% RE4551 1 @ 2 H4 @ 1 4
[26] VGA_AC_DET KBRST#/GPB6(3)
RE4568 1 @ 2 0_0201_5% PCH_BEEP [8,31]
IT8227 PWM0/GPA0
PWM1/GPA1
M5
N5
PWR_LED_WIT#
@ RE4576 2 1 0_0402_5% PWR_LED_WIT#
EC_3/5V_USM [54]
[30]
+3VS

[8] ECLPM_BREAK
0_0201_5% RE4575 1 @ 2
EC_RTCRST#_ON
ECLPM_BREAK_R
E5
D2 CRX0/GPC0
CTX0/TMA0/GPB2(3) CIR
VFBGA PWM2/GPA2
PWM3/GPA3
SMCLK5/PWM4/GPA4
M6
N6
K6
J6
EC_KB_BKL_EN
EC_FAN_PWM
RE4570 1 @
RE4522 1 @

2 0_0201_5%
2 0_0201_5%
BATT_LOW_LED#
EC_KB_BKL_EN
EC_FAN_PWM [39]
[46]
[46]
GPU/Thermal
EC_SMB_CK0
EC_SMB_DA0
1
2
RE4523
4 2.2K_0404_4P2R_5%
3
SMDAT5/PWM5/GPA5 PM_SLP_S4# [11,41,47]
+3VL_EC
H_PROCHOT#_EC
PWM
B13
EC_ILIM D1 DAC4/DCD0#/GPJ4(3)
M11 EC_FAN_SPEED RE4589
[53] EC_ILIM FDIO3/DSR0#/GPG6 TACH0A/GPD6(3) FPR_PWR_EN EC_FAN_SPEED [39] EC_SMB_DA4
[56] EC_ANS RE4588 1 @ 2 0_0201_5% N7 M12 RE4580 1 @ 2 0_0201_5% 1 4 2.2K_0404_4P2R_5%
GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) FPR_PWR_EN [38] EC_SMB_CK4 2 3
C C
EC_VR_ON C12 C2
[56] EC_VR_ON DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) CHG_MOD3 [30]
E1 SUSP#
M1 TMRI1/GPC6(3) SUSP# [47] EC_PD_INT# RE4525 1 2 100K_0402_5%
[40] EC_TX TXD/SOUT0/LPCPD#/GPE6
M2
[40] EC_RX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
RE4526
ADP_I F10 A5 NOVO# EC_SMB_DA3 1 4 2.2K_0404_4P2R_5%
[53] ADP_I NOVO# [30]
0_0201_5% RE4554 1 @ 2 DCIN_ATTACHED_EC_R F12 ADC5/DCD1#/GPI5(3) GPE4
N1 RE4571 1 @ 2 0_0201_5% EC_SMB_CK3 2 3
[52] DCIN_ATTACHED_EC ADC6/DSR1#/GPI6(3) UART port WAKE UP RI1#/GPD0(3) USB_ON# PM_SLP_S3# [11]
PSYS E13 N3 PMIC
[53,56] PSYS ADC7/CTS1#/GPI7(3) RI2#/GPD1 USB_ON# [30]
1K_0201_5% 1 2 RE4527 N8
[11] PCH_DPWROK BATT_CHG_LED#_R RTS1#/GPE5
RE4521 1 @ 2 0_0201_5% K7
[46] BATT_CHG_LED# SYS_PWROK PWM7/RIG1#/GPA7 EC_ON_5V
F4 A1
[11] SYS_PWROK EC_SMB_DA3 D7 FDIO2/DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7
B4 ON/OFF
EC_ON_5V
ON/OFF [30]
[54] when mirror, GPG2 pull high
[55] EC_SMB_DA3
[55] EC_SMB_CK3
EC_SMB_CK3 E8 CTX1/SOUT1/GPH2/SMDAT3/ID2
CRX1/SIN1/SMCLK3/GPH1/ID1
PWRSW/GPB3
GPB4
A2
A3
EC_ON_3V_R RE4549 1 @
LID_0D_SW#
2 0_0201_5% EC_ON_3V
EC_ON_3V [54] when no mirror, GPG2 pull low +3VL_EC
LID_0D_SW# [39]
RE4529 1 2 1/20W_100_1%_0201 EC_SPI_CLK B5 GPB1
A4 ACIN# RE4530 1 @ 2 0_0201_5%
[7] SPI_CLK EC_SPI_CS0# A7 FSCK GPB0 ACIN [53] RE45321 2 100K_0402_5%
GPG2
[7] EC_SPI_CS0# 1 2 1/20W_100_1%_0201 EC_SPI_SI B6 FSCE#
RE4533 EXTERNAL SERIAL FLASH
[7] SPI_SI 1 2 1/20W_100_1%_0201 EC_SPI_SO A6 FMOSI
G10 EC_VCCST_EN EC_ON_3V
RE4534 0_0201_5% RE4528 1 @ 2 RE4535 1 2 100K_0402_5%
[7] SPI_SO EC_VCCST_EN [47]
FMISO ADC0/GPI0(3)
G13 PM_SLP_S0#_R RE4536 1 @ 2 0_0201_5%
K13 ADC1/GPI1(3)
G12 BATT_TEMP_R @ RE4547 2 BATT_TEMP
1 0_0402_5% PM_SLP_S0# [11,47] PCH_PWR_EN
KSO16 NEED CONFRIM RE4537 1 @ 2 100K_0402_5%
KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) PM_SLP_SUS#_R BATT_TEMP [53]
KSO17 J10 F9 RE4538 1 @ 2 0_0201_5%
EC_VPP_PWREN KSO17/SMISO/GPC5(3) ADC3/GPI3(3) CPU_VR_READY PM_SLP_SUS# [11] EC_ON_5V
M7 F13 RE4539 1 2 100K_0402_5%
[55] EC_VPP_PWREN PWM6/SSCK/GPA6 ADC4/GPI4(3) CPU_VR_READY [56]
GPG2 E7 A/D D/A
EC_OTG RE4581 1 @ 2 0_0201_5% E2 SSCE0#/GPG2
[53] EC_OTG SSCE1#/GPG0 SPI ENABLE EC_VCCST_PWRGD
E12
TACH2A/GPJ0 EC_MUTE#_R RE4542 1 @ EC_VCCST_PWRGD [11]
KSO0 M8 D13 2 0_0201_5% EC_MUTE# [31]
KSO1 J7 KSO0/PD0 TACH2B/GPJ1
D12 EC_TP_ON SUSP# RE4540 1 2 100K_0402_5%
KSI[0..7] KSO2 N9 KSO1/PD1 DAC2/TACH0B/GPJ2(3)
C13 BKOFF# EC_TP_ON [46]
[46] KSI[0..7] KSO2/PD2 DAC3/TACH1B/GPJ3(3) BKOFF# [33]
KSO3 M9
KSO3/PD3
KSO[0..17] KSO4 K8
[46] KSO[0..17] KSO4/PD4 EC_VCCST_EN RE4543 1
KSO5 J8 @ 2 100K_0201_5%
KSO5/PD5
KSO6 N10
KSO6/PD6
KSO7 M10 BKOFF# RE4545 1 2 100K_0402_5%
KSO7/PD7
KSO8 N11
KSO8/ACK# EC_VPP_PWREN RE4591 1
KSO9 K9 2 100K_0201_5%
KSO9/BUSY
KSO10 N12
B KSO10/PE PCH_PWR_EN RE4592 1 B
KSO11 N13 G1 RE4574 1 @ 2 0_0201_5% EC_ADP_CTRL [52]
2 100K_0201_5%
KSO11/ERR# GPJ7
RE4562 1 @ 2 0_0402_5% KSO12 M13 CLOCK F2 RE4548 1 @ 2 0_0201_5%
[11,26,37,40,42,45] PLT_RST# KSO12/SLCT GPJ6 AC_PRESENT_R [11]
KSO13 L12
EC_ESPI_RST# KSO13
RE4563 2 @ 1 0_0402_5% KSO14 L13
[7] ESPI_RST# K12 KSO14
B12 CHG_MOD1
KSO15 KBMX
KSO15 EGCLK/GPE3 CHG_MOD1 [30]
A12
EGCS#/GPE2 EC_PD_INT# FPR_AL0 [38] EC_SMB_CK0
A13 EC_PD_INT# [41] CE45121 @2 100P 25V J NPO 0201
EGAD/GPE1
KSI0 J12
KSI0/STB# EC_SMB_DA0
KSI1 J13 CE45131 2 100P 25V J NPO 0201
KSI2 J9 KSI1/AFD#
N2 EC_SMB_CK4 @
H12 KSI2/INIT# SMCLK4/L80HLAT/BAO/GPE0
M3 EC_SMB_DA4 EC_SMB_CK4 [41]
KSI3
KSI3/SLIN# SMDAT4/L80LLAT/GPE7 EC_SMB_DA4 [41]
KSI4 H9 GPIO
KSI5 H10 KSI4
J4 USB_CHG_EN
KSI5 GPH7 PCH_PWROK USB_CHG_EN [30] PM_SLP_S4#
1KSI6 H13 B7 PCH_PWROK [11]
CE45151 2 1000P_50V_K_X7R_0201
TP4501 @ 1KSI7 G9 KSI6 ID6/GPH6
A8 FPR_LED_AMBER#_R
RE4585 1 @ 2 FPR_LED_AMBER#
0_0201_5% EMC_NS@
KSI7 ID5/GPH5 FPR_LED_AMBER# [30] PM_SLP_S3#
TP4502 @ B8 RE4586 1 @ 2 0_0201_5% CE45161 2 1000P_50V_K_X7R_0201
ID4/GPH4 FPR_DELINK_E [38]
A9 RE4582 1 @ 2 0_0201_5% PCH_PWR_EN [55] EMC_NS@
ID3/GPH3
VCORE

D8 RE4555 1 2 1K_0201_5%
AVSS

EC_RSMRST# [11]
VSS1
VSS2
VSS3
VSS4
VSS5

CLKRUN#/ID0/GPH0

NOVO# CE45181 2 0.01U_0201_10V6K

@
D6
F5
G4
G5
H5

E10

K5

PECI_EC CE45191 2 47P_25V_J_NPO_0201

EMC_NS@
VCOREVCC 1 2 CE4520 BATT_TEMP CE45211 2 100P 25V J NPO 0201
0.1U_6.3V_K_X5R_0201 EMC_NS@
ACIN# CE45221 2 100P 25V J NPO 0201
RE4546 1 @ 2 0_0201_5% PM_SLP_S0#_R EMC_NS@
[38] FPR_SCL
RE4587 1 @ 2 0_0201_5% EC_AGND ON/OFF CE4523 1 2 1U_6.3V_M_X5R_0201
[30] AOU_DET# EC_RTC_RST# [10]
@
PLT_RST# CE45241 2 220P_25V_K_X7R_0201
EC_SMI RE4579 1 @ 2 0_0201_5% EMC_NS@
[7] EC_SMI
For ESD
Emergency Power Loss Early De-assertion of DSW_PWROK control circuit
1

RE4558 1 @ 2 0_0201_5% H_PROCHOT# [6,13,55] QE4501 DE4502

[53,56] VR_HOT#
1

ALW_PWRGD @ RE4559 2 1 0_0402_5% 1 2 EC_RSMRST#

A RE4560 EC_RTCRST#_ON 2 [54,55] ALW_PWRGD A
1
100_0402_5% CE4525 1 2
1

47P_25V_J_NPO_0201 SSM3K15AMFV_2-1L1B RB521CM-30T2R_VMN2M-2

3

@ RE4561 DE4503
2

2 10K_0201_5%
1 2 PCH_DPWROK
1

QE4502
2

1 2

H_PROCHOT#_EC RB521CM-30T2R_VMN2M-2
2
Security Classification LC Future Center Secret Data Title
SSM3K15AMFV_2-1L1B
3

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. EC
Date: Tuesday, August 11, 2020 Sheet 45 of 61
5 4 3 2 1
 5 4 3 2 1

KB Backlight Connector
+5VALW +5VS +VCC_KB_LED

QI4601 BL@

2
3 1

D
RI4601 LP2301ALT1G_SOT-23-3
BL@
10K_0201_5%

G
1

2
D D

1
BL@ CI4601
RI4602 1 BL@ 2 30K_0402_1% 0.1u_0201_10V6K
2

1
QI4602 1
BL@
BL@ CI4602
RI4603 1 @ 2 0_0201_5% 2 0.01U_0201_10V6K
[45] EC_KB_BKL_EN 2
1
SSM3K15AMFV_2-1L1B

3
CI4603 BL@
0.1u_0201_10V6K
2

+VCC_KB_LED ME@
HIGHS_FC1AF040-1201H
6
GND2
5
GND1

4
4
3
3
1 2
2
1
CI4604 1

0.1u_0201_10V6K @ JKBL
2

C C

RI4626 1 2 200_0402_1% JP1 TP/B Connector

K/B Connector +3VS
RI4611 1 @ 2 200_0402_1% PWR_CAPS/NUM_LED 1
+3VALW CAPS_LED#_R 1
@ RI4610 2 1 0_0402_5% 2
[45] CAPS_LED# 2
KSO15 3
3
KSO10 4
KSI[0..7] 4
KSO11 5
[45] KSI[0..7] 5
KSO14 6
KSO[0..17] 6
KSO13 7
[45] KSO[0..17] 7
KSO12 8
8
KSO3 9 JTP ME@
KSO6 10 9
RI4606 1 @ 2 0_0201_5% EC_TP_ON_R 1
PWR_CAPS/NUM_LED 10 [45] EC_TP_ON TP_INT# 1
100P 25V J NPO 0201 EMC_NS@ 2 1 CI4605 KSO8 11 RI4607 1 @ 2 0_0201_5% 2
11 [8] PCH_TP_INT# 2
KSO7 12 3
12 3
KSO4 13 4
100P 25V J NPO 0201 2 1 CI4608 CAPS_LED#_R KSO2 14 13
5 4

KSI0 15 14 PCH_I2C1_SDA_TP RI4608 1 @ 2 0_0201_5% TP_I2C_SDA_R 6 5

15 [8] PCH_I2C1_SDA_TP PCH_I2C1_SCL_TP TP_I2C_SCL_R 6
KSO1 16 RI4609 1 @ 2 0_0201_5% 7
17 16 [8] PCH_I2C1_SCL_TP 8 7
DI4601 EMC@ KSO5
17 TP_PWR 8
18

100P 25V J NPO 0201

100P 25V J NPO 0201

KSI3
18 1 1
2 1 KSI2 19 9
2 1 19 GND1
KSO0 20 10
20 GND2
KSI5 21

EMC_NS@

EMC_NS@
21
AZ5123-01F.R7GR_DFN1006P2X2 KSI4 22 2 2 HIGHS_FC5AF081-2931H

CI4606

CI4607
22
KSO9 23
23
KSI6 24
24
DI4606 EMC@ KSI7 25
25
KSI1 26
2 1 NUM_LED# KSO16 27 26
2 1 27
KSO17 28
28
29
[8,45] NUM_LED# 29
AZ5123-01F.R7GR_DFN1006P2X2 30
RI4615 1 PWR_Fnlk/Mute/Mic_LED
2 200_0402_1% 31 30
35
+3VALW 32 31 GND2
36
DI4607 EMC@ @
32 GND1
+3VS RI4625 1 2 200_0402_1% 33
2 1 Fnlk_LED# 34 33
B 2 1 34 B

[8] Fnlk_LED#
AZ5123-01F.R7GR_DFN1006P2X2
HIGHS_FC8AF341-3201H
ME@
+3VS TP_PWR

@ RI4612 2 1 0_0402_5%
+3VALW 1
CI4609
LED1
0.1U_6.3V_K_X5R_0201
2
[45] BATT_LOW_LED# 1 2 300_0402_5% 1 2 RI4613

L-C192JFCT-LCFC_SUPER_AMBER
+3VALW

LED2
1 2 300_0402_5% 1 2 RI4614
[45] BATT_CHG_LED# TP_I2C_SCL_R

L-C192WDT-LCFC_WHITE
TP_I2C_SDA_R

1
1

1
DI4602 DI4603
AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2
EMC_NS@ EMC_NS@

2
2

2
A A
BATT_CHG_LED#

BATT_LOW_LED#
1

LED Stute LED Behavior

1

DI4604 DI4605
Battery only OFF AZ5123-01F.R7GR_DFN1006P2X2 AZ5123-01F.R7GR_DFN1006P2X2 Title
EMC_NS@ EMC_NS@ Security Classification LC Future Center Secret Data
Charge LED Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL
2

Amber_on(battery£º1%~90%)
Charging
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
White_on(battery£º91%~100%) C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. KB/FP/TP_CONN.
Date: Sunday, August 02, 2020 Sheet 46 of 61
5 4 3 2 1
 A B C D E

+3VALW +5VALW
+5VS

0.01U_0402_25V7K
CX4709
1 CX4702 J3 @
1U_6.3V_M_X5R_0201 UX4702 +5VS_LS 1 2
2 1 2
1 14
2 IN1_1 OUT1_2 13
1 JUMP_43X79 1
2 IN1_2 OUT1_1
+3VALW_PCH @
@ CX4701 PJ4701 RX4704 1 2 0_0402_5% 5VSON 3 12 CX4705 1 2 1000P_50V_K_X7R_0201 CX4706
1U_6.3V_M_X5R_0201 +3VALW_PCH_LS 1 2 [45,47] SUSP# EN1 CT1
UX4701 0.1U_6.3V_K_X5R_0201
2 1 2 2
1 14 4 11
IN1_1 OUT1_2 +5VALW VBIAS GND
2 13 JUMP_43X79 1 @
IN1_2 OUT1_1
@ RX4706 1 2 0_0402_5% 3VSON 5 10 CX4708 1 2 1000P_50V_K_X7R_0201
[44,45] EC_ON_PCH
RX4703 1 2 0_0402_5% 3VPCHON 3
EN1 CT1
12 CX47031 2 1000P_50V_K_X7R_0201 @ CX4704
EN2 CT2 +3VS
1 0.1U_6.3V_K_X5R_0201 6 9 J4 @ 1
2 IN2_1 OUT2_2 +3VS_LS
+5VALW RX4733 1 @ 2 0_0201_5% VBIAS 4 11 +1.8VGS 7 8 1 2
VBIAS GND IN2_2 OUT2_1 1 2

0.01U_0402_25V7K
CX4712

0.01U_0402_25V7K
CX4713
@ 1 1 1
1.8VGS_PWR_EN 1.8VGS_PWR_EN2
RX4710 1 2 0_0402_5% 5 10 CX47071 2 1000P_50V_K_X7R_0201 15 JUMP_43X79
[23,26] 1.8VGS_PWR_EN EN2 CT2 Thermal Pad
CX4714

1
1 6 9 OPT@ G2898KD1U_TDFN14P_2X3
0.1u_0201_10V6K

0.1U_6.3V_K_X5R_0201
7 IN2_1 OUT2_2 8 2 2 +3VALW 2

CX4732
RX4745 PJ4702
IN2_2 OUT2_1 +1.8VGS_LS 1 2
100K_0402_5% 1 @ @
1 2
@ UMA@ 15
DX1 RX4744 2 Thermal Pad
@ @ JUMP_43X39 CX4731

2
@ 1 2 1 2 0.1U_6.3V_K_X5R_0201 1
49.9K_0402_1%
2 OPT@
RB521CM-30T2R_VMN2M-2 CX4716
1U_10V_M_X5R_0201
2

CX4715
RX4711 1 @ 2 0_0402_5% 1U_6.3V_M_X5R_0201
+1.8VALW 2
@ OPT@
+1.8V_AON RX4713 1 2 0_0402_5%

+5VL +1.8VALW +1.8VS

QV4711
0.6A
3 1 LP2301ALT1G_SOT-23-3

D
2
1
RV4780 1

G
2
100K_0402_5% CV4780
0.1U_6.3V_K_X5R_0201 CV4782
2 0.1U_6.3V_K_X5R_0201 1 1

1
2
CV4783 CV4784
SUSP RV4781 1 @ 2 0_0201_5% 0.1U_6.3V_K_X5R_0201
2 2 0.1U_6.3V_K_X5R_0201

1
QV4710 1
SSM3K15AMFV_2-1L1B
2 @ RV4782 CV4781
[45,47] SUSP#
470K_0402_5% 0.1U_6.3V_K_X5R_0201
2

2
SUSP [34]
2 2

+3VS

1
+3VALW +VCC1.05_OUT_FET
R3116
100K_0201_5%
@ 1 1

2
CX4717 CX4718
R3118 1 @ 2 0_0201_5% 1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
[11,45] PM_SLP_S0# 2 2
UX4704 UX4710
VCCSTG_EN_A VCCSTG_EN_A VCCSTG_EN_B
R3119 1 2 0_0402_5% 1 4 1 4
[11] CPU_C10_GATE# EC_VCCST_EN IN B OUT Y VCCIN_AUX_VALID IN B OUT Y
RX4736 1 @ 2 0_0201_5% 2 2 +VCCSTG_CPU
[45] EC_VCCST_EN IN A IN A
+VCCSTG_CPU_LS
SLP_S3# @ 3 5 3 5 UX4703 @ 150mA
3V3_VCCST_OVERRIDE 1 2 0_0402_5% GND Vcc GND Vcc 2 4 RX4720 1 2 0_0402_5%
VIN VOUT
RX4737
MC74VHC1G32DFT2G_SC70-5 MC74VHC1G32DFT2G_SC70-5 5 3
VBIAS NC
+3VALW @ +3VALW @
VCCSTG_EN_A 2 0_0402_5%VCCSTG_EN
OR Gate OR Gate RX4738 1 6 1
ON GND
VCCSTG_EN_B
1 RX4739 1 2 0_0201_5% EM5201BJ-45_SOT23-6
1 @
C3132
C3131 @ 0.1U_6.3V_K_X5R_0201

1
0.1U_6.3V_K_X5R_0201 2
2 RX4716
200K_0402_5%

2
3 3

+3VALW +VCC1.05_OUT_FET
+VCCST_CPU

1 1

CX4723 CX4724
1U_6.3V_M_X5R_0201 10U 6.3V M X5R 0402
2 2
+VCCST_CPU_LS
+3VALW UX4706 @
2 4 RX4730 1 2 0_0402_5%
VIN VOUT
1

5 3
VBIAS NC
RX4719 @
PM_SLP_VCCST_OVRD VCCST_EN 6
100K_0402_5% RX4735 1 2 0_0402_5% 1
ON GND
+3VALW UX4705 UX4707 EM5201BJ-45_SOT23-6
3V3_VCCST_OVERRIDE PM_SLP_VCCST_OVRD PM_SLP_VCCST_OVRD_R VCCST_EN_R
2

1 4 RX4724 1 2 0_0201_5% 1 4 RX4725 1 2 0_0201_5%

EC_VCCST_EN 2 0_0402_5% +VCCST_EN IN B OUT Y IN B OUT Y
RX4721 1 2 @ 2 @
1

IN A IN A

RX4722 @ 3 5 3 5 RX4728 1 2 0_0201_5%

GND Vcc GND Vcc [11,41,45] PM_SLP_S4#
100K_0402_5% +3VALW @

1
3

QX4701B MC74VHC1G32DFT2G_SC70-5 RX4727 MC74VHC1G32DFT2G_SC70-5

2

OR Gate 1 1/20W_200K_5%_0201 @ OR Gate

D2

VCCST_OVERRIDE#

1
5 @
G2
CX4725 RX4729

2
0.1U_6.3V_K_X5R_0201 +3VALW 200K_0402_5%
S2

2
4

2
PJT7838_SOT363-6
1
6

QX4701A
CX4726
D1

2 0.1U_6.3V_K_X5R_0201
[11] VCCST_OVERRIDE G1 2
S1

PJT7838_SOT363-6
1

4 UX4711 4
1 4 VCCIN_AUX_VALID VCCIN_AUX_VCCST_PRESENT
RX4731 1 2 0_0201_5%
[13,55] VCCIN_AUX_VID0 2 IN B OUT Y
@
[13,55] VCCIN_AUX_VID1

1
IN A
3 5 RX4732
GND Vcc
1/20W_200K_5%_0201
+3VALW @
MC74VHC1G32DFT2G_SC70-5

2
@ OR Gate
1

CX4730
0.1U_6.3V_K_X5R_0201
2

Security Classification LC Future Center Secret Data Title

Issued Date 2018/12/04 Deciphered Date 2018/08/20

S550-IIL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Name Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. DC V TO VS Interface
Date: Saturday, August 01, 2020 Sheet 47 of 61
A B C D E
 5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, May 28, 2020 Sheet 48 of 61
5 4 3 2 1
 5 4 3 2 1

NH1 H2
HOLEA HOLEA

PCB Fedical Mark PAD

1
1

FD1 FD2

pad_c2p5d2p5n pad_ct7p0d2p5

1
@ @
@ @

FD3 FD4

H3 H4
HOLEA H5 H6 H7
HOLEA

1
D HOLEA HOLEA HOLEA D
@ @
1

FD5 FD6
1

1
PAD_C7P0D3P3

1
PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3 PAD_C7P0D3P3
@
@ @ @ @ @ @

H8 H9 H10
HOLEA HOLEA HOLEA NH11
HOLEA
1
1

PAD_C6P0D2P5 PAD_C7P0D3P3 pad_ct7p0d3p7x3p2 pad_o2p5x3p0d2p5x3p0n

@ @ @
@

SH1 SH2 SH3

1 1 1
1 1 1

SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P

ME@ ME@ ME@
C C
SH4 SH5 SH6

1 1 1
1 1 1

SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P

ME@ ME@ ME@
SH7 SH8 SH9

1 1 1
1 1 1

SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P

ME@ ME@ ME@

SH10 SH11 SH12

1 1 1
1 1 1

SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P SHIELDING_SUL-15A3M_6X1P2_1P

ME@ ME@ ME@

B B

MEMORY SHELDING

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/20 Deciphered Date 2016/08/20 S550-IIL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Hole
Date: Thursday, August 13, 2020 Sheet 49 of 61
5 4 3 2 1
 5 4 3 2 1

+3VLP/ 100mA

Richtek +3VALW/ 6A
EN
RT6585B
D D

+5VLP/ 100mA

Adaptor Converter +5VALW/10A

65W/95W FOR SYSTEM
EN PGOOD

+VDDQ/8A

+0.6V/1A

Richtek +1.8VPP/1A

LV5116A
+VCCIN_AUX/14A
SYSON S0
PMIC ANEPC
EC_VPP_PWREN S3
C
+1.8VALW/3A APL5930CQBI C
PCH_PWR_EN EN
FOR DDR PGOOD LDO 1.0VGS/1A
TI
BQ25710ARUYR EN

Battery Charger
Switch Mode

Richtek +VCCIN/39A

RT3612EB
SMBus V9B+ Converter
EN FOR CPU Core
PGOOD

Battery Richtek +1.35V/8A

B B
polymer
LV5095B
3S1P/4S1P
EN GPU PMIC
FOR GPU VRAM PGOOD

UPI
UP1666QQKF +VGA_CORE/30A

EN Switch Mode
PGOOD
FOR GPU VDDC

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 S550-IIL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR-Power Diagram
Date: Thursday, May 28, 2020 Sheet 51 of 61
5 4 3 2 1
 5 4 3 2 1

CHARGER_IN
APDIN_1 PQ106 APDIN_2 PQ100

1
AONR21357_DFN8
8 8
AONR21357_DFN8
1
4.5A
3.5A HCB2012KF-121T50_0805
2
3
7
6
7
6
2
3
JDCIN1
PL100 5 5

1000P_50V_K_X7R_0201

1000P_50V_K_X7R_0201

1000P_50V_K_X7R_0201

1000P_50V_K_X7R_0201

1000P_50V_K_X7R_0201
1 ADPIN 1 2

1000P_0402_50V7K
1
2

402K_0402_1%

1000P_0402_50V7K
EMC@

4
GND1

1
3

402K_0402_1%

PC114
1 1 1 1 1

SPHV24-01ETG-C_SOD882-2
1

1
GND2

PC101

PC103

PC104

PC102

PC105
4

PR113

PR100

PC100
470P_50V_K_X7R_0201

1000P_50V_K_X7R_0201
GND3
5

499K_0402_1%
PD100
HCB2012KF-121T50_0805

1000P_50V_K_X7R_0201

470P_50V_K_X7R_0201
1

1
GND4
6

PC106

PC107
PL101

2
2

2
GND5 2 2 2 2 2
7 1 2

PC108

PC109

PR101

2
GND6

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
EMC@

1
D HIGHS_PJSSR26-D1005-1H D

EMC_NS@

2
2
ME@

1
EMC@ EMC@ PR102 PR114

EMC@ EMC@
100K_0402_5% 100K_0402_5%

2
6

3
D D
2 PQ107A 5 PQ107B
L2N7002KDW1T1G_SOT363-6
G G L2N7002KDW1T1G_SOT363-6 APDIN_1
S S

4
APDIN_1

2
PR105
1/20W_200K_1%_0201

1
PR103

1
PR106 PR107 2 1 100K_0201_5%
DCIN_ATTACHED 1 2 300K_0402_1%

2
1
100K_0402_5%

2
1

1
PR104
PC110 100K_0402_5% PC116 1 3
1000P_0402_50V7K 0.1U_25V_K_X5R_0402 DCIN_ATTACHED_EC [45]

0.1U_25V_K_X5R_0402
2

2
TYPEC ADP=95W, Pull high

PC111
SSM3K15AMFV_2-1L1B
Others, pull low 53.6K_0402_1% PQ103

2
PR108

1
1

1
PQ108 PQ102
EC_ADP_CTRL
SSM3K15AMFV_2-1L1B
PD_VBUS_C_CTRL1_R
SSM3K15AMFV_2-1L1B DCIN_ATTACHED_EC connecrt to EC, As
C 2 2 C
[45] EC_ADP_CTRL Slim Tip Adapter attached signal
3

3
1

PR115
100K_0402_5%
2

VBUS_TBTA VCC3_LDO_PD

@
PR117 1 2 PR109 1 @ 2 0_0402_5%
10K_0402_5%

2
1
PU100
4.5A PC112
PR118
1/16W_100K_5%_4P2R_0404
1 2 B2 B3
VBUS1 OVLO
C2 A2

3
4
HCB2012KF-121T50_0805 1U_25V_K_X5R_0402 D2 VBUS2 ACK PD_ACK_SNK1
VBUS3 PD_ACK_SNK1 [41]
PL102 E1 C3
CHARGER_IN 1 2 CHARGER_OUT E2 VBUS4 GND1
D3
VBUS5 GND2
EMC@ E3
GND3 PR110
A1
HCB2012KF-121T50_0805 B1 VINT1
A3 PD_VBUS_C_CTRL1_EN# 1 @ 2 PD_VBUS_C_CTRL1
VINT2 EN#
PL103 C1
VINT3
1 2 D1
VINT4 0_0402_5%
EMC@

2
NX20P5090UK_WLCSP15 PR111
2

0_0402_5%
PC113 @
B B
1U_25V_K_X5R_0402
1

1
100K_0402_5%
PR116

1
1 2 TBTA_GATE_VSYS [41]
PQ104
PR112
SSM3K15AMFV_2-1L1B
2 PD_VBUS_C_CTRL1_R 1 2 PD_VBUS_C_CTRL1 [41]
@

3
100K_0402_5%

1
PQ105
SSM3K15AMFV_2-1L1B
2 DCIN_ATTACHED
PD_VBUS_C_CTRL1 H --> TPYE C 1 Use --> PD_VBUS_C_CTRL1_EN# Low

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2015/08/20 Deciphered Date 2016/08/20 POWER SYMBOL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550 ICL
Date: Thursday, July 30, 2020 Sheet 52 of 61
5 4 3 2 1
 A B C D

MOSFET based on adapter power and choice from common pool ADIN_R V9B+
6pcs MLCC when VAP enable
9V~17.6V/10A

2200P_0201_25V7-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K

0.1U_0201_25V6-K
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

EMC@
EMC_OPT@
1 1 1 1 1 1 1 1

EMC_NS@

EMC_NS@
220P_0201_25V7-K

1
EMC_OPT@

PC9928
PQ300 PQ301

PC300

PC301

PC302

PC303

PC304

PC305

PC9929

PC9930

PC9931

PC9932

PC9933
AON6324_DFN8-5 AON7380_DFN8-5

2
2 2 2 2 2 2 2 2
4 4

6pcs MLCC when VAP enable

MLCCs must be placed 1
PL9901
2

3
2
1

1
2
3
CHARGER_IN mirror on Top and Bottom. HCB2012KF-121T50_0805
1
4.5A 1
PR300
4 1
PL300
2
PL9902
1 EMC@ 2
1

2.2UH_CMMB103T-2R2MS_13.2A_20% HCB2012KF-121T50_0805
2 3 EMC@

0.1U_0402_25V6
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
1 1 1 1 1 1

5
PQ304

5
BATT+
PC306

PC307

PC308

PC309

PC310

PC311

PC312
0.01_1206_1% AON7405_DFN8-5

0.047U_0402_25V7K

0.047U_0402_25V7K
PQ302

D
1

1
PQ303 1 JBATT5 ME@

PC313

PC314
AON6324_DFN8-5

4.7_0603_5%
PR303

2
2 2 2 2 2 2 AONR32340C_DFN8-5 2 1
9V~17.6V/10A

EMC_NS@

EMC_NS@
1

4.7_0603_5%
1
3 5 1 4 2

PR301

PR302
2

2
4 4 EC_SMCLK_BATT 3 2
G 2 3 EC_SMDAT_BATT 4 3

1
BATT_TEMP 5 4
MLCCs must be placed

S1
S2
S3

1 2

4
6 5 9

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
PR304 1 1

1 2
0.01_1206_1% 6 GND1
mirror on Top and Bottom.

100P_0201_25V8J
0.1U_0402_25V6
1_0603_5% 7 10

PC318

PC319
EMC_NS@
0_0402_5%

0_0402_5%

710_BATDRV
1

3
2
1

1
2
3

1
7 GND2

0.1U_0402_25V6
8 11

PR307

PC316

PR308

PC317
EMC_NS@
8 GND3 12

PC315
2

2
2 2 GND4
PR305 PR306

2
4.99_0402_1% 4.99_0402_1% PR309 @ HIGHS_WS33081-S120C-1H
@ @ 2 1
PU300
2

1
@
layout note: put near IC 1PC3202 0_0402_5% PC322
0.033U_25V_K_X7R_0402

0.033U_25V_K_X7R_0402

1
710_BTST1 30 25 710_BTST2 1 2
BT ST 1 BT ST 2

1U_25V_K_X5R_0402
PR335
trace as pair PR336
1

1
710_PH1 710_PH2

0.1U_0402_25V6

0.1U_0402_25V6
0.1U_0402_25V6 32 23 0.1U_0402_25V6 100_0402_1%

PC324
SW1 SW2 100_0402_1%

0.1U_0402_25V6
@
PC323

PC321

PC327
1

1
710_LG1 29 26 710_LG2

PC325

PC326
2

2
LODRV1 LODRV2
710_UG1 31 24 710_UG2 layout note: put near IC

2
HIDRV1 HIDRV2

CHRG_GND CHRG_GND
710_VBUS 1
VBUS VSYS
22 trace as pair
CHRG_GND CHRG_GND
710_ACN 2 21 710_BATDRV_N
ACN BAT DRV# EC_SMB_CK1
710_VDD 710_VDDA 710_ACP 3 20 710_SRP 2 1 10_0402_1%
PR310
PR311 ACP SRP
1 2 710_VDDA 7 19 710_SRN PR312 2 1 10_0402_1%
VDDA SRN
2 710_VDDA 2
1

174K_0402_1%

710_VDD EC_SMB_DA1
10_0603_5%
1

710_ILIM
1U_0402_10V6K

6 28 PC329 1 2 2.2U_10V_K_X5R_0603
PC328

PR313

1
ILIM _HIZ REGN
PC330
1 2 PR314 1 2 40.2K_0402_1% 710_COMP1 710_COMP2
PC331 2 1 15P_0402_50V8J PR316
CHRG_GND
2

16 17 33.2K_0402_1%
CHRG_GND
2

1 2 33P_0402_50V8J COM P1 COM P2 2 1 10K_0402_1% 2 1 680P_0402_50V7K

1800P_0402_50V7-K PC332 PR315 PC333
check pull high in EC or CPU @
1

2
100K_0402_1%

710_PROCH 11 710_PRES
PR317 2 1 0_0402_5% 18
[45,56] VR_HOT# PROCHOT # CELL_BAT PRES
@
PR318

1
PR319 2 1 0_0402_5% 710_SCL 13 @
[45] EC_SMB_CK1 SCL 8 710_IADP
@ PR3202 1 0_0402_5%

PR321
100K_0402_1%
PR322 2 1 0_0402_5% 710_SDA 12 IADPT ADP_I [45]
[45] EC_SMB_DA1
2

@
SDA 9 710_IDCHG
PR323 2 1 0_0402_5% 710_CHGOK 4 IBAT
@

2
CHRG_GND [45] ACIN CHRG_OK
10 710_PSYS PR3242 1 0_0402_5%
1 2 710_OTG 5 PSYS PSYS [45,56]
+3VL

20K_0402_1%
1

1
137K_0402_1%
ENZ_OT G

100P_0201_25V8J

100P_0201_25V8J

100P_0201_25V8J
PR337 100K_0402_5% 27
+3VL
1

1
PGND
SSM3K15AMFV_2-1L1B

15 CHRG_GND

PR326

PC334

PC335

PR327

PC336
1

100K_0402_1%
CM POUT 33
PQ305

default: L 1 2 100K_0402_1% 14 PAD

+3VALW PR325 PR328

1
2

2
SSM3K15AMFV_2-1L1B

2 CM PIN
[45] EC_ILIM

2
PR329 @ PR330
1
1/20W_1M_1%_0201

1 2 100K_0402_1% 100K_0402_5%
+3VL
1

1
CHRG_GND
PQ306

BQ25710RSNR_QFN32_4X4 CHRG_GND
CHRG_GND CHRG_GNDCHRG_GND CHRG_GND PQ307
PR331

2
2 CHRG_GND SSM3K15AMFV_2-1L1B
[45] EC_OTG PJ300 2
[45] BATT_TEMP
1/20W_1M_1%_0201

default: L 1 2
2

3
@

JUMPER PR333
PR332

@ 1M_0402_1%
@
2

2
CHRG_GND
PR334 1 2 0_0402_5%
@

3 3

IND IN USE PR326 # of CELL VCELL_PRES PR316

IDPM V(ILIM) PR313
500mA 1.2V 402K 1uH 93K 1-CELL 1.5V 301K
1.0A 1.4V 332K 2.2uH 137K LOGIC 2-CELL 2.4V 150K
1.5A 1.6V 280K 3.3uH 169K 3-CELL 3.3V 82K
2.0A 1.8V 237K
LOGIC 4-CELL 4.5V 33.2K LOGIC
3.0A 2.2V 174K
3.25A 2.3V 162K
4.0A 2.6V 162K
VILIM=1V+40x(VACP-VACN)=1+40xIDPMxRAC

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/10/25 Deciphered Date 2018/10/25 P-0301-V1.0
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Docum ent Num ber Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Cus tom S550-ICL 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Thursday, July 30, 2020 Sheet 53 of 61
A B C D
 A B C D

PJ9803
1 2
+3VLP 1 2 +3VL
3V5V_VIN +5VLP +3VLP @ JUMP_43X39
1A

0.1U_25V_K_X5R_0402
PJ9816 PJ2005
1 2

4.7U_0603_6.3V6K
2 1
1 +5VLP 1 2 +5VL

PC2003

4.7U_0603_6.3V6K
2 1
3V5V_VIN @

1/16W_16K_1%_0402
JUMP_43X39

1
PC2004

PC2005
JUMP_43X118

20K_0402_1%
V9B+ 2 3V5V_VIN

PR2001

PR2002
@
PJ2002

2
1
2 1 +5VALW 1

+3V5V_CS22

+3V5V_CS12
2 1

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
+3VALW

EMC_NS@
JUMP_43X118

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
+3VALW

EMC_NS@
@ 1 1 1 1 1 1

PC2006

PC2007

PC2008

PC2009

PC2010

PC2011
2
PR2003 PU2001
2 2 2 2 2 2

5
100K_0402_1%

12

13
5

3
RT6585CGQW_WQFN20_3X3

1
5
PQ2000

CS2

CS1

LDO5

LDO3
VIN
21 AON7506_DFN8-5 PJ9802

1
D

1
1

GND
PQ2004 7
[45,55] ALW_PWRGD PGOOD JUMP_43X118
PJ9801 AONR32340C_DFN8-5
1

16 +5V_UG 4

2
JUMP_43X118 +3V_UG UGATE1 @
4 10 PR2004 PC2013

2
G UGATE2
2

@ PC2012 PR2005 2.2_0603_5% 0.1U_0603_25V7K

0.1U_0603_25V7K 2.2_0603_5% 17 +5V_BST1 2 1 2

S1
S2
S3
PL2002
2

1.5UH_PCMB063T-1R5MS_10A_20% 1 2 1 2 +3V_BST 9 BOOT1

P_+5V_BST_R_30
12A

3
2
1
BOOT2
1 2

P_+3V_BST_R_30
+5VALWP

1
2
3
PL2001 +5V_LX
18
8A +3VALWP 1 2 +3V_LX 8 PHASE1
1.5UH_CMME063T-1R5MS_12A_20%

5
PHASE2

1000P_0402_50V9-J 1/8W_4.7_5%_0805
5
PQ2001 15 +5V_LG PQ2002

1/8W_4.7_5%_0805
LGATE1

EMC_NS@
+3V_LG 11

330P_0402_50V7K
AON6380_DFN8-5

PR2006
EMC_NS@
LGATE2
14

680K_0402_1%
AON7380_DFN8-5

SKIPSEL
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

2
BYP1

1
4

EN2

EN1
PC2014

PR2007

PR2008

FB2

FB1

220U_B2_6.3VM_R25M

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1 1 1 1 1 1 1 1 4 1

1
PC2015

PC2016

PC2017

PC2018

PC2019

PC2020

PC2021

PC2022

1 1

20

19

2
P_+5V_SN_30 +

PC2002

PC2023

PC2024
2

EMC_NS@
3
2
1
2 2 2 2 2 2 2 2 P_+3V_SN_30

PC2028
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
1
2
3
1000P_0402_50V9-J

1
P_+3V_COMP +3V_FB +5V_FB 2 2 2

@
@ @
13K_0402_1%
2

2
EMC_NS@

30K_0402_1%
1 1

1
@ PC2025

PR2009

PR2010

PC2029
PC2027
0.01U_0402_25V7K

2
1
PC2026

+3VLP

2
2
2 2 2
1

1
2

+3VLP @ @
2

1
PR2012
Vout=3.3V+-5% PR2011 @ 100K_0402_5%
3VALW_ON
Vset=3.3V+-1.5% 20K_0402_1%
[45] EC_ON_3V
PR2013 2 1 0_0402_5%

FSW=475KHz Vout=5V+-5%
1

2
1
P_+3V/5V_USM

1M_0402_5%
1

1
0.1U_0402_10V7K
Vset=5.06V+-1.5%

PR2014
@ PC2030
TDC=8A OCP=14A 3

@
OVP=Vout*113% FSW=400KHz PR2015 Vout=2V*(1+PR2009/PR2016)

2
Vout=2V*(1+PR2008/PR2011) 19.6K_0402_1%
UVP=Vout*52% TDC=10A OCP=20A

2
1

2
EC_3/5V_USM [45]
Q1
USM@ OVP=Vout*113%
@
5VALW_ON
L2SK3541M3T5G_SOT723-3 UVP=Vout*52%
PR2016 2 1 0_0402_5%
[45] EC_ON_5V 2

1
P_+3V/5V_USM_R

1M_0402_5%
1

1
PR2017
0.1U_0402_10V7K
PR2018

@ PC2031
1K_0402_5%

2
USM@

2
@

2
3 RT6585B&TPS51285B RT6575D&TPS51275B 3

Mode DEM/CCM USM/CCM

3V FSW 475K 355K
5V FSW 400K 300K
CSx Rlimit=(Ilimit*Rdson)*8/50uA Rlimit=(Ilimit*Rdson)*8/10uA

RT6585B&TPS51285B BOM to BOM

RT6575D&TPS51275B BOM to BOM
RT6585B&RT6575D PIN to PIN, with different work mode, FSW, and CS setting

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/11/06 Deciphered Date 2019/11/05 Yoga C750-TGL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. PWR_3VALW/5VALW
Date: Saturday, August 01, 2020 Sheet 54 of 61
A B C D
 5 4 3 2 1

@
P_LV5116A_EN
PR9800 1 2 0_0402_5%
[45,54] ALW_PWRGD
@
VTT_EN
PR9801 1 2 0_0402_5%
[5] CPU_DRAMPG_CNTL
@
+1.8VALW_EN
PR9802 1 2 0_0402_5%
[45] PCH_PWR_EN V9B+

2
@
VDDQ_VPP_EN
PR9803 1 2 0_0402_5% +5VL
D [45] EC_VPP_PWREN PR9804 D
2.2_0603_5%

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K

0.1u_0201_10V6K
1 P_LV5116A_VCC_30 P_LV5116A_VSY S_10

1
2

2
PC9800

PC9801

PC9802

PC9803
2
PR9806 1
+5VALW 2.2_0603_5% PC9805

1
1U_0402_10V6K PC9804
@ @ @ @ 1 0.1U_25V_K_X7R_0402 +5VALW
2 PJ9813
2 1 1 2
2
1 2 1A

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
PR9808 @ JUMP_43X39
2.2_0603_5% PC9806
1U_0402_10V6K
1 PU9800
1 1
6

PC9807

PC9808
VSYS
36 @
VCC +1.8VALW
P_LV5116A_PVCC_30 4 27 P_+1.8VALW_VIN_S 2 2
PVCC V1P8A_IN
P_VDDQ_UG_30 1 PJ9806
PR9810
VDDQ_HG 25 P_+1.8VALW_LX_S 1 2 +1.8VALW_P 1 2 4A
1 2P_VDDQ_BST_R_30 1 2 P_VDDQ_BST_30 40 V1P8A_PH1 1 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1
VDDQ_BOOT 26
1/10W_0_5%_0603 PL9800 JUMP_43X79
V1P8A_PH2
PC9892 2 1 PR9812 1UH_PCMB053T-1R0MS_7A_20%
P_VDDQ_LX_30 +1.8VALW_P
0.1U_25V_K_X5R_0402 2
VDDQ_PH V1P8A_SNS
29 +3VALW 4.7_0603_5% @
PC9816 PJ9814 EMC_NS@ 1 1 1 1
P_VDDQ_LX_SENS_10 39 9 P_VDDQ_VPP_IN
10U 6.3V M X5R 0402 1 2 1A

1 2
VDDQ_SWSNS VPP_IN 1 2
P_VDDQ_LG_30 3 8 P_VDDQ_VPP +VDDQ_OUT

PC9809

PC9812

PC9810

PC9811
JUMP_43X39 @
VDDQ_LG VPP 2 2 2 2
PJ9815 PC9814
13 P_VTT_IN_30 1A 1 2 1200P_50V_K_X7R_0402

2
+VDDQ_OUT 12 VTT_IN 1 2
2 1 VDDQ_SNS 14 P_VDDQ_VTT EMC_NS@
@ JUMP_43X39
VTT
PC9893 @ 2 1 @ +0.6VS
0.1U_25V_K_X7R_0402 15
P_VCCIN_AUX_EN_10 23 VTT_SNS
PC9894 PJ9807
AUX_DRVEN
P_LV5116A_DDR_ID_10
10U 6.3V M X5R 0402
P_VDDQ_VTT 1
1 2
2 1A
28

10U 6.3V M X5R 0402

P_VCCIN_AUX_PWM_10 21 DDR_ID
1 @ JUMP_43X39
AUX_PWM 20 P_LV5116A_AUX_CS_10
PR9816 1 2

PC9817
300K_0402_1%
AUX_CS
5 P_LV5116A_VDDQ_CS_10
PR9817 1 2 1/16W_240K_1%_0402 +3VALW +3VALW
P_VCCIN_AUX_LXSENS_10 22 VDDQ_CS 2
@
P_VCCIN_AUX_VCCSENSE_10 AUX_SWSNS
PR9818 2 1 0_0402_5% +VCCIN_AUX OCP=41A +2.5V_DDR
[13] VCCIN_AUX_VCCSENSE P_VCCIN_AUX_VCCSENSE_10 19 P_LV5116A_V1P8A_CTRL_10

2
24

2
AUX_SNS V1P8A_CTRL
PC9818
30 P_LV5116A_AUX_SET_10 +VDDQ OCP=13A
1000P_0402_50V7K PR9828 PR9829 PJ9808
C AUX_SET P_VDDQ_VPP 1 2 C
@ @ P_VCCIN_AUX_VSSSENSE_10 @ 100K_0402_5% 100K_0402_5%
1A
1

PR9819 2 1 0_0402_5% PR9820 2 1 0_0402_5% P_LV5116A_PROCHOT# 7 1 2

[13] VCCIN_AUX_VSSSENSE [6,13,45] H_PROCHOT# VCCIN_AUX_VID0

22UC_6.3VC_MC_X5RC_0603
PROCHOT# 16 @ JUMP_43X39
P_VCCIN_AUX_PG_1011 AUX_VID0 VCCIN_AUX_VID0 [13,47]
PR9821 1 2 100K_0402_5%
+3VALW PG_ARAIL VCCIN_AUX_VID1
17
VDDQ_PGOOD AUX_VID1 VCCIN_AUX_VID1 [13,47]
PR9823 1 2 100K_0402_5% 10 @

10U 6.3V M X5R 0402

+3VALW P_LV5116A_CLK_5

2
PG_DDR 33 PR9824 2 1 0_0402_5%

PC9813
EC_SMB_CK3 [45] 1 1
SCL

PC9815
@ @
34 P_LV5116A_DAT_5
PR9825 2 1 0_0402_5% PR9833 PR9834
P_LV5116A_EN SDA EC_SMB_DA3 [45]
38 10K_0402_5% 10K_0402_5%
PMIC_EN 2 2
@ @ @

1
0_0402_5% 1 @ 2 PR9827 P_LV5116A_DIGITAL_CTL_10 37 @
DIGITAL_CTRL P_VCCIN_AUX_VSSSENSE_10
PR9826 2 1 0_0402_5% 18
+5VL +1.8VALW_EN 35 AUX_RGND
+5VALW +5VALW +5VALW
SLP_SUS#
VDDQ_VPP_EN 32 41
DIGITAL_CTRL Control Mode

100K_0402_5%
2

2
SLP_S4# GND
AUX_VID1 AUX_VID0 Vout_AUX

0_0402_5%

10K_0402_5%
VTT_EN 31

PR9830

PR9831

PR9832
DDR_VTT_CTRL
High HW Control @
@ 0 0 0V

1
P_LV5116A_DDR_ID_10
Low SW Control LV5116AGQW_WQFN40_5X5
P_LV5116A_V1P8A_CTRL_10
@
P_LV5116A_AUX_SET_10 0 1 1.1V

2
P_VCCIN_AUX_VIN_S PL9803 V9B+ 1 0 1.65V

0_0402_5%

10K_0402_5%

10K_0402_5%
1 2

PR9835

PR9836

PR9837
AUX_SET VCCIN_AUX Internal RAMP @
HCB2012KF-121T50_0805
3A 1 1 1.8V
PL9804 High RAMP1

1
1 2 @ @
10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
HCB2012KF-121T50_0805
0.1U_0201_25V6-K

P_VCCIN_AUX_BST_R_30
Low RAMP2 DDR_ID Type VPP VDDQ VTT/VDDQTX
EMC@
P_VCCIN_AUX_BST_30

PC9820

PC9821

PC9822

+5VALW 1 1
1

PR9839
5

1 2 1 2
1/10W_0_5%_0603 PQ9800
Floating RAMP3 Low DDR4 2.5V 1.2V VDDQ/2(VTT)
2

PC9819 AON6380_DFN8-5 2 2
--
2

0.22U_25V_K_X5R_0402 Floating LPDDR4 1.8V 1.1V

PR9840
P_VCCIN_AUX_UG_30
4
2.2_0603_5% DIGITAL_CTRL V1P8A_CTRL V1P8A Sequence V9B+
PU9801
4
1 High LPDDR4X 1.8V 1.1V 0.6V(VDDQTX)
P_VCCIN_AUX_VCC_30 +VCCIN_AUX
1

BOOT
8
VCC 3 P_VCCIN_AUX_UG_30
PC9824 High Low V1P8A follow PMIC_EN
1.5A
3
2
1

P_VCCIN_AUX_PWM_10 5 UGATE 2
2200P_0402_50V_X7R_0402 PJ9817
1U_0402_10V6K

PWM 2 P_VCCIN_AUX_LX_S 1 2 P_VDDQ_VIN_S 1 2

High High V1P8A follow SLP_SUS#

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
P_VCCIN_AUX_EN_10
1

1 PHASE 1 2
PC9823

PL9801

330U_B2_2.5VM_R9M
EN
7 P_VCCIN_AUX_LG_30
0.22UH_CMMS063T-R22MS2R107_26A_20% 1 @

5
LGATE JUMP_43X39
6
Low Low V1P8A follow PMIC_EN

PC9828

PC9827
1 1 1

D
2

B GND1 9 + B

EMC_NS@
PC9825

PC9826
PQ9801
2

GND2
PR9842 PJ9800 AONR32340C_DFN8-5
5

RT9610CGQW_WDFN8_2X2
PQ9802
2.2_0805_5% JUMPER
2 Low High V1P8A follow I2C P_VDDQ_UG_30 4 2 2 2
EMC_NS@ @
1

G
AON6324_DFN8-5
2

+1.2V

S3
S2
S1
place close to VCCIN_ALX LMOS drain +VDDQ_OUT
1

4
8A

3
2
1
PC9829
1000P_0201_50V7-K
PL9802 PJ9809
2

P_VCCIN_AUX_LXSENS_10 P_VDDQ_LX_30 1 2 1 2
Rdson=2.8mohm@Vth=4.5V EMC_NS@ 1 2
PQ9803
3
2
1

0.47UH_PCMB053T-R47MS_13A_20%

5
AON7380_DFN8-5 JUMP_43X118

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
@

2
1 1 1 1 1 1

PC9830

PC9831

PC9935

PC9833

PC9834

PC9835
+VCCIN_AUX VCCIN_AUX Vout CAP Config Vboot=1.8V Loadline=6m¦¸ 4.7_0603_5%
PR9844
P_VDDQ_LG_30 4
AC+DC Ripple=(-10%~+5%)*VOUT @ @
EMC_NS@ 2 2 2 2 2 2
#1:Pure MLCC 22U/0603*20pcs

1
TDC=14A Iccmax=32A place close to VDDQ LMOS drain
Rdson=10.5mohm@Vth=4.5V

1
#2:POSCAP+MLCC 330U/9mohm*1pcs+22U/0603*7pcs CURRENT LIMIT=45A

3
2
1
PC9851
1200P_50V_K_X7R_0402
Max Overshoot:2.13v/500us

2
EMC_NS@
OVP=(1.2~1.3)*Vref P_VDDQ_LX_SENS_10 +VDDQ_OUT
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

UVP=(0.45~0.55)*Vref
1

1
PC9836

PC9837

PC9838

PC9839

PC9840

PC9841

PC9842

PC9843

PC9844

PC9845

PC9846

PC9847

PC9848

PC9849

PC9850

PC9860

Fsw=600Khz
2

@ @ @ @ @ @ @ @ @
10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
PC9862

PC9863

PC9864

PC9865

PC9870

PC9936

PC9937

PC9938

PC9947

PC9948
2

A A

@ @ @ @

1 1 1 1 1 1 1 1 1
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
PC9875

PC9877

PC9878

PC9883

PC9886

PC9887

PC9888

PC9889

PC9891

2 2 2 2 2 2 2 2 2 Title
Security Classification LC Future Center Secret Data
Issued Date 2015/08/20 Deciphered Date 2016/08/20 PWR PMIC-LV5116
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
@ @ @ @ @ @ @ @ @ DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. S550 ICL
Date: Saturday, August 01, 2020 Sheet 55 of 61
5 4 3 2 1
 5 4 3 2 1

V9B+
Vboot=1.8V Loadline= 2mohm
PJ3501
Ripple=30mV(0A~1A) +5VALW 0.22U_0603_16V7K
P_VCCIN_VIN_S
1 2
1 2

10U_25V_M_X5R_0603
PC3519

22U_B2_25VM_R100M
Ripple=30mV(1A~5A) 1 2 1 2

10U_25V_M_X5R_0603
JUMP_43X118

0.1U_0201_25V6-K
PU3501 1 1 1

1
PR3556

PC3515

PC3516

PC3517
Ripple=15mV(5A~TDC) 2.2_0603_5% PQ3501 + @

PC3514
+5VALW P_VCCIN_VIN_S

2
AON6380_DFN8-5
TDC=40A Iccmax=65A

2
PR3553 2 2
PR3528 PR3502 2
2.2_0603_5%
1/10W 6.2 1% 0603
P_RT 3613EE_VCC_20 P_RT 3613EE_VIN_10
2.2_0402_1% OCP=85A PU3502
P_VCCIN_BST 1_30
4 +VCCIN
1 2 24 8 1 2 4

4.7U_0603_6.3V6K
Max Overshoot:200mv/500us P_VCCIN_VCC1_30

1
VCC VIN 8 BOOT
VCC P_VCCIN_UG1_30
PR3554 3
OVP=VID+400mV P_VCCIN_PWM1 P_VCCIN_PWM1_10 PL3501

1
@ 20_0402_5%1 5 UGATE

1U_0402_10V6K
P_VCCIN_PH1_S

3
2
1
PWM 2 1 2
PC3510 @

PC3504
UVP=VID-150mV P_VCCIN_Driver_EN_10 P_VCCIN_EN1_10

1
2 1 1 PHASE 0.22UH_CMMS063T -R22MS2R107_26A_20%

PC3513
0.1U_0402_25V7-K P_VCCIN_LG1_30

1
EN 7
0_0402_5%
Fsw=1000 Khz PR3555 6 LGATE
PQ3502 PR3557 @ @

2
GND1 9 2.2_0805_5%
GND2
AON6324_DFN8-5
EMC_NS@ PJ3503 PJ3504
P_VCCIN_PWM1 RT 9610CGQW_WDFN8_2X2 P_VCCIN_PH1_SN_S JUMPER JUMPER

1
D 16 12 4 D
[45,53] VR_HOT #

P_VCCIN_ISEN1P_10

P_VCCIN_ISEN1N_10
VR_HOT# PWM1

1
RT3613EE_VREF PC3518
P_VCCIN_PWM2 1000P_0201_50V7-K

3
2
1

2
26 13 EMC_NS@
VREF06 PWM2

1
PR3541
3.9_0402_1% 11

1/20W_12.1K_1%_0201
P_VCCIN_VREF06_R_10 PWM3

2 2
10K_0201_1%

2M_0402_5%

19.6K_0402_1%
P_VCCIN_Driver_EN_10
15

PR3533

PR3520

PR3536

PR3537
DRVEN
@ PC3507

1
0.47U_0402_25V6K

1
PR3552
V9B+
2

2
100K_0201_5% P_VCCIN_ISEN1P_R_10 3.9K_0402_1% P_VCCIN_ISEN1P_10
PR3517 4 1 PR3526 2
ISEN1P

1
@ 110K_0402_1% @ PJ3502
2 P_VCCIN_VIN_S

2
1 2 PR3530 1 2
1 2

10U_25V_M_X5R_0603
@ 1.4K_0402_1% PC3503

22U_B2_25VM_R100M
10U_25V_M_X5R_0603
P_VCCIN_ISEN1N_R_10 PR3531 0.1U_0402_10V7K P_VCCIN_ISEN1N_10 U42@ JUMP_43X118

0.1U_0201_25V6-K
P_VCCIN_T SEN_R_10 P_VCCIN_T SEN_10 1 1 1
+5VALW

1
1 2 7 3 1 2 1 0.22U_0603_16V7K

PC3523

PC3524
2 2
TSEN ISEN1N PC3521 + @

U42@
PC3522
PH3501 1/16W_680_1%_0402 U42@ 1 2 1 2

PC3525
5

2
100K_0402_1%_T SM0B104F4251RZ PC3502 PR3542 PR3561 2 2
P_VCCIN_SET 1_10 2
22 0.1u_0201_10V6K 3.65K_0402_1%P_VCCIN_ISEN2P_10 2.2_0603_5% PQ3503
P_VCCIN_SET 2_10 P_VCCIN_ISEN2P_R_10

2 1

2
21 SET1 1 1 2
P_VCCIN_SET 3_10 SET2 ISEN2P U42@ AON6380_DFN8-5

2
20 PR3564 PR3558 U42@

1/20W_15.4K_1%_0201
SET3 2
U22@ 0_0201_5% PR3504 U42@ 2.2_0603_5% U42@ +VCCIN
10K_0402_1%

PR3503 1.33K_0402_1% PC3505 U42@ PU3503 4 U42@

P_VCCIN_BST 2_30
1

1
4 U42@
8.25K_0402_1%

@ P_VCCIN_EN_10 P_VCCIN_ISEN2N_R_10 PR3543 U42@ 0.1U_0402_10V7K P_VCCIN_ISEN2N_10 P_VCCIN_VCC2_30

1
PR3539 2 1 9 2 1 U42@ 2 1 8 BOOT
PR3507

PR3523

PR3510

[45] EC_VR_ON