ISSCC 2019 / SESSION 4 / POWER AMPLIFIERS / 4.

4.9 A 60GHz CMOS Power Amplifier with Cascaded the resulting loads for all DAT sections (N=3) exhibit close symmetry and balanced
Asymmetric Distributed-Active-Transformer Achieving differential impedance. Therefore, the design theory of the proposed cascaded
asymmetric DAT PA predicts the PA behavior well in practice and enables its
Watt-Level Peak Output Power with 20.8% PAE and “equation-driven” design at high mm-wave frequency.
Supporting 2Gsym/s 64-QAM Modulation
Different from the conventional DAT with a folded-transformer layout, the
Huy Thong Nguyen, Doohwan Jung, Hua Wang proposed structure embraces a straight-line configuration, which, for N=3,
combines the power from 6 differential output ports of 3 DAT sections to a single-
Georgia Institute of Technology, Atlanta, GA ended port (Fig. 4.9.3). This convenient physical layout allows us to additionally
Since its invention in early 2000s, Distributed Active Transformer (DAT) has been incorporate the cascaded DAT with parallel combiners for further output-power
a popular power-combiner technique for high-power high-efficiency Power boosting. For example, we employ an 8-to-1 zero-degree combiner to combine 8
Amplifiers (PAs) in voltage-limited Silicon processes at GHz frequencies [1,2]. cascaded asymmetric DAT outputs. The simulated insertion loss of the 3-section
However, successful DAT implementations at high mm-wave frequencies still DAT output combiner is 0.9dB, while the zero-degree combiner adds an additional
remain elusive. Substantial inter-winding capacitance causes asymmetry in 0.75dB (Fig. 4.9.3). Overall, the proposed asymmetric DAT PA combines the
impedance transformation among the DAT sections, resulting in mismatched and power from 48 differential ports (24 unit PAs) to a single-ended 50Ω load to
non-optimum loads for high-frequency mm-wave DAT PAs, including those using achieve Watt-level output power.
transformer-based DAT combiners [3]. Moreover, the DAT physical size at mm- Figure 4.9.3 depicts the top-level schematic of the proposed DAT PA. The unit PA
wave frequencies is comparable to a mm-wave signal wavelength, which leads to consists of a common-source driver stage and a cascode PA stage. Transformers
significant physical phase delays between DAT sections. As a result, the combined are used for input and inter-stage matching. Extra T-lines improve the current
vectoral signal at the DAT output is substantially mismatched, causing appreciable gain of the cascode PA, and neutralization capacitors enhance reverse isolation.
degradation in the DAT output power and efficiency [4]. The asymmetric DAT PA sections demand similar input power with desirable
In this work, we present a cascaded asymmetric DAT PA that allows all DAT PA phase shifts. Various techniques can achieve this input power-splitting and phase-
sections to achieve symmetric and optimum load impedance as well as in-phase shifting. In this work, we employ coupler-based equivalent T-junctions for power
high-efficiency power combining even with large inter-winding capacitance and a splitting and delay T-lines for phase shifting to achieve the 1-to-6 input feedline
wavelength-comparable DAT combiner. A proof-of-concept design is implemented for the DAT PA.
in a CMOS 45nm CMOS SOI process together with an 8:1 zero-degree combiner, As a proof-of-concept, the proposed cascaded asymmetric DAT PA is
which efficiently combines 48 differential output ports of 24 unit-PAs into one implemented in a 45nm CMOS SOI process and occupies a 3×2.2mm2 active area.
single-ended 50Ω port and delivers 29.1-to-30.1dBm peak output power with The nominal supply/bias voltage is 2V for the PA stage, 1V for the driver, and
18.5-to-20.8% peak PAE at 60GHz. This watt-level 60GHz CMOS PA also supports 1.3V for the PA cascode gate bias. As shown in Fig. 4.9.4, for the high-gain mode
linear amplification of wideband modulations, and 2Gsym/s 16-QAM and 64-QAM (driver and PA gate bias =0.42V), the PA demonstrates a small-signal gain of
signals are demonstrated at an average Pout of 22.3dBm and 20.9dBm, 25dB, a 3dB S21 bandwidth from 53 to 65GHz, and a broadband -10dB input
respectively. matching from 49 to 63GHz. The large-signal continuous-wave (CW) test shows
Figure 4.9.1 depicts the general topology of the proposed cascaded asymmetric 29.1dBm Psat with 18.5% peak PAE. The -1dB Psat bandwidth is 55 to 64GHz. With
DAT combiner. It consists of N-unit DAT sections, each of which is loaded by an a slightly elevated PA/driver supply to 2.2V/1.1V, the PA achieves 30.1dBm Psat
output dual coupled-line combiner and is fed by a phase-shifted input signal. In with 20.8% peak PAE. For the high-linearity mode (driver and PA gate bias
contrast to conventional symmetric DAT, each DAT section has a different coupler =0.27V), the CW test demonstrates 28.5dBm Psat with 18.9% peak PAE and
even-/odd-mode impedance and input phase shift, both of which are determined 26.5dBm P1dB with 15.5% PAE at P1dB.
by the DAT section location. The cascaded asymmetric DAT resolves the issues The PA is tested with 16-QAM and 64-QAM modulated signals at a high-gain
of the conventional DAT as follows. First, as the DAT size is comparable to the mode. Without any digital pre-distortion, the PA achieves -23.6dB EVM with
wavelength, signals from different DAT PA sections experience various phase 22.5dBm average Pout for an 8Gb/s (2Gym/s) 16-QAM signal, and -27.1dB EVM
delays to travel to output. Proper input phase shifting is needed to align the signals with 20.9dBm average Pout for a 12Gb/s (2Gsym/s) 64-QAM signal.
from multiple DAT sections at the total DAT PA output, which results in maximum
vectoral addition and high overall DAT combing efficiency. Second, the coupled- The series connection of the proposed cascaded asymmetric DAT allows the PA
line combiner naturally absorbs the inevitable inter-winding capacitance at to access a broad physical area to collect power. As a result, the PA demonstrates
mm-wave. It also provides inherent differential-to-single-ended combining, the highest output power and highest average modulation power compared to all
obviating the need for additional baluns and ensuring balanced differential load reported silicon PAs at high mm-wave in [3-9] (Fig. 4.9.6).
impedance and low loss. Third, due to output combining and inter-winding
Acknowledgements:
capacitance, a conventional practical DAT combiner experiences significant active
We would like to thank GlobalFoundries for chip fabrication and members of
load modulation on each section, resulting in their further load mismatches. To
Georgia Tech GEMS group for their technical supports.
ensure a symmetric and optimum load, each section in our proposed asymmetric
DAT employs its output dual coupled-line combiner with a judiciously designed References:
coupling factor and even/odd impedances. In this paper, the theoretical analysis [1] I. Aoki et al., "Fully Integrated CMOS Power Amplifier Design Using the
of the proposed asymmetric DAT PA is presented and further verified by Distributed Active-Transformer Architecture" IEEE JSSC, vol. 37, no. 3, pp. 371-
EM/device simulations, enabling equation-driven design and demonstration of the 383, Mar. 2002.
1W 60GHz DAT PA in a 45nm CMOS SOI process. [2] I. Aoki et al., "Distributed Active Transformer-A New Power-Combining and
Impedance-Transformation Technique", IEEE TMTT, vol. 50, no. 1, pp. 316-331,
The design theory of the asymmetric DAT PA is analyzed next (Fig. 4.9.2). First,
Jan. 2002.
based on the [Y] matrix of an ideal coupled-line, the [Y] matrix of a unit DAT PA
[3] U. R. Pfeiffer and D. Goren, "A 23-dBm 60-GHz Distributed Active Transformer
section with its dual coupled-line combiner is derived, considering its differential
in a Silicon Process Technology," IEEE TMTT, vol. 55, no. 5, pp. 857-865, May
PA driving and single-ended interaction with adjacent DAT sections. Next, to
2007.
obtain the load impedance of each DAT PA section, we connect N DAT PA sections
[4] K. Wang et al., "A 1V 19.3dBm 79GHz Power Amplifier in 65nm CMOS," ISSCC,
in cascade and apply the termination conditions, i.e. AC ground on the left-most
pp. 260-261, Feb. 2012.
port, inter-section interaction, and antenna load on the right-most port. To ease
[5] R. Bhat et al., “Large-Scale Power Combining and Mixed-Signal Linearizing
practical implementations, we assume all unit PAs are identical and see the same
Architectures for Watt-Class mmWave CMOS Power Amplifiers,” IEEE TMTT, vol.
optimum load-line impedance, so that the coupled-line parameters and input
63, no. 2, pp. 703–718, Feb. 2015.
phase shifts are solved.
[6] K. Datta and H. Hashemi, “Watt-level mm-Wave Power Amplification with
For further comparison, a conventional symmetric DAT at 60GHz with in-phase Dynamic Load Modulation in a SiGe HBT Digital Power Amplifier,” IEEE JSSC,
driving leads to asymmetric and non-optimum PA loads (Fig. 4.9.2). This vol. 52, no. 2, pp. 371–388, Feb. 2017.
impedance mismatch further deteriorates when the number of DAT sections (N) [7] T. Chi et al., "A 60GHz On-Chip Linear Radiator with Single-Element 27.9dBm
increases. For N=3, the load seen by PA 1 is substantially far away from the load Psat and 33.1dBm Peak EIRP Using Multifeed Antenna for Direct On-Antenna
seen by PA 3. Power Combining", ISSCC, pp. 296-297, Feb. 2017.
[8] H. Park et al., "Millimeter-Wave Series Power Combining Using Sub-Quarter-
In contrast, with the cascaded asymmetric DAT architecture, the loads of all DAT Wavelength Baluns," IEEE JSSC, vol. 49, no. 10, pp. 2089-2102, Oct. 2014.
sections are identical in theory and matched to the optimum load-line impedance [9] H. Wang et al., "Power Amplifiers Performance Survey 2000-present,"
at 60GHz (Fig. 4.9.2). Using 3D EM simulation to model asymmetric couplers Accessed on Sept. 10, 2018, [Online].
predicted by the design equations, even including the loss and other non-idealities, Available: https://gems.ece.gatech.edu/PA_survey.html

90 • 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE

 ISSCC 2019 / February 18, 2019 / 4:45 PM

Figure 4.9.2: Equation-driven design of the proposed cascaded asymmetric DAT

Figure 4.9.1: Conventional symmetric distributed active transformer at high PA using the coupled-line model, calculated and 3D EM simulated load
mm-wave frequencies, proposed cascaded asymmetric DAT, and the impedance for a conventional symmetric DAT PA and the proposed asymmetric
comparison of design concepts. DAT PA with 3 DAT sections in 45nm CMOS SOI at 60GHz.

Figure 4.9.3: Top-level schematic of the proposed 60GHz cascaded asymmetric

DAT PA with 24 unit DAT PAs, a unit DAT PA schematic, and an 8-to-1 zero-
degree PA output combiner. Figure 4.9.4: PA small-signal and large-signal CW performances at 60GHz.

Figure 4.9.5: Dynamic performances of the proposed cascaded asymmetric DAT Figure 4.9.6: Comparison to the prior-art mm-wave high-power PA designs and
PA at high-gain mode with 16-QAM and 64-QAM modulated signals. 60-to-80GHz PA designs.

DIGEST OF TECHNICAL PAPERS • 91

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Figure 4.9.7: Die micrograph.

• 2019 IEEE International Solid-State Circuits Conference 978-1-5386-8531-0/19/$31.00 ©2019 IEEE