FUNCTIONAL COVERAGE

FOLLOW THE BUGS !!

 When do you start coverage?
 During initial stges of verification both code and functional coverage will be low.
 Code and functional coverage add to simulation overhead.
 So don’t turn on code /functional coverage at the beginning of the project.
 But what does ‘beginning’ of the project mean?When does beginning end.

That’s where the bugs come into picture!

1) Create Bug rate charts

2) During the beginning time,bug rate will be high.

3) When the bug rate starts dropping,the beginning has come to an end.

4) That’s when your existing test strategy is running out of steam.

5) That’s when you start code and functional coverage to determine

6) If new tests are simply banging on the same logic repeatedly.

Which part of logic is not yet covered.
Develop tests for the uncovered functionality.

7) Your bug rate will indeed go up(guaranteed)

Functional Coverage:
1) Used to measure the quality of design and Verification.
2) Functional coverage deals with covering design functionality.

System Verilog Covergroup

1) Define covergroup
2) Coverage points
3) Bins
4) Cross coverage

COVERGROUP:
Covergroup is a user defined construct. That encapsulates coverage model specification.
A covergroup can be defined in a program,class,module,interface.
Covergroup encapsulates the specification of

1) Set of coverage point.

2) Cross coverage between coverage points.
3) A clocking event that synchronizes coverage points.
4) Coverage options
5) Optional formal argument.

Syntax :
1) Basic covergroup syntax:

covergroup <coverage model name>

endgroup
…………………
2) Covergroup syntax with clocking event:

covergroup <coverage model name> @(<clocking event>);

…………
……………
endgroup
………………..
3) Covergroup with list of arguments

covergroup < coverage model name> (<list of arguments>);

…………
…………
endgroup
 // system verilog covergroup basics //

bit [1:0] addr;

logic [7:0] data;

covergroup cg @(posedge clk); // 1. Declare a covergroup

2.cg is the name of the covergroup required.
3.@(posedge clk): it defines the event at which the
coverage points are sampled.

If the clocking event is omitted, you must procedurally

trigger the coverage sampling using the built in sample
method

a : coverpoint addr;

b : coverpoint data; //1. Declare coverpoints

2. a and b are the coverpoint labels(which is optional)
3.addr and data are the coverpoint variable
4.Covergroup can contain one or more coverpoint.

endgroup // End a covergroup

cg cov=new(); //instantiate covergroup using new operator.

Note : Covergroup without a coverpoint is useless.you wont

get compile error, but there is nothing to cover without a
coverpoint.
COVERPOINT
A coverpoint is an integral expression or variable that has to be covered on sampling the
covergroup.

A covergroup can have one or more coverage points that can be labled.

Each coverpoint associated with single or multiple bins that can be explicitly defined.

Syntax:

covergroup < covergroup name>

<coverpoint_label> : coverpoint < coverpoint name>;

<coverpoint_label> : coverpoint < coverpoint name>;

endgroup

Coverpoint label is optional.if we are not specified any label.simulator provides its own
label.(Which make no sense).

BINS
Bins is something to collect coverage information.

To provide facility to create a set of bins for a particular range.

The bins can be automatically or explicitly written by an engineer.
Types of bins:
1) Implicit bins
2) Explicit bins
3) Auto_bin_max
4) Array of bins
 5) Bins with enum type.
6) Usedcases.

The goal of functional coverage analysis is to achieve sufficient coverage on all the defined
bins to ensure thorough verification of the design.

If a certain bin is never hit, it indicates that the corresponding condition or value has not
been exercised in the testbench, and more test cases might be needed to cover that
particular scenario.

Implicit bins:

While defining coverpoint,if you do not specify any bins system verilog will automatically
create bins.

For any coverage pont, N is 2^M where M is the number of bits required to represent the
variable.

Ex:

class coverage;

bit[2:0] addr;

covergroup cg;

c1 : coverpoint addr; // No bins are specified : implicit bins

will create 2^M=2^3=8 bins

endgroup

function new();

cg=new();

endfunction

endclass

…………………………………..

Explicit bins:

We can explicitly create bins

A separate bins for each value in a given range.

A single bin for all the values in a range list.

Example:

bit [7:0] addr;

covergroup cg;

coverpoint addr{

bins a = {[0:3]}; // single bin to cover all addr values 0,1,2,3

bins b[]={[4:5]}; //individual bins

b[1]=4

b[2]=5

bins c[2]={[6:8]};//fixed array of bins

c[1]=6

c[2]=7,8

bins d[3]={[9:10]}; // fixed array of bins

d[1] = 9

d[2]=10;

d[3]=empty

bins e[]={[9:12],[11:16]}; // Overlapping values

will create an array of 8 bins

for addr from 9 to 16

bins f = {[31:$]}; // from 31 to 256

bins other = default; // add everything else that’s not covered by bins above

//Default Bins: A coverpoint can also have a default bin that captures
all values not covered by other explicit bins.

Endgroup
CROSS COVERAGE
1) Cross coverage is specified between two or more coverpoints variable.
2) Cross coverage is allowed only between coverpoints defined within the same
covergroup.
3) Expression cannot be used directly in a cross
4) Cross coverage is a combination of coverpoints and variables also.
5) When variable is used without a defined coverpoint for the variable,a
coverpoint is explicitly covered.

Example 1:

bit [1:0] offset;

bit [3:0] addr;

covergroup cg;

c1 : coverpont offset {bins a[]={[0:3]};} //4 bins for 4 values (0,1,2,3) of offset

c2 : coverpoint addr { bins b[]= {[0:3]};} //4 bins of 4 values (0,1,2,3) of addr

c1xc2 : cross c1,c2; // cross of offset and addr gives 16 coverpoints

(4 coverpoints for offset,4 coverpoints for addr)

endgroup

What cross really means

Assume that addr==0 has been covered and offset==0 also has been
covered but if addr==0 && offset==0 never happened together

(not necessarily at the same clock) then the cross of addr[0] and offset[0]
will be empty.
Example 2)

enum {r,g,b} color;

bit [3:0] addr;

bit [1:0] offset;

covergroup cg1 @(posedge clk);

C1 : coverpoint offset; // autogenerated bins (4 bins because offset is 2 bit)

C2 : coverpoint addr
{
bins a= {[0:7]}; //Explicit bins : a covers addr values 0 to 7

bins b ={[8:15]}; // Explicit bins: b covers addr values 8 to 15

C3 : cross color,C2; // cross between coverpoints enum and coverpoint C2

Total cross coverpoints =6 ( 3 of color crossed with 2 of addr

SV implicitly creates coverpoint for the variable color in order to track
its cross coverage.
C4 : cross C2,C1; // cross between coverpoint C2 and C1.
Total cross coverpoints = 8 ( 4 of offset crossed with 2 of aadr)

endgroup

Note: the default auto_bin_max of 64 does not apply to cross. So cross will create as many
bins as required. So we need to filter those bins.
1) Cross using ignore_bins
2) Cross using with clause
3) Cross of transition
TRANSITION COVERAGE
Transition coverage is a powerful tool for capturing and analyzing state changes in
sequential circuits, and it helps ensure that the design is thoroughly tested for all
possible transitions.

Example:

bit [7:0] addr;

bit data;

covergroup cg@(posedge clk);

C1 : coverpoint addr
{
bins a = (8'h00 => 8'hff); // addr is 00 at this posedge clk and it should be ff at the
next posedge clk

C2 : coverpoint data;
{
bins b =(1'b1 => 1'b0); // data is 1 followed by 0 at successive sample points
}

C1C2 : cross C1,C2; // This means that the following condition is met that the cross
will be covered
addr=00 && data=1 at this posedge clk
and at the next posedge clk
addr=ff && data=0

endgroup

……………………………………………….
Example 2

bit [7:0] addr;

covergroup cg @(posedge clk);

C1: coverpoint addr

 {
bins a= (1=>2=>3); // addr covers 1 followed by 2 followed by 3

bins b[]=(1,2 => 3,4); //This is equal to 4 transition

1=>3,1=>4,2=>3,2=>4
Four bins are created ,one for each transition

bins c =('hf[*3]); // Consecutive transition

‘hf => ‘hf => ‘hf

bins d =('ha[-> 3]); // Non consecutive transition

(…’ha => …’ha=> …’ha);
where … means any transition that does not contain the value
‘ha

}
--------------------------
Example 3

bit [7:0] addr;

covergroup cg @(posedge clk);

C1 : coverpoint addr
{
bins a[] = (1,2 => 3,4); // This is equal to 4 transitions(1=>3,1=>4,2=>3,2=>4)

bins b[] = (1=>3,1=>4,2=>3,2=>4);// this is not same as (1,2 => 3,4)

bins b[]=(1 =>(3,1) =>(4,2) => (3,2)=>4);

WILDCARD BINS
Wildcard is a keyword associated with bins.
Wildcard characters are x and z or ? each of which evaluate to 0 and 1.
Value of few bits from vector do not effect functionaity.
Ex: We can use this types of bins for priority encoder.

Example:

covergroup cg @(posedge clk);

 c1: coverpoint addr;
{
wildcart bins a = {4'b 11??}; //bins a = 1100,1101,1110,1111
wildcart bins b[]=(2'b0x => 2'b1x); //bins b 00=>10, 00=>11,01=>10,01=>11
bins b[] is used for bins,the simulator will
create 1 bin for each of the 4 transition

wildcart bins c=(2'b0x => 2'b1x); // only 1 bin c is used for the transition
}
endgroup

IGNORE BINS
All values or transitions associated with ignore_bins are excluded from coverage

Example:

bit [3:0] addr;

covergroup cg@(posedge clk);

C1:coverpoint addr //no bins is specified,SV will create 16 auto bins

{
ignore_bins a={4,5}; //ignore coverage for addr=4,5
ignore_bins b={[6:$]}; // ignore coverage for addr=6 to 15
}
Endgroup

//exclude bins from 4 to 15

ILLEGAL BINS
All values or transitions associated with illegal_bins are excluded from coverage
and will give a run time error if encountered.

Example:

bit [3:0] addr;

covergroup cg@(posedge clk);

 C1:coverpoint addr
{
illegal_bins a={0}; //if addr == 0 ever during simulation,this will give run time
error

}
Endgroup

WITH CLAUSE
Allows creation of bins if condition specified with clause method.

Example:

module tb;
bit [3:0]a;

covergroup cg; 2/8=25%

option.per_instance=1;
coverpoint a{
bins used_a[]=a with (item%2==0);
}
endgroup

initial begin
cg cov=new();
repeat(10) begin
a=$random;
cov.sample();
$display("a=%0d",a);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# =============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# =============================================================
# | TYPE /tb/cg | 25.000% | 100.000% | Uncovered |
# =============================================================
# | INSTANCE <UNNAMED1> | 25.000% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | COVERPOINT <UNNAMED1>::a | 25.000% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | bin used_a[0] | 0 | 1 | Zero |
# | bin used_a[2] | 1 | 1 | Covered |
# | bin used_a[4] | 1 | 1 | Covered |
# | bin used_a[6] | 0 | 1 | Zero |
# | bin used_a[8] | 0 | 1 | Zero |
# | bin used_a[10] | 0 | 1 | Zero |
# | bin used_a[12] | 0 | 1 | Zero |
# | bin used_a[14] | 0 | 1 | Zero |
# =============================================================

https://www.edaplayground.com/x/SJ_G

Example :

module tb;
bit [3:0]a;

covergroup cg;
option.per_instance=1;
coverpoint a{
bins used_a[]={[1:10]} with (item%2==0); // 2,4,6,8,10
}
endgroup

initial begin
cg cov=new();
repeat(10) begin
a=$random;
cov.sample();
$display("a=%0d",a);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# =============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# =============================================================
# | TYPE /tb/cg | 40.000% | 100.000% | Uncovered |
# =============================================================
# | INSTANCE <UNNAMED1> | 40.000% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | COVERPOINT <UNNAMED1>::a | 40.000% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | bin used_a[4] | 1 | 1 | Covered |
# | bin used_a[6] | 0 | 1 | Zero |
# | bin used_a[8] | 0 | 1 | Zero |
# | bin used_a[10] | 0 | 1 | Zero |
# =============================================================

Total 5 bins and 2 bins are hitted

%coverage =40%
 https://www.edaplayground.com/x/M_cn

DEFAULT BINS
suppose variable is 4 bits and bins b0 defined 0 to 12. So, 13
to 15 value will be cover under default bins.

Example:
module tb;
bit [3:0]a;

covergroup cg;
option.per_instance=1;
coverpoint a{
bins used_a[]={[0:3]};
bins used_a1[]={[6:12]};
bins unused_a=default;
}
endgroup

initial begin
cg cov=new();
repeat(10) begin
a=$random;
cov.sample();
$display("a=%0d",a);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# =============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# =============================================================
# | TYPE /tb/cg | 36.363% | 100.000% | Uncovered |
# =============================================================
# | INSTANCE <UNNAMED1> | 36.363% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | COVERPOINT <UNNAMED1>::a | 36.363% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | bin used_a[0] | 0 | 1 | Zero |
# | bin used_a[1] | 2 | 1 | Covered |
# | bin used_a[2] | 1 | 1 | Covered |
# | bin used_a[3] | 1 | 1 | Covered |
# | bin used_a1[6] | 0 | 1 | Zero |
# | bin used_a1[7] | 0 | 1 | Zero |
# | bin used_a1[8] | 0 | 1 | Zero |
# | bin used_a1[9] | 1 | 1 | Covered |
# | bin used_a1[10] | 0 | 1 | Zero |
# | bin used_a1[11] | 0 | 1 | Zero |
# | bin used_a1[12] | 0 | 1 | Zero |
# | default bin unused_a | 5 | - | Occurred |
# =============================================================

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COVERGROUP BUILT IN METHODS

Sample()
Get_coverage
Get_instance_coverage()
Set_instance_name(string)
Start()
Stop()

Example:
bit a,b;

covergroup cg;
C1 : coverpoint a;
C2 : coverpoint b;
endgroup

cg cov = new();

always@(posedge req) //start collecting coverage information when req is asserted

cov.start();

always@(posedge gnt) //stop collecting coverage information when gnt is asserted

cov.stop();

always@(posedge clk) // in between assertion of req and gnt collect coverage

information at every posedge clk
begin
cov.sample();
end

COVERAGE OPTION IN FUNCTIONAL COVERAGE

 The coverage option control the behaviour,coverpoint and cross
Specific instance of a covergroup

Option.<option_name> = <expression>

Option=built in member of any covergroup

 Option.per_instance=1 // track coverage information for each instance “

cov” in addition to the cumulative coverage information for covergroup

 Option.comment

 Option.weight

 Option.auto_bin_max

Example 1) coverage- overlapping of bins

module tb; 8/3 = 2

a[0]= 3,4
a[1]=5,6

a[2]= 7,3,4,5
bit [2:0] a;

covergroup cg;
option.per_instance=1;

coverpoint a{
bins a[3] = {[3:$],3,4,5};
}
endgroup

initial
 begin
cg cov=new();
repeat(10)

begin
a=$random;
cov.sample();
$display("a=%0d",a);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# ============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# ============================================================
# | TYPE /tb/cg | 100.000% | 100.000% | Covered |
# ============================================================
# | INSTANCE <UNNAMED1> | 100.000% | 100.000% | Covered |
# |--------------------------|----------|----------|---------|
# | COVERPOINT <UNNAMED1>::a | 100.000% | 100.000% | Covered |
# |--------------------------|----------|----------|---------|
# | bin a[0] | 2 | 1 | Covered |
# | bin a[1] | 4 | 1 | Covered |
# | bin a[2] | 6 | 1 | Covered |
# ============================================================

https://www.edaplayground.com/x/npaw

Example 2) coverage- array of bins for different range

module tb;
bit [2:0] a;

covergroup cg;
option.per_instance=1;
coverpoint a{
bins a={0,[3:7]};
}
endgroup

initial

begin
cg cov=new();
repeat(10)
begin
a=$random;

cov.sample();
$display("a=%0d",a);
#1;
end
end

endmodule

COVERGROUP COVERAGE
# ============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# ============================================================
# | TYPE /tb/cg | 100.000% | 100.000% | Covered |
# ============================================================
# | INSTANCE <UNNAMED1> | 100.000% | 100.000% | Covered |
# |--------------------------|----------|----------|---------|
# | COVERPOINT <UNNAMED1>::a | 100.000% | 100.000% | Covered |
# |--------------------------|----------|----------|---------|
# | bin a | 6 | 1 | Covered |
# ============================================================

https://www.edaplayground.com/x/M_cG

Example 3) coverage-multiple value in a bins

module tb;
bit a;

covergroup cg;
option.per_instance=1;
 coverpoint a{
bins b0={0,1};
}

endgroup

initial begin
cg cov=new();
repeat(1) begin

a=$random;
cov.sample();
$display("a=%0d",a);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# ============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# ============================================================
# | TYPE /tb/cg | 100.000% | 100.000% | Covered |
# ============================================================
# | INSTANCE <UNNAMED1> | 100.000% | 100.000% | Covered |
# |--------------------------|----------|----------|---------|
# | COVERPOINT <UNNAMED1>::a | 100.000% | 100.000% | Covered |
# |--------------------------|----------|----------|---------|
# | bin b0 | 1 | 1 | Covered |
# ============================================================
#

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Example 4) covarage of enum

module tb;

typedef enum bit[1:0] {S0,S1,S2,S3}fsmstate;

fsmstate var1;
int temp;
 covergroup cg;
option.per_instance=1;

coverpoint var1{bins b0={S0};

bins b1={S1};
}
endgroup

initial begin
cg cov=new();
repeat(5) begin

temp=$random();

var1=fsmstate'(temp); // static casting

cov.sample();
$display("var1=%s",var1.name);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# ===============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# ===============================================================
# | TYPE /tb/cg | 100.000% | 100.000% | Covered |
# ===============================================================
# | INSTANCE <UNNAMED1> | 100.000% | 100.000% | Covered |
# |-----------------------------|----------|----------|---------|
# | COVERPOINT <UNNAMED1>::var1 | 100.000% | 100.000% | Covered |
# |-----------------------------|----------|----------|---------|
# | bin b0 | 1 | 1 | Covered |
# | bin b1 | 3 | 1 | Covered |

https://www.edaplayground.com/x/GZzK

Example 5) coverage- bins for array

module tb;
bit [2:0]a;

covergroup cg;
option.per_instance=1;
coverpoint a{
bins a[]={[3:$],3,4,5};
}

endgroup

initial begin
cg cov=new();
repeat(10) begin

a=$random;
cov.sample();
$display("a=%0d",a);
#1;

end
end
endmodule

COVERGROUP COVERAGE
# =============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# =============================================================
# | TYPE /tb/cg | 60.000% | 100.000% | Uncovered |
# =============================================================
# | INSTANCE <UNNAMED1> | 60.000% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | COVERPOINT <UNNAMED1>::a | 60.000% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | bin a[3] | 1 | 1 | Covered |
# | bin a[4] | 1 | 1 | Covered |
# | bin a[5] | 4 | 1 | Covered |
# | bin a[6] | 0 | 1 | Zero |
# | bin a[7] | 0 | 1 | Zero |
# =============================================================
Total bins 3 to 7 is 5
Total hit =3
%coverage =60%

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Example 6)

module tb;
reg [7:0] a; /// 00 01 10 11 -> 0 1 2 3

reg clk = 0;
integer i = 0;

always #5 clk = ~clk;

initial begin
#100;
$finish();
end

covergroup c;
option.per_instance=1;
coverpoint a; // implicit bin (4 bins)
endgroup

initial begin
c ci = new();
for(i = 0; i < 10; i++) begin
@(posedge clk);
a = $urandom();
 $info("Value of a : %0d", a);
ci.sample();
end

end

endmodule

COVERGROUP COVERAGE
# =============================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# =============================================================
# | TYPE /tb/c | 12.500% | 100.000% | Uncovered |
# =============================================================
# | INSTANCE <UNNAMED1> | 12.500% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | COVERPOINT <UNNAMED1>::a | 12.500% | 100.000% | Uncovered |
# |--------------------------|---------|----------|-----------|
# | bin auto[0:3] | 1 | 1 | Covered |
# | bin auto[4:7] | 0 | 1 | Zero |
# | bin auto[8:11] | 1 | 1 | Covered |
# | bin auto[12:15] | 0 | 1 | Zero |
# | bin auto[16:19] | 0 | 1 | Zero |
# | bin auto[20:23] | 0 | 1 | Zero |
# | bin auto[24:27] | 0 | 1 | Zero |
# | bin auto[28:31] | 0 | 1 | Zero |
# | bin auto[32:35] | 0 | 1 | Zero |
# | bin auto[36:39] | 0 | 1 | Zero |
# | bin auto[40:43] | 0 | 1 | Zero |
# | bin auto[44:47] | 0 | 1 | Zero |
# | bin auto[48:51] | 0 | 1 | Zero |
# | bin auto[52:55] | 0 | 1 | Zero |
# | bin auto[56:59] | 0 | 1 | Zero |
# | bin auto[60:63] | 0 | 1 | Zero |
# | bin auto[64:67] | 1 | 1 | Covered |
# | bin auto[68:71] | 0 | 1 | Zero |
# | bin auto[72:75] | 0 | 1 | Zero |
# | bin auto[76:79] | 2 | 1 | Covered |
# | bin auto[80:83] | 0 | 1 | Zero |
# | bin auto[84:87] | 1 | 1 | Covered |
# | bin auto[88:91] | 0 | 1 | Zero |
# | bin auto[92:95] | 0 | 1 | Zero |
# | bin auto[96:99] | 0 | 1 | Zero |
# | bin auto[100:103] | 0 | 1 | Zero |
# | bin auto[104:107] | 0 | 1 | Zero |
# | bin auto[108:111] | 0 | 1 | Zero |
# | bin auto[112:115] | 1 | 1 | Covered |
# | bin auto[116:119] | 0 | 1 | Zero |
# | bin auto[120:123] | 0 | 1 | Zero |
# | bin auto[124:127] | 0 | 1 | Zero |
# | bin auto[128:131] | 0 | 1 | Zero |
# | bin auto[132:135] | 0 | 1 | Zero |
# | bin auto[136:139] | 0 | 1 | Zero |
# | bin auto[140:143] | 0 | 1 | Zero |
# | bin auto[144:147] | 0 | 1 | Zero |
# | bin auto[148:151] | 0 | 1 | Zero |
# | bin auto[152:155] | 0 | 1 | Zero |
# | bin auto[156:159] | 0 | 1 | Zero |
# | bin auto[160:163] | 0 | 1 | Zero |
# | bin auto[164:167] | 0 | 1 | Zero |
# | bin auto[168:171] | 2 | 1 | Covered |
# | bin auto[172:175] | 0 | 1 | Zero |
# | bin auto[176:179] | 0 | 1 | Zero |
# | bin auto[180:183] | 0 | 1 | Zero |
# | bin auto[184:187] | 0 | 1 | Zero |
# | bin auto[188:191] | 0 | 1 | Zero |
# | bin auto[192:195] | 0 | 1 | Zero |
# | bin auto[196:199] | 0 | 1 | Zero |
# | bin auto[200:203] | 0 | 1 | Zero |
# | bin auto[204:207] | 0 | 1 | Zero |
# | bin auto[208:211] | 0 | 1 | Zero |
# | bin auto[212:215] | 0 | 1 | Zero |
# | bin auto[216:219] | 0 | 1 | Zero |
# | bin auto[220:223] | 0 | 1 | Zero |
# | bin auto[224:227] | 0 | 1 | Zero |
# | bin auto[228:231] | 1 | 1 | Covered |
# | bin auto[232:235] | 0 | 1 | Zero |
# | bin auto[236:239] | 0 | 1 | Zero |
# | bin auto[240:243] | 0 | 1 | Zero |
# | bin auto[244:247] | 0 | 1 | Zero |
# | bin auto[248:251] | 0 | 1 | Zero |
# | bin auto[252:255] | 0 | 1 | Zero |
# =============================================================

https://www.edaplayground.com/x/hTtW

Example 5) coverage- Explicit bins

module tb;
bit [1:0]a,b;

covergroup cg;
coverpoint a{
bins b0={0};
bins b1={2};
}

coverpoint b{
bins b0={1};
}
endgroup

initial begin
cg cov=new();
 repeat(5) begin
a=$random;
b=$random;

cov.sample();
$display("a=%0d, b=%0d",a,b);
#1;

end

end
endmodule

COVERGROUP COVERAGE
# ================================================
# | Covergroup | Hits | Goal / | Status |
# | | | At Least | |
# ================================================
# | TYPE /tb/cg | 75.000% | 100.000% | Uncovered |
# ================================================

https://www.edaplayground.com/x/RpJK