Configuration des blocs de PIC10F200:
● RAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM_PIC10F200 is
Port ( Clock : in STD_LOGIC;
Reset : in STD_LOGIC;
Address : in STD_LOGIC_VECTOR(6 downto 0);
DataIn : in STD_LOGIC_VECTOR(7 downto 0);
DataOut : out STD_LOGIC_VECTOR(7 downto 0));
end RAM_PIC10F200;
architecture Behavioral of RAM_PIC10F200 is
type RAM_Type is array (0 to 127) of STD_LOGIC_VECTOR(7 downto 0);
signal Memory : RAM_Type := (others => (others => '0'));
begin
process (Clock, Reset)
begin
if Reset = '1' then
Memory <= (others => (others => '0'));
elsif rising_edge(Clock) then
if Address >= "0000000" and Address <= "1111111" then
if DataIn /= (others => 'Z') then
Memory(to_integer(unsigned(Address))) <= DataIn;
end if;
DataOut <= Memory(to_integer(unsigned(Address)));
end if;
end if;
end process;
end Behavioral;
● UAL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity UAL_PIC10F200 is
Port ( Operand1, Operand2 : in STD_LOGIC_VECTOR(7 downto 0);
Instruction : in STD_LOGIC_VECTOR(5 downto 0);
Result : out STD_LOGIC_VECTOR(7 downto 0));
end UAL_PIC10F200;
architecture Behavioral of UAL_PIC10F200 is
begin
process (Operand1, Operand2, Instruction)
begin
case Instruction is
when "000000" => -- ADDWF
Result <= Operand1 + Operand2;
when "000001" => -- ANDWF
Result <= Operand1 AND Operand2;
when "000010" => -- COMF
Result <= not Operand1;
when "000011" => -- DECF
Result <= Operand1 - 1;
when "000100" => -- DECFSZ
if Operand1 = "00000000" then
Result <= "00000000";
else
Result <= Operand1 - 1;
end if;
when "000101" => -- GOTO
Result <= (others => '0');
when "000110" => -- INCF
Result <= Operand1 + 1;
when "000111" => -- INCFSZ
if Operand1 = "11111111" then
Result <= "00000000";
else
Result <= Operand1 + 1;
end if;
when "001000" => -- MOVF
Result <= Operand1;
when "001001" => -- MOVWF
Result <= Operand2;
when "001010" => -- NOP
Result <= Operand1;
when "001011" => -- RETFIE
Result <= Operand1;
when "001100" => -- RETURN
Result <= Operand1;
when "001101" => -- RLF
Result <= '0' & Operand1(6 downto 0) & Operand1(7);
when "001110" => -- RRF
Result <= Operand1(0) & Operand1(7 downto 1);
when "001111" => -- SLEEP
Result <= Operand1;
when "010000" => -- SWAP
Result <= Operand1(3 downto 0) & Operand1(7 downto 4);
when "010001" => -- TRIS
Result <= Operand1;
when "010010" => -- XORWF
Result <= Operand1 XOR Operand2;
when "010011" => -- BCF
Result <= Operand1 AND (not Operand2);
when "010100" => -- BSF
Result <= Operand1 OR Operand2;
when "010101" => -- CALL
Result <= Operand1;
when "010110" => -- CLRW
Result <= (others => '0');
when "010111" => -- CLRZ
Result <= (others => '0');
when "011000" => -- CPFSG
Result <= (others => '0');
when "011001" => -- CPFSSZ
Result <= (others => '0');
when "011010" => -- LSF
Result <= Operand1(6 downto 0) & '0';
when "011011" => -- MOVLB
Result <= Operand1(7 downto 4) & (others => '0');
when "011100" => -- OPTION
Result <= Operand1;
when "011101" => -- RETLW
Result <= "11011011";
when "011110" => -- RRB
Result <= Operand1(7) & Operand1(0 to 6);
when "011111" => -- SETF
Result <= (others => '1');
when "100000" => -- SUBWF
Result <= Operand1 - Operand2;
when "100001" => -- TESTWF
Result <= (others => '0');
when "100010" => -- SWAPF
Result <= Operand1(3 downto 0) & Operand1(7 downto 4);
when others =>
Result <= (others => '0');
end case;
end process;
end Behavioral;
● Séquenceur/décodeur:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SequencerDecoder_PIC10F200 is
Port ( CLK : in STD_LOGIC;
Reset : in STD_LOGIC;
Instruction : out STD_LOGIC_VECTOR(5 downto 0));
end SequencerDecoder_PIC10F200;
architecture Behavioral of SequencerDecoder_PIC10F200 is
signal Counter : integer range 0 to 35 := 0;
constant Instruction_Length : integer := 6;
process (CLK, Reset)
begin
if Reset = '1' then
Counter <= 0;
elsif rising_edge(CLK) then
if Counter = 35 then
Counter <= 0;
else
Counter <= Counter + 1;
end if;
end if;
end process;
Instruction <= std_logic_vector(to_unsigned(Counter, Instruction_Length));
end Behavioral;
