TECHNICAL BRIEF

Cadence Modus DFT Software Solution

Reduce test time by up to 3X without impact to fault coverage
or chip size

The Cadence ® Modus DFT Software Solution introduces a

ground-breaking new physically aware 2D Elastic Compression
architecture which reduces manufacturing test time by up
to 3X, saving test cost and making chips more profitable. This
Test Time (cost)

innovative patented technology can also reduce the overhead

of compression logic on chip routing resource by up to 2.6X,
improving die size and accelerating time to market. The
Cadence Modus DFT Software Solution is natively integrated
with Cadence’s full-flow digital solution, which provides 2X

faster design closure, better predictability, and best-in-

class power, performance, and area (PPA).

Introduction 130nm 90nm 65nm 45nm 28nm 16nm

Every year, the chip industry spends roughly $4B on
automated test equipment (ATE) for manufacturing test,
Process Node
according to industry experts. This cost must be absorbed Figure 1: Test costs rise as process nodes shrink.
into the overall production cost of each working chip coming
off production lines. At the same time, chips at advanced no impact on chip size or yield. Alternatively, for the same
nodes are becoming increasingly complex to enable ever test time as current industry solutions, the Cadence Modus
richer user experiences. This results in more and more DFT Software Solution can reduce the overhead of DFT
logic gates to be tested on ATEs, further driving up the logic on chip routing resources by up to 2.6X. Its patented
$4B market (see Figure 1). physically aware 2D Elastic Compression architecture is
the foundation behind these unique benefits.
Time on ATEs breaks down into several components – testing
of memories, chip I/O interfaces, analog logic, and digital
logic. Testing of digital logic typically ranges from 10-50%
XOR Compression
of total test time, which equates to a significant portion of XOR-based test compression is the approach most widely
the overall $4B annual ATE industry market size. used in the chip industry today to minimize digital logic ATE
test cost. XOR compression reduces test time by partitioning
The Cadence Modus DFT Software Solution is a new design-
registers in a design into more scan chains than there are
for-test (DFT) solution that reduces test time for digital logic
scan pins on the chip to connect to the ATE.
by up to 3X compared to current industry solutions, with
 Cadence Modus DFT Software Solution

scan_in pins scan_in pins

XOR Decompressor XOR Decompressor

Increase
Compression
Ratio
scan scan
chain chain

XOR Compressor XOR

XORDecompressor
Compressor

scan_out pins scan_out pins

Figure 2: As compression ratio increases, the number of patterns required to maintain fault coverage rises.

As the ratio between the number of scan chains and the Compression Ratio Impact on Chip Size
number of scan pins increases, the length of each scan chain
decreases, which means fewer clock cycles to shift in each In addition to fault coverage drop and pattern count growth,
test pattern. For a constant pattern count, fewer shift clock increasing the compression ratio also has a significant
cycles per pattern means less total test time on the ATE. impact on the physical implementation of a chip. That’s
because every scan chain must be connected to and from
the XOR compression logic (Figure 4).
Compression Ratio Impact on Coverage
and Test Time Scan Chains
XOR Decompressor

Fewer clock cycles per pattern also means fewer bits of XOR
Compression
information in each pattern to control register values and Logic

detect faults. At some point, if the compression ratio becomes Every scan chain must
have connection to/from
wiring to/from
scan chains
compression logic

too high, the achievable fault coverage drops since some

XOR Decompressor
XOR circuit
wiring

faults will require more register values to be controlled than

there are bits in a test pattern. Also, as the compression ratio Figure 4: Wiring overhead associated with compression logic.
increases, even if fault coverage can be maintained the number
At a typical industry compression ratio of 100X, the average
of patterns required to maintain this coverage rises rapidly since
impact of XOR compression logic across a range of common
it becomes more difficult to pack the detection of multiple faults
digital components is 3-5% of total chip routing resource. If
into a single pattern (Figure 2, above). As a result, there is a
the compression ratio is increased to 400X, then the impact
diminishing benefit on total test time from increasing the
on chip routing resource increases to a staggering 10%, which
compression ratio (Figure 3). The asymptote of this curve
would require a significant increase in die size to accommodate
is typically around 50-100X the compression ratio.
and ultimately outweigh any potential cost savings from the
# patterns reduced test time. See Table 1.
coverage % Chip Routing in
test time
Compression

length of chain
Design #Instances 100X 400X
(M)
compression ratio compression ratio CPU 1.3 5% 15%
Figure 3: Comparison of iSpatial and Spatial flows. GPU 2.6 3% 8%
Networking 1.6 3% 9%
DSP 2.3 5% 11%
Automotive 2.5 3% 6%
4% 10%

Table 1: Impact of increased compression ratio on chip routing.

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 Cadence Modus DFT Software Solution

2D Elastic Compression In Figure 6, the wirelength of the 2D grid structure scales

sub-linearly with the compression ratio, and at a 400X
The Cadence Modus DFT Software Solution introduces
compression ratio is still no worse for routing resource
two major innovations backed by an extensive portfolio
than traditional “one-dimensional” XOR compression at
of over 18 US patents granted to address the fundamental
a 100X compression ratio.
challenges of rising compression ratio: 2D Compression
and Elastic Compression. When combined, the Modus 2D
Elastic Compression architecture enables compression Elastic Compression
ratios beyond 400X with up to a 3X reduction in test time scan_in pins Sequential circuit with
compared to traditional XOR compression at a 100X XOR gates and registers
compression ratio. There is no impact on fault coverage
Elastic Decompressor
or chip routing resource.
Alternatively, if 2D compression is used on a traditional
non-elastic XOR compression structure at a 100X compression
ratio, then the impact of the compression logic on chip routing Scan
chain
resource is only 2%, an up to 2.6X improvement over current
industry solutions.

2D Compression XOR Compressor

Modus 2D Compression targets the impact of high compression
ratios on chip routing resource. The key insight behind Modus scan_out pins
2D Compression is to leverage the two-dimensional nature
Figure 7: With the sequential elastic decompressor, the ATPG
of a physical chip layout to build an XOR network which can algorithm can control register values in a single fault capture cycle.
unfold into a grid structure across the chip (Figure 5).
Modus Elastic Compression pairs with Modus 2D Compression
to mitigate the fault coverage and pattern count impact of high
compression ratios. It differs from traditional XOR compression
by leveraging registers and sequential feedback loops alongside
traditional XOR logic in the decompressor circuit.
The sequential nature of an elastic decompressor enables
the automatic test pattern generation (ATPG) algorithm to
leverage multiple shift cycles to control register values in a
Figure 5: In 2D Compression, an XOR network unfolds single fault capture cycle (Figure 7). Conceptually, this is
into a grid structure across the chip.

Traditional XOR Compression at 100X Modus 2D Compression at 400X

Same
Wirelength

% Chip Routing in Compression

Design #Instances (M) 1D-100X 1D-400X 2D-100X 2D-400X

CPU 1.3 5% 14.6% 3% 5%
GPU 2.6 2.9% 7.7% 2% 3%
Networking 1.6 3.3% 9.4% 2% 3%
DSP 2.3 4.6% 11.5% 3% 4%
Automotive 2.5 2.6% 5.6% 2% 2%
4% 10% 2% 4%

Figure 6: 2D Compression via the Cadence Modus DFT Software Solution yields a 400X compression ratio.

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 Cadence Modus DFT Software Solution

like being able to “borrow” scan bits from previous clock Verilog/SystemVerilog/VHD

cycles to help detect more challenging faults in the current

clock cycle. An elastic decompressor can also adaptively Genus Modus
Physical Synthesis DFT
increase the number of shift cycles in a test pattern to be
larger than the scan chain length to provide yet more
Insertion of 2D grid
controllability to detect tough faults. natively integrated
Innovus Test Patterns
Place and Route
within Genus physical
synthesis flow
Unified Compression and LBIST in
a Physically Aware Environment Tempus
Timing Signoff
Common
User Interface
Building on the 2D Elastic architecture, Unified Compression
is a new approach that unifies scan compression and logic Figure 8: A common UI in Cadence’s digital implementation flow
built-in self-test (LBIST). This new physically aware approach helps improve user productivity.
to LBIST allows designs to target the high coverage needed
route in the InnovusTM Implementation System, and timing
for safety-critical applications without impacting the design
signoff in the TempusTM.Timing Signoff Solution—shares a
convergence. On a sample design, area savings of 35-47%
common unified user interface for TCL scripting and reporting
and scan wirelength savings of 63-77% for the same channel
(Figure 8). This streamlines flow development, simplifies user
length can be demonstrated. Also, with the same area and
training, and improves productivity of multi-tool users.
scan wirelength budget, the channel length can instead be
reduced by half to reduce the overall test time with the same
fault coverage. Automotive and safety-critical designs stand Comprehensive Functionality
to benefit from this unique solution that is effective for both In addition to Modus 2D Elastic Compression, the Cadence
in-system test and 0-DPPM manufacturing test. Modus DFT Software Solution includes comprehensive support
For more information, read the “Unified Compression and for all other industry-standard DFT structures, such as fullscan,
LBIST in a Physically Aware Environment” white paper. XOR and MISR compression, X-masking, low-pin-count test,
programmable memory BIST, logic BIST, JTAG controllers, IEEE
1500 wrappers, iJTAG embedded instrument access, and
Integration with Implementation Flow timing-driven automatic testpoint insertion.
Bringing the two dimensionality of the physical world into
Modus ATPG supports hierarchical test, low-power ATPG
the creation of XOR compression logic requires a seamless
with scan and capture toggle count limits, and distributed
integration of compression logic insertion, logic synthesis,
test pattern generation with near-linear runtime scalability.
and gate placement. This is achieved through a native code
Modus Diagnostics includes single- and multi-die volume
level unification of the Cadence Modus DFT Software Solution
diagnostics, both with physical defect location callout and
with RTL physical synthesis using Cadence’s Genus™ Synthesis
root-cause analysis.
Solution. The output of the Genus Synthesis Solution with
Modus 2D Elastic Compression is a fully placed design,
including a placed 2D XOR grid structure. Further Information
Also, the complete suite of Cadence ® tools used for digital For more information, please check out our data sheet and
implementation—including test in the Cadence Modus DFT product page at www.cadence.com/modus.
Software Solution, the Genus Synthesis Solution, place and

Cadence is a pivotal leader in electronic design and computational expertise, using their Intelligent
System Design Strategy to turn design concepts into reality. Cadence customers are the world’s
most creative and innovative companies, delivering extraordinary electronic products from
chips to boards to systems in the most dynamic market applications. www.cadence.com

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