COMBINATIONAL LOGIC

DESIGN

Dr.Leela Kumari Balivada

Associate Professor
Cascading of Comparators
Code Converter
The logic circuit used to convert one code into another code is called as ‘Code
Converter’.
• Designing of 4-bit binary to BCD code convertor:
• Given 4-bit binary code has to convert into BCD code. We know
BCD has valid numbers only from 0 to 9. To make the values
above the 9 as valid BCD numbers, a value ‘6’ is added.
• Here we have 4-binary bits at input so there is a possibility of 16
combinations. For 0 to 9 only the valid BCD code we can generate,
for combinations from 10 to 15 a number 6 is added to get valid
BCD numbers
BCD to Binary code convertor:
Design of BCD to Excess-3 code convertor
Design of Binary to Gray code convertor:
GrayCode is used in digital circuits because it
has an advantage that only one bit is
changed between two successive numbers.
In Gray code the first or MSB digit is obtained
by taking MSB bit of corresponding binary
numbers asit is and next digit in gray code is
obtained by exclusive-or operation between
two successive binary digits
Parity circuit
• A parity bit is an extra added bit to the binary information bits
used to detect the errors during transmission. The parity bit
does not carry any information. It included in binary
information at the time of transmission to make the number
of 1s either even or odd.
• The message included with parity bit is transmitted and
checked at the receiver end for errors.
• An error will be detected if the received message is not
corresponds to the transmitted one.
• The circuit that generates the parity bit at the transmitter is
called Parity Generator and the circuit that checks the parity
in the receiver is called Parity Checker.
• In even parity the added parity bit makes total number of 1’s
as even amount. In odd parity the added parity bit makestotal
number of 1’s as odd amount.
Parity error checker circuit
• A parity bit is an extra added bit to the binary information bits used to
detect the errors during transmission. The parity bit does not carry any
information. It included in binary information at the time of transmission
to make the number of 1s either even or odd.
• The message included with parity bit is transmitted and checked at the
receiver end for errors. An error will be detected if the received
message is not corresponds to the transmitted one.
• The circuit that generates the parity bit at the transmitter is called Parity
• Generator and the circuit that checks the parity in the receiver is called
Parity Checker.
• In even parity the added parity bit makes total number of 1’s as even
amount. In odd parity the added parity bit makes total number of 1’s as
odd amount.
• Parity Error Checker circuit verifies is there any error bit in received
data or not. If received data stream has number of 1’s as even number
then there is no error. If it has odd number of 1’s then Parity Error
checker(PEC) gives a value 1, which means there is an error.
VHDL code Design a priority encoder for 16 inputs using two IC74X148s
Dual priority 16-bit barrel shifter circuit
library ieee;
encoder Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Entity barrel is
Port( din: in std_logic_vector (15 downto 0);
S: in unsigned(3 downto 0);
Dout: out std_logic_vector (15 downto 0));
End barrel;
Architecture behavioural of barrel is
Subtype dataword is std_logic_vector (15
downto 0);
Variable N: integer;
Variable tempd: dataword;
Begin
Procee(din, s)
Begin
N:=conv_integer(s);
For I in 1 to N loop
tempd := tempd(14 downto 0) & tempd(15);
end loop;
Dout<=tempd;
End Process;
End behavioural;