LTC2208

16-Bit, 130Msps ADC

FEATURES DESCRIPTION
n Sample Rate: 130Msps The LTC®2208 is a 130Msps, sampling 16-bit A/D converter
n 78dBFS Noise Floor designed for digitizing high frequency, wide dynamic
n 100dB SFDR range signals with input frequencies up to 700MHz. The
n SFDR >83dB at 250MHz (1.5VP-P Input Range) input range of the ADC can be optimized with the PGA
n PGA Front End (2.25VP-P or 1.5VP-P Input Range) front end.
n 700MHz Full Power Bandwidth S/H
n
The LTC2208 is perfect for demanding communications
Optional Internal Dither
n
applications, with AC performance that includes 78dBFS
Optional Data Output Randomizer
n
Noise Floor and 100dB spurious free dynamic range
LVDS or CMOS Outputs
n
(SFDR). Ultra low jitter of 70fsRMS allows undersampling
Single 3.3V Supply
n
of high input frequencies with excellent noise performance.
Power Dissipation: 1.25W
n
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
Clock Duty Cycle Stabilizer
n
missing codes).
Pin Compatible 14-Bit Version
130Msps: LTC2208 (16-Bit), LTC2208-14 (14-Bit) The digital output can be either differential LVDS or
n 64-Pin (9mm × 9mm) QFN Package single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
APPLICATIONS demultiplexed buses running at half data rate. A separate
output power supply allows the CMOS output swing to
n Telecommunications range from 0.5V to 3.6V.
n Receivers
n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially
n Spectrum Analysis or single-ended with a sine wave, PECL, LVDS, TTL or
n Imaging Systems CMOS inputs. An optional clock duty cycle stabilizer al-
n ATE lows high performance at full speed with a wide range of
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
clock duty cycles.
Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION
3.3V
SENSE
64k Point FFT, FIN = 15.1MHz,
1.25V INTERNAL ADC
OVDD –1dB, PGA = 0
VCM 0.5V TO 3.6V
COMMON MODE REFERENCE 0
2.2μF BIAS VOLTAGE GENERATOR 1μF –10
–20
OF –30
AIN+ CLKOUT
+ –40
AMPLITUDE (dBFS)

16-BIT CORRECTION OUTPUT D15 CMOS

ANALOG S/H PIPELINED –50
LOGIC AND DRIVERS • OR
INPUT AMP ADC CORE –60
SHIFT REGISTER • LVDS
AIN–
– • –70
D0 –80
–90
OGND
–100
CLOCK/DUTY –110
CYCLE VDD 3.3V
–120
CONTROL 1μF 1μF 1μF
GND –130
2208 TA01 0 10 20 30 40 50 60
FREQUENCY (MHz)
–
ENC + ENC PGA SHDN DITH MODE LVDS RAND
2208 TA01b

ADC CONTROL INPUTS

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LTC2208
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
OVDD = VDD (Notes 1 and 2)
TOP VIEW
Supply Voltage (VDD) ................................... –0.3V to 4V

58 D15+/DA14
57 D15–/DA13
56 D14+/DA12
55 D14–/DA11
54 D13+/DA10
53 D13–/DA9
52 D12+/DA8
51 D12–/DA7
59 OF–/DA15
60 OF+/OFA
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V

62 MODE

50 OGND
63 RAND

49 OVDD
61 LVDS
64 PGA
Analog Input Voltage (Note 3) ...... –0.3V to (VDD + 0.3V)
Digital Input Voltage..................... –0.3V to (VDD + 0.3V) SENSE 1 48 D11+/DA6
GND 2 47 D11–/DA5
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) VCM 3 46 D10+/DA4
45 D10–/DA3
Power Dissipation ............................................ 2000mW GND 4
VDD 5 44 D9+/DA2
43 D9–/DA1
Operating Temperature Range VDD 6
GND 7 42 D8+/DA0
LTC2208C ................................................ 0°C to 70°C AIN+ 8
AIN– 9
65
41 D8–/CLKOUTA
40 CLKOUT+/CLKOUTB
LTC2208I .............................................–40°C to 85°C GND 10 39 CLKOUT –/OFB
GND 11 38 D7+/DB15
Storage Temperature Range ..................–65°C to 150°C ENC+ 12 37 D7–/DB14
ENC– 13 36 D6+/DB13
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V GND 14 35 D6–/DB12
VDD 15 34 D5+/DB11
VDD 16 33 D5–/DB10

VDD 17
GND 18
SHDN 19
DITH 20
D0 /DB0 21
DO /DB1 22
D1–/DB2 23
D1+/DB3 24
D2–/DB4 25
D2+/DB5 26
D3–/DB6 27
D3+/DB7 28
D4–/DB8 29
D4+/DB9 30
OGND 31
OVDD 32
–
+
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
TJMAX = 150°C, θJA = 20°C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2208CUP#PBF LTC2208CUP#TRPBF LTC2208UP 64-Lead (9mm × 9mm) Plastic QFN 0°C to 70°C
LTC2208IUP#PBF LTC2208IUP#TRPBF LTC2208UP 64-Lead (9mm × 9mm) Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Integral Linearity Error Differential Analog Input (Note 5) TA = 25°C ±1.2 ±4.0 LSB
Integral Linearity Error Differential Analog Input (Note 5) l ±1.5 ±4.5 LSB
Differential Linearity Error Differential Analog Input l ±0.3 ±1 LSB
Offset Error (Note 6) l ±2 ±8.5 mV
Offset Drift ±10 μV/°C
Gain Error External Reference l ±0.2 ±1.5 %FS
Full-Scale Drift Internal Reference ±30 ppm/°C
External Reference ±15 ppm/°C
Transition Noise External Reference 2.9 LSBRMS

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 LTC2208
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 3.135V ≤ VDD ≤ 3.465V 1.5 or 2.25 VP-P
VIN, CM Analog Input Common Mode Differential Input (Note 7) l 1 1.25 1.5 V
IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD l –1 1 μA
ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD l –3 3 μA
IMODE MODE Pin Pull-Down Current to GND 10 μA
ILVDS LVDS Pin Pull-Down Current to GND 10 μA
CIN Analog Input Capacitance Sample Mode ENC+ < ENC– 6.5 pF
Hold Mode ENC+ > ENC– 1.8 pF
tAP Sample-and-Hold 1 ns
Acquisition Delay Time
tJITTER Sample-and-Hold 70 fs RMS
Acquisition Delay Time Jitter
CMRR Analog Input 1V < (AIN+ = AIN–) <1.5V 80 dB
Common Mode Rejection Ratio
BW-3dB Full Power Bandwidth RS < 25Ω 700 MHz

DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0) 77.7 dBFS
5MHz Input (1.5V Range, PGA = 1) 75.3 dBFS
30MHz Input (2.25V Range, PGA = 0) TA = 25°C 76.5 77.6 dBFS
30MHz Input (2.25V Range, PGA = 0) l 76.1 77.3 dBFS
30MHz Input (1.5V Range, PGA = 1) 75.2 dBFS
70MHz Input (2.25V Range, PGA = 0) 77.5 dBFS
70MHz Input (1.5V Range, PGA = 1) 75.1 dBFS
140MHz Input (2.25V Range, PGA = 0) 76.9 dBFS
140MHz Input (1.5V Range, PGA = 1) TA = 25°C 73.8 74.8 dBFS
140MHz Input (1.5V Range, PGA = 1) l 73.4 74.5 dBFS
250MHz Input (2.25V Range, PGA = 0) 75.4 dBFS
250MHz Input (1.5V Range, PGA =1) 73.8 dBFS
SFDR Spurious Free 5MHz Input (2.25V Range, PGA = 0) 100 dBc
Dynamic Range 5MHz Input (1.5V Range, PGA = 1) 100 dBc
2nd or 3rd Harmonic 30MHz Input (2.25V Range, PGA = 0) TA = 25°C 88 95 dBc
30MHz Input (2.25V Range, PGA = 0) l 87 94 dBc
30MHz Input (1.5V Range, PGA = 1) 100 dBc
70MHz Input (2.25V Range, PGA = 0) 90 dBc
70MHz Input (1.5V Range, PGA = 1) 95 dBc
140MHz Input (2.25V Range, PGA = 0) 85 dBc
140MHz Input (1.5V Range, PGA = 1) TA = 25°C 86 90 dBc
140MHz Input (1.5V Range, PGA = 1) l 84 89 dBc
250MHz Input (2.25V Range, PGA = 0) 78 dBc
250MHz Input (1.5V Range, PGA = 1) 83 dBc

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LTC2208
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS unless otherwise noted. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SFDR Spurious Free 5MHz Input (2.25V Range, PGA = 0) 100 dBc
Dynamic Range 5MHz Input (1.5V Range, PGA = 1) 100 dBc
4th Harmonic 30MHz Input (2.25V Range, PGA = 0) l 90 100 dBc
or Higher 30MHz Input (1.5V Range, PGA = 1) 100 dBc
70MHz Input (2.25V Range, PGA = 0) 100 dBc
70MHz Input (1.5V Range, PGA = 1) 100 dBc
140MHz Input (2.25V Range, PGA = 0) 95 dBc
140MHz Input (1.5V Range, PGA = 1) l 88 95 dBc
250MHz Input (2.25V Range, PGA = 0) 90 dBc
250MHz Input (1.5V Range, PGA = 1) 90 dBc
S/(N+D) Signal-to-Noise 5MHz Input (2.25V Range, PGA = 0) 77.7 dBFS
Plus Distortion Ratio 5MHz Input (1.5V Range, PGA = 1) 75.3 dBFS
30MHz Input (2.25V Range, PGA = 0) TA = 25°C 76.3 77.5 dBFS
30MHz Input (2.25V Range, PGA = 0) l 75.9 77.5 dBFS
30MHz Input (1.5V Range, PGA = 1) 75.2 dBFS
70MHz Input (2.25V Range, PGA = 0) 77.4 dBFS
70MHz Input (1.5V Range, PGA = 1) 75 dBFS
140MHz Input (2.25V Range, PGA = 0) 76.4 dBFS
140MHz Input (1.5V Range, PGA = 1) TA = 25°C 73.6 74.5 dBFS
140MHz Input (1.5V Range, PGA = 1) l 73.2 74.5 dBFS
250MHz Input (2.25V Range, PGA = 0) 73.6 dBFS
250MHz Input (1.5V Range, PGA = 1) 72.9 dBFS
SFDR Spurious Free Dynamic Range 5MHz Input (2.25V Range, PGA = 0) 105 dBFS
at –25dBFS 5MHz Input (1.5V Range, PGA = 1) 105 dBFS
Dither “OFF” 30MHz Input (2.25V Range, PGA = 0) 105 dBFS
30MHz Input (1.5V Range, PGA = 1) 105 dBFS
70MHz Input (2.25V Range, PGA = 0) 105 dBFS
70MHz Input (1.5V Range, PGA = 1) 105 dBFS
140MHz Input (2.25V Range, PGA = 0) 100 dBFS
140MHz Input (1.5V Range, PGA = 1) 100 dBFS
250MHz Input (2.25V Range, PGA = 0) 100 dBFS
250MHz Input (1.5V Range, PGA = 1) 100 dBFS
SFDR Spurious Free Dynamic Range 5MHz Input (2.25V Range, PGA = 0) 115 dBFS
at –25dBFS 5MHz Input (1.5V Range, PGA = 1) 115 dBFS
Dither “ON” 30MHz Input (2.25V Range, PGA = 0) l 100 115 dBFS
30MHz Input (1.5V Range, PGA = 1) 115 dBFS
70MHz Input (2.25V Range, PGA = 0) 115 dBFS
70MHz Input (1.5V Range, PGA = 1) 115 dBFS
140MHz Input (2.25V Range, PGA = 0) 110 dBFS
140MHz Input (1.5V Range, PGA = 1) 110 dBFS
250MHz Input (2.25V Range, PGA = 0) 105 dBFS
250MHz Input (1.5V Range, PGA = 1) 105 dBFS

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 LTC2208
COMMON MODE BIAS CHARACTERISTICS The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.15 1.25 1.35 V
VCM Output Tempco IOUT = 0 +40 ppm/°C
VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 1 mV/ V
VCM Output Resistance 1mA ≤ | IOUT | ≤ 1mA 2 Ω

DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
VID Differential Input Voltage (Note 7) l 0.2 V
VICM Common Mode Input Voltage Internally Set 1.6 V
Externally Set (Note 7) 1.2 3.0 V
RIN Input Resistance (See Figure 2) 6 kΩ
CIN Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH High Level Input Voltage VDD = 3.3V l 2 V
VIL Low Level Input Voltage VDD = 3.3V l 0.8 V
IIN Digital Input Current VIN = 0V to VDD l ±10 μA
CIN Digital Input Capacitance (Note 7) 1.5 pF
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
VOH High Level Output Voltage VDD = 3.3V IO = –10μA 3.299 V
IO = –200μA l 3.1 3.29 V
VOL Low Level Output Voltage VDD = 3.3V IO = 160μA 0.01 V
IO = 1.6mA l 0.10 0.4 V
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = 3.3V 50 mA
OVDD = 2.5V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V
OVDD = 1.8V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.60mA 0.1 V
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS
VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV
VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V
LOW POWER LVDS
VOD Differential Ouptut Voltage 100Ω Differential Load l 125 175 250 mV
VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V

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LTC2208
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 V
PSHDN Shutdown Power SHDN = VDD 0.2 mW
STANDARD LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V
IVDD Analog Supply Current l 380 450 mA
IOVDD Output Supply Current l 74 90 mA
PDIS Power Dissipation l 1498 1782 mW
LOW POWER LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V
IVDD Analog Supply Current l 380 450 mA
IOVDD Output Supply Current l 31 50 mA
PDIS Power Dissipation l 1356 1650 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 3.6 V
IVDD Analog Supply Current l 380 450 mA
PDIS Power Dissipation l 1250 1485 mW

TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 130 MHz
tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) l 3.65 3.846 1000 ns
Duty Cycle Stabilizer On (Note 7) l 2.6 3.846 1000 ns
tH ENC High Time Duty Cycle Stabilizer Off (Note 7) l 3.65 3.846 1000 ns
Duty Cycle Stabilizer On (Note 7) l 2.6 3.846 1000 ns
tAP Sample-and-Hold Aperture Delay –1 ns
LVDS OUTPUT MODE (STANDARD and LOW POWER)
tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 ns
tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns
tRISE Output Rise Time 0.5 ns
tFALL Output Fall Time 0.5 ns
Data Latency Data Latency 7 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1.3 2.7 4.0 ns
tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4.0 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns
Data Latency Data Latency Full Rate CMOS 7 Cycles
Demuxed 7 Cycles

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 LTC2208
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
may cause permanent damage to the device. Exposure to any Absolute fit straight line” to the transfer curve. The deviation is measured from the
Maximum Rating condition for extended periods may affect device center of the quantization band.
reliability and lifetime. Note 6: Offset error is the offset voltage measured from –1/2LSB when the
Note 2: All voltage values are with respect to GND, with GND and OGND output code flickers between 0000 0000 0000 0000 and 1111 1111 1111
shorted (unless otherwise noted). 1111 in 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above VDD, they Note 7: Guaranteed by design, not subject to test.
will be clamped by internal diodes. This product can handle input currents Note 8: Recommended operating conditions.
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/
ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P
with differential drive (PGA = 0), unless otherwise specified.

TIMING DIAGRAMS
LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
tAP
N+1 N+4
ANALOG
INPUT N N+3
N+2
tH
tL
–
ENC

ENC+
tD

D0-D15, OF N–7 N–6 N–5 N–4 N–3

tC
CLKOUT+

CLKOUT – 2208 TD01

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LTC2208
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
tAP
N+1 N+4
ANALOG
INPUT N N+3
N+2
tH
tL

ENC–

ENC+
tD

DA0-DA15, OFA N–7 N–6 N–5 N–4 N–3

tC
CLKOUTA

CLKOUTB

DB0-DB15, OFB HIGH IMPEDANCE

2208 TD02

Demultiplexed CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels
tAP
N+1 N+4
ANALOG
INPUT N N+3
N+2
tH
tL

ENC–

ENC+
tD

DA0-DA15, OFA N–8 N–6 N–4

tD

DB0-DB15, OFB N–7 N–5 N–3

tC
CLKOUTA

2208 TD03
CLKOUTB

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 LTC2208
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) vs Differential Nonlinearity (DNL) vs
Output Code Output Code AC Grounded Input Histogram
2 1 10000
0.8 9000
1.5
0.6 8000
1
0.4 7000

DNL ERROR (LSB)

INL ERROR (LSB)

0.5 0.2 6000

COUNT
0 0 5000
0.2 4000
–0.5
0.4 3000
–1
0.6 2000
–1.5 0.8 1000
–2 1 0
0 16384 32768 49152 65536 0 16384 32768 49152 65536 32736 32740 32744 32748 32752 32756
OUTPUT CODE OUTPUT CODE 2208 G02
OUTPUT CODE
2208 G01 2208 G14

128k Point FFT, fIN = 4.93MHz, 64k Point FFT, fIN = 15.1MHz, 64k Point FFT, 15.1MHz, –20dBFS,
–1dBFS, PGA = 0 –1dBFS, PGA = 0 PGA = 0, Internal Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40 –40
AMPLITUDE (dBFS)

–40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2208 G15 2208 G03 2208 G04

32k Point 2-Tone FFT, 32k Point 2-Tone FFT,

64k Point FFT, 15.1MHz, –20dBFS, fIN = 21.14MHz and 14.25MHz, fIN = 20.14MHz and 14.25MHz,
PGA = 0, Internal Dither “On” –7dBFS, PGA = 0 –25dBFS, PGA = 0
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40
–50
–50 –50
–60
–60 –60
–70
–70 –70
–80
–90 –80 –80
–100 –90 –90
–110 –100 –100
–120 –110 –110
–130 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2208 G05 2208 G06 2208 G07

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LTC2208
TYPICAL PERFORMANCE CHARACTERISTICS

SFDR vs Input Level, fIN = 15MHz, SFDR vs Input Level, fIN = 15MHz, 64k Point FFT, fIN = 30.1MHz,
PGA = 0, Dither “Off” PGA = 0, Dither “On” –1dBFS, PGA = 0
140 140 0
130 130 –10
120 120 –20
110 110 –30
SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

100 100 –40

AMPLITUDE (dBFS)
90 90
–50
80 80
–60
70 70
–70
60 60
50 –80
50
40 40 –90
30 30 –100
20 20 –110
10 10 –120
0 0 –130
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60
INPUT LEVEL (dBFS) 2208 G08 INPUT LEVEL (dBFS) 2208 G09
FREQUENCY (MHz)
2208 G16

128k Point FFT, fIN = 30.1MHz, 64k Point FFT, fIN = 70.1MHz, 64k Point FFT, fIN = 70.1MHz,
–25dBFS, PGA = 0, Dither “On” –1dBFS, PGA = 0 –10dBFS, PGA = 0
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40 –40 –40
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–50 –50 –50

–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2208 G17 2208 G18 2208 G19

64k Point FFT, fIN = 70.1MHz, 128k Point FFT, fIN = 70.1MHz, 64k Point FFT, fIN = 70.1MHz,
–20dBFS, PGA = 0 –25dBFS, PGA = 0, Dither “On” –1dBFS, PGA = 1
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40
AMPLITUDE (dBFS)

–40 –40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–50 –50 –50

–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
–130 –130 –130
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2208 G20 2208 G21 2208 G22

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 LTC2208
TYPICAL PERFORMANCE CHARACTERISTICS
SFDR vs Input Level, SFDR vs Input Level,
fIN = 70.2MHz, fIN = 70.2MHz, 64k Point FFT, fIN = 67.2MHz and
PGA = 0, Dither “Off” PGA = 0, Dither “On” 74.4MHz, –7dBFS, PGA = 0
130 130 0
120 120 –10
–20
110 110
–30

SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

100 100 –40

AMPLITUDE (dBFS)
90 90 –50
–60
80 80
–70
70 70 –80
60 60 –90
50 –100
50
–110
40 40
–120
30 30 –130
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS) FREQUENCY (MHz)
2208 G28 2208 G29 2208 G24

64k Point FFT, fIN = 67.2MHz and 64k Point FFT, fIN = 140.1MHz, 64k Point FFT, fIN = 140.1MHz,
74.4MHz, –15dBFS, PGA = 0 –1dBFS, PGA = 0 –1dBFS, PGA = 1
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
–40 AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40
–50
–50 –50
–60
–60 –60
–70
–70 –70
–80
–90 –80 –80
–100 –90 –90
–110 –100 –100
–120 –110 –110
–130 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2208 G25 2208 G27 2208 G26

SFDR vs Input Level, SFDR vs Input Level,

fIN = 140.2MHz, fIN = 140.2MHz, 64k Point FFT, fIN = 170.1MHz,
PGA = 1, Dither “Off” PGA = 1, Dither “On” –1dBFS, PGA = 1
130 130 0
120 120 –10
–20
110 110
–30
SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

100 100
AMPLITUDE (dBFS)

–40
90 90 –50
80 80 –60
70 70 –70
–80
60 60
–90
50 50
–100
40 40 –110
30 30 –120
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS) FREQUENCY (MHz)
2208 G30 2208 G31 2208 G34

2208fc

11
LTC2208
TYPICAL PERFORMANCE CHARACTERISTICS

64k Point FFT, fIN = 250.1MHz, 64k Point FFT, fIN = 250.1MHz, 64k Point FFT, fIN = 380MHz,
–1dBFS, PGA = 1 –10dBFS, PGA = 1 –1dBFS, PGA = 1
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–40 –40 –40
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
2208 G36 2208 G37 2208 G38

64k Point FFT, fIN = 380MHz, SFDR (HD2 and HD3) vs

–10dBFS, PGA = 1 Input Frequency SNR vs Input Frequency
0 105 78
–10
100 77
–20
–30 95 76
PGA = 0
AMPLITUDE (dBFS)

–40
90 75
SNR (dBFS)
SFDR (dBc)

–50 PGA = 1
–60 85 74
–70 PGA = 1
80 73
–80
PGA = 0
–90 75 72
–100
70 71
–110
–120 65 70
0 10 20 30 40 50 60 0 100 200 300 400 500 0 100 200 300 400 500
FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz)
2208 G39 2208 G23 2208 G40

SNR and SFDR vs Sample Rate, SNR and SFDR vs Supply IVDD vs Sample Rate, 5MHz Sine
fIN = 5MHz Voltage (VDD), fIN = 5MHz Wave, –1dBFS
110 110 420
LIMIT LOWER LIMIT
105 105
400
SFDR SFDR
100 100
SNR AND SFDR (dBFS)
SNR AND SFDR (dBFS)

380
95 95
IVDD (mA)

UPPER LIMIT
90 90 360

85 85
340
80 SNR 80 SNR
320
75 75

70 70 300
0 25 50 75 100 125 150 175 200 2.8 3 3.2 3.4 3.6 0 50 100 150
SAMPLE RATE (Msps) SUPPLY VOLTAGE (V) SAMPLE RATE (Msps)
2208 G32 2208 G33 2208 G13

2208fc

12
 LTC2208
TYPICAL PERFORMANCE CHARACTERISTICS
Normalized Full Scale vs
Temperature, Internal Reference,
SNR and SFDR vs Duty Cycle 5 Units
110 1.01

100

NORMALIZED FULL SCALE

1.005
SFDR AND SNR (dBFS)

90
1
80

SNR DCS OFF 0.995

70 SNR DCS ON
SFDR DCS OFF
SFDR DCS ON
60 0.99
30 40 50 60 70 –40 –20 0 20 40 60 80
DUTY CYCLE (%) TEMPERATURE (°C)
2208 G10 2208 G11

SFDR vs Analog Input Common

Input Offset Voltage vs Mode Voltage, 10MHz and 70MHz,
Temperature, 5 Units –1dBFS, PGA = 0
5 110
4 105
3 100
10MHz
OFFSET VOLTAGE (mV)

2 95
SFDR (dBc)

1 90
0 85
–1 80
–2 75 70MHz

–3 70
–4 65
–5 60
–40 –20 0 20 40 60 80 0.5 0.75 1 1.25 1.5 1.75 2
TEMPERATURE (°C) ANALOG INPUT COMMON MODE VOLTAGE (V)
2208 G12
2208 G41

Mid-Scale Settling After Wake Full-Scale Settling After Wake

Up from Shutdown or Starting Up from Shutdown or Starting
Encode Clock Encode Clock
1.0 5
0.8 4
0.6 3
FULL-SCALE ERROR (%)

FULL-SCALE ERROR (%)

0.4 2
0.2 1
0 0
–0.2 –1
–0.4 –2
–0.6 –3
–0.8 –4
–1.0 –5
0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 500 600 700 800 900 1000
TIME AFTER WAKE-UP OR CLOCK START (μs) TIME FROM WAKE-UP OR CLOCK START (μs)
2208 G42 2208 G43

2208fc

13
LTC2208
PIN FUNCTIONS
For CMOS Mode. Full Rate or Demultiplexed CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
SENSE (Pin 1): Reference Mode Select and External at the sample rate in full rate CMOS mode or at 1/2 the
Reference Input. Tie SENSE to VDD to select the internal sample rate in demultiplexed mode. Latch the data on the
2.5V bandgap reference. An external reference of 2.5V or falling edge of CLKOUTB.
1.25V may be used; both reference values will set a full CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
scale ADC range of 2.25V (PGA = 0). will toggle at the sample rate in full rate CMOS mode or
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. at 1/2 the sample rate in demultiplexed mode. Latch the
data on the rising edge of CLKOUTA.
VCM (Pin 3): 1.25V Output. Optimum voltage for input com-
mon mode. Must be bypassed to ground with a minimum DA0-DA15 (Pins 42-48 and 51-59): Digital Outputs, A Bus.
of 2.2μF. Ceramic chip capacitors are recommended. DA15 is the MSB. Output bus for full rate CMOS mode
and demultiplexed mode.
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin.
Bypass to GND with 1μF ceramic chip capacitors. OFA (Pin 60): Over/Under Flow Digital Output for the A
Bus. OFA is high when an over or under flow has occurred
AIN+ (Pin 8): Positive Differential Analog Input. on the A bus.
AIN– (Pin 9): Negative Differential Analog Input. LVDS (Pin 61): Data Output Mode Select Pin. Connecting
ENC+ (Pin 12): Positive Differential Encode Input. The LVDS to 0V selects full rate CMOS mode. Connecting LVDS
sampled analog input is held on the rising edge of ENC+. to 1/3VDD selects demultiplexed CMOS mode. Connecting
Internally biased to 1.6V through a 6.2k resistor. Output LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
data can be latched on the rising edge of ENC+. ing LVDS to VDD selects Standard LVDS mode.
ENC– (Pin 13): Negative Differential Encode Input. The MODE (Pin 62): Output Format and Clock Duty Cycle
sampled analog input is held on the falling edge of ENC –. Stabilizer Selection Pin. Connecting MODE to 0V selects
Internally biased to 1.6V through a 6.2k resistor. Bypass to offset binary output format and disables the clock duty
ground with a 0.1μF capacitor for a single-ended Encode cycle stabilizer. Connecting MODE to 1/3VDD selects offset
signal. binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3VDD selects 2’s complement
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results
output format and enables the clock duty cycle stabilizer.
in normal operation. SHDN = high results in powered
Connecting MODE to VDD selects 2’s complement output
down analog circuitry and the digital outputs are placed
format and disables the clock duty cycle stabilizer.
in a high impedance state.
RAND (Pin 63): Digital Output Randomization Selection
DITH (Pin 20): Internal Dither Enable Pin. DITH = low
Pin. RAND low results in normal operation. RAND high
disables internal dither. DITH = high enables internal dither.
selects D1-D15 to be EXCLUSIVE-ORed with D0 (the
Refer to Internal Dither section of this data sheet for details
LSB). The output can be decoded by again applying an
on dither operation.
XOR operation between the LSB and all other bits. This
DB0-DB15 (Pins 21-30 and 33-38): Digital Outputs, B Bus. mode of operation reduces the effects of digital output
DB15 is the MSB. Active in demultiplexed mode. The B interference.
bus is in high impedance state in full rate CMOS.
PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low
OGND (Pins 31 and 50): Output Driver Ground. selects a front-end gain of 1, input range of 2.25VP-P. High
OVDD (Pins 32 and 49): Positive Supply for the Output selects a front-end gain of 1.5, input range of 1.5VP-P.
Drivers. Bypass to ground with 1μF capacitor. GND (Exposed Pad): ADC Power Ground. The exposed
OFB (Pin 39): Over/Under Flow Digital Output for the B Bus. pad on the bottom of the package must be soldered to
OFB is high when an over or under flow has occurred on the ground.
B bus. At high impedance state in full rate CMOS mode.
2208fc

14
 LTC2208
PIN FUNCTIONS
For LVDS Mode. STANDARD or LOW POWER OGND (Pins 31 and 50): Output Driver Ground.
SENSE (Pin 1): Reference Mode Select and External OVDD (Pins 32 and 49): Positive Supply for the Output
Reference Input. Tie SENSE to VDD to select the internal Drivers. Bypass to ground with 0.1μF capacitor.
2.5V bandgap reference. An external reference of 2.5V or
CLKOUT–/CLKOUT + (Pins 39 and 40): LVDS Data Valid
1.25V may be used; both reference values will set a full 0utput. Latch data on the rising edge of CLKOUT +, falling
scale ADC range of 2.25V (PGA = 0). edge of CLKOUT –.
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. OF–/OF+ (Pins 59 and 60): Over/Under Flow Digital Output
VCM (Pin 3): 1.25V Output. Optimum voltage for input com- OF is high when an over or under flow has occurred.
mon mode. Must be bypassed to ground with a minimum
LVDS (Pin 61): Data Output Mode Select Pin. Connecting
of 2.2μF. Ceramic chip capacitors are recommended.
LVDS to 0V selects full rate CMOS mode. Connecting LVDS
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. to 1/3VDD selects demultiplexed CMOS mode. Connecting
Bypass to GND with 1μF ceramic chip capacitors. LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
ing LVDS to VDD selects Standard LVDS mode.
AIN + (Pin 8): Positive Differential Analog Input.
MODE (Pin 62): Output Format and Clock Duty Cycle
AIN – (Pin 9): Negative Differential Analog Input.
Stabilizer Selection Pin. Connecting MODE to 0V selects
ENC + (Pin 12): Positive Differential Encode Input. The offset binary output format and disables the clock duty
sampled analog input is held on the rising edge of ENC+. cycle stabilizer. Connecting MODE to 1/3VDD selects offset
Internally biased to 1.6V through a 6.2k resistor. Output binary output format and enables the clock duty cycle sta-
data can be latched on the rising edge of ENC+. bilizer. Connecting MODE to 2/3VDD selects 2’s complement
ENC – (Pin 13): Negative Differential Encode Input. The output format and enables the clock duty cycle stabilizer.
sampled analog input is held on the falling edge of ENC –. Connecting MODE to VDD selects 2’s complement output
Internally biased to 1.6V through a 6.2k resistor. Bypass to format and disables the clock duty cycle stabilizer.
ground with a 0.1μF capacitor for a single-ended Encode RAND (Pin 63): Digital Output Randomization Selection Pin.
signal. RAND low results in normal operation. RAND high selects
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results D1-D15 to be EXCLUSIVE-ORed with D0 (the LSB). The
in normal operation. SHDN = high results in powered output can be decoded by again applying an XOR operation
down analog circuitry and the digital outputs are set in between the LSB and all other bits. The mode of operation
high impedance state. reduces the effects of digital output interference.

DITH (Pin 20): Internal Dither Enable Pin. DITH = low PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low
disables internal dither. DITH = high enables internal dither. selects a front-end gain of 1, input range of 2.25VP-P. High
Refer to Internal Dither section of the data sheet for details selects a front-end gain of 1.5, input range of 1.5VP-P.
on dither operation. GND (Exposed Pad Pin 65): ADC Power Ground. The
D0–/D0+ to D15–/D15+ (Pins 21-30, 33-38, 41-48 and exposed pad on the bottom of the package must be sol-
51-58): LVDS Digital Outputs. All LVDS outputs require dered to ground.
differential 100Ω termination resistors at the LVDS receiver.
D15+/D15– is the MSB.

2208fc

15
LTC2208
BLOCK DIAGRAM

AIN+
VDD
INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED
S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE
AIN–
GND

DITHER
SIGNAL
GENERATOR
CORRECTION LOGIC
AND
SHIFT REGISTER

RANGE ADC CLOCKS

SELECT OVDD
CLKOUT+
CLKOUT–
SENSE OF+
DIFFERENTIAL
ADC OF–
INPUT
PGA
REFERENCE CONTROL OUTPUT D15+
LOW JITTER LOGIC DRIVERS • D15–
CLOCK
VCM DRIVER •
BUFFER •
D0+
D0–
VOLTAGE
REFERENCE

2208 F01
OGND
ENC+ ENC– SHDN PGA RAND M0DE LVDS DITH

Figure 1. Functional Block Diagram

2208fc

16
 LTC2208
OPERATION
DYNAMIC PERFORMANCE If two pure sine waves of frequencies fa and fb are ap-
plied to the ADC input, nonlinearities in the ADC transfer
Signal-to-Noise Plus Distortion Ratio function can create distortion products at the sum and
The signal-to-noise plus distortion ratio [S/(N+D)] is the difference frequencies of mfa ± nfb, where m and n =
ratio between the RMS amplitude of the fundamental input 0, 1, 2, 3, etc. For example, the 3rd order IMD terms
frequency and the RMS amplitude of all other frequency include (2fa + fb), (fa + 2fb), (2fa - fb) and (fa - 2fb). The
components at the ADC output. The output is band lim- 3rd order IMD is defined as the ration of the RMS value
ited to frequencies above DC to below half the sampling of either input tone to the RMS value of the largest 3rd
frequency. order IMD product.

Signal-to-Noise Ratio Spurious Free Dynamic Range (SFDR)

The signal-to-noise (SNR) is the ratio between the RMS The ratio of the RMS input signal amplitude to the RMS
amplitude of the fundamental input frequency and the RMS value of the peak spurious spectral component expressed
amplitude of all other frequency components, except the in dBc. SFDR may also be calculated relative to full scale
first five harmonics. and expressed in dBFS.

Total Harmonic Distortion Full Power Bandwidth

Total harmonic distortion is the ratio of the RMS sum The Full Power bandwidth is that input frequency at which
of all harmonics of the input signal to the fundamental the amplitude of the reconstructed fundamental is reduced
itself. The out-of-band harmonics alias into the frequency by 3dB for a full scale input signal.
band between DC and half the sampling frequency. THD
Aperture Delay Time
is expressed as:
The time from when a rising ENC + equals the ENC– voltage
⎛
THD = –20Log ⎜
⎝ ( )
V22 + V32 + V42 +… VN2
⎞
/ V1⎟
⎠
to the instant that the input signal is held by the sample-
and-hold circuit.
where V1 is the RMS amplitude of the fundamental fre- Aperture Delay Jitter
quency and V2 through VN are the amplitudes of the second
through nth harmonics. The variation in the aperture delay time from convertion
to conversion. This random variation will result in noise
Intermodulation Distortion when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can SNRJITTER = –20log (2π • fIN • tJITTER)
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.

2208fc

17
LTC2208
APPLICATIONS INFORMATION
CONVERTER OPERATION SAMPLE/HOLD OPERATION AND INPUT DRIVE
The LTC2208 is a CMOS pipelined multistep converter
Sample/Hold Operation
with a front-end PGA. As shown in Figure 1, the converter
has five pipelined ADC stages; a sampled analog input Figure 2 shows an equivalent circuit for the LTC2208 CMOS
will result in a digitized value seven cycles later (see the differential sample and hold. The differential analog inputs
Timing Diagrams section). The analog input is differen- are sampled directly onto sampling capacitors (CSAMPLE)
tial for improved common mode noise immunity and to through NMOS transitors. The capacitors shown attached
maximize the input range. Additionally, the differential to each input (CPARASITIC) are the summation of all other
input drive will reduce even order harmonics of the sample capacitance associated with each input.
and hold circuit. The encode input is also differential for
During the sample phase when ENC is low, the NMOS
improved common mode noise immunity.
transistors connect the analog inputs to the sampling
The LTC2208 has two phases of operation, determined capacitors and they charge to, and track the differential
by the state of the differential ENC+/ENC – input pins. For input voltage. When ENC transitions from low to high, the
brevity, the text will refer to ENC+ greater than ENC – as sampled input voltage is held on the sampling capacitors.
ENC high and ENC+ less than ENC – as ENC low. During the hold phase when ENC is high, the sampling
Each pipelined stage shown in Figure 1 contains an ADC, capacitors are disconnected from the input and the held
a reconstruction DAC and an interstage amplifier. In op- voltage is passed to the ADC core for processing. As ENC
eration, the ADC quantizes the input to the stage and the transitions for high to low, the inputs are reconnected to
quantized value is subtracted from the input by the DAC the sampling capacitors to acquire a new sample. Since
to produce a residue. The residue is amplified and output the sampling capacitors still hold the previous sample,
by the residue amplifier. Successive stages operate out a charging glitch proportional to the change in voltage
of phase so that when odd stages are outputting their between samples will be seen at this time. If the change
residue, the even stages are acquiring that residue and between the last sample and the new sample is small,
vice versa. the charging glitch seen at the input will be small. If the
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors, LTC2208
VDD
inside the “input S/H” shown in the block diagram. At the CSAMPLE
4.9pF
instant that ENC transitions from low to high, the voltage
AIN+
on the sample capacitors is held. While ENC is high, the CPARASITIC
held input voltage is buffered by the S/H amplifier which VDD 1.8pF
CSAMPLE
drives the first pipelined ADC stage. The first stage acquires 4.9pF
the output of the S/H amplifier during the high phase of AIN–
ENC. When ENC goes back low, the first stage produces CPARASITIC
1.8pF
its residue which is acquired by the second stage. At the VDD
same time, the input S/H goes back to acquiring the analog
input. When ENC goes high, the second stage produces
its residue which is acquired by the third stage. An iden- 1.6V
tical process is repeated for the third and fourth stages, 6k
resulting in a fourth stage residue that is sent to the fifth ENC+
stage for final evaluation.
ENC–
Each ADC stage following the first has additional range to
6k
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that 1.6V

the results can be properly combined in the correction 2208 F02

logic before being sent to the output buffer. Figure 2. Equivalent Input Circuit
2208fc

18
 LTC2208
APPLICATIONS INFORMATION
input change is large, such as the change seen with input provide isolation from ADC S/H switching. The LTC2208
frequencies near Nyquist, then a larger charging glitch has a very broadband S/H circuit, DC to 700MHz; it can
will be seen. be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC filter.
Common Mode Bias
Figures 3, 4a and 4b show three examples of input RC
The ADC sample-and-hold circuit requires differential filtering at three ranges of input frequencies. In general
drive to achieve specified performance. Each input should it is desirable to make the capacitors as large as can be
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
tolerated—this will help suppress random noise as well
for the 1.5V range (PGA = 1), around a common mode
as noise coupled from the digital circuitry. The LTC2208
voltage of 1.25V. The VCM output pin (Pin 3) is designed
does not require any input filter to achieve data sheet
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC specifications; however, no filtering will put more stringent
input level or as a reference level to an op amp differential noise requirements on the input drive circuitry.
driver circuit. The VCM pin must be bypassed to ground
Transformer Coupled Circuits
close to the ADC with 2.2μF or greater.
Figure 3 shows the LTC2208 being driven by an RF trans-
Input Drive Impedence former with a center-tapped secondary. The secondary
As with all high performance, high speed ADCs the dy- center tap is DC biased with VCM, setting the ADC input
namic performance of the LTC2208 can be influenced signal at its optimum DC level. Figure 3 shows a 1:1 turns
by the input drive circuitry, particularly the second and ratio transformer. Other turns ratios can be used; however,
third harmonics. Source impedance and input reactance as the turns ratio increases so does the impedance seen by
can influence SFDR. At the falling edge of ENC the the ADC. Source impedance greater than 50Ω can reduce
sample and hold circuit will connect the 4.9pF sampling the input bandwidth and increase high frequency distor-
capacitor to the input pin and start the sampling period. tion. A disadvantage of using a transformer is the loss of
The sampling period ends when ENC rises, holding the low frequency response. Most small RF transformers have
sampled input on the sampling capacitor. Ideally, the poor performance at frequencies below 1MHz.
input circuitry should be fast enough to fully charge Center-tapped transformers provide a convenient means
the sampling capacitor during the sampling period of DC biasing the secondary; however, they often show
1/(2F encode); however, this is not always possible and the poor balance at high input frequencies, resulting in large
incomplete settling may degrade the SFDR. The sampling 2nd order harmonics.
glitch has been designed to be as linear as possible to
VCM
minimize the effects of incomplete settling.
2.2μF
For the best performance it is recommended to have a 5Ω
10Ω 5Ω AIN+
source impedence of 100Ω or less for each input. The LTC2208
T1
source impedence should be matched for the differential 8.2pF
35Ω
inputs. Poor matching will result in higher even order 8.2pF
harmonics, especially the second. 0.1μF
35Ω
10Ω 5Ω AIN–

INPUT DRIVE CIRCUITS T1 = MA/COM ETC1-1T 8.2pF

2208 F03
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Input Filtering EXCEPT 2.2μF

A first order RC low pass filter at the input of the ADC can Figure 3. Single-Ended to Differential Conversion
serve two functions: limit the noise from input circuitry and Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz
2208fc

19
LTC2208
APPLICATIONS INFORMATION
Figure 4a shows transformer coupling using a transmis- Reference Operation
sion line balun transformer. This type of transformer has Figure 6 shows the LTC2208 reference circuitry consisting
much better high frequency response and balance than of a 2.5V bandgap reference, a programmable gain ampli-
flux coupled center tap transformers. Coupling capacitors fier and control circuit. The LTC2208 has three modes of
are added at the ground and input primary terminals to
allow the secondary terminals to be biased at 1.25V. Figure VCM

4b shows the same circuit with components suitable for 2.2μF

HIGH SPEED
higher input frequencies. DIFFERENTIAL
AMPLIFIER 25Ω AIN+
LTC2208
VCM
ANALOG + 12pF
INPUT +
2.2μF CM
0.1μF
– –
10Ω 5Ω AIN+ 25Ω AIN–
ANALOG
LTC2208
INPUT
25Ω 0.1μF 4.7pF 12pF
AMPLIFIER = LTC6600-20, 2208 F05
T1 LTC1993, ETC.
1:1 4.7pF
0.1μF 25Ω
10Ω 5Ω AIN–
Figure 5. DC-Coupled Input with Differential Amplifier
T1 = MA/COM ETC1-1-13 4.7pF
RESISTORS, CAPACITORS
2208 F04a
reference operation: Internal Reference, 1.25V external
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF
reference or 2.5V external reference. To use the internal
reference, tie the SENSE pin to VDD. To use an external
Figure 4a. Using a Transmission Line Balun Transformer.
Recommended for Input Frequencies from 100MHz to 250MHz
reference, simply apply either a 1.25V or 2.5V reference
voltage to the SENSE input pin. Both 1.25V and 2.5V applied
VCM to SENSE will result in a full scale range of 2.25VP-P (PGA
2.2μF
= 0). A 1.25V output, VCM is provided for a common mode
0.1μF bias for input drive circuitry. An external bypass capacitor is
5Ω AIN+
ANALOG
INPUT
LTC2208 required for the VCM output. This provides a high frequency
25Ω 0.1μF 2.2pF low impedance path to ground for internal and external
T1
1:1
circuitry. This is also the compensation capacitor for the
0.1μF 25Ω
5Ω AIN– reference; it will not be stable without this capacitor. The
2.2pF
minimum value required for stability is 2.2μF.
T1 = MA/COM ETC1-1-13 2208 F04b
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF RANGE
SELECT
Figure 4b. Using a Transmission Line Balun Transformer. AND GAIN
TIE TO VDD TO USE INTERNAL
CONTROL
Recommended for Input Frequencies from 250MHz to 500MHz INTERNAL 2.5V ADC
REFERENCE REFERENCE
OR INPUT FOR SENSE
Direct Coupled Circuits EXTERNAL 2.5V
REFERENCE PGA
OR INPUT FOR
Figure 5 demonstrates the use of a differential amplifier to EXTERNAL 1.25V
convert a single ended input signal into a differential input REFERENCE
2.5V
signal. The advantage of this method is that it provides BANDGAP
REFERENCE
low frequency input response; however, the limited gain
VCM
bandwidth of any op amp or closed-loop amplifier will de- BUFFER 1.25V
2.2μF
grade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifiers tend to have
high noise. As a result, the SNR will be degraded unless 2208 F06

the noise bandwidth is limited prior to the ADC input. Figure 6. Reference Circuit
2208fc

20
 LTC2208
APPLICATIONS INFORMATION
The internal programmable gain amplifier provides the In applications where jitter is critical (high input frequen-
internal reference voltage for the ADC. This amplifier has cies), take the following into consideration:
very stringent settling requirements and is not accessible 1. Differential drive should be used.
for external use.
2. Use as large an amplitude possible. If using trans-
The SENSE pin can be driven ±5% around the nominal 2.5V former coupling, use a higher turns ratio to increase the
or 1.25V external reference inputs. This adjustment range amplitude.
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the 3. If the ADC is clocked with a fixed frequency sinusoidal
SENSE pin should be tied to VDD as close to the converter signal, filter the encode signal to reduce wideband
as possible. If the sense pin is driven externally it should noise.
be bypassed to ground as close to the device as possible 4. Balance the capacitance and series resistance at both
with 1μF ceramic capacitor. encode inputs such that any coupled noise will appear
VCM at both inputs as common mode noise.
1.25V
2.2μF The encode inputs have a common mode range of 1.2V
LTC2208
to VDD. Each input may be driven from ground to VDD for
2 6 SENSE
3.3V LTC1461-2.5 single-ended drive.
1μF 4 2.2μF
VDD
LTC2208
2208 F07
TO INTERNAL
Figure 7. A 2.25V Range ADC with ADC CLOCK
DRIVERS
an External 2.5V Reference VDD 1.6V

PGA Pin 6k
+
ENC
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P; VDD 1.6V

PGA = 1 selects an input range of 1.5VP-P. The 2.25V input 6k

range has the best SNR; however, the distortion will be ENC–
higher for input frequencies above 100MHz. For applica-
tions with high input frequencies, the low input range will
have improved distortion; however, the SNR will be 1.8dB 2208 F08a

worse. See the typical performance curves section. Figure 8a. Equivalent Encode Input Circuit
Driving the Encode Inputs
The noise performance of the LTC2208 can depend on 0.1μF T1 ENC+ LTC2208
the encode signal quality as much as for the analog input.
50Ω
The encode inputs are intended to be driven differentially, 100Ω
8.2pF
primarily for noise immunity from common mode noise
0.1μF 50Ω
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point 0.1μF ENC–
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits. 2208 F08b

T1 = MA/COM ETC1-1-13
Any noise present on the encode signal will result in ad- RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter. Figure 8b. Transformer Driven Encode
2208fc

21
LTC2208
APPLICATIONS INFORMATION
ENC+ The lower limit of the LTC2208 sample rate is determined
VTHRESHOLD = 1.6V
by droop of the sample and hold circuits. The pipelined
1.6V ENC– LTC2208 architecture of this ADC relies on storing analog signals on
0.1μF small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
2208 F09
for the LTC2208 is 1Msps.
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
DIGITAL OUTPUTS
3.3V Digital Output Modes
3.3V
MC100LVELT22 130Ω 130Ω The LTC2208 can operate in four digital output modes:
ENC+
Q0
standard LVDS, low power LVDS, full rate CMOS, and
D0
demultiplexed CMOS. The LVDS pin selects the mode of
ENC– LTC2208
operation. This pin has a four level logic input, centered at
Q0
0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can
83Ω 83Ω
2208 F10 be used to set the 1/3VDD and 2/3VDD logic levels. Table 1
shows the logic states for the LVDS pin.
Figure 10. ENC Drive Using a CMOS to PECL Translator Table 1. LVDS Pin Function
LVDS DIGITAL OUTPUT MODE
Maximum and Minimum Encode Rates 0V(GND) Full-Rate CMOS
1/3VDD Demultiplexed CMOS
The maximum encode rate for the LTC2208 is 130Msps.
2/3VDD Low Power LVDS
For the ADC to operate properly the encode signal should
VDD LVDS
have a 50% (±5%) duty cycle. Each half cycle must have at
least 3.65ns for the ADC internal circuitry to have enough
Digital Output Buffers (CMOS Modes)
settling time for proper operation. Achieving a precise 50%
duty cycle is easy with differential sinusoidal drive using Figure 11 shows an equivalent circuit for a single output
a transformer or using symmetric differential logic such buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
as PECL or LVDS. When using a single-ended ENCODE buffer is powered by OVDD and OGND, isolated from the
signal asymmetric rise and fall times can result in duty ADC power and ground. The additional N-channel transistor
cycles that are far from 50%. in the output driver allows operation down to low voltages.
The internal resistor in series with the output makes the
An optional clock duty cycle stabilizer can be used if the
output appear as 50Ω to external circuitry and eliminates
input clock does not have a 50% duty cycle. This circuit
the need for external damping resistors.
uses the rising edge of ENC pin to sample the analog input.
The falling edge of ENC is ignored and an internal falling As with all high speed/high resolution converters, the
edge is generated by a phase-locked loop. The input clock digital output loading can affect the performance. The
duty cycle can vary from 30% to 70% and the clock duty digital outputs of the LTC2208 should drive a minimum
cycle stabilizer will maintain a constant 50% internal duty capacitive load to avoid possible interaction between the
cycle. If the clock is turned off for a long period of time, digital outputs and sensitive input circuitry. The output
the duty cycle stabilizer circuit will require one hundred should be buffered with a device such as a ALVCH16373
clock cycles for the PLL to lock onto the input clock. To CMOS latch. For full speed operation the capacitive load
use the clock duty cycle stabilizer, the MODE pin must be should be kept under 10pF. A resistor in series with the
connected to 1/3VDD or 2/3VDD using external resistors.
2208fc

22
 LTC2208
APPLICATIONS INFORMATION
output may be used but is not required since the ADC has resistor, even if the signal is not used (such as OF+/OF– or
a series resistor of 43Ω on chip. CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
Lower OVDD voltages will also help reduce interference
from the digital outputs. together. To minimize clock skew all LVDS PC board traces
should have about the same length.
LTC2208 In Low Power LVDS Mode 1.75mA is steered between
OVDD
0.5V
TO 3.6V
the differential outputs, resulting in ±175mV at the LVDS
VDD VDD
0.1μF receiver’s 100Ω termination resistor. The output com-
mon mode voltage is 1.20V, the same as standard LVDS
OVDD
Mode.
DATA PREDRIVER 43Ω TYPICAL
FROM
LATCH
LOGIC DATA Data Format
OUTPUT
The LTC2208 parallel digital output can be selected for
OGND
offset binary or 2’s complement format. The format is
selected with the MODE pin. This pin has a four level
2208 F11
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
Figure 11. Equivalent Circuit for a Digital Output Buffer external resistor divider can be user to set the 1/3VDD
and 2/3VDD logic levels. Table 2 shows the logic states
Digital Output Buffers (LVDS Modes) for the MODE pin.
Figure 12 shows an equivalent circuit for an LVDS output Table 2. MODE Pin Function
pair. A 3.5mA current is steered from OUT+ to OUT– or MODE OUTPUT FORMAT CLOCK DUTY
vice versa, which creates a ±350mV differential voltage CYCLE STABILIZER
across the 100Ω termination resistor at the LVDS receiver. 0(GND) Offset Binary Off
A feedback loop regulates the common mode output volt- 1/3VDD Offset Binary On
age to 1.20V. For proper operation each LVDS output pair 2/3VDD 2’s Complement On
must be terminated with an external 100Ω termination VDD 2’s Complement Off

LTC2208 OVDD
3.3V
3.5mA
0.1μF
VDD
VDD
OVDD

43Ω
DATA PREDRIVER 10k 10k
FROM LOGIC
LATCH OVDD LVDS
100Ω RECEIVER

43Ω

+
1.20V – OGND

2208 F12

Figure 12. Equivalent Output Buffer in LVDS Mode

2208fc

23
LTC2208
APPLICATIONS INFORMATION
Overflow Bit LSB and all other bits. The LSB, OF and CLKOUT output
An overflow output bit (OF) indicates when the converter are not affected. The output Randomizer function is active
is over-ranged or under-ranged. In CMOS mode, a logic when the RAND pin is high.
high on the OFA pin indicates an overflow or underflow on
the A data bus, while a logic high on the OFB pin indicates
an overflow on the B data bus. In LVDS mode, a differen- CLKOUT CLKOUT
tial logic high on OF+/OF– pins indicates an overflow or
underflow.
OF OF

Output Clock
D15
The ADC has a delayed version of the encode input avail- D15/D0
able as a digital output, CLKOUT. The CLKOUT pin can
be used to synchronize the converter data to the digital D14
D14/D0
system. This is necessary when using a sinusoidal en-
code. In both CMOS modes, A bus data will be updated •
•
as CLKOUTA falls and CLKOUTB rises. In demultiplexed •
D2
CMOS mode the B bus data will be updated as CLKOUTA D2/D0
falls and CLKOUTB rises.
In Full Rate CMOS Mode, only the A data bus is active; D1
D1/D0
data may be latched on the rising edge of CLKOUTA or
the falling edge of CLKOUTB. RAND = HIGH,
SCRAMBLE
RAND
ENABLED
In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both D0 D0
the A bus and the B bus may be latched on the rising edge
2208 F13
of CLKOUTA or the falling edge of CLKOUTB.
Figure 13. Functional Equivalent of Digital Output Randomizer
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes Output Driver Power
unavoidable. Interference from the digital outputs may be Separate output power and ground pins allow the output
from capacitive or inductive coupling or coupling through drivers to be isolated from the analog circuitry. The power
the ground plane. Even a tiny coupling factor can result in supply for the digital output buffers, OVDD, should be tied
discernible unwanted tones in the ADC output spectrum. to the same power supply as for the logic being driven.
By randomizing the digital output before it is transmitted For example, if the converter is driving a DSP powered
off chip, these unwanted tones can be randomized, trading by a 1.8V supply, then OVDD should be tied to that same
a slight increase in the noise floor for a large reduction in 1.8V supply. In CMOS mode OVDD can be powered with
unwanted tone amplitude. any logic voltage up to the 3.6V. OGND can be powered
The digital output is “Randomized” by applying an exclu- with any voltage from ground up to 1V and must be less
sive-OR logic operation between the LSB and all other data than OVDD. The logic outputs will swing between OGND
output bits. To decode, the reverse operation is applied; and OVDD. In LVDS Mode, OVDD should be connected to
that is, an exclusive-OR operation is applied between the a 3.3V supply and OGND should be connected to GND.

2208fc

24
 LTC2208
APPLICATIONS INFORMATION
PC BOARD Internal Dither
FPGA
CLKOUT The LTC2208 is a 16-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfec-
tions in the transfer function will result in unwanted tones.
OF
Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
D15/D0 mode can be enabled to randomize the input location on
D15 the ADC transfer curve, resulting in improved SFDR for
LTC2208
low signal levels.
D14/D0
D14 As shown in Figure 15, the output of the sample-and-hold
• amplifier is summed with the output of a dither DAC. The
• dither DAC is driven by a long sequence pseudo-random
D2/D0 • number generator; the random number fed to the dither
D2
DAC is also subtracted from the ADC result. If the dither
D1/D0 DAC is precisely calibrated to the ADC, very little of the
D1 dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
D0
DAC is calibrated to result in less than 0.5dB elevation in
D0
the noise floor of the ADC, as compared to the noise floor
with dither off.

2208 F14

Figure 14. Descrambling a Scrambled Digital Output

LTC2208
CLKOUT
OF
AIN+ D15
16-BIT •
ANALOG S/H DIGITAL OUTPUT
PIPELINED •
INPUT AMP SUMMATION DRIVERS
ADC CORE
AIN– •
D0

CLOCK/DUTY MULTIBIT DEEP

CYCLE PRECISION PSEUDO-RANDOM
CONTROL DAC NUMBER
GENERATOR

2208 F15

+ –
ENC ENC DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF

Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit

2208fc

25
LTC2208
APPLICATIONS INFORMATION
Grounding and Bypassing connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2208 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an The LTC2208 differential inputs should run parallel and
internal ground plane is recommended. The pinout of the close to each other. The input traces should be as short
LTC2208 has been optimized for a flowthrough layout so as possible to minimize capacitance and to minimize
that the interaction between inputs and digital outputs is noise pickup.
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated Heat Transfer
as much as possible. In particular, care should be taken Most of the heat generated by the LTC2208 is transferred
not to run any digital track alongside an analog signal from the die through the bottom-side exposed pad. For
track or underneath the ADC. good electrical and thermal performance, the exposed
High quality ceramic bypass capacitors should be used pad must be soldered to a large grounded pad on the PC
at the VDD, VCM, and OVDD pins. Bypass capacitors must board. It is critical that the exposed pad and all ground
be located as close to the pins as possible. The traces pins are connected to a ground plane of sufficient area
with as many vias as possible.

2208fc

26
 LTC2208
APPLICATIONS INFORMATION

Layer 1 Component Side Layer 2 GND Plane

2208fc

27
LTC2208
APPLICATIONS INFORMATION

Layer 3 GND Layer 4 GND

2208fc

28
 LTC2208
APPLICATIONS INFORMATION

Layer 5 GND Layer 6 Bottom Side

2208fc

29
30
3.3V
1 2
VCC J4

12
25
26
47
48
C26 3 4
VDD ON
0.1μF 5 6
GND OFF

VC1
VC2
VC3
VC4
VC5
C25
3
0.1μF EN12
22
LTC2208

C16 R37 R3 EN34

0.1μF 100Ω 27
DNP EN58
C18 R16 46
EN78
OPT 100Ω 13 MEC8-150-02-L-D-EDGE_CONNRE-DIM
EN J1E J1O
C19 R17
R9 OPT 100Ω 4 O1N 5 2 1
R45 I1N
10Ω 5 O1P 44 4 3
86.6Ω I1P
R28 R18 6 5
C6 10Ω 100Ω 6 O2N 43 8 7
J5 L1 T1 I2N
0.01μF 7 O2P 42 10 9
AIN 56nH MABA-007159- T2 I2P
R11 R19 12 11
000000 • • 33.2Ω 100Ω 8 U3 O3N 41 14 13
C8 I3N
9 FIN1108 O3P 40 16 15
4.7pF I3P

• •
R36 R44 R20 18 17
86.6Ω 86.6Ω R12 R27 100Ω 10 O4N 39 20 19
I4N
33.2Ω 10Ω 11 O4P 38 22 21
I4P
R10 R21 24 23
10Ω 100Ω 14 O5N 35 26 25
C8 C10 C7 I5N
15 O5P 34 28 27

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
8.2pF 8.2pF 0.01μF I5P
R22 30 29
100Ω 16 O6N 33 32 31
I6N

OF+
OF–

PGA
17 O6P 32 34 33

D15+
D15–
D14+
D14–
D13+
D13–
D12+
D12–

LVDS

RAND
MODE
1 48 I6P
SENSE D11+ R23 36 35

OVDD49
OGND50
R15 2 47 100Ω 18 O7N 31 38 37
GND2 D11– I7N
100Ω 19 O7P 30 40 39
3 46 I7P
VCM D10+ R30 42 41
C5 C12 C13 4 45 100Ω 20 O8N 29 44 43
GND D10– I8N
0.01μF 0.1μF 2.2μF 21 O8P 28 46 45
5 44 I8P
VDD5 D9+ 48 47
50 49

VE1
VE2
VE3
VE4
VE5
6 43
TP1 VDD6 D9– 52 51

1
2
EXT REF C17 7 42

23
36
37
R14 GND7 D8+ 54 53
2.2μF 1000Ω 8 41
AINP D8–
R5 9 U2 40
APPLICATIONS INFORMATION

J7 AINN LTC2208IUP CLKCOUT+ 3.3V

5.1Ω
ENCODE C2 10 39
T3 R13 GND10 CLKOUT–
CLOCK 0.01μF ETC1-1-13 100Ω 11 38
R2 +
GND11 D7

12
25
26
47
48
• • 49.9Ω 12 37
C4 ENCP D7– 56 55
13 36 58 57

VC1
VC2
VC3
VC4
VC5
8.2pF ENCN D8+
R1 3 60 59
49.9Ω R4 14 35 EN12
C3 GND14 D8– 22 62 61
5.1Ω EN34
C1 0.01μF 15 34 64 63
VDD15 D5+ 27
0.01μF 16 33 EN58 66 65
VDD16 D5– 46 68 67
VCC EN78
J3 13 70 69
EN
1 2 R31 72 71

VDD17
GND18
SHDN
DITH
D0–
D0+
D1–
D1+
D2–
D2+
D3–
D3+
D4–
D4+
OGND31
OVDD32
VCC DITHER 100Ω 4 45 74 73
3 4 5 I1N O1N 44
SHDN ON 76 75
I1P O1P

17
18
19
20
21
22
23
24
25
26
27
27
29
30
31
32
65
5 3.3V
6 R32 78 77
RUN OFF 100Ω 6 43 80 79
7 I2N O2N 42 R29
82 81
I2P O2P 4990Ω
R33 84 83
VCC 100Ω 8 41 86 85
I3N U4 O3N
TP5 9 40 88 87
3.3V I3P FIN1108 O3P
R6 1000Ω R34 90 89
100Ω 10 39 92 91
1 2 11 I4N O4N 38 94 93
TP2 J9 1 2 I4P O4P
3 4 R35 96 95
PWR AUX PWR J2 MODE 100Ω 14 35
5 98 97
GND CONNECTOR 6 3 4 R7 15 I5N O5N 34
VDD 100 99
1000Ω I5P O5P
R38
5 6 100Ω
GND 16 33
17 I6N O6N 32
I6P O6P
R39
R8 100Ω 18 31
19 I7N O7N 30
1000Ω I7P O7P
R40
100Ω 20 29
21 I8N O8N 28
I8P O8P
R24
VE1
VE2
VE3
VE4
VE5

100k
1
2
23
36
37

C20
0.1μF 3.3V C34 C27
C22 0.1μF 0.1μF
* VERSION TABLE
0.1μF C35
0.1μF R25
ASSEMBLY U2 BITS C8 C9-10 L1 R36, 44 R45 T2 R41 4990Ω
100Ω C36
R42 R43 U1
DC996B-A LTC2208IUP 16 4.7pF 8.2pF 56nH 86.6 86.6 MABAES0060 0.1μF
FERRITE BEAD FERRITE BEAD 8 24LC02ST
C28 6 R26
DC996B-B LTC2208IUP 16 1.8pF 3.9pF 18nH 43.2 182 WBC1-1LB U5 0.1μF VCC 6CL 4990Ω
C14 C24 C38 5
FIN1101K8X C29 6DA
DC996B-C LTC2208IUP-14 14 4.7pF 8.2pF 56nH 86.6 86.6 MABAES0060 1 8 4.7μF 4.7μF 4.7μF 7
RIN– RIN+ 0.1μF ARRAY WP
2 7 C30 EEPROM 3
DC996B-D LTC2208IUP-14 14 1.8pF 3.9pF 18nH 43.2 182 WBC1-1LB GND VCC A2
3 6 0.1μF 2
EN DOUT+ A1
4 5 C31 1
GND DOUT– 0.1μF GND A0
C32
0.1μF 4 2208 F16

C15
0.1μF

2208fc
 LTC2208
PACKAGE DESCRIPTION
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)

0.70 ±0.05

7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)

7.15 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

9 .00 ± 0.10 0.75 ± 0.05 R = 0.115

(4 SIDES) R = 0.10 TYP
TYP 63 64

0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5) 1
2

PIN 1
CHAMFER
C = 0.35

7.15 ± 0.10
7.50 REF
(4-SIDES)

7.15 ± 0.10

(UP64) QFN 0406 REV C

0.200 REF 0.25 ± 0.05
0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 BOTTOM VIEW—EXPOSED PAD
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE

2208fc

31
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2208
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
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LT1993 High Speed Differential Op Amp 600MHz BW, 75dBc Distortion at 70MHz
LTC2202 16-Bit, 10Msps ADC 150mW, 81.6dB SNR, 100dB SFDR
LTC2203 16-Bit, 25Msps ADC 230mW, 81.6dB SNR, 100dB SFDR
LTC2204 16-Bit, 40Msps ADC 470mW, 79dB SNR, 100dB SFDR
LTC2205 16-Bit, 65Msps ADC 530mW, 79dB SNR, 100dB SFDR
LTC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR
LTC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR
LTC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps ADC 910mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2249 14-Bit, 65Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps ADC 395mW, 72.4dB SNR, 5mm × 5mm QFN Package
LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm × 9mm QFN Package
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver with 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
Digitally Controlled Gain
LT5522 600MHz to 2.7GHz High Linearity Downconverting 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB, 50Ω Single-Ended RF
Mixer and LO Ports

2208fc

LT 0909 REV C • PRINTED IN USA

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