19-2698; Rev 3; 2/05

2-Wire-Interfaced 8-Bit I/O Port Expander

with Reset
General Description Features

MAX7310
The MAX7310 provides 8-bit parallel input/output port ♦ 400kHz 2-Wire Interface
expansion for SMBus™-compatible and I2C™-compati-
ble applications. The MAX7310 consists of an input port ♦ 2.3V to 5.5V Operation
register, an output port register, a polarity inversion reg- ♦ Low Standby Current (1.7µA typ)
ister, a configuration register, a bus timeout register,
and an SMBus/I2C-compatible serial interface. The sys- ♦ Bus Timeout for Lock-Up-Free Operation
tem master can invert the MAX7310 input data by writ- ♦ 56 Slave ID Addresses
ing to the active-high polarity inversion register. The
system master can enable or disable bus timeout by ♦ Polarity Inversion
writing to the bus timeout register. ♦ Eight I/O Pins that Default to Inputs on Power-Up
Any of the eight I/O ports may be configured as input or
♦ 5V Tolerant Open-Drain Output on I/O0
output. An active-low reset input sets the eight I/Os as
inputs. Three address select pins configure one of 56 ♦ 4mm x 4mm, 0.8mm Thin QFN Package
slave ID addresses.
♦ -40°C to +125°C Operation
The MAX7310 is available in 16-pin thin QFN, TSSOP,
and QSOP packages and is specified over the -40°C to
+125°C automotive temperature range.
Applications
Servers Ordering Information
RAID Systems PIN- PKG
Industrial Control PART TEMP RANGE
PACKAGE CODE
Medical Equipment
MAX7310AUE -40°C to +125°C 16 TSSOP —
Instrumentation, Test Measurement
MAX7310AEE -40°C to +125°C 16 QSOP —
SMBus is a trademark of Intel Corp. MAX7310ATE -40°C to +125°C 16 Thin QFN T1644-4

Purchase of I2C components of Maxim Integrated Products, Inc.,

or one of its sublicensed Associated Companies, conveys a
license under the Philips I2C Patent Rights to use these compo-
nents in an I2C system, provided that the system conforms to the
I2C Standard Specification as defined by Philips.

Pin Configurations
I/O4
I/O7

I/O6

I/O5

TOP VIEW
12 11 10 9
SCL 1 16 V+

SDA 2 15 RESET RESET I/O3

13 8
AD0 3 14 I/O7
V+ 14 7 I/O2
AD1 4 13 I/O6
MAX7310 MAX7310ATE
AD2 5 12 I/O5 SCL 15 6 GND
I/O0 6 11 I/O4
SDA 16 5 I/O1
I/O1 7 10 I/O3

GND 8 9 I/O2
1 2 3 4
AD0

AD1

AD2

I/O0

TSSOP/QSOP

THIN QFN

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
ABSOLUTE MAXIMUM RATINGS
MAX7310

V+ to GND ................................................................-0.3V to +6V Continuous Power Dissipation (TA = +70°C)

I/O1–I/O7 as an Input .......................(VSS - 0.3V) to (VDD + 0.3V) 16-Pin TSSOP (derate 5.7mW/°C above +70°C) .........457mW
I/O0 as an Input..............................................(VSS - 0.3V) to +6V 16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW
SCL, SDA, AD0, AD1, AD2, RESET ...............(VSS - 0.3V) to +6V 16-Pin Thin QFN (derate 16.9mW/°C above +70°C) ...1349mW
DC Current on I/O0 ........................................................ +400µA Operating Temperature Range .........................-40°C to +125°C
DC Current on I/O1 to I/O7 ............................................. ±50mA Junction Temperature ......................................................+150°C
Maximum GND and V+ Current........................................180mA Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage V+ 2.3 5.5 V
All outputs floating, V+ = 2.3V 19 30
Supply Current I+ all inputs at V+ or GND, V+ = 3.3V 29 40 µA
fSCL = 400kHz V+ = 5.5V 65 80
All outputs floating, V+ = 2.3V 1.5 3.4
Standby Current all inputs at V+ or GND, V+ = 3.3V 1.7 3.9 µA
fSCL = 0 V+ = 5.5V 2.1 5
Power-On Reset Voltage 1.6 2.1 V
SCL, SDA
Input Voltage Low VIL 0.8 V
Input Voltage High VIH 2 V
Low-Level Output Voltage VOIL ISINK = 6mA 0.4 V
Leakage Current IL -1 +1 µA
Input Capacitance CI 10 pF
I/Os
Input Voltage Low VIL 0.8 V
Input Voltage High VIH 2 V
Input Leakage Current IL All inputs at V+ or GND -1 +1 µA
V+ = 2.3V, VOL = 0.5V 8 14
Low-Level Output Current IOL V+ = 3.3V, VOL = 0.5V 12.5 22 mA
V+ = 5.5V, VOL = 0.5V 19 30
V+ = 3.3V, VOH = 2.4V 6.5 11
High Output Current for I/O1–I/O7 IOH mA
V+ = 5.5V, VOH = 4.5V 12.5 18
AD0, AD1, AD2, AND RESET
Input Voltage Low 0.8 V
Input Voltage High 2 V

2 _______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
DC ELECTRICAL CHARACTERISTICS (continued)

MAX7310
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = 3.3V, TA = +25°C.)
(Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Leakage Current -1 +1 µA
Input Capacitance 10 pF

AC ELECTRICAL CHARACTERISTICS
(V+ = 2.3V to 5.5V, GND = 0, RESET = V+, TA = -40°C to +125°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 2) 400 kHz
BUS Timeout tTIMEOUT 30 60 ms
Bus Free Time Between STOP
tBUF Figure 2 1.3 µs
and START Condition
Hold Time (Repeated) START
tHD, STA Figure 2 0.6 µs
Condition
Repeated START Condition Setup
tSU, STA Figure 2 0.6 µs
Time
STOP Condition Setup Time tSU, STO Figure 2 0.6 µs
Data Hold Time tHD, DAT Figure 2 (Note 3) 0.9 µs
Data Setup Time tSU, DAT Figure 2 0.1 µs
SCL Low Period tLOW Figure 2 1.3 µs
SCL High Period tHIGH Figure 2 0.7 µs
SCL/SDA Fall Time (Transmitting) tF Figure 2 (Note 4) 250 ns
Pulse Width of Spike Supressed tSP (Note 5) 50 ns
PORT TIMING
Output Data Valid tPV Figure 9 1 µs
Input Data Setup Time tPS Figure 10 29 µs
Input Data Hold Time tPH Figure 10 0 µs
RESET
Reset Pulse Width 100 ns

Note 1: All parameters are 100% production tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Minimum SCL clock frequency is limited by the MAX7310 bus timeout feature, which resets the serial bus interface if either
SDA or SCL is held low for a 30ms minimum.
Note 3: A master device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIL of the SCL signal) in
order to bridge the undefined region of SCL’s falling edge.
Note 4: tF measured between 90% to 10% of V+.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.

_______________________________________________________________________________________ 3
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
MAX7310

Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

SUPPLY CURRENT STANDBY SUPPLY CURRENT SUPPLY CURRENT

vs. TEMPERATURE vs. TEMPERATURE vs. SUPPLY VOLTAGE
32 2.50 70
MAX7310 toc01

MAX7310 toc02

MAX7310 toc03
V+ = 3.3V, fSCL = 440kHz, V+ = 3.3V, fSCL = 0, fSCL = 440kHz,
NO LOAD ON I/O0–I/O7 NO LOAD ON I/O0–I/O7 NO LOAD ON I/O0–I/O7
31 2.25 60
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)

SUPPLY CURRENT (µA)

30 2.00 50

29 1.75 40

28 1.50 30

27 1.25 20

26 1.00 10
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TEMPERATURE (°C) TEMPERATURE (°C) SUPPLY VOLTAGE (V)

I/O0–I/O7 OUTPUT SINK CURRENT I/O0–I/O7 OUTPUT SINK CURRENT I/O1–I/O7 OUTPUT SOURCE CURRENT
vs. TEMPERATURE vs. SUPPLY VOLTAGE vs. TEMPERATURE
30 35 9
MAX7310 toc04

MAX7310 toc05

MAX7310 toc06
V+ = 2.3V,
VOH = 1.4V
25 30
8
VCC = 3.3V
SOURCE CURRENT (mA)

25
SINK CURRENT (mA)

SINK CURRENT (mA)

20
7
20
15 VCC = 2.3V
15
6
10
10
5
5 5
VOL = 0.5V VOL = 0.5V
0 0 4
-40 -25 -10 5 20 35 50 65 80 95 110 125 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C) SUPPLY VOLTAGE (V) TEMPERATURE (°C)

4 _______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Pin Description

MAX7310
PIN
TSSOP/ THIN
NAME FUNCTION
QSOP QFN

1 15 SCL Serial Clock Line

2 16 SDA Serial Data Line

3 1 AD0 Address Input 0

4 2 AD1 Address Input 1

5 3 AD2 Address Input 2

6 4 I/O0 Input/Output Port 0 (Open Drain)

7 5 I/O1 Input/Output Port 1

8 6 GND Supply Ground

9–14 7–12 I/O2–I/O7 Input/Output Port 2—Input/Output Port 7

External Reset (Active Low). Pull RESET low to configure I/O pins as inputs. Set RESET
15 13 RESET
high for normal operation.
16 14 V+ Supply Voltage. Bypass with a 0.047µF capacitor to GND.
Exposed
— PAD Exposed Pad on Package Underside. Connect to GND.
pad

AD0
AD1 MAX7310
AD2
I/O0
I/O1
SCL INPUT/
SMBus I/O2
INPUT 8 BIT OUTPUT
SDA CONTROL I/O3
FILTER PORTS
I/O4
I/O5
WRITE PULSE I/O6
N READ PULSE I/O7

V+
POWER-ON
RESET RESET

GND

Figure 1. MAX7310 Block Diagram

Detailed Description port register, a polarity inversion register, a configura-

tion register, and a bus timeout register. An active-low
The MAX7310 general-purpose input/output (GPIO)
reset input sets the eight I/O lines as inputs. Three
peripheral provides up to eight I/O ports, controlled
slave ID address select pins (AD0, AD1, and AD2)
through an I 2 C-compatible serial interface. The
choose one of 56 slave ID addresses (Figure 1).
MAX7310 consists of an input port register, an output

_______________________________________________________________________________________________________ 5
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Table 1 is the register address table. Tables 2–6 list SCL is high. The bus is then free for another transmis-
MAX7310

register 0 through register 4 information. sion (Figure 3).

Serial Interface Bit Transfer
One data bit is transferred during each clock pulse.
Serial Addressing The data on SDA must remain stable while SCL is high
The MAX7310 operates as a slave that sends and (Figure 4).
receives data through a 2-wire interface. The interface
uses a serial data line (SDA) and a serial clock line Acknowledge
(SCL) to achieve bidirectional communication between The acknowledge bit is a clocked 9th bit, which the
master(s) and slave(s). A master, typically a microcon- recipient uses as a handshake receipt of each byte of
troller, initiates all data transfers to and from the data (Figure 5). Thus, each byte transferred effectively
MAX7310, and generates the SCL clock that synchro- requires 9 bits. The master generates the 9th clock
nizes the data transfer (Figure 2). pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is sta-
Each transmission consists of a start condition sent by
ble low during the high period of the clock pulse. When
a master, followed by the MAX7310 7-bit slave address
the master is transmitting to the MAX7310, the
plus an R/W bit, a register address byte, one or more
MAX7310 generates the acknowledge bit since the
data bytes, and finally a stop condition (Figure 3).
MAX7310 is the recipient. When the MAX7310 is trans-
Start and Stop Conditions mitting to the master, the master generates the
Both SCL and SDA remain high when the interface is acknowledge bit.
not busy. A master signals the beginning of a transmis-
sion with a start (S) condition by transitioning SDA from
Slave Address
The MAX7310 has a 7-bit-long slave address (Figure
high to low while SCL is high. When the master has fin-
6). The 8th bit following the 7-bit slave address is the
ished communicating with the slave, it issues a stop (P)
R/W bit. Set this bit low for a write command and high
condition by transitioning SDA from low to high while
for a read command.

SDA

tBUF
tSU, DAT tSU, STA
tHD, STA
tLOW tHD, DAT tSU, STO
SCL

tHIGH
tHD, STA
tR tF

START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION

Figure 2. 2-Wire Serial Interface Timing Diagrams

SDA

SCL S P
START STOP
CONDITION CONDITION

Figure 3. Start and Stop Conditions

6 _______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset

MAX7310
SDA

SCL
DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED

Figure 4. Bit Transfer

START CONDITION CLOCK PULSE FOR ACKNOWLEDGMENT

SCL

1 2 8 9

SDA
BY TRANSMITTER

S
SDA
BY RECEIVER

Figure 5. Acknowledge

FIXED PROGRAMMABLE

SDA 0 A5 A4 A3 A2 A1 A0 R/W ACK

MSB LSB

SCL

Figure 6. Slave Address

The first bits (MSBs) of the MAX7310 slave address are ister address byte acts as a pointer to determine which
always zero. Slave address bits AD2, AD1, and AD0 register is written or read.
choose 1 of 56 slave ID addresses (Table 7). The input port register is a read-only port. It reflects the
Registers incoming logic levels of the I/O ports, regardless of
The register address byte is the first byte to follow the whether the pin is defined as an input or an output by
address byte during a read/write transmission. The reg- the configuration register. Writes to the input port regis-
ter are ignored.

_______________________________________________________________________________________ 7
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
The polarity inversion register enables polarity inversion
MAX7310

Table 1. Register Address

of ports defined as inputs by the configuration register.
REGISTER Set the bit in the polarity inversion register (write with a
ADDRESS FUNCTION PROTOCOL 1) to invert the corresponding port pin’s polarity. Clear
(hex) the bit in the polarity inversion register (write with a
0x00 Input port register Read byte. zero) to retain the corresponding port pin’s original
0x01 Output port register Read/write byte.
polarity.
The configuration register configures the directions of
Polarity inversion
0x02
register
Read/write byte. the ports. Set the bit in the configuration register to
enable the corresponding port pin as an input with a
0x03
Configuration
Read/write byte.
high-impedance output driver. Clear the bit in the con-
register figuration register to enable the corresponding port pin
0x04 Timeout register Read/write byte. as an output.
Set bit T0 to enable the bus timeout function and low to
Factory reserved.
0xFF Reserved register Do not write to this
disable the bus timeout function. Enabling the timeout
register. feature resets the serial bus interface when SCL stops
either high or low during a read or write access to the
MAX7310. If either SCL or SDA is low for more than
Table 2. Register 0—Input Port Register 30ms min and 60ms max after the start of a valid serial
transfer, the interface resets itself. Resetting the serial
BIT I7 I6 I5 I4 I3 I2 I1 I0 bus interface sets up SDA as an input. The MAX7310
then waits for another start condition.
The output port register sets the outgoing logic levels of Standby
the I/O ports, defined as outputs by the configuration The MAX7310 goes into standby when all pins are set
register. Reads from the output port register reflect the to V+ or GND. Standby supply current is typically
value that is in the flip-flop controlling the output selec- 1.7µA.
tion, not the actual I/O value, which may differ if the out-
put is overloaded.

Table 3. Register 1—Output Port Register

BIT O7 O6 O5 O4 O3 O2 O1 O0
Default 0 0 0 0 0 0 0 0

Table 4. Register 2—Polarity Inversion Register

BIT I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Default 1 1 1 1 0 0 0 0

Table 5. Register 3—Configuration Register

BIT I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Default 1 1 1 1 1 1 1 1

Table 6. Register 4—Timeout Register

BIT T7 T6 T5 T4 T3 T2 T1 T0
Default x x x x x x x 1

8 _______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset

MAX7310
Table 7. MAX7310 Address Map
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0
GND SCL GND 0 0 0 1 0 0 0
GND SCL V+ 0 0 0 1 0 0 1
GND SDA GND 0 0 0 1 0 1 0
GND SDA V+ 0 0 0 1 0 1 1
V+ SCL GND 0 0 0 1 1 0 0
V+ SCL V+ 0 0 0 1 1 0 1
V+ SDA GND 0 0 0 1 1 1 0
V+ SDA V+ 0 0 0 1 1 1 1
GND GND SCL 0 0 1 0 0 0 0
GND GND SDA 0 0 1 0 0 0 1
GND V+ SCL 0 0 1 0 0 1 0
GND V+ SDA 0 0 1 0 0 1 1
V+ GND SCL 0 0 1 0 1 0 0
V+ GND SDA 0 0 1 0 1 0 1
V+ V+ SCL 0 0 1 0 1 1 0
V+ V+ SDA 0 0 1 0 1 1 1
GND GND GND 0 0 1 1 0 0 0
GND GND V+ 0 0 1 1 0 0 1
GND V+ GND 0 0 1 1 0 1 0
GND V+ V+ 0 0 1 1 0 1 1
V+ GND GND 0 0 1 1 1 0 0
V+ GND V+ 0 0 1 1 1 0 1
V+ V+ GND 0 0 1 1 1 1 0
V+ V+ V+ 0 0 1 1 1 1 1
SCL SCL SCL 0 1 0 0 0 0 0
SCL SCL SDA 0 1 0 0 0 0 1
SCL SDA SCL 0 1 0 0 0 1 0
SCL SDA SDA 0 1 0 0 0 1 1
SDA SCL SCL 0 1 0 0 1 0 0
SDA SCL SDA 0 1 0 0 1 0 1
SDA SDA SCL 0 1 0 0 1 1 0
SDA SDA SDA 0 1 0 0 1 1 1
SCL SCL GND 0 1 0 1 0 0 0
SCL SCL V+ 0 1 0 1 0 0 1
SCL SDA GND 0 1 0 1 0 1 0
SCL SDA V+ 0 1 0 1 0 1 1
SDA SCL GND 0 1 0 1 1 0 0
SDA SCL V+ 0 1 0 1 1 0 1
SDA SDA GND 0 1 0 1 1 1 0
SDA SDA V+ 0 1 0 1 1 1 1

_______________________________________________________________________________________ 9
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
MAX7310

Table 7. MAX7310 Address Map (continued)

AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0
SCL GND SCL 0 1 1 0 0 0 0
SCL GND SDA 0 1 1 0 0 0 1
SCL V+ SCL 0 1 1 0 0 1 0
SCL V+ SDA 0 1 1 0 0 1 1
SDA GND SCL 0 1 1 0 1 0 0
SDA GND SDA 0 1 1 0 1 0 1
SDA V+ SCL 0 1 1 0 1 1 0
SDA V+ SDA 0 1 1 0 1 1 1
SCL GND GND 0 1 1 1 0 0 0
SCL GND V+ 0 1 1 1 0 0 1
SCL V+ GND 0 1 1 1 0 1 0
SCL V+ V+ 0 1 1 1 0 1 1
SDA GND GND 0 1 1 1 1 0 0
SDA GND V+ 0 1 1 1 1 0 1
SDA V+ GND 0 1 1 1 1 1 0
SDA V+ V+ 0 1 1 1 1 1 1

Applications Information Chip Information

Power-Supply Consideration TRANSISTOR COUNT: 10,256
The MAX7310 operates from a supply voltage of 2.3V to PROCESS: BiCMOS
5.5V. Bypass the power supply to GND with a 0.047µF
capacitor as close to the device as possible. For the
QFN version, connect the underside exposed pad to
GND.

10 ______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset

MAX7310
DATA FROM
SHIFT REGISTER
CONFIGURATION
REGISTER
DATA FROM D Q
SHIFT REGISTER OUTPUT PORT
FF REGISTER DATA
D Q
WRITE CK Q
CONFIGURATION
PULSE FF I/O0

WRITE PULSE CK Q ESD-PROTECTION DIODE

OUTPUT
PORT GND
REGISTER
INPUT
PORT
REGISTER
D Q INPUT PORT
REGISTER DATA
FF

CK Q
READ PULSE

DATA FROM D Q POLARITY

SHIFT REGISTER REGISTER DATA
FF

WRITE POLARITY CK Q
PULSE
POLARITY
INVERSION
REGISTER

Figure 7. Simplified Schematic of I/O0

______________________________________________________________________________________ 11
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
MAX7310

DATA FROM OUTPUT PORT

SHIFT REGISTER REGISTER DATA
CONFIGURATION
REGISTER V+
DATA FROM D Q
SHIFT REGISTER
FF ESD-PROTECTION DIODE
D Q
WRITE CK Q
CONFIGURATION
PULSE FF I/O1 TO I/O7

WRITE PULSE CK Q
ESD-PROTECTION DIODE
OUTPUT
PORT
INPUT
REGISTER GND
PORT
REGISTER
D Q INPUT PORT
REGISTER DATA
FF

CK Q
READ PULSE

DATA FROM D Q POLARITY

SHIFT REGISTER REGISTER DATA
FF

WRITE POLARITY CK Q
PULSE
POLARITY
INVERSION
REGISTER

Figure 8. Simplified Schematic of I/O1–I/O7

12 ______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset

MAX7310
SCL 1 2 3 4 5 6 7 8 9

SLAVE ADDRESS COMMAND BYTE DATA TO PORT

SDA S 0 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A DATA 1 A P

START CONDITION R/W ACKNOWLEDGE ACKNOWLEDGE ACKNOWLEDGE

FROM SLAVE FROM SLAVE FROM SLAVE
WRITE TO
PORT

DATA OUT
DATA 1 VALID
FROM PORT
tPV

Figure 9. Write to Output Port Register Through Write-Byte Protocol

SLAVE ADDRESS DATA FROM PORT DATA FROM PORT

SDA S1 0 A5 A4 A3 A2 A1 A0 1 A DATA 1 A DATA 4 NA P

START CONDITION R/W ACKNOWLEDGE ACKNOWLEDGE NO ACKNOWLEDGE STOP

FROM SLAVE FROM MASTER FROM MASTER CONDITION
WRITE FROM
PORT

DATA INTO
DATA 2 DATA 3 DATA 4
PORT
tPH tPS

NOTE 1: THIS FIGURE ASSUMES THE COMMAND HAS PREVIOUSLY BEEN PROGRAMMED WITH 0x00.
NOTE 2: TRANSFER OF DATA CAN BE STOPPED AT ANY MOMENT BY A STOP CONDITION. WHEN THIS OCCURS,
DATA PRESENT AT THE LAST ACKNOWLEDGED PHASE IS VALID (OUTPUT MODE). INPUT DATA IS LOST.

Figure 10. Read Input Port Register Through Receive-Byte Protocol

______________________________________________________________________________________ 13
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Package Information
MAX7310

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

24L QFN THIN.EPS

PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
1
21-0139 C 2

PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
2
21-0139 C 2

14 ______________________________________________________________________________________
 2-Wire-Interfaced 8-Bit I/O Port Expander
with Reset
Package Information (continued)

MAX7310
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)

TSSOP4.40mm.EPS
QSOP.EPS

PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH

1
21-0055 E 1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15

© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.