Student Copy. For personal studies only. Do not distribute.

11/1/2023

Tentative Course Schedule

• Week 0x1 ‐ Introduction to Course
•
MICROPROCESSORS •
•
Week 0x2 ‐ Architecture
Week 0x3 ‐ Assembly Language Introduction
Week 0x4 ‐ Assembly Language Usage, Memory and Faults
LECTURE 3: •
•
Week 0x5 ‐ Embedded C, Toolchain and Debugging
Week 0x6 ‐ Interrupts
ARM ASSEMBLY LANGUAGE • Week 0x7 ‐ Timers
• Week 0x8 ‐ Modulation
FALL 2023 • Week 0x9 ‐ Serial Communications I
Dr. Ihsan Cicek • Week 0xA ‐ Serial Communications II
• Week 0xB ‐ Analog Interfacing
• Week 0xC ‐ Memory and DMA
• Week 0xD ‐ RTOS
• Week 0xE ‐ Wireless Communications
• Week 0xF – FINAL BREAK

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Review: ARM Processor Families Review: Complexity based ISA Classification

There are three branches in ARM Cortex family cores:
● Complex instruction set computers (CISC)
● Cortex‐A : Application processors. Designed as fully functional
computers capable of running complex operating systems.
○ Uses single complex instruction that can perform many
operations
Commonly used in mobile phones, tablets, and laptops such as
Raspberry PI, Android phones, iPhones, iPads, ... usually requiring multiple cycles
● Cortex‐R : Real‐time processors. Designed to be fast reacting to ○ Usually supports varying instruction length
events. Have low interrupt latency and more deterministic in tight ○ More complex hardware, simplified compiler
situations. Often used in critical systems where data interpretation is
● Reduced instruction set computers (RISC)
essential such as medical devices, car systems, basebands and
low‐level device controllers, such as hard drive controllers. ○ Uses simplified instructions that can use many
● Cortex‐M : Microcontroller series. Designed to be ultra‐low‐power instructions to perform
and small form‐factor. Runs at a way slower clock speed then A and an operation usually completing one instruction per cycle
R series. They are used in robotic systems and small consumer ○ More simplified hardware, complex compiler to
electronics. transform code

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Review: Complexity based ISA Classification Review: Memory Interface‐based Classification

There are two widely used memory interface
architectures:
von Neumann (Princeton)‐ uses a common bus for
both data and code
Harvard ‐ uses separate buses for data and code

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Review: Operation of The Microprocessor Review: Register – Register Architecture

Where do operands come from and results go to? ● Also called load‐store
architecture
● Register‐Register architecture
operands need to be in registers
(or immediates)
● Special instructions are used to get
and send data from / to memory.
(LDR, STR)
● Common in RISC architectures.
● 2 or 3 explicitly named operands
are allowed. (ADD R1, R2, R3)
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Review: ARM Cortex M0+ 2‐stage pipeline Review: ARM M0+ Regular & Special Registers
In Cortex‐M0+, there are 16x 32‐bit registers (13 general
and 3 special use)
○ R0 ‐ R15 with R0‐R12
being general purpose
registers.
○ due to size, mostly only
low registers can be used
with 16‐bit Thumb code.
○ data needs to be loaded
from memory to
registers to be
processed (load/store)

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Review: ARM Cortex M0+ Special Use Registers Review: ARM Cortex M0+ Special Registers
R13 ‐ Stack Pointer (SP) ‐ points to the top of the stack
‐ POP and PUSH instructions are used to access memory.
‐ Banked ‐ Main (MSP) and Process Stack Pointer (PSP). Can be
changed, but only one of them is visible
‐ Special register access instructions MRS and MSR is used to
change between them.
‐ Access is 32‐bits so lowest 2 bits are always 0.
R14 ‐ Link Register (LR) ‐ keeps the return address of a subroutine
or function call
‐ Lowest bit is usually set to 1 to indicate Thumb state. Otherwise
it can imply an attempt to switch the processor to ARM state ‐
which is not supported ‐ thus can cause a fault.
R15 ‐ Program Counter (PC) ‐ points to the next instruction in line
‐ Lowest bit is usually set to 1 to indicate Thumb state. Otherwise
it can imply an attempt to switch the processor to ARM state ‐
which is not supported ‐ thus can cause a fault.
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Review: ARM Cortex M0+ Memory System Review: Stack Memory Operation
• Cortex‐M processors have 4 GB of memory address space. ● Stack memory is a memory usage mechanism that allows the
• Memory space is architecturally defined into a number of regions system memory to be used as temporary data storage that behaves
as a first‐in‐last‐out (FILO) buffer.
• As a result, all the Cortex‐M devices have the same programming
model for interrupt control and debug. ● Content can be added with PUSH instruction and can be acquired
using POP instruction
● Usually located at the top of SRAM, and grows downwards ‐
meaning if data is added it gets filled toward lower addresses (full‐
descending)
● Stack Pointer shows the top of the stack

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Review: Nested Vectored Interrupt Controller Review: Vector Table

● Used for prioritizing the interrupt requests and ● The beginning of the program image has the vector table
handling other exceptions which contains the starting address of exceptions.
● The size of the vector table depends on the number of
interrupts implemented.
● The interrupt management function is controlled ● First two addresses are important for reset operation. The
by registers in the NVIC located within the next two are important for faulty recovery.

System Control Space (SCS)

● NVIC supports:
○ Flexible interrupt management
○ Nested interrupt support
○ Vectored exception entry
○ Interrupt masking
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Review: Reset Sequence Review: Software Design for Microprocessors

● We have already seen what happens after reset in • Software Program Flows – Polling (Super‐Loop)
terms of software routines. ● Uses one big loop, and
● First address in the vector table indicates the stack completes tasks in order
pointer value. (SP is set)
● As tasks get bulkier or
● Second address in the vector table is the Reset
Handler. (PC is set) tasks increase in number,
● Then PC makes the jump to the pointing address. the execution frequency
of tasks decreases

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Review: Inside A Program Image Review: Programming Microcontrollers

When we compile code for the target platform, there A typical reset circuit
are different components:
● vector table ‐ contains the starting
address of each exception and interrupt
● reset handler ‐ some software and hardware
initialization routines, clock initialization
● startup code ‐ initialization of data and calling of
main() function.
● application code ‐ your code
● runtime library functions ‐ any functions that you
didn't implement
● other data ‐ other global and static variables

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Review: Typical Program Generation Flow Review: Programming and Debugging

● After generating the binary (elf / bin) we can
program the board using a debugger (or
bootloader if present)
○ Usually are more expensive and has debugging
capabilities.
● Program can be debugged using an in‐circuit
debugger.

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Instruction Set Thumb instruction set for Cortex‐M0+

● Processors carry out operations by executing sequences of
instructions for
○ web browsing, video playback, text editing, etc.

● Each instruction defines a simple operation, and processors

require a minimum of
data processing ‐ arithmetic and logic operations,
memory access ‐ read and write operations,
program flow control ‐ branches, function calls ● Thumb is designed for having good code density.
types of instructions.
● Very limited set of instructions, not intended for
● The instruction set supported by the Cortex‐M Processors is
high performance computing.
called Thumb, and Cortex‐M0+ supports only a subset of ● Sometimes implemented with ARM instruction set
them (56). Most of them are 16‐bits and a couple of them are
32‐bits. in processors for both performance / code density.
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Assembly Syntax Labels

Based on different tools and assemblers, syntax will label:
look different. We will use GNU assembler syntax mnemonic operand1, operand2, ... ; comments

For armcc assembler ● label is used as a reference to an address or location

label
mnemonic operand1, operand2, ... ; comments ● can be used to get the instruction address to be
used as branch target
For GNU assembler
● can also be used as a reference point for arrays
label:
mnemonic operand1, operand2, ... ; comments ● will get removed after assembler
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Mnemonic and operands Definitions

● Usually instruction, destination, sources. ● definitions can be made with .equ keyword
● Number of operands depend on the instruction ● and later can be used with instructions
● Immediate data usually prefixed with # ● <= 8‐bit ones can be used with MOV
MOVS R0, #0x12 /* Set R0 to 18 */ ● > 8‐bit ones needs to be used with LDR, which
MOVS R1, #'A' // Set R1 to ASCII A gets converter to PC‐relative addressing.
MOVS R2, #22 @ Set R2 to 22 .equ NVIC_IRQ_SETEN, 0xE000E100
● Multi line comments can be made with /* */ .equ NVIC_IRQ0_ENABLE, 0x1
pairs LDR R0,=NVIC_IRQ_SETEN /* Put 0xE000E100 in R0 */
MOVS R1, #NVIC_IRQ0_ENABLE /* Put immediate data (0x1)
● Single line comments can be made with // or @ into register R1 */
symbols.
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Inserting data Suffixes

Different directives for inserting data with different sizes ● Some instructions can follow suffixes as shown
below.
● Most data processing instructions will update APSR
flags.
MOV R0, R1 /* Move R1 into R0 */
MOVS R0, R1 /* Move R1 into R0, update NZ flags */
● Other group can be combined with branch
operation to alter program flow.

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Unified Assembler Language (UAL) Instructions: Moving data within Processor

● With the ARM, Thumb, and Thumb‐2 technology, MOV <Rd>, <Rm> /* Rd = Rm. Both can be high or low
registers */
Unified Assembler Language (UAL) syntax is
MOVS <Rd>, <Rm> /* Rd = Rm, update flags (Z, N).
developed to have a consistent syntax across all Both low registers */
codes. ADDS <Rd>, <Rm>, #0 /* Rd = Rm, update flags (Z, N,
● .syntax unified directive in GNU assembler. C). Both low registers */
ADDS R0, R0, R1 /* R0 = R0 + R1, update APSR */ MOVS <Rd>, #imm8 /* Rd = imm8, update flags. (Z,
N). Immediate data range 0 to +255. low register */
in most cases second R0 can be omitted if tools
allow it. Note: If we want to load immediate data that is more
ADDS R0, R1 than 8‐bits, we first need to store the data in memory
space, then use memory access instructions.

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Exercise Exercise
Q1. R1 holds 0x13 and R2 holds 0x24 Swap them. Q1. R1 holds 0x13 and R2 holds 0x24 Swap them.
MOV R3, R1 /* R3 = 0x13 */
Q2. Write 0x24 into R9. MOV R1, R2 /* R1 = 0x24 */
MOV R2, R3 /* R2 = 0x13 */

Q2. Write 0x24 into R9.

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Exercise Instructions: Special Register Access

Q1. R1 holds 0x13 and R2 holds 0x24 Swap them.
Special registers require special instructions to access.
MOV R3, R1 /* R3 = 0x13 */
MOV R1, R2 /* R1 = 0x24 */ MRS <Rd>, <SpecialReg>/*Read special register into Rd*/
MOV R2, R3 /* R2 = 0x13 */
MSR <SpecialReg>, <Rd>/*Move Rd into special registr*/
Q2. Write 0x24 into R9.
Thumb‐ISA can only use the first eight (R0‐R7) registers and the R13, R14,
R15 registers.
MSR is used to write to CONTROL Regs, but we need to write pattern to a
low reg first (no direct access to R9)
MOV R1, #0x24
MOV R9, R1

Note: In Thumb instruction set, it is very tricky to play

with high registers (R8 ‐ R12). So avoid using them.

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Exercise Exercise

Q1. Change Main Stack Pointer to Process Stack Q1. Change Main Stack Pointer to Process Stack
Pointer Pointer
MSR is used to write to CONTROL Reg, but we need a MSR is used to write to CONTROL Reg, but we need a
reg to hold data
reg to hold data
MOVS R7, #0x02 //0x0000_0010, bit1=1
MSR CONTROL, R7
Q2. Change Process Stack Pointer to Main Stack
Pointer
Q2. Change Process Stack Pointer to Main Stack
Pointer

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Exercise Instructions: Memory Access

There are several memory access instructions
Q1. Change Main Stack Pointer to Process Stack Pointer supporting various sizes.
MSR is used to write to CONTROL Reg, but we need a reg
to hold data LDR <Rt>, [<Rn>, <Rm>] /* Word read single memory
data into register. Rt = Memory[Rn + Rm]. All are low
MOVS R7, #0x02 //0x0000_0010, bit1=1
registers */
MSR CONTROL, R7
LDRH <Rt>, [<Rn>, <Rm>] * Half read */
Q2. Change Process Stack Pointer to Main Stack Pointer LDRB <Rt>, [<Rn>, <Rm>] /* Byte read */
MOVS R7, #0x00 //0x0000_0010, bit0=0
MSR CONTROL, R7

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Instructions: Memory Access Instructions: Memory access ‐ Immediate

● Memory accesses should always be aligned. ● We can also use immediate addressing
● Unaligned accesses are not supported and will ● All are low registers
cause a HardFault exception. LDR <Rt>, [<Rn>, #imm5] /* Word read single
○ Word accesses should have bits[1:0] = 00 memory data into register.
Rt = memory[Rn + ZeroExtend (#imm5 << 2)] */
○ Half word accesses should have bit[0] = 0
Example:
LDRH <Rt>, [<Rn>, #imm5] * Half read
Rt = memory[Rn + ZeroExtend (#imm5 << 1)] */
LDR R4, [R3, R2]
/* R3 + R2 should be 0x[XXXXXX00] */ LDRB <Rt>, [<Rn>, #imm5] /* Byte read
Rt = memory[Rn + ZeroExtend (#imm5)] */
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Exercise Exercise
Q1. Read from memory location 0x24 to R0 using Q1. Read from memory location 0x24 to R0 using
different offset methods different offset methods
MOVS R1, #0x24/* R1 = 0x24 */
LDR R0, [R1,0] /* R0 = [0x24+0] = LDR R0, [R1] */

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Exercise Exercise
Q1. Read from memory location 0x24 to R0 using Q1. Read from memory location 0x24 to R0 using
different offset methods different offset methods
MOVS R1, #0x24/* R1 = 0x24 */
MOVS R1, #0x24/* R1 = 0x24 */
LDR R0, [R1,0] /* R0 = [0x24+0] = LDR R0, [R1] */
LDR R0, [R1,0] /* R0 = [0x24+0] = LDR R0, [R1] */
MOVS R1, #0x20/* R1 = 0x24 */
MOVS R1, #0x20/* R1 = 0x24 */ LDR R0, [R1,#1] /* 1 << 2 will be 0b100=4 so R0 = [0x20+4] */
LDR R0, [R1,#1] /* 1 << 2 will be 0b100=4 so R0 = [0x20+4] */
MOVS R1, #0x24/* R1 = 0x24 */
MOVS R2, #0x00/* R2 = 0x00 */
LDR R0, [R1,R2] /* R0 = [R1+R2] so R0 = [0x24+0] */

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Instructions: Memory Access – PC Relative Instructions: Memory Access – Store

● Cortex‐M processors support PC relative addressing, ● Store instructions follow the same syntax as load
that
is generated by the pseudo instruction. instructions.
● The data is stored in literal data blocks along side
instructions (literal pool). STR <Rt>, [<Rn>, #imm5] /* Word write single
● Rt should be low register.
● +4 is used for pipelining nature of the processor.
register into memory. memory[Rn + ZeroExtend
(#imm5 << 2)] = Rt */
LDR <Rt>, [PC, #imm8] /* Word read Rt =
memory[WordAligned(PC + 4) + ZeroExtend(#immed8 <<
2)] */
Note: There are also multiple store / load instructions,
LDR R0,=0x12345678 [<Rn>, #imm5] * 0x12345678 will be but we will not really use them when writing assembly
stored somewhere in the memory (literal pool) and will be code. Make sure to check them out for debugging
transferred to R0 */ purposes.
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Exercise Exercise
Q1. Memory address 0x20000024 holds data 1124 Q1. Memory address 0x24 holds data 1124
Memory address 0x28 holds data 749812
Memory address 0x20000028 holds data 749812
mem[0x20000024] = 1124,
mem[0x20000024] = 1124, mem[0x20000028] = 749812
mem[0x20000028] = 749812 Swap them.
Swap them. LDR R0, =0x20000024
LDR R1, =0x20000028
LDR R2, [R0] //Load from mem to R2 = 1124
LDR R3, [R1] // Load from mem to R3 = 749812
STR R3, [R0] // mem[0x20000024] = 749812
STR R2, [R1] // mem[0x20000028] = 1124

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Instructions: Stack memory access Instructions: Stack memory access

● There are two memory instructions dedicated for stack ● A common combinations happen with function calls.
memory access. PUSH and POP
● Save processor state and return address.
● Only low registers and LR, PC are supported
● Then after the function completes, restore the processor
PUSH {<Ra>} /* Push Ra into Stack */
POP {<Ra>} /* Pop Stack valute to Ra */ state, and update the program counter to the return
● Multiple registers can be pushed / popped address.
● Register range should be ascending order
● Higher register will be pushed first my_func:
PUSH {R4, R5, R7, LR} /* Store R4, R5, R7, LR */
PUSH {R1, R2, R5 – R7, LR} /* function body */
/* Store R1, R2, R5, R6, POP {R4, R5, R7, PC} /* Restore R4, R5, R7, and
R7, and LR to stack. */ pop LR value to PC */
PUSH {R4, R5, R7, LR}
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Instructions: Arithmetic Operations ‐ Add Instructions: Arithmetic Operations ‐ Sub

● Most basic arithmetic operations are supported ● Most basic arithmetic operations are supported
● Can be register ‐ register, or register ‐ immediate ● Can be register ‐ register, or register ‐ immediate
● All are low registers ● All are low registers
ADD <Rd>, <Rn>, <Rm> // Rd = Rn + Rm SUB <Rd>, <Rn>, <Rm> // Rd = Rn ‐ Rm
ADDS <Rd>, <Rn>, <Rm> // Rd = Rn + Rm, flags SUBS <Rd>, <Rn>, <Rm> // Rd = Rn ‐ Rm, flags
ADDS <Rd>, <Rn>, #imm3 // Rd = Rn + #imm3, flags SUBS <Rd>, <Rn>, #imm3 // Rd = Rn ‐ #imm3, flags
ADDS <Rd>, #imm8 // Rd = Rd + #imm8, flags SUBS <Rd>, #imm8 // Rd = Rd ‐ #imm8, flags
ADR <Rd>, <label> // Pseudo ‐ same as above SBCS <Rd>, <Rd>, <Rm> // Rd = Rd ‐ Rm ‐ Borrow,
ADCS <Rd>, <Rm> // Rd = Rd + Rm + Carry, flags flags
RSBS <Rd>, <Rn>, #0 // Rd = 0 ‐ Rn, flags
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Exercise Exercise
Q1. mem[0x20000024] = 15, mem[0x2000028] = 18, Q1. mem[0x20000024] = 15, mem[0x20000028] = 18,
mem[0x2000002C] = 17, mem[0x20000030] = 16
mem[0x2000002C] = 17, mem[0x20000030] = 16 Find their sum and save the result into mem[0x20000034]
Find their sum and save the result into LDR R0, =0x20000024
mem[0x20000034] LDR R1, [R0] //Load from mem to R1 = 15
LDR R2, [R0, 1] //Load from mem+4 to R2=18
ADDS R1, R1, R2 //R1 = R2 + R1 = 33
LDR R2, [R0, 2] //Load from mem+8 to R2 = 17
ADDS R1, R1, R2 //R1 = R2 + R1 = 50
LDR R2, [R0, 3] //Load from mem+12 to R2 = 16
ADDS R1, R1, R2 //R1 = R2 + R1 = 66
STR R1, [R0, 4] // Store R1 = 66 into mem+16 mem[0x20000034]

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Instructions: Arithmetic Operations ‐ Compare Instructions: Arithmetic Operations ‐ Multiply

● There are also instructions that compare two ● There are is a multiplication instruction that
operands multiplies two 32‐bit numbers and returns 32‐bit
(using subtract) and update APSR register result.
● Result is not stored
CMP <Rn>, <Rm> /* Calculate Rn ‐ Rm, flags*/ MULS <Rd>, <Rn>, <Rm> /* Rd = Rn * Rm, N and Z
CMP <Rn>, #imm8 /* Calculate Rn ‐ #imm8, flags. Rn update. All are low registers */
is low register */
CMN <Rn>, <Rm /* Calculate negative, Rn ‐ NEG(Rm), Note: There is NO division instruction...
flags*/

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Instructions: Logical Operations Instructions: Logical Operations

● Logical operations update NZ flags ● Logical operations update NZ flags
● All use low registers ● All use low registers
ANDS <Rd>, <Rn>, <Rm> /* And, Rd = Rn & Rm, NZ */ ANDS <Rd>, <Rn>, <Rm> /* And, Rd = Rn & Rm, NZ */
ORRS <Rd>, <Rn>, <Rm> /* Or, Rd = Rn | Rm, NZ */ ORRS <Rd>, <Rn>, <Rm> /* Or, Rd = Rn | Rm, NZ */
EORS <Rd>, <Rn>, <Rm> /* Xor, Rd = Rn ^ Rm, NZ */ EORS <Rd>, <Rn>, <Rm> /* Xor, Rd = Rn ^ Rm, NZ */
BICS <Rd>, <Rn>, <Rm> /* Bit clear, Rd = Rn & ~Rm, BICS <Rd>, <Rn>, <Rm> /* Bit clear, Rd = Rn & ~Rm,
NZ */ NZ */
MVN <Rd>, <Rm> /* Not, Rd = ~Rm, NZ */ MVN <Rd>, <Rm> /* Not, Rd = ~Rm, NZ */
TST <Rn>, <Rm> /* And, Rn & Rm, NZ, result is not TST <Rn>, <Rm> /* And, Rn & Rm, NZ, result is not
stored */ stored */
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Exercise Exercise
Q1. mem[0x50002024] = 0x14142424, Set bit 4 Q1. mem[0x50002024] = 0x14142424, Set bit 4

LDR R1,=#0x50002024 //Load address to R1

LDR R0, [R1] //Load from mem[R1] to R0 =
0x14142424
MOVS R2, #0x10 // Bit mask bit 4 is 0b0001_0000
ORRS R0, R0, R2 // Set bit 4 by OR ing with MASK
STR R0, [R1] // Store back into mem

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Exercise Exercise
Q2. mem[0x50002024] = 0x141C2424, Clear bit 19 Q2. mem[0x50002024] = 0x141C2424, Clear bit 19

LDR R0,=#0x50002024 //Load address to R1

LDR R1, [R0] //Load from mem[R1] to R0
// (19 > 8 so we cannot use MOVS with imm here)
LDR R2, =0x80000 //0b1000_0000_0000_0000_0000
BICS R1, R1, R2// Invert Bit MASK (0x7FFFF) and AND MASK
// MVN R2,R2 // Invert Bit MASK (0x7FFFF)
// ANDS R1, R1, R2 // Clear bit 19 by AND ingwith MASK
STR R0, [R1] // Store back into mem
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Instructions: Shift and Rotate Operations Exercise

ASRS <Rd>, <Rd>, <Rm> /* Rd = Rd >> Rm, CNZ */ Q1. mem[0x50002024] = 0x141C2424, Set bit 12
ASRS <Rd>, <Rd>, #imm5 /* Rd = Rd >> #imm5, CNZ */
LSLS <Rd>, <Rd>, <Rm> /* Rd = Rd << Rm, CNZ */
LSLS <Rd>, <Rd>, #imm5 /* Rd = Rd << #imm5, CNZ */
LSRS <Rd>, <Rd>, <Rm> /* Rd = Rd >> Rm, CNZ */
LSRS <Rd>, <Rd>, #imm5 /* Rd = Rd >> #imm5, CNZ */
RORS <Rd>, <Rd>, <Rm> /* Rd = Rd rotate by Rm bits, CNZ */

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Exercise Exercise
Q1. mem[0x50002024] = 0x141C2424, Set bit 12 Q2. mem[0x50002024] = 0x141C2424, Clear bit 19

LDR R0,=#0x50002024 //Load address to R1

LDR R1, [R0] //Load from mem[R1] to R0
// Load R2 with 1 and shift left12 times
LDR R2, 1//0b0_0000_0000_0001
LSLS R2, R2, #12// Shift Left 0b1_0000_0000_0000
ORRS R1, R1, R2 // Set bit 12 by OR ing with MASK
STR R1, [R0] // Store back into mem

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Exercise Instructions: Program Flow Control

Q2. mem[0x50002024] = 0x141C2424, Clear bit 19 B <label> /* Branch to address. ‐+ 2046 bytes
offset of PC range */
LDR R0,=#0x50002024 //Load address to R1 B<cond> <label> /* Depending on APSR, branch to address. ‐+
254 bytes of PC range */
LDR R1, [R0] //Load from mem[R1] to R0 Example:
// Load R2 with 1 and shift left12 times MOVS R0, #3
MOV R2, #0x01//0b0000_0000_0000_0000_0001 loop:
LSLS R2, R2, #19// 0b1000_0000_0000_0000_000 SUBS R0, #1
MVN R2, R2// Invert Bit MASK (0x7FFFF) for AND BGT loop // jump to loop if greater than
ANDS R1, R1, R2 // Clear bit 19 by AND ing with MASK NOP // No/empty instruction

STR R1, [R0] // Store back into mem

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Exercise Exercise
Q1. mem[0x20000024] = 15, mem[0x20000028] = 18, Q1. mem[0x20000024] = 15, mem[0x20000028] = 18, …
mem[0x20000040] = 11, Find the sum and save it in mem[0x20000044].
mem[0x2000002C] = 17, mem[0x20000030] = 16, LDR R0, =0x20000024 //Load base address to R0
mem[0x20000034] = 14, mem[0x20000038] = 12, … LDR R1, [R0] // R1 = 15
mem[0x2000003C] = 13, mem[0x20000040] = 11, MOVS R7, #0 // Loop counter = 0
Find the sum and save it in mem[0x20000044]. loop:
ADDS R7, R7, #4 // Increment loop counter for the next address
LDR R2, [R0, R7] // Load the data at the loop counter offset
ADDS R1, R1, R2 // Accumulate sum at R1
CMP R7, #28 // Compare if we have reached the last address
BNE loop // Go to loop if not reached
LDR R0, =0x20000044 // Load the write back address to R0
STR R1, [R0] // Store Sum back into mem pointed by R0

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Exercise Exercise
Q1. mem[0x20000024] = 15, mem[0x20000028] = 18, Q1. mem[0x20000024] = 15, mem[0x20000028] = 18, …
mem[0x20000040] = 11, Find the sum and save it in mem[0x20000044].
mem[0x2000002C] = 17, mem[0x20000030] = 16, MOVS R0, #0 //Accumulator
mem[0x20000034] = 14, mem[0x20000038] = 12, … MOVS R7, #28 // Loop counter
mem[0x2000003C] = 13, mem[0x20000040] = 11, LDR R2, =0x20000024 // R2 = 15
Find the sum and save it in mem[0x20000044]. loop:
LDR R1, [R2, R7] // Load the data at the loop counter offset
ADDS R0, R0, R1 // Accumulate sum at R0
SUBS R7, R7, #4 // Decrement loop counter for the next addr
CMP R7, #0
BNE loop // Go to loop if not reached
LDR R1, =0x20000044 // Load the write back address to R1
STR R0, [R1] // Store Sum back into mem pointed by 1

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Instructions: Branch <cond> suffixes Instructions: Program Flow Control

● BL <label> Branch and Link. Branch to address and
store return address to Link Register. Used for function
calls. Range is ‐+ 16MB of PC
● BX <Rm> Branch and Exchange. Branch to register
value, and change processor state depending on register
bit[0]. Since Cortex‐M0+ only supports Thumb mode,
Register bit[0] should be 1. Otherwise hard fault exception occurs.
● BLX <Rm> Branch, Link and Exchange. Branch to
register value, save return address to Link Register, and
change processor state depending on register bit[0].

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Instructions: Function calls Exception and Sleep Mode Instructions

● Use BL <label> for function calls. It will update LR with ● Sometimes, for critical sections, we don't want to be
LSB set to 1, and BX LR to return back from function. interrupted:
main:
... CPSIE I // Enable all interrupts (Clear PRIMASK)
BL func1 /* b to func1, set LR to next instr */ CPSID I // Disable all interrupts (Set PRIMASK)
MOVS R0, R2
... Sleep mode instructions:
func1: WFI // Wait for Interrupt
... WFE // Wait for Event (or interrupt)
BX LR /* return to where LR points to */

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Exercise Exercise
mem[0x50000800] = 0xDEADABAB
mem[0x50000800] = 0xDEADABAB
Q1. Write 01 to bits[13:12] to 0x50000800 without changing the rest of the
Q1. Write 01 to bits[13:12] to 0x50000800 without bits.
changing the rest of the bits.
LDR R0,=0x50000800 //Load address to R0
LDR R1, [R0] //Load from mem[R0] to R1 = 0xXXXXXXXX
MOVS R7, #3 // Load R7 with 3 and R7 = 0x00000003
LSLS R7, R7, #12 // shift left 12 times R7 = 0x0003000 12th 13rd bits are 0
BICS R1, R1, R7// Invert Bit MASK

MOVS R7, #1 // Load R7 with 1 and R7 = 0x00000001

LSLS R7, R7, #12 // shift left 12 times R7 = 0x0001000 12th bit is 1
ORRS R1, R1, R7 //
STR R1, [R0] // Store back into mem 0XDEAD9BAB

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Exercise Exercise
mem[0x50000814] = 0xDEADABAB mem[0x50000814] = 0xDEADABAB
Q2. Write 1 to bit[6] to 0x50000814 without changing Q2. Write 1 to bit[6] to 0x50000814 without changing
the rest of the bits. the rest of the bits.

LDR R0,=0x50000814 //Load address to R0

LDR R1, [R0] //Load from mem[R0] to R1 =
0xDEADABAB
MOVS R7, #0x40 // Load R7 with 0b0100_0000
ORRS R1, R1, R7 // Set bit 6 of R1 by OR ing with
MASK
STR R1, [R0] // Store R1 back into mem pointed by R0
//0XDEADABEB
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Useful Links End of Lecture 3 ‐ EoL

ARMv6‐M Architecture Reference Manual:
https://developer.arm.com/documentation/ddi0419/c/

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