Chapter (1):

The 80x86 Microprocessor

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 Chapter (1):

The 80x86 Microprocessor

➢ Brief history of the 80x86 family
➢ Inside the 8088/8086
➢ Introduction to the assembly programming
➢ Introduction to program segments
➢ 80x86 addressing modes

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Company 4 bit 8 bit 16 bit 32 bit 64 bit

8008 8088/6
4004 80386 80860
intel 8080 80186
4040 80486 pentium
8085 80286

Z8000
zilog Z80 Z8001
Z8002

6800 68006 68020

Motorola 6802 68008 68030
6809 68010 68040

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8/26/2022 4
 U?
8086 vs 8088 U?
33 16 33 16
MN AD0 15 MN AD0 15
22 AD1 14 22 AD1 14
19 READY AD2 13 19 READY AD2 13
21 CLK
RESET
AD3
AD4
12 21 CLK
RESET
AD3
AD4
12 8_bit Data Bus
11 11
18 AD5 10 18 AD5 10
INTR AD6 9 INTR AD6 9
AD7
AD8
8 16_bit Data Bus AD7
A8
8
AD9
7
6 20_bit Address A9
7
6 20_bit Address
AD10 5 A10 5
AD11 4 A11 4
AD12 3 A12 3
AD13 2 A13 2
AD14 39 A14 39
AD15 38 A15 38
A16/S3 37 A16/S3 37
A17/S4 36 A17/S4 36
A18/S5 35 A18/S5 35
A19/S6 A19/S6
34 34
BHE/S7 SSO
26 26
DEN 27 DEN 27
DT/R 28 DT/R 28
30 M/IO 30 IO/M
31 HLDA 32 31 HLDA 32
17 HOLD RD 29 17 HOLD RD 29
23 NMI WR 25 23 NMI WR 25
TEST ALE 24 TEST ALE 24
INTA INTA

8086 8088
8086MIN 8088MIN

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➢8086 Pin Assignment

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➢8086 Pin Description
Vcc (pin 40) : Power
Gnd (pin 1 and 20) : Ground
AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus
MN/MX’ (input) : Indicates Operating mode
READY (input , Active High) : take uP to wait state
CLK (input) : Provides basic timing for the processor
RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately
terminate its present activity.
TEST’ (input , Active Low) : Connect this to HIGH
HOLD (input , Active High) : Connect this to LOW
HLDA (output , Active High) : Hold Ack
INTR (input , Active High) : Interrupt request
INTA’ (output , Active Low) : Interrupt Acknowledge
NMI (input , Active High) : Non-maskable interrupt

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➢8086 Pin Description
DEN’ (output) : Data Enable. It is LOW when processor wants to
receive data or processor is giving out data (to74245)

DT/R’ (output) : Data Transmit/Receive.

When High, data from uP to memory
When Low, data is from memory to uP (to74245 dir)

IO/M’ (output) : If High uP access I/O Device.

If Low uP access memory

RD’ (output) : When Low, uP is performing a read operation

WR’ (output) : When Low, uP is performing a write operation

ALE (output) : Address Latch Enable , Active High

Provided by uP to latch address
When HIGH, uP is using AD0..AD7, A19/S6,
A18/S5, A17/S4, A16/S3 as address lines
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❑ We concern on the two important internal operation of 8086
➢ Pipelining
➢ Registers

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 Address bus (20 bits)
AH AL General purpose
BH BL register 

CH CL
Execution Unit
DH DL
(EU) Data bus
SP CS (16 bits)
Segment
BP register DS
SI SS
DI ALU Data bus ES
(16 bits)
IP

Bus
control
ALU Instruction Queue External bus
EU
control
Flag register
Bus Interface Unit (BIU)
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❑ Registers
➢ In CPU, the register are used to store the information temporarily
➢ In register, the information could be one or two bytes of data to be
processed or the address of data.
➢ The registers of the 8088/8086 fall into six categories

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❑ Registers
15 8 7 0
AX AH AL Accumulator

Data Group BX BH BL Base

General purpose
register CX CH CL Counter

DX DH DL Data

15 0

SP Stack Pointer

BP Base Pointer
Pointer and
Index registers
SI Source Index

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❑ Registers
15 0
CS Code Segment
Segment
DS Data Segment
registers
SS Stack Segment
ES Extra Segment
15 0
Flag ⎯ ⎯ ⎯ ⎯
OF DF IF TF SF ZF AF PF CF
register

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❑ Registers
➢ Data registers
➢ Used for arithmetic and data movement
➢ Each register can be addressed as either a 16-bits or 8-bits value.
1. AX (accumulator): arithmetic operations and other operations.
2. BX (base): hold the address of a procedure or variable same to SI,
DI, and BP, and perform arithmetic and data movement
3. CX (counter): acts as a counter for repeating or loop instructions.
These instructions automatically repeat and decrement CX.
4. DX (data): a special role in multiply and division operations

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❑ Registers
➢ Segment registers
➢ Used as base locations for program instructions, data, and stack.
➢ Each register has a 16-bits.
1. CS (code segment ): hold the base location of all executable
instructions (code) in a program.
2. DS (data segment): is a default base location for variables.
3. SS (stack segment): contains the base location of stack.
4. ES (extra segment): is an additional base location for memmory
variables.

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❑ Registers
➢ Index registers
➢ Contain the offsets of data and instructions.
➢ Offset refer to the distance of variable, label, or instruction from the its
base segment.
1. BP (base pointer): contains an assumed offset from the SS register,
often used by a subroutine to locate variables that were passed on
the stack by a call program.
2. SP (stack pointer): contain the offset of the top of the stack. SP &
SS combine to form the complete address of the top of the stack.
3. SI (source index): point the source string.
4. DI (destination index): acts as a destination for string movement
instructions.
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❑ Registers
➢ Status and Control registers
1. IP (instruction pointer): always contains the offset of the next
instruction to be executed within the current code segment. IP &
CS combine to form the complete address of the next instruction.
2. Flag: a special register used to show the status of the CPU or the
results of arithmetic operations. Two types (control flag & status
flag)

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❑ In 8086 microprocessor, address bus has 20-bits then its access
memory 220 = 1048676 = 1Mbytes. (00000h) to (FFFFFh)

❑ All registers have 16-bits then its access 216 = 65536 = 64K-bytes.
❑ its impossible to access the memory, for this reason, the memory
is divided to segments (each segment = 64K-bytes) (0000h -
FFFFh).
❑ Inside each segment, any address can be identify by offset.
❑ Then, to determine the address in the memory, used segment
value & offset (Segment : Offset). Ex. (AABB:5566). Its called
logical address.
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❑ Logical address & Physical address
❑ 8086 has three types of addresses (physical – offset - logical)
➢ Physical address: is the 20-bits address that is actually put on the address
bus, this is the actual physical location in RAM or ROM.
➢ Offset address: is a location within a 64k-bytes segment range.
➢ Logical address: consists of a segment value and offset address.
➢ The logical address of an instruction always consist of CS & IP (CS:IP)
❑ Physical address = (segment value * 16) + offset
❑ Or by shifting the segment value left one hex digit and then adding
it to the offset address.
❑ Example: if logical address (9A32h:001Bh), determine the physical
address??
9A320 + 001B = 9A33B (physical address)

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❑ Logical address & Physical address

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❑ Memory Map:

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❑ Two widely instructions were used in assembly language:
➢ MOV instruction
➢ ADD instruction
❑ MOV instruction: copies data from one location to another
❑ MOV destination,source ; copy source operand to destination
❑ Example: the following program first loads CL with value 55H, then
moves this value around to various registers inside the CPU.

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❑ Two widely instruction were used in assembly language:
➢ MOV instruction
➢ ADD instruction
❑ MOV instruction: copies data from one location to another
❑ MOV destination,source ; copy source operand to destination
❑ Example: the following program first loads CL with value 55H, then
moves this value around to various registers inside the CPU.

❑ Another program:

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❑ Another program: we have some notes

1. Values can be moved among all registers (except FR)

2. Values can not loaded directly into any segment register (CS, DS, ES, SS).
But first load it to a non segment register and then move it to the segment
register
3. Moving a large value into register will cause error.

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❑ ADD instruction: has the following format
❑ ADD destination,source ; add source operand to destination
❑ Example:

❑ Then

❑ The ADD instruction can be rewritten as

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❑ Example: add 5 bytes of data (25H, 12H, 15H, 1FH, and 2BH)

❑ This program can be rewritten as

❑ Assume the offset of data segment is 200H

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❑ Example (cont.): add 5 bytes of data (25H, 12H, 15H, 1FH, and 2BH)
❑ Because DS uses only BX, DI, and SI to hold the offset address
of the data. Then BX or DI or SI is called pointer.
❑ This program can be rewritten as

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❑ Stack:
❑ Stack is a section of RAM used to storage the information
temporally.
❑ Two registers are used to access the stack (SS & SP). These
registers must be loaded before any instructions accessing the
stack are used.
❑ Used two operation with stack (POP & PUSH)
❑ PUSH: storing a CPU register in the stack.
➢ When the content of register (2-bytes) push into the
stack, then the SP decrement by 2.
➢ If a byte push into the stack, then the SP decrement by 1.
❑ POP: loading the contents of the stack into the CPU register
❑ Using the SS & SP registers to compute the physical address of
the stack.
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❑ Stack: Push onto the stack

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❑ Stack: Pop the stack

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❑ Example on the access memory:

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❑ Example on the overlapping in the memory:

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❑ Flag Register:

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❑ Flag Register with ADD instruction:

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❑ Flag Register with ADD instruction:

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❑ Using the Zero Flag in the Looping:

❑ (ZF = 1) if the result is equal zero.

❑ JNZ instruction come after the DEC instruction, then the ZF check
the result of counter.

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❑ 80x86 provide a seven distinct addressing modes:
1. Register
2. Immediate
3. Direct
4. Register indirect
5. Based relative
6. Indexed relative
7. Based indexed relative
❑ Register addressing mode: use the register to hold data.

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❑ Immediate addressing mode: source operand is constant.

MOV AX,0123H
MOV DS,AX
❑ Direct addressing mode:

❑ Register indirect addressing mode:

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❑ Based relative addressing mode:

❑ Indexed relative addressing mode:

❑ Based indexed addressing mode:

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 Any Question?

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