1

 Gate-level minimization is the design task of finding an optimal gate-level implementation of the Boolean functions
describing a digital circuit.

 This task is well understood, but is difficult to execute by manual methods when the logic has more than a few inputs.

 Fortunately, computer-based logic synthesis tools can minimize a large set of Boolean equations efficiently and
quickly.

 Nevertheless, it is important that a designer understand the underlying mathematical description and solution of the
problem

KARNAUGH MAPS

- Graphical Device used to Simplify Boolean expressions

- Relates inputs to Outputs

- Useful upto six variables

 Row of a Truth Table corresponds to a square in K-map

 Adjacent square differ in only one variable

2
 Combine squares with 1’s
3
 There are four minterms for two variables; hence, the map in (a) consists of four squares, one for each minterm.

 The map is redrawn in (b) to show the relationship between the squares and the two variables x and y .

 The 0 and 1 marked in each row and column designate the values of variables.

 Variable x appears primed in row 0 and unprimed in row 1.

 Similarly, y appears primed in column 0 and unprimed in column 1.

4
 There are eight minterms for three binary variables; therefore, the map consists of eight squares.

 Note that the minterms are arranged, not in a binary sequence, but in a sequence similar to the Gray code.

 The characteristic of this sequence is that only one bit changes in value from one adjacent column to the next.

5
 00 01 11 10
0
1
00 01 11 10
0
1

6
 00 01 11 10
0
1

00 01 11 10
0
1

7
 00 01 11 10
0
1

8
 00 01 11 10
0
1

00 01 11 10
0
1

9
10
 00 01 11 10
0
1

11
 00 01 11 10
0
1

00 01 11 10
0
1

12
 00 01 11 10
0
1

13
 00 01 11 10 00 01 11 10
0 0
1 1

00 01 11 10 00 01 11 10
0 0
1 1

14
 00 01 11 10 00 01 11 10
0 0
1 1

15
16
17
 00 01 11 10 00 01 11 10
0 0
1 1

18
19
00 01 11 10 00 01 11 10

20
21
22
23
24
25
 Don’t Care Conditions

- Unspecified outputs for certain inputs

- Used in Map to provide further simplification

- X is marked inside the square for don’t care input

- Choose to include each don’t care minterm with either 1 or 0

26
27
28
29
30
31
 POS Simplification

- Combine valid adjacent squares containing 0’s

- Obtain simplified expression of the complement in SOP form

- Compliment further to get function in POS form

32
F(A,B,C,D) = (0,1,2,5,8,9,10)

1 1 0 1
0 1 0 0
0 0 0 0
1 1 0 1

33
F(A,B,C,D) = (0,1,2,5,8,9,10)

1 1 0 1
0 1 0 0
0 0 0 0
1 1 0 1

34
F’ = AB + CD + BD’

By De Morgan’s

F = (A’+B’) (C’+D’)(B’+D)

35
36
37
 Digital circuits are frequently constructed with NAND or NOR gates rather than with AND and OR gates.

 NAND and NOR gates are easier to fabricate with electronic components and are the basic gates used in all IC digital
logic families.

 Because of the prominence of NAND and NOR gates in the design of digital circuits, rules and procedures have been
developed for the conversion from Boolean functions given in terms of AND, OR, and NOT into equivalent NAND and
NOR logic diagrams.

 The NAND gate is said to be a universal gate because any logic circuit can be implemented with it.

 The logical operations of AND, OR, and complement can be obtained with NAND gates alone.

38
 The NAND gate is said to be a universal gate because any logic circuit can be implemented with it.

 The logical operations of AND, OR, and complement can be obtained with NAND gates alone.

39
 A convenient way to implement a Boolean function with NAND gates is to obtain the simplified Boolean
function in terms of Boolean operators and then convert the function to NAND logic.

 The conversion of an algebraic expression from AND, OR, and complement to NAND can be done by simple circuit
manipulation techniques that change AND–OR diagrams to NAND diagrams.

 To facilitate the conversion to NAND logic, it is convenient to define an alternative graphic symbol for the gate.

 Two equivalent graphic symbols for the NAND gate are:

40
 The implementation of Boolean functions with NAND gates requires that the functions be in sum-of-products form.

 To see the relationship between a sum-of-products expression and its equivalent NAND implementation, consider the logic
diagrams drawn to implement the function
F = AB + CD

 The NAND implementation in (c) can be

verified algebraically.

 The function it implements can easily be

converted to sum-of-products form by
DeMorgan’s theorem:

 F = ((AB)‘(CD)‘)‘ = AB + CD

41
 The standard form of expressing Boolean functions results in a two-level implementation.

 There are occasions, however, when the design of digital systems results in gating structures with three or more levels.

 The most common procedure in the design of multilevel circuits is to express the Boolean function in terms of AND,
OR, and complement operations.

 The function can then be implemented with AND and OR gates.

 After that, if necessary, it can be converted into an all-NAND circuit.

 Consider, for example, the Boolean function

F = A (CD + B) + BC’

42
43
 The NOR operation is the dual of the NAND operation. Therefore, all procedures and rules for NOR logic are the
duals of the corresponding procedures and rules developed for NAND logic.

 The NOR gate is another universal gate that can be used to implement any Boolean function.

 The implementation of the complement, OR, and AND operations with NOR gates is shown

44
 The two graphic symbols for the mixed notation are shown in

 The OR-invert symbol defines the NOR operation as an OR followed by a complement.

 The invert-AND symbol complements each input and then performs an AND operation.

 The two symbols designate the same NOR operation and are logically identical because of DeMorgan’s theorem.

45
 The transformation from the OR–AND diagram to a NOR diagram is achieved by changing

- the OR gates to NOR gates with OR-invert graphic symbols and

- the AND gate to a NOR gate with an invert-AND graphic symbol.

 A single literal term going into the second-level gate must be complemented.
46
 For converting a multilevel AND–OR diagram to an all-NOR diagram, we must convert
- each OR gate to an OR-invert symbol and
- each AND gate to an invert-AND symbol

47
 The XOR is equal to 1 if x and y differ in value.

 Exclusive-NOR (XNOR), also known as equivalence, performs the following Boolean operation:

The XNOR is equal to 1 if both x and y are equal

 Following identities apply to XOR  XOR operation is both commutative and associative

48
The first NAND gate performs the operation (xy)’ = (x’ + y’).

The other two-level NAND circuit produces the sum of

products of its inputs:

49
 The XOR operation with three or more variables can be converted into an ordinary Boolean function by replacing the XOR
symbol with its equivalent Boolean expression.

In case of 3 or more variables, an odd number of variables be equal to 1.

Multiple-variable XOR operation is defined as an odd function.

50
 XOR functions are very useful in systems requiring error detection and correction codes.

 A parity bit is used for the purpose of detecting errors during the transmission of binary information.

 A parity bit is an extra bit included with a binary message to make the number of 1’s either odd or even.

 The message, including the parity bit, is transmitted and then checked at the receiving end for errors.

 An error is detected if the checked parity does not correspond with the one transmitted.

 The circuit that generates the parity bit in the transmitter is called a parity generator.

 The circuit that checks the parity in the receiver is called a parity Checker.

51
For even parity, the bit P must be generated to make
the total number of 1’s (including P ) even.

52
 Since the information was transmitted with even parity, the
four bits received must have an even number of 1’s.

 An error occurs during the transmission if the four bits

received have an odd number of 1’s, indicating that one bit
has changed in value during transmission.

 The output of the parity checker, denoted by C , will be equal

to 1 if an error occurs—that is, if the four bits received have
an odd number of 1’s.

53
 Manual methods for designing logic circuits are feasible only when the circuit is small.

 For anything else (i.e., a practical circuit), designers use computer-based design tools.

 Prototype integrated circuits are too expensive and time consuming to build, so all modern design tools rely
on a hardware description language to describe, design, and test a circuit in software before it is
manufactured.

 A hardware description language (HDL) is a computer-based language that describes the hardware of digital
systems in a textual form.

 It resembles an ordinary computer programming language, such as C, but is specifically oriented to

describing hardware structures and the behavior of logic circuits.

 It can be used to represent logic diagrams, truth tables, Boolean expressions, and complex abstractions of
the behavior of a digital system.

 One way to view an HDL is to observe that it describes a relationship between signals that are the inputs to a
circuit and the signals that are the outputs of the circuit.

 For example, an HDL description of an AND gate describes how the logic value of the gate’s output is
determined by the logic values of its inputs. 54
 HDLs are used in several major steps in the design flow of an integrated circuit:

o design entry
o functional simulation or verification
o logic synthesis
o timing verification and
o fault simulation

 Design entry creates an HDL-based description of the functionality that is to be implemented in hardware.

- Depending on the HDL, the description can be in a variety of forms:

Boolean logic equations, truth tables, a netlist of interconnected gates, or an abstract behavioral model.

- The HDL model may also represent a partition of a larger circuit into smaller interconnected and
interacting functional units.

55
 Logic simulation displays the behavior of a digital system through the use of a computer.

- A simulator interprets the HDL description and either produces readable output, such as a time-ordered
sequence of input and output signal values, or displays waveforms of the signals.

- The simulation of a circuit predicts how the hardware will behave before it is actually fabricated.

- Simulation detects functional errors in a design without having to physically create and operate the circuit.

- Errors that are detected during a simulation can be corrected by modifying the appropriate HDL statements.

- The stimulus (i.e., the logic values of the inputs to a circuit) that tests the functionality of the design is called
a test bench.

- Thus, to simulate a digital system, the design is first described in an HDL and then verified by simulating
the design and checking it with a test bench, which is also written in the HDL.

- An alternative and more complex approach relies on formal mathematical methods to prove that a circuit is
functionally correct.

We will focus exclusively on simulation. 56

 Logic synthesis is the process of deriving a list of physical components and their interconnections (called a
netlist ) from the model of a digital system described in an HDL.

- The netlist can be used to fabricate an integrated circuit or to lay out a printed circuit board with the
hardware counterparts of the gates in the list.

- Logic synthesis is similar to compiling a program in a conventional high-level language. The difference is
that, instead of producing an object code, logic synthesis produces a database describing the elements
and structure of a circuit.

- The database specifies how to fabricate a physical integrated circuit that implements in silicon the
functionality described by statements made in an HDL.

- Logic synthesis is based on formal exact procedures that implement digital circuits and addresses that part
of a digital design which can be automated with computer software.

The design of today’s large, complex circuits is made possible by logic synthesis software.

57
 Timing verification confirms that the fabricated, integrated circuit will operate at a specified speed.

- Because each logic gate in a circuit has a propagation delay, a signal transition at the input of a circuit
cannot immediately cause a change in the logic value of the output of a circuit.

- Propagation delays ultimately limit the speed at which a circuit can operate.

- Timing verification checks each signal path to verify that it is not compromised by propagation delay.

- This step is done after logic synthesis specifies the actual devices that will compose a circuit and before the
circuit is released for production.

 In VLSI circuit design, fault simulation compares the behavior of an ideal circuit with the behavior of a circuit
that contains a process-induced flaw.

- Dust and other particulates in the atmosphere of the clean room can cause a circuit to be fabricated with a
fault. A circuit with a fault will not exhibit the same functionality as a fault-free circuit.

- Fault simulation is used to identify input stimuli that can be used to reveal the difference between the faulty
circuit and the fault-free circuit.

Test patterns are used to test fabricated devices to ensure that only good devices are shipped to customer.
58
 Companies that design integrated circuits use proprietary and public HDLs.

 In the public domain, there are two standard HDLs that are supported by the IEEE: VHDL and Verilog.

 VHDL is a Department of Defense–mandated language. (The V in VHDL stands for the first letter in VHSIC, an
acronym for very high-speed integrated circuit.)

 Verilog began as a proprietary HDL of Cadence Design Systems, but Cadence transferred control of Verilog to a
consortium of companies and universities known as Open Verilog International (OVI) as a step leading to its
adoption as an IEEE standard.

 VHDL is more difficult to learn than Verilog.

 Because Verilog is an easier language than VHDL to describe, learn, and use, we have chosen it for this course.

 Our emphasis will be on the modeling, verification, and synthesis (both manual and automated) of Verilog
models of circuits having specified behavior.

 The Verilog HDL was initially approved as a standard HDL in 1995; revised and enhanced versions of the
language were approved in 2001 and 2005.
59
 The language reference manual for the Verilog HDL presents a syntax that describes precisely the constructs
that can be used in the language.

 In particular, a Verilog model is composed of text using keywords, of which there are about 100.

 Keywords are predefined lowercase identifiers that define the language constructs.
E.g. module, endmodule, input, output, wire, and, or, and not.

 For clarity, keywords will be displayed in boldface in the text in all examples of code

 Any text between two forward slashes ( // ) and the end of the line is interpreted as a comment and will have no
effect on a simulation using the model.

 Multiline comments begin with / * and terminate with * /. Blank spaces are ignored, but they may not appear
within the text of a keyword, a user-specified identifier, an operator, or the representation of a number.

 Verilog is case sensitive (e.g., not is not the same as NOT).

 A module is the fundamental descriptive unit in the Verilog language. It is declared by the keyword module and
must always be terminated by the keyword endmodule. 60
 Combinational logic can be described by a schematic connection of gates, or by a set of Boolean equations, or
by a truth table

o The name ( Simple_Circuit in this example) is an identifier.

o Identifiers are names given to modules, variables (e.g., a signal), and other elements of the language so
that they can be referenced in the design.

o Identifiers must start with an alphabetic character or an underscore, but they cannot start with a number.
61
 The port list of a module is the interface between the module and its environment. In this example, the ports
are the inputs and outputs of the circuit.

 keywords input and output specify which of the ports are inputs and which are outputs. Internal
connections are declared as wire.

 Each gate instantiation consists of an optional name (such as G1, G2 , etc.) followed by the gate output and
inputs separated by commas and enclosed within parentheses.

 Each statement must be terminated with a semicolon, but there is no semicolon after endmodule. 62
 The terms declaration and instantiation are not same.

 A Verilog module is declared. Its declaration specifies the input–output behaviour of the hardware it
represents.

 Predefined primitives are not declared, as their definition is specified by the language, and cannot be
changed by user.

 Primitives are used (i.e., instantiated), just as gates are used to populate a printed circuit board.

 Once a module has been declared, it may be used (instantiated) within a design.

 Note that Simple_Circuit is not a computational model like those developed in an ordinary programming
language:

 The sequential ordering of the statements instantiating gates in the model has no significance and
does not specify a sequence of computations.

 A Verilog model is a descriptive model. Simple_Circuit describes what primitives form a circuit and
how they are connected.
63
 All physical circuits exhibit a propagation delay between the transition of an input and a resulting transition
of an output.

 When an HDL model of a circuit is simulated, it is sometimes necessary to specify the amount of delay from
the input to the output of its gates.

 In Verilog, the propagation delay of a gate is specified in terms of time units and by the symbol #.

 The numbers associated with time delays in Verilog are dimensionless.

 The association of a time unit with physical time is made with the ` timescale compiler directive.
(Compiler directives start with the ( ` ) back quote, or grave accent, symbol.)

 Such a directive is specified before the declaration of a module and applies to all numerical values of time in
the code that follows. An example of a timescale directive is ` timescale 1ns/100ps

 The first number specifies the unit of measurement for time delays. The second number specifies the
precision for which the delays are rounded off, in this case to 0.1 ns.

 If no timescale is specified, a simulator may display dimensionless values or default to a certain time unit,
64
usually 1ns (=10-9 s). Our examples will use only the default time unit.
 If the circuit is simulated and the inputs change from
A , B , C = 0 to A , B , C = 1, the outputs change as shown

 The output of the inverter at E changes from 1 to 0 after a 10-ns delay. The output of the AND gate at w1 changes
from 0 to 1 after a 30-ns delay.

 The output of the OR gate at D changes from 1 to 0 at t = 30 ns and then changes back to 1 at t = 50 ns.

 In both cases, the change in the output of the OR gate results from a change in its inputs 20 ns earlier. It is clear
from this result that although output D eventually returns to a final value of 1 after the input changes, the gate
65
delays produce a negative spike that lasts 20 ns before the final value is reached.
 In order to simulate a circuit with an HDL, it is necessary
to apply inputs to the circuit so that the simulator will
generate an output response.

 An HDL description that provides the stimulus to a

design is called a test bench.

 Here is a test bench for simulating the circuit with delay.

(Note the distinguishing name
Simple_Circuit_prop_delay .)

 In its simplest form, a test bench is a module containing a

signal generator and an instantiation of the model that is
to be verified.

 Note that the test bench ( t_Simple_Circuit_prop_delay )

has no input or output ports, because it does not interact
with its environment.

66
 In general, test bench is named with the prefix t_
concatenated with the name of the module that is to be
tested by the test bench, but that choice is left to the
designer.

 Within the test bench, the inputs to the circuit are declared
with keyword reg and the outputs are declared with the
keyword wire . The module Simple_Circuit_prop_delay is
instantiated with the instance name M1.

 Every instantiation of a module must include a unique

instance name.

 Note that using a test bench is similar to testing actual

hardware by attaching signal generators to the inputs of a
circuit and attaching probes (wires) to the outputs of the
circuit.

67
 Hardware signal generators are not used to verify an HDL
model: The entire simulation exercise is done with software
models executing on a digital computer under the direction
of an HDL simulator.

 The waveforms of the input signals are abstractly modelled

(generated) by Verilog statements specifying waveform
values and transitions.

 The initial keyword is used with a set of statements that

begin executing when the simulation is initialized; the
signal activity associated with initial terminates execution
when the last statement has finished executing.

 The initial statements are commonly used to describe

waveforms in a test bench. The set of statements to be
executed is called a block statement and consists of several
statements enclosed by the keywords begin and end.

68
 The action specified by the statements begins when the
simulation is launched, and the statements are executed in
sequence, left to right, from top to bottom, by a simulator in
order to provide the input to the circuit.

 Initially, A, B, C = 0. ( A, B, and C are each set to 1’b0, which

signifies one binary digit with a value of 0.)

 After 100 ns, the inputs change to A, B, C = 1.

 After another 100 ns, the simulation terminates at time 200 ns.

 A second initial statement uses the $finish system task to

specify termination of the simulation.

 If a statement is preceded by a delay value (e.g., #100), the

simulator postpones executing the statement until the
specified time delay has elapsed.

69
 The timing diagram of waveforms that result
from the simulation is shown below.

 The total simulation generates waveforms

over an interval of 200 ns.

 The inputs A, B, and C change from 0 to 1

after 100 ns.

 Output E is unknown for the first 10 ns

(denoted by shading), and output D is
unknown for the first 30 ns.

 Output E goes from 1 to 0 at 110 ns. Output

D goes from 1 to 0 at 130 ns and back to 1 at
150 ns, just as we predicted in Table 3.5.

70
 Boolean equations describing combinational logic are specified in Verilog with a continuous assignment statement
consisting of the keyword assign followed by a Boolean expression.

 To distinguish arithmetic operators from logical operators, Verilog uses the symbols (&&), ( || ), and (!) for logical AND,
OR, and NOT (complement), respectively.

 Example: Describe a circuit that is specified with the following two Boolean expressions:
 E = A + BC + B’D
 F = B’C + BC’D’
The equations specify how the logic values E and F are determined by the values of A, B, C, and D .

71
 A digital circuit can be described with HDL statements, just as it can be drawn in a circuit diagram or specified
with a Boolean expression.

 A third alternative is to describe combinational logic with a truth table.

 The logic gates used in Verilog descriptions with keywords and, or, etc., are defined by the system and are
referred to as system primitives. (Caution: Other languages may use these words differently .)

 The user can create additional primitives by defining them in tabular form.

 These types of circuits are referred to as user-defined primitives (UDPs).

72
This example defines a UDP with a truth table.

• It is declared with the keyword primitive, followed by

a name and port list.

• There can be only one output, and it must be listed

first in the port list and declared with keyword output

• There can be any number of inputs. The order in

which they are listed in the input declaration must
conform to the order in which they are given values in
the table that follows.

• The truth table is enclosed within the keywords table

and endtable.

• The values of the inputs are listed in order, ending

with a colon (:). The output is always the last entry in a
row and is followed by a semicolon (;)

• The declaration of a UDP ends with the keyword

endprimitive. 73
  The system recognizes the variables by the order in which
they are listed in the input declaration.

 A user-defined primitive can be instantiated in the

construction of other modules (digital circuits), just as the
system primitives are used.

 Although Verilog HDL uses this kind of description for UDPs

only, other HDLs and computer-aided design (CAD) systems
use other procedures to specify digital circuits in tabular form.

 The tables can be processed by CAD software to derive an

efficient gate structure of the design.

 None of Verilog’s predefined primitives describes sequential

logic.

 The model of a sequential UDP requires that its output be

declared as a reg data type, and that a column be added to
; the truth table to describe the next state.

 So the columns are organized as inputs : state : next state.

74
 Section 4.12 to continue with this topic.
Thank You

75