electronics

Article
Multiple Modulation Strategy of Flying Capacitor
DC/DC Converter
Pengcheng Li 1, * , Chunjiang Zhang 2 , Sanjeevikumar Padmanaban 3, *
and Leonowicz Zbigniew 4
1 Department of Electrical Engineering, Hebei University of Science and technology,
Shijiazhuang 050018, China
2 Department of Electrical Engineering, Yanshan University, Qinhuangdao 066004, China
3 Department of Energy Technology, Aalborg University, 6700 Esbjerg, Denmark
4 Faculty of Electrical Engineering, Wroclaw University of Science and Technology, Wyb. Wyspianskiego 27,
50370 Wroclaw, Poland
* Correspondence: [email protected] (P.L.); [email protected] (S.P.); Tel.: +86-18630322865 (P.L.)




Received: 24 May 2019; Accepted: 5 July 2019; Published: 11 July 2019


Abstract: Flying-capacitor multiplexed modulation technology is suitable for bipolar DC microgrids

with higher voltage levels and higher current levels. The module combination and corresponding
modulation method can be flexibly selected according to the voltage level and capacity level. This paper
proposes a bipolar bidirectional DC/DC converter and its interleaved-complementary modulation
strategy that is suitable for bipolar DC microgrids. The converter consists of two flying-capacitor
three-level bidirectional DC/DC converters that are interleaved in parallel 90◦ , and then cascaded with
another module to form a symmetrical structure of the upper and lower arms; the complementary
modulation of the upper and lower half bridges constitutes an interleaved complementary multilevel
bidirectional DC/DC converter. If the bidirectional converter needs to provide a stronger overcurrent
capability, more bridge arms can be interleaved in parallel. Once n bridge arms are connected in
parallel, the bridge arms should be interleaved 180◦ /n in parallel. In bipolar DC microgrids, the upper
and lower arms should be complementarily modulated, and the input and output are isolated by the
inductance. To solve the current difference, caused by the inconsistent parasitic, the voltage-current
double closed-loop-control is used, and the dynamic response is faster during bidirectional operation.
This paper proposes theoretical analysis and experiments that verify bipolar bidirectional DC/DC
converter for high-power energy storage.

Keywords: bidirectional DC/DC converter (BDC); dual mode operation; current sharing; multiplexed
modulation

1. Introduction
With the high penetration of intermittent energy, such as solar and wind [1–3], a power electronic
interface for distributed energy storage is becoming increasingly attractive. The bidirectional DC/DC
converter (BDC) is an important piece of equipment for distributed energy storage in DC microgrids,
which helps to promote intermittent energy scale applications. The BDCs are widely used in DC
microgrids, due to their simple structure, easy expansion, and transmission power being independent
of transformers [4–7].
In particular, it plays a large irreplaceable role in the distributed energy storage of high voltage
and high power. For BDCs, current research focuses on buck/boost two-level converters and control
strategies for suppressing load disturbances [8,9]; however, switches are subject to low-voltages
applications. The voltage and current stresses of the converter are relatively high, so a multilevel

Electronics 2019, 8, 774; doi:10.3390/electronics8070774 www.mdpi.com/journal/electronics

Electronics 2019, 8, 774 2 of 15

converter is required. A multiplexed multiphase and multilevel BDC is used for a wide range of
voltage variations (voltage conversion level less than 10 times); different from multilevel converters
required for a high-voltage DC transmission (voltage conversion level more than 10 times), relying on
transformer boosting to achieve a higher level of voltage conversion [10–12]. The n-level structure of
the multiplexed multilevel BDC reduce voltage stress only 1/n of the high-side voltage; the m-phase
of the multiplexed multiphase BDC reduce current stress only 1/m of the low-side current [13]. The
multiphase and multilevel BDC adopts the interleaved phase modulation technology to improve the
output current ripple frequency, reduce the filter capacitor ripple value in a DC microgrid [14–17].
When a battery is connected to a DC microgrid by a BDC, the BDC needs to have strong input and
output impedance matching capability to keep the system stable. In particular, when the BDC operates
in buck mode, the input impedance is large; when operating in boost mode, the input impedance
is small; when operating in bidirectional mode, the impedance adjustment range is wider, and the
response speed is faster, which is beneficial to the system stability [18].
H. L. Do. [19] proposed a soft-switching DC/DC converter with high voltage gain by a boost cell
and a coupled inductor cell. Soft-switching characteristic reduces the switching loss of active power
switches and increase the converter efficiency. However, the converter can only work in boost mode,
and only S2 and D4 can achieve ZVS turn-on. The S1 -D4 current stress is uneven, and S1 has a higher
current stress. In high-voltage and high-power distributed energy storage, it is necessary to consider
the equalization and current sharing problems. X. S. Zhang et al. [20] proposed the idea of battery
energy storage systems (BESSs) with integrated wind farms to stabilize the grid power. High-power
BDCs are required to meet high power requirements.
R. Naderi et al. [21] proposed a dual flying capacitor active-neutral-point-clamped (DFC-ANPC)
DC/AC inverter with a five-level modulation method that achieves soft switching and neutral point
voltage balancing. More importantly, the five-level modulation method eliminates the transient
voltage balancing issue by series-connected switches of S5 and S6 and decreases the switching loss. F.
Mohammadi [22] discussed the configuration, operation and decoupled control mode of a VSC-HVDC.
Compared to the pulse width modulation (PWM) strategies, the vector control method generates
fewer voltage harmonics and allows to control the active and reactive power independently. The
vector control method is used to control the VSC-HVDC system, which is based on transforming a 3-ϕ
system into a 2-ϕ system by d-q frame. Droop control is easily affected by the line impedance and the
frequency fluctuation of the power grid, which reduces the distribution accuracy of the active and
reactive power. In the future, the bidirectional DC/DC converter (BDC) will be connected to a bipolar
DC microgrid by droop control.
Reference [23] used a DC bus capacitor to provide a three-level state (buck/boost synchronous
PWM modulation). However, the converter operates at high gain, and S1 is subjected to high current
stress, which exacerbates the switching losses. In Reference [24], a two-level buck/boost converter is
cascaded to form a three-level bidirectional DC/DC converter. However, the modulation method easily
causes inconsistent duty ratios of the upper and lower half bridges to be inconsistent, thereby affecting
the voltage equalization effect of the DC bus, and requires an additional voltage equalization control
loop at boost mode, which increases the complexity of the control structure.
This paper proposes a multiplexed modulation technique of the flying capacitor DC/DC converter
to meet the high-voltage and high-power requirements. The BDC has many advantages: (1) the bus
capacitor voltage is easily stabilized by the midpoint potential balance control of the rear inverter
circuit; (2) the BDC is easy to combine by the PWM sequence to achieve multiple modulations; (3) it is
easy to design the control loop and suppress phase-to-phase circulation; and (4) the BDC has a strong
fault tolerance ability, and failure of any one of the arms does not affect the operation of other arms.
The BDC is suitable for battery energy storage systems in bipolar DC microgrids.
This paper organized as follows. The Flying capacitor type three-level DC/DC basic unit in
Section 2. Multiple modulation techniques are presented in Section 3. Controller design in Section 4.
Experimental verifications in Section 5. Some conclusions are given in Section 6.
Experimental verifications in Section 5. Some conclusions are given in Section 6.

2. Flying Capacitor Type Three-level DC-DC Basic Unit

Electronics 2019, 8, 774 3 of 15
This paper proposes a bidirectional DC/DC converter (BDC) topology with multiplexed
modulation2.strategy for a high-power system, as shown in Figure 1. The parallel operation improves
Flying Capacitor Type Three-level DC-DC Basic Unit
the current capability of the BDC; the voltage level is increased in series operation; and the
This paper proposes a bidirectional DC/DC converter (BDC) topology with multiplexed modulation
high-voltage and large-capacity
strategy characteristics
for a high-power system, as shown in are realized
Figure in series-parallel
1. The parallel operation.
operation improves The symbols
the current
and reference directions
capability are the
of the BDC; indicated in isthe
voltage level figure.
increased The operation;
in series basic unit and of
the the flying-capacitor-type
high-voltage and
large-capacity characteristics are realized in series-parallel operation. The symbols
three-level bidirectional DC/DC converter (3L_BDC) easily forms a bipolar BDC of high-voltage and and reference
directions are indicated in the figure. The basic unit of the flying-capacitor-type three-level bidirectional
high-current systems.
DC/DC converter (3L_BDC) easily forms a bipolar BDC of high-voltage and high-current systems.

iH iH
S1 S1 S5
S2 L1 S2 S6 CH
iL L +C U + iL A Cf1
+ + +-
A H H - C Cf2 UH
S3 L2 S S7
3
+- UL CL +- UL CL
S4 S4 S8
B B D
(a) Basic Unit (b) Two arms parallel
iH iH
S1 S1 S5
S2 + L1 S2 S6
iL + iL + + + C
A Cf1 CH1 A Cf1 C Cf2 H1
L1 L2 S3
S3 S7
S4 S4 S8
+- UL B UL CL B D
CL UH +- +- UH +-
Q1 Q1 Q5
Q L3 Q2 Q6
L2 2 + + + + + C
C Cf2 CH2 E Cf3 G Cf4 H2
Q3 L4 Q3 Q7
Q4 Q4 Q8
D F H
(c) Two arms series (d) Four arms mixed

Figure 1. The proposed bidirectional DC/DC converter. (a) Flying capacitor type three-level DC-DC
Figure 1. The proposed bidirectional DC/DC converter. (a) Flying capacitor type three-level DC-DC
basic unit. (b) Two basic units parallel. (c) Two basic units parallel. (d) Four basic units mixed.
basic unit. (b) Two basic units parallel. (c) Two basic units parallel. (d) Four basic units mixed.
In Figure 1a, UL is the input-side voltage, UH is the DC bus side voltage, CL is the battery-side
capacitance, and CH is the DC bus side capacitance. The conduction time of S3 and S4 is defined as Ton
In Figure 1a, UL is the input-side voltage, UH is the DC bus side voltage, CL is the battery-side
in the switching period Ts , and the duty ratio is D = Ton /Ts . To facilitate the analysis, define the switch
capacitance,function
and Cas H is the DC bus side capacitance.
follows: 
The conduction time of S3 and S4 is defined as Ton
in the switching period Ts, and the duty 

 00 ( S
ratio , S
1 is2 D = ST
ON, 3 , on Ts.) To facilitate the analysis, define the
S4 /OFF

 01 (S2 , S4 ON, S1 , S3 OFF)

switch function as follows:

Mk =  . (1)
 10 (S1 , S3 ON, S2 , S4 OFF)



00 ( S1、S2 ON，S3、S4 OFF )
 11 (S3 , S4 ON, S1 , S2 OFF)


 on the basic unit of the flying-capacitor-type three-level

 01( S2、S4 ON，S1、S3 OFF )
The modal analysis is performed
M
bidirectional DC/DC converter. The =  waveform is shown in Figure 2..When the operating mode at
k key (1)
10 ( Sonly
D > 0.5, the switching mode of S3 andS4 is 1、S01,
3 ON ，S 、S4 OFF
10, 11, 2and not ) voltage at the two points of
00. The
( Smode 00,) 01, 10, and not 11. The voltage

AB is 0.5UH or 0; at D < 0.5, the switching 3、Sof4 ON ，SS1、
S3 and 4 isSonly
2 OFF
of AB is UH or 0.5UH . The inductive current flowing from the low-voltage side to the high-voltage
The modal analysis
side is defined ispositive
as the performed
direction.on the basic unit of the flying-capacitor-type
three-level
bidirectional DC/DC converter. The key waveform is shown in Figure 2. When the operating mode
at D > 0.5, the switching mode of S3 and S4 is only 01, 10, 11, and not 00. The voltage at the two points
of AB is 0.5UH or 0; at D < 0.5, the switching mode of S3 and S4 is only 00, 01, 10, and not 11. The
voltage of AB is UH or 0.5UH. The inductive current flowing from the low-voltage side to the
high-voltage side is defined as the positive direction.
Electronics 2019, 8, 774 4 of 15
Electronics 2019, 8, x FOR PEER REVIEW 4 of 15

S1 S1
S2 S2
S3 S3
S4 S4
iL iL
UAB UH/2 UAB UH UH/2
1 0 1 1 1t 0 1 0 0 0 t
1 1 1 0 1 0 0 0 1 0
(a) D>0.5 (b) D<0.5

Figure2.2.The
Figure Themain
mainwaveform
waveformofofthe
thebasic
basicunit.
unit.(a) ModeDD>>0.5.
(a)Mode 0.5. (b)
(b) Mode D << 0.5.
Mode D 0.5.

2.1. Operational Modal Analysis D > 0.5

2.1. Operational Modal Analysis D > 0.5
During the switching cycle, there are three modes of 11, 01, and 10 for each arm.
During the switching cycle, there are three modes of 11, 01, and 10 for each arm.
1.1. ModeM
Mode M3 3==11,
11,S1Sand
1 andS2 Sare
2 are turned
turned off,off, S3 and
S3 and S4 areS4 turned
are turned
on, Son, S1 S
1 and and S2 voltage
2 voltage stressstress
are Uare
H/2,
UH /2,
the the voltage
voltage of AB oftwo-point is UABis=U0,
AB two-point ABthe = 0,inductor
the inductor voltage
voltage across L1 isLU
across L, U
1 is L , and
and iL flows
iL flows to
to the
the high-voltage side and linearly
high-voltage side and linearly increases: increases:
 .
 rL rL i 1+ 1 U
 iLiL==−− iLL +L ULL L
. L 1L




 U H
U . = −
= −
1 R H CH UH . (2)

 HU = 0 UH . (2)
 f RHCH
U =0
 f
2. Mode M1 = 01, S1 and S3 turn off, S2 and S4 turn on, the S1 and S3 voltage stresses are UH /2,
the flying capacitor Cf1 charge according to the differential equation Cf1 dUf1 /dt = Ic , that is
2. Mode M1 = 01, S1 and S3 turn off, S2 and S4 turn on, the S1 and S3 voltage stresses are UH/2, the
∆Uf1 =t2 Ic /Cf1 = Qc /Cf1 , UAB = Uf1 = UH /2, the inductor L1 is UL - UAB < 0, the inductor current iL
flying capacitor Cf1 charge according to the differential equation Cf1 dUf1/dt = Ic, that is
decreases linearly, and the average inductor current is IL = Ic .
ΔUf1=t2Ic/Cf1 = Qc/Cf1, UAB = Uf1 = UH/2, the inductor L1 is UL - UAB < 0, the inductor current iL
decreases linearly, and the average .
inductor r current is IL = Ic.
 iL = − LL iL + L1 UL − L1 Uf
.


 U =− 1 U 1

. (3)

 iL. =H− rL iLR+H C1HU L H
 − Uf
1
 Uf = LC iL L

 L
 f
1
 H
U = − UH . (3)
3. Mode M3 = 11, S1 and S2 are turned  off, S RHC H S4 are turned on, the S1 and S2 voltage stresses
3 and
 1 is U =0, the voltage of the inductance L is U , and
are UH /2, the voltage of the two-point
 U f of
= AB iL AB 1 L

i flows to high voltage side and linearly Cfincrease, as shown in Equation (2).
L
4.
3. ModeM
Mode M32==11,10,S1Sand
2 andS2Sare
4 are turned
turned off, S3Sand
off, S4 Sare
1 and 3 are turned
turned on,on, S1 S
thethe 2 and
and S4 voltage
S2 voltage stresses
stresses are
Uare UH
H/2, /2,voltage
the flying capacitor Cf1 is discharged,
of the two-point of AB is U UAB =U
AB=0, H−
the Uf1 = U
voltage /2, the
ofHthe voltage across
inductance L1 is Uinductor
L, and iL
L1 is U
flows − UAB
toL high < 0, and
voltage sideiLand
flows to theincrease,
linearly high-pressure
as shownsideinand decreases
Equation (2). linearly. The column
4. differential equation can be obtained as:
Mode M2 = 10, S2 and S4 are turned off, S1 and S3 are turned on, the S2 and S4 voltage stresses are
UH/2, flying capacitor Cf1 is discharged,
 . r
UAB = UH − Uf1 = UH/2, the voltage across inductor L1 is UL
1 1 1
iL = − LL iL +
− UAB < 0, and iL flows to the high-pressure

side L + decreases
L Uand L Uf − L UHlinearly. The column differential
.


1 1

 U. H = CH iL − RH CH UH . (4)

equation can be obtained as:  
 U =−1i

f C L
 r
f
1 1 1
 iL = − L iL + U L + U f − U H
 L L L L

According to the duty cycle definition, 1 each 1equation group for the modal action time can be
listed during the switching period: U H = iL − UH . (4)
 CH RHCH
 1
t1 + t2 + t3U=f =DT
− s iL
 
t2 = (1 − D)Ts



C
 

 f 
t1 + t3 + t4 = DTs ⇒ t4 = (1 − D)Ts . (5)
 

 
 
According to the duty
 t +
1 cycle definition, each
t2 + t3 + t4 = Ts equation
 group
( for the
)
t1 + t3 = 2D − 1 Ts modal action time can be
listed during the switching period:
Electronics 2019, 8, 774 5 of 15

The inductance satisfies the volt-second balance condition:

UH 1
UL (2D − 1)Ts + (UL − UH /2)(2 − 2D)Ts = 0 ⇒ = . (6)
UL 1−D

2.2. Operational Modal Analysis D < 0.5

During the switching cycle, each arm has three modes of 00, 10, and 01.

1. Mode M0 = 00, S3 and S4 are turned off, S1 and S2 are turned on, the voltage of AB is UAB =
UH , S3 and S4 voltage stress are UH /2, the voltage of inductance L1 is UL − UH , iL flows to the
high-voltage side and decreases linearly, and the corresponding differential equation can be
expressed as:
 . r

 iL = − LL iL + L1 (UL − UH )
 .
UH = − R 1C UH

. (7)

 H H
 U. = 0



f

2. Mode M2 = 10, S2 and S4 are turned off, S1 and S3 are turned on, S2 and S4 voltage stress are UH /2,
Cf1 is discharging, UAB = UH − Uf1 = UH /2, the voltage across inductor L1 is UL − UAB >0, iL flows
to the high-voltage side and increases linearly, and the differential equation can be expressed as
Equation (4).
3. Mode M0 = 00, S3 and S4 are turned off, S1 and S2 are turned on, the voltage of AB is UAB = UH ,
S3 and S4 voltage stress are UH /2, inductance L1 voltage is UL − UH , iL flow to high voltage side
and the linearity is reduced, and the differential equation can be expressed as Equation (7).
4. Mode M1 = 01, S1 and S3 are turned off, S2 and S4 are turned on, S1 and S3 voltage stresses are
UH /2, flying capacitor Cf1 is charging, UAB = Uf1 = UH /2, the inductor voltage across L1 is UL −
UAB > 0, iL flows to the high-voltage side and increases linearly, and the differential equation can
be expressed as Equation (3). According to the duty cycle definition, each mode action time can
be expressed as:


 t2 = DTs

t4 = DTs . (8)




 t + t = (1 − 2D)T
1 3 s

The inductance satisfies the volt-second balance:

UH 1
2DTs (UL − UH /2) + (1 − 2D)Ts (UL − UH ) = 0 ⇒ = . (9)
UL 1−D

3. Multiple Modulation Technique

3.1. Two Arms Interleaved Parallel Modulation

Two arms are paralleled, as shown in in Figure 1b, to increase the overcurrent capability and
reduce the input side ripple. Arm 1 is composed of S1 -S4 , the inductor L1 and the flying capacitor Cf1 ;
and arm 2 is composed of S5 , S6 , S7 , S8 , the inductor L2 and the flying capacitor Cf2 . Among them,
S1 and S4 are turned on complementarily, S2 and S3 are turned on complementarily, the modulated
waves of S1 and S2 are interleaved 180◦ , and the S3 and S4 modulated waves are interleaved 180◦ , as
shown in Figure 3. Arm 2 is modulated in the same manner as arm 1 with a phase lag of 90◦ .
Two arms are interleaved 90◦ in parallel; eight modes are used at 0.5 < D < 0.75, and other eight
modes are used at 0.25 < D < 0.5. The working mode of the space ratio is shown in Table 1. In the
forward power flow (Boost mode), the inductor currents iL1 and iL2 are positive and flow from the
low voltage side to the high voltage side. When the negative power flows (Buck mode), the inductor
currents of iL1 and iL2 are negative, and the high voltage side flows to the low voltage side. The driving
signal between the two arms is interleaved 90◦ , and the other side bridge arm switch maintains the
 Two arms are interleaved 90° in parallel; eight modes are used at 0.5 < D < 0.75, and other eight
modes are used at 0.25 < D < 0.5. The working mode of the space ratio is shown in Table 1. In the
forward power flow (Boost mode), the inductor currents iL1 and iL2 are positive and flow from the
low voltage side to the high voltage side. When the negative power flows (Buck mode), the inductor
Electronics 2019, 8, 774 6 of 15
currents of iL1 and iL2 are negative, and the high voltage side flows to the low voltage side. The
driving signal between the two arms is interleaved 90°, and the other side bridge arm switch
maintains
original state thewhen
original
one state when one
side bridge arm side bridge arm
is operated. Afteristhe
operated.
inductorAfter theisinductor
current currentthe
superimposed, is
superimposed,
low-voltage side thecurrent is iL =side
low-voltage iL1 +current is iL = iL1
iL2 doubling the+ ipulsation
L2 doubling the pulsation
frequency, frequency,
and the and
ripple of thetheiL
ripple of
is reduced. the iL is reduced.

S3 S3
S4 S4
S7 S7
S8 S8
iL1 iL1
iL2 iL2
iL iL
t t
0 0 0 1 1 11 1 0 0 01 1 1 1 10 0 0 0 0 1 1 1 0 0
1 1 1 1 0 00 1 1 1 11 0 0 0 00 1 1 1 0 0 0 0 0 1
1 1 0 0 0 11 1 1 1 00 0 0 0 11 1 0 0 0 0 0 1 1 1
0 1 1 1 1 10 0 0 1 11 1 1 0 00 0 0 1 1 1 0 0 0 0

(a) 0.5<D<0.75 (b) 0.25<D<0.5

Figure 3. The main waveform of two parallel arms. (a) Mode 0.5 < D < 0.75, (b) Mode 0.25 < D < 0.5.
Figure 3. The main waveform of two parallel arms. (a) Mode 0.5 < D < 0.75, (b) Mode 0.25 < D < 0.5.
Table 1. Two arms interleaved parallel coding.
Table 1. Two arms interleaved parallel coding.
0~0.25 D = 0.25 0.25~0.5 D = 0.5 0.5~0.75 D = 0.75 0.75~1
0 ~ 0.25 D = 0.25 0.25 ~ 0.5 D = 0.5 0.5 ~ 0.75 D = 0.75 0.75 ~ 1
0000 0010 1010 1010 0101 1101 1111
0000 0010 1010 1010 0101 1101 1111
0010 0010 0010 1010 1101 1101 1101
0010 0010 0010 1010 1101 1101 1101
0000 0100 0110 0110 1001 1011 1111
0000
0100 0100
0100 0110
0100 0110
0110 1001
1011 1011
1011 1111
1011
0100
0000 0100
0001 0100
0101 0110
0101 1011
1010 1011
1110 1011
1111
0000
0001 0001
0001 0101
0001 0101
0101 1010
1110 1110
1110 1111
1110
0001
0000 0001
1000 0001
1001 0101
1001 1110
0110 1110
0111 1110
1111
0000
1000 1000
1000 1001
1000 1001 0110
0111 0111 1111
0111
1000 1000 1000 1001 0111 0111 0111

Then the inductor

inductor current
currentisissuperimposed,
superimposed,the thelow-voltage
low-voltagesidesidecurrent
current iL i=
is is L = iL1++ iiL2
iL1 L2 doubling

the pulsation frequency,

frequency, and
andthe
theripple
rippleof theiLiLisisreduced.
ofthe reduced.According
AccordingtotoEquations
Equations(2)–(9),
(2–9), the ripple
current of three-level bi-directional DC/DC(3L-BDC)
DC/DC(3L-BDC) in in Figure 1b, ∆I
Figure 1b, ΔIL1_3L_LBDC , can
L1_3L_LBDC, can bebe calculated
calculated asas
 (U(UHH− 2ULL)()(1−D
1 − )D )
( D>0.5
0.5))
−2U


2L f , , (D
∆IL1_3L_BDC = 

 (2U −U 2 L1 fs
1 s
. (10)
I L1_ 3L _ BDC =
 L H ) D
(D ≤ 0.5) . (10)
( 2U 2L− Ufs ) D,


L 1 H
, ( D  0.5)
 2 L1 fs
Correspondingly, the ripple current of the inductor of two-level bidirectional DC/DC (2L_ BDC)
can be calculated as
Correspondingly, the ripple current of the inductor of two-level bidirectional DC/DC (2L_
( UH − UL ) D
BDC) can be calculated as ∆IL1_2L_BDC = . (11)
L1 fs
I L1_ = H L (U −U )D
To reduce currents ripple, n arms can2L _be
BDCcascaded, and. the drive signals between the arms (11)
L1 f s
are interleaved 180◦ /n. The more arms that participate in interleaved parallel connection, the more
To reduce
obvious currents
the ripple ripple,effect,
reduction n armsandcan thebemore
cascaded, and the drive
characteristic pointssignals
of zerobetween the arms
ripple appear at are
the
interleaved 180°/n.zero
same time—these Theripple
morepoints
arms show
that participate in interleaved
a uniform distribution law.parallel connection, the
The aforementioned more
analysis
shows that the voltage stress on the switches and the flying capacitors of the 3L_BDC is half of UH ,
which is just half of the traditional 2L_BDC. To reduce the voltage stress, it is necessary to employ a
series connection.
obvious the ripple reduction effect, and the more characteristic points of zero ripple appear at the
same time—these zero ripple points show a uniform distribution law. The aforementioned analysis
shows that the voltage stress on the switches and the flying capacitors of the 3L_BDC is half of UH,
which is just half of the traditional 2L_BDC. To reduce the voltage stress, it is necessary to employ
Electronics 2019, 8, 774
a
7 of 15
series connection.

3.2. Two
3.2. Two Arms
Arms Complementary
Complementary Series
Series Modulation
Modulation
The topology
The topology is is connected
connected in in series
series with
with two
two inductors
inductors to to reduce
reduce the the inductor
inductor current
current ripple
ripple
amplitude; the
amplitude; thelowlowvoltage
voltagesideside is isolated
is isolated fromfrom the output
the output side byside
twoby two inductors,
inductors, which can which
improvecan
improve the energy storage unit safety; the series structure can reduce the
the energy storage unit safety; the series structure can reduce the voltage stress of the switches and voltage stress of the
switchesthe
increase and increase
voltage theofvoltage
level the DBC, level of the in
as shown DBC,
Figure as 1c.
shownThe in Figurecurrent
inductor 1c. Thewaveform
inductor current
during
waveform during
complementary complementary
modulation is shown modulation
in Figure 4.is Sshown
4 and Qin1 Figure
are the 4.
sameS 4 and
driveQ are
signal,
1 the
S3 same
and Qdrive
2 are
signal,
the same S3 drive
and Qsignal,
2 are theS2same
and Q drive
3 aresignal,
the same S2 and
driveQ3signal,
are theandsameS1 drive
and Qsignal, and
4 are the S1 and
same Q4 are
drive the
signal;
sameis,drive
that signal;modulation
the switch that is, theisswitch
based on modulation
the topology.is based on the topology.
The switching The switching
period inductance period
fluctuation
inductanceis fluctuation
frequency equal to twice frequency is equalfrequency,
of the switching to twice the of inductance
the switching frequency,
fluctuation the inductance
amplitude is half of
fluctuation
that amplitude
of the single submodule,is half of remaining
and the that of the modesingle submodule,series
complementary and modulation
the remaining is shownmodein
complementary
Table 2. series modulation is shown in Table 2.

S3 S3
S4 S4
Q3 Q3
Q4 Q4
iL iL
t t
0 1 1 1 0 11 1 0 0 0 1 00
1 1 0 1 1 10 0 0 1 0 0 01
1 0 0 0 1 00 0 1 1 1 0 11
0 0 1 0 0 01 1 1 0 1 1 10
(a) 0.5<D<0.75 (b) 0.25<D<0.5

Figure4.4.The
Figure Thekey
keywaveform
waveformofoftwo
twoarms
armsseries.
series.(a)
(a)Mode 0.5<<DD<< 0.75,
Mode0.5 0.75, (b)
(b) Mode 0.25 <
Mode 0.25 <DD << 0.5.
0.5.

Table 2. Two arms complementary series coding.

The voltage stress on the switches and the flying capacitors is 0.25 UH in Figure 1c. In order to
reduce the voltage0~0.25
and current0.25stress,
0.25~0.5 0.5 to 0.5~0.75
it is necessary 0.75
increase the series 0.75~1
and parallel bridge arms
simultaneously. The ripple current
00/11 00/11 of L 1 in Figure
00/11 1c, ΔIL1_3L_LBDC
01/10 11/00 , can be calculated
11/00 11/00 as
01/1001/10 01/10 10/01 10/01 10/01 10/01
00/1100/11 00/11  (U H01/10
− 2U L )(1 −11/00
D)
(  0.5 )
11/00 11/00
 , D
10/0110/01 10/01  210/01( L1 + L3 ) fs01/10 01/10 01/10
I L1_ 3L _ BDC =  . (12)
 ( 2U L − U H ) D ,
 2( L + L ) f ( D  0.5)
The voltage stress on the switches andthe flying
1 3 capacitors
s is 0.25 U
in Figure 1c. In order to
H
reduce the voltage and current stress, it is necessary to increase the series and parallel bridge arms
simultaneously. The ripple current of L1 in Figure 1c, ∆IL1_3L_LBDC , can be calculated as
Table 2. Two arms complementary series coding.

(UH −2UL )(1−D)
0 ~ 0.25 0.25 0.25 ~ 0.5 2(L0.5
 (D > 0.5
0.5 ,~ 0.75 0.75) 0.75 ~ 1
1 + L 3 ) fs
∆I

00/11 00/11 =
00/11 (2U01/10
−U )D 11/00 . 11/00 (12)
(D ≤11/00
L1_3L_BDC 
 2(LL +L H) f , 0.5)


s
01/10 01/10 01/10 10/01
1 3 10/01 10/01 10/01
00/11 00/11 00/11 01/10 11/00 11/00 11/00
3.3. Four Arms Mixed Modulation
10/01 10/01 10/01 10/01 01/10 01/10 01/10
To meet the large-capacity requirements in the bipolar DC bus, the voltage and current stress of
the
3.3.switching
Four Armstube should
Mixed be reduced, so a four-arms mixed converter is proposed, that is, the cascaded
Modulation
form of the interleaved parallel flying-capacitor type three-level converter, as shown in Figure 1d. The
To meet the large-capacity requirements in the bipolar DC bus, the voltage and current stress of
left and right parallel arms are interleaved 90◦ parallel modulation, and the upper and lower series
the switching tube should be reduced, so a four-arms mixed converter is proposed, that is, the
arms are complementarily connected in series. For example, when 0.5 < D < 0.75, in mode 0101/1010,
cascaded form of the interleaved parallel flying-capacitor type three-level converter, as shown in
it means S3 is off, S4 is on, S7 is off, S8 is on; while, Q3 is on, Q4 is off, Q7 is on, and Q8 is off. The
modulation rule of the BDC is shown in Figure 5.
Electronics 2019, 8, x FOR PEER REVIEW 8 of 15

Figure 1d. The left and right parallel arms are interleaved 90° parallel modulation, and the upper
and lower series arms are complementarily connected in series. For example, when 0.5 < D < 0.75, in
mode 0101/1010,
Electronics 2019, 8, 774it means S3 is off, S4 is on, S7 is off, S8 is on; while, Q3 is on, Q4 is off, Q7 is on, and
8 ofQ
158
is off. The modulation rule of the BDC is shown in Figure 5.

S3 S3
S4 S4
S7 S7
S8 S8
Q3 Q3
Q4 Q4
Q7 Q7
Q8 Q8
iL1 iL1
iL2 iL2
iL iL
t t
0 0 0 1 1 11 1 0 0 0 1 1 1 1 1 0 0 00 0 1 11 0 0
1 1 1 1 0 00 1 1 1 1 1 0 0 0 0 0 1 11 0 0 00 0 1
1 1 0 0 0 11 1 1 1 0 0 0 0 0 1 1 1 00 0 0 01 1 1
0 1 1 1 1 10 0 0 1 1 1 1 1 0 0 0 0 01 1 1 00 0 0
1 1 1 0 0 00 0 1 1 1 0 0 0 0 0 1 1 11 1 0 00 1 0
0 0 0 0 1 11 0 0 0 0 0 1 1 1 1 1 0 00 1 1 11 1 1
0 0 1 1 1 00 0 0 0 1 1 1 1 1 0 0 0 11 1 1 10 0 1
1 0 0 0 0 01 1 1 0 0 0 0 0 1 1 1 1 10 0 0 11 1 0
(a) 0.5<D<0.75 (b) 0.25<D<0.5

Figure 5. The
Figure 5. The key
key waveform
waveform of
of the
thefour
fourarms
armsmixed.
mixed.(a)
(a)Mode 0.5<<D
Mode0.5 D<< 0.75,
0.75, (b)
(b) Mode 0.25<< D
Mode0.25 D< 0.5.
< 0.5.

By mixed modulation,
By mixed the average
modulation, inductor
the average current
inductor is only
current half half
is only of the
of single-arm current,
the single-arm the
current,
ripple doubled, the flying capacitor voltage is 0.25 U
the ripple frequency is doubled, the flying capacitor voltage is 0.25 UH, and the voltage stressthe
frequency is H , and the voltage stress of of
switch is only 0.25 U H compared to the 2L_BDC. The modulation is shown in
the switch is only 0.25 UH compared to the 2L_BDC. The modulation is shown in Table 3. ToTable 3. To compare the
characteristics
compare the of the structure, shown
characteristics in structure,
of the Figure 1, the voltage
shown in and current
Figure 1, thestress conditions
voltage are listed
and current in
stress
Tableconditions
3, and the four arms mixed modulation is more suitable for bipolar high-power applications.
are listed in Table 3, and the four arms mixed modulation is more suitable for bipolar This
modulation strategy helps to control
high-power applications. and protect the
This modulation designhelps
strategy of thetocircuit.
control A and
topological
protectcomparison
the design ofof
the proposed BDC
the circuit. in this paper
A topological with othersofare
comparison theshown in Table
proposed BDC4.in this paper with others are shown
in Table 4.
Table 3. Four arms mixed modulation coding.

0~0.25 D = 0.25 Table 3. Four arms D

0.25~0.5 mixed
= 0.5modulation coding. D = 0.75
0.5~0.75 0.75~1
0000/1111
0 ~ 0.25 D =0010/1101
0.25 1010/0101
0.25 ~ 0.5 1010/0101
D = 0.5 0101/1010
0.5 ~ 0.75 1101/0010
D = 0.75 1111/0000
0.75 ~ 1
0010/1101
0000/1111 0010/1101
0010/1101 0010/1101
1010/0101 1010/0101
1010/0101 1101/0010
0101/1010 1101/0010
1101/0010 1101/0010
1111/0000
0000/1111
0010/1101 0100/1011
0010/1101 0110/1001
0010/1101 0110/1001
1010/0101 1001/0110
1101/0010 1011/0100
1101/0010 1111/0000
1101/0010
0100/1011
0000/1111 0100/1011
0100/1011 0100/1011
0110/1001 0110/1001
0110/1001 1011/0100
1001/0110 1011/0100
1011/0100 1011/0100
1111/0000
0000/1111 0001/1110 0101/1010 0101/1010 1010/0101 1110/0001 1111/0000
0100/1011 0100/1011 0100/1011 0110/1001 1011/0100 1011/0100 1011/0100
0001/1110 0001/1110 0001/1110 0101/1010 1110/0001 1110/0001 1110/0001
0000/1111 0001/1110 0101/1010 0101/1010 1010/0101 1110/0001 1111/0000
0000/1111 1000/0111 1001/0110 1001/0110 0110/1001 0111/1000 1111/0000
0001/1110
1000/0111 0001/1110
1000/0111 0001/1110
1000/0111 0101/1010
1001/0110 1110/0001
0111/1000 1110/0001
0111/1000 1110/0001
0111/1000
0000/1111 1000/0111 1001/0110 1001/0110 0110/1001 0111/1000 1111/0000
1000/0111 1000/0111 1000/0111 1001/0110 0111/1000 0111/1000 0111/1000
4. Controller design
Define the state variable as x = [ iL , UH , Uf ]T , the input variable as u = UL , the transfer function
as Gid (s) from the duty cycle d to the inductor current iL and the transfer function Gud (s) from the duty
cycle d to the output voltage UH , according to Equations (2)–(9).

UL CH RH 2UL
1−D s + 1−D
Gid (s) = , (13)
CH LRH s2 + Ls + RH (1 − D)2 + rL

LUL rL UL
− s + RH UL −
(1−D)2 (1−D)2
Gud (s) = 2
, (14)
CH LRH s2 + Ls + RH (1 − D) + rL
where, RH is Rload , and rL is the inductance parasitic resistance.
Electronics 2019, 8, 774 9 of 15

The main circuit parameters of the converter are shown in Table 5. Due to the inconsistent
impedance of the IGBT parasitic parameters and the inductor winding process, the main loop has a
certain degree of impedance difference. The controller’s PI regulator is Gc (s) = k1 + k2 /s, where k1 = 0.1,
2 = 50, and
kElectronics 2019,the
8, xcontrol
FOR PEER REVIEW
block diagram is shown in Figure 6. 10 of 15

The main circuit parameters ofTable the 4.

converter arecomparison.
Topological shown in Table 5. Due to the inconsistent
impedance of the IGBT parasitic parameters and the inductor winding process, the main loop has a
(a) Comparison in terms of passive component and out gain, inductor ripple current and switching
certainfrequency.
degree of impedance difference. The controller's PI regulator is Gc(s) = k1 + k2/s, where k1 = 0.1,
k2 = 50, and the control block diagram is shown in Figure 6.
Number of
Proposed Gain of Voltage ∆iL f∆iL
Elements
Table 5. The Parameters
(UH −2UL )D
2UL of BDC.
SC [23] C=3S=4L=1 2L fs
1−D
fs
UH (1−D)D UParameters
Double Buck/Boost [24] C = 3 S = 4 L = 2 Value
Parameters Value L fs
L
1−D
2f s

UL / V 150~220 CL / μF   (UH220−2UL )(1−D)
, ( D > 0.5 )
UL 2L1 fs
C =U3HS/ = V 4 L = 1 400

Basic FC [5] 2f s

1−D CH / μF  (2UL110−UH )D
, (D ≤ 0.5)


2L 1 fs

Po / kW 1 Cf1 / μF  110
(UH −2UL )(1−D)
, (D > 0.5)

L1=~ 4L2S/ =mH 2 UL Cf2 / μF  110

2L1 fs
8L=2

Interleaved FC [7] C 1−D  (2UL −UH )D
 4f s
rL / Ω 0.2 fs / kHz  2L20
1 f s
, (D ≤ 0.5)

(UH −2UL )(1−D)
UL


2(L1 +L3 ) fs
, (D > 0.5)
C=5S=8L=2

Complementary FC [21] 2f s

The Bode diagram of the proposed control strategy 1−D by a single
 (2ULvoltage
−UH )D
 2(L +L ) f ,

 loop,
(D ≤as0.5
shown
) in Figure
1 3 s
6c. The low frequency range is 30 dB, the high frequency band traverses 0 dB with a slope of −20

( U −2U )( 1−D )
UL

 H L
2(L1 +L3 ) fs
, (D > 0.5)
= = =

This paper C 7 S 16 L 4 4f

dB/dec, and the corner frequency is 120 Hz. The gain1−D crossover frequency
 (2UL −UH )D is 4 kHz, the phase margin
, (D ≤ 0.5)
s
2(L1 +L3 ) fs
is 90°, and the system is stable; however, the gain is higher than 0dB at 0.1 times of switching
(b) Comparison in terms of out capacitor, flying capacitor voltage, voltage across switch, inductor current
frequency. The current inner loop uses inductor current feedback, as shown in Figure 6d. The PI
and fault tolerant capabilities
regulator is Gc(s) = 0.1 + 50/s, the crossing frequency of the open-loop transfer function is 449 Hz
Output Capacitor Flying capacitor Switch Inductor Fault
when crossing Proposed.
the 0 dB line, and Voltage
the phase marginvoltage is 70° at the Voltage
crossing frequency.
Current It Tolerance
can be judged
that the closed loop system is stable.
SC [23] A first-order
2 UL /(1-D) 0.5low-pass
UH filter
0.5 Uis
H
added ItoL
the loop due to the
Weak
influence of high
Double frequency
Buck/Boost [24] noise. /(1-D)cutoff frequency
ULThe No of the first-order
0.5 UH low-pass
IL filter Weak
(ωc = 2πfc) is
Basic FC [5] UL /(1-D) 0.5 UH 0.5 UH IL Weak
set at 0.1 times the switching frequency, and the gain margin kg (f c = 2 kHz) is 13.4 dB, which is ideal.
Interleaved FC [7] UL /(1-D) 0.5 UH 0.5 UH 0.5 IL Average
The pole introducedFCby
Complementary the first-order
[21] UL /(2-2D)LPF is far from
0.25 Uthe
H
real axis,
0.25 Uand
H
has little
IL effect on the bode
Average
diagram and can
This be ignored. UL/(2-2D)
paper 0.25 UH 0.25 UH 0.5 IL Strong

uref d uH uref d uH
+− k1+k2/s 1/Vm Gud(s) +− k1+k2/s +− 1/Vm Gud(s)
Gc(s) Gpwm=1 iL
Gid(s)

(a) Single voltage loop (b) Double voltage and current loop
80 60
Magnitude (dB)

(120Hz, 60dB) (120Hz, 41.4dB)

Magnitude (dB)

60 40
40 20
20 (2kHz, 7dB) 0 (2kHz, -13.4dB)
0 -20
-20 -40
45 45
Phase (deg)

Phase (deg)

0 0
-45
-45 (449Hz, -110°)
(2kHz, -93°) -90
-90 -135 (2kHz, -95°)
(4kHz, -90°)
-135 -180
101 102 103 104 HZ 101 102 103 104 HZ
(c) Without current loop control (d) With current loop control

Figure 6. The control strategy. (a) & (c) are single voltage loop and its Bode without current loop
Figure 6. The control strategy. (a) & (c) are single voltage loop and its Bode without current loop
control. (b) & (d) are double voltage-current loop and its Bode with current loop control.
control. (b) & (d) are double voltage-current loop and its Bode with current loop control.
The Bode diagram of the proposed control strategy by a single voltage loop, as shown in Figure 6c.
5. Experimental result
The low frequency range is 30 dB, the high frequency band traverses 0 dB with a slope of −20 dB/dec,
Thecorner
and the experimental
frequencyplatform is shown
is 120 Hz. in Figure
The gain 7. Infrequency
crossover the platform, the DC
is 4 kHz, the power supply is
phase margin E 90 ◦,
and
resistance R are used to simulate the power generation change of the renewable energy source. The
rated voltage of the DC power supply E is 450 V, and the DC bus voltage rating is 400 V. Super
capacitor rated voltage is 250 V, rated capacity is 10 F, maximum discharge current is 15 A, charging
current is 10 A, super capacitor voltage UL range is 150 ~ 220 V; switching frequency fs is 20 kHz. DC
power supply Chroma 62050H-600 (Chroma Systems Solutions, Inc., Foothill Ranch, CA, USA), DC
Electronics 2019, 8, 774 10 of 15

and the system is stable; however, the gain is higher than 0dB at 0.1 times of switching frequency.
The current inner loop uses inductor current feedback, as shown in Figure 6d. The PI regulator is
Gc (s) = 0.1 + 50/s, the crossing frequency of the open-loop transfer function is 449 Hz when crossing the
0 dB line, and the phase margin is 70◦ at the crossing frequency. It can be judged that the closed loop
system is stable. A first-order low-pass filter is added to the loop due to the influence of high frequency
noise. The cutoff frequency of the first-order low-pass filter (ωc = 2πfc) is set at 0.1 times the switching
frequency, and the gain margin kg (f c = 2 kHz) is 13.4 dB, which is ideal. The pole introduced by the
first-order LPF is far from the real axis, and has little effect on the bode diagram and can be ignored.

Table 5. The Parameters of BDC.

Parameters Value Parameters Value

UL /V 150~220 CL /µF 220
UH /V 400 CH /µF 110
Po /kW 1 Cf1 /µF 110
L1 ~L2 /mH 2 Cf2 /µF 110
rL /Ω 0.2 f s /kHz 20

5. Experimental result
The experimental platform is shown in Figure 7. In the platform, the DC power supply E and
resistance R are used to simulate the power generation change of the renewable energy source. The
rated voltage of the DC power supply E is 450 V, and the DC bus voltage rating is 400 V. Super
capacitor rated voltage is 250 V, rated capacity is 10 F, maximum discharge current is 15 A, charging
current is 10 A, super capacitor voltage UL range is 150~220 V; switching frequency f s is 20 kHz.
DC power2019,
Electronics supply Chroma
8, x FOR 62050H-600 (Chroma Systems Solutions, Inc., Foothill Ranch, CA, USA),
PEER REVIEW 11 of 15
DC probe YOKOGAWA 701934 (Yokogawa Electric, Inc., Tokyo, Japan), oscilloscope Tek DPO2024B
(Tektronix,
(Tektronix, Inc., Beaverton,
Inc., Beaverton, OR,
OR,USA).
USA). TheThe control chip
control chipuses DSP
uses DSP(TMS28335)
(TMS28335) combined
combinedwith withFPGA
FPGA
(EP3C25Q240); DSP is used for signal sampling and control signal generation,
(EP3C25Q240); DSP is used for signal sampling and control signal generation, and FPGA is used and FPGA is used toto
generate
generatethe themodulated
modulated wave.
wave.ToTo test thethe
test feasibility of of
feasibility multiple
multipleapplications,
applications, super
super capacitor
capacitorULU=L =
200V, high side load R = 200 Ω, adjustable power supply E = 450 V, resistance
200V, high side loadHRH = 200 Ω, adjustable power supply E = 450 V, resistance R = 10 Ω; during R = 10 Ω; during
switch
switch S disconnection,
S disconnection, super capacitor
super capacitor discharge,
discharge,converter
converter operates
operates ononboost
boost < <D D
0.50.5 < <0.75
0.75mode,
mode,
the high
the highside capacitor
side capacitor voltage is is
voltage stable
stable UHU=
to to 400
H = 400V.V.
Super
Supercapacitor
capacitorULU= 250
L = 250V,V,high-voltage-side
high-voltage-side
load
loadRHRH==200 200Ω,Ω,adjustable
adjustablepower supplyEE==450
powersupply resistanceR R= =1010Ω;Ω;during
450V,V,resistance switchS Sclosing,
duringswitch closing,
super
super capacitor
capacitor charging.
charging.

Q2Q3 Q1Q4 Q6Q7 Q5 Q8

arm 3 arm 1
arm 4 arm 2

S3 S2 S4 S1 S7 S6 S8 S5

BI-DC/DC UH(udc) − − − −
+

+
+

c
s +c W2 W3180°W4
W1180°
iL1 90°
DC Load
uref +− k1+k2/s +−
S +− fs=20 kHz
Super-capacitor iL2
(a) System photo (b) Control System

Figure Experimental
7. 7.
Figure setup.
Experimental (a)(a)
setup. The experimental
The system,
experimental (b)(b)
system, Control system
Control logic.
system logic

InIn
the project,
the due
project, toto
due the inconsistent
the IGBT
inconsistent IGBTparasitic parameters
parasitic parameters and
andthe inconsistent
the inconsistentimpedance
impedance
caused by the inductor winding process, the main loop objectively has impedance differences.
caused by the inductor winding process, the main loop objectively has impedance differences.
The
Thevoltage and
voltage current
and double
current closed-loop
double PI regulators
closed-loop are used
PI regulators for impedance
are used matching.
for impedance The
matching.
two control loops share the voltage outer loop, and the current inner loop uses respective
The two control loops share the voltage outer loop, and the current inner loop uses respective inductor
inductor current feedback. The control loop is shown in Figure 7b. The difference in the modulation
signals generated by the control loop adjusts the respective output impedances to achieve current
sharing control. The left and right arms are interleaved 90° parallel, the two inductor current ripples
cancel each other, and the output voltage is stable, as shown in Figures 8 and 9. The current iL
fluctuating frequency is twice of the switching frequency, and the inductor current fluctuation
 (a) System photo (b) Control System

Figure 7. Experimental setup. (a) The experimental system, (b) Control system logic

In the project, due to the inconsistent IGBT parasitic parameters and the inconsistent impedance
caused
Electronics 2019,by the inductor winding process, the main loop objectively has impedance differences.
8, 774 11 of 15
The voltage and current double closed-loop PI regulators are used for impedance matching.
The two control loops share the voltage outer loop, and the current inner loop uses respective
inductor
current current
feedback. Thefeedback.
controlThe
loopcontrol loop is
is shown inshown
Figurein7b.
Figure
The7b. The difference
difference in theinmodulation
the modulationsignals
signalsby
generated generated by the
the control loopcontrol
adjustsloop adjusts
the the respective
respective output output impedances
impedances to achieve
to achieve current
current sharing
sharing
control. control.
The left The left
and right andare
arms right arms are interleaved
interleaved 90°the
90◦ parallel, parallel, the two inductor
two inductor current ripples
current ripples cancel each
cancel each other, and the output voltage is stable, as shown in Figures 8 and 9. The current iL
other, and the output voltage is stable, as shown in Figures 8 and 9. The current iL fluctuating frequency
fluctuating frequency is twice of the switching frequency, and the inductor current fluctuation
is twice of the switching frequency, and the inductor current fluctuation amplitude is reduced, due to
amplitude is reduced, due to iL through two inductors evenly. Two arms series, the flying capacitor
iL through two inductors evenly. Two arms series, the flying capacitor voltage is 0.25 U , as shown in
voltage is 0.25 UH, as shown in Figure 10. The inductor current ripple is small, and Hthe flying
Figurecapacitor
10. Thevoltage
inductor current
is equal UH. is small, and the flying capacitor voltage is equal to 0.25 UH .
ripple
to 0.25

(1-D)Ts DTs
S3
90°
S7
iL1
iL2
1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0
1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1
0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0
1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1

(a) Boost mode without circumferential inhibition

(1-D)Ts DTs
S3
S7 90°
1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0
0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0
0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0
1 0 0 0 0 0 1 1 1 0 0 0 0 0 1 1
iL2
iL1
Electronics 2019, 8, x FOR PEER REVIEW 12 of 15
(b) Buck mode without circumferential inhibition
Figure
Figure 8. Left
8. Left andand right
right arms
arms interleaved90º
interleaved 90º parallel without
parallel withoutcircumferential
circumferentialinhibition. (a) Boost
inhibition. (a) Boost
mode. (b) Buck
mode. (b) Buck mode. mode.

(1-D)Ts DTs
S3 90°
S7
iL2 iL1
1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0
1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1
0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0
1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1

(a) Boost mode with circumferential inhibition

(1-D)Ts DTs
S3
S7 90°
1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0
0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0
0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0
1 0 0 0 0 0 1 i1L2 1 0 0 0 0 0 1 1

iL1

(b) Buck mode with circumferential inhibition

Figure 9. Left
Figure andand
9. Left right arms
right interleaved
arms interleaved90º
90ºparallel withcircumferential
parallel with circumferential inhibition.
inhibition. (a) Boost
(a) Boost mode,mode,
(b) Buck
(b) Buck mode.
mode.

(1-D)Ts charging
Switch S is turned on at tON, and the supercapacitor DTspower is 800 W in buck mode. Switch S is
S3
turned off at tOFF, and the supercapacitor discharging power isU1200
H W in boost mode, as shown in Figure 11.
Ucf1=0.25UH
The dynamic response time is less than 20 ms from charging to discharging. The dynamic response time is
iL>0
1 1 1 0 1 1 1 0
1 0 1 1 1 0 1 1

(a) Boost mode

 1 0 0 0 1 1 1 1 1 0 0 0 1 1 1 1
0 0 1 1 1 1 1 0 0 0 1 1 1 1 1 0
1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1

(a) Boost mode with circumferential inhibition

Electronics 2019, 8, 774 (1-D)Ts DTs 12 of 15
S3
S7 90°
1 1 1 0 0 0 0 0
400 ms from discharging to charging in the four-arms mixed1 1 0 0The
1 modes. 0 0capacitor voltage is always
0 flying
0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0
stable, and the DC bus voltage fluctuation is less than 20 V. The input voltage varies between 150–220 V, the
0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0
output voltage is stable at 14000V, and
0 0 the0 change
0 1 range of D is 0.63–0.45. From the experimental results in
i1L2 1 0 0 0 0 0 1 1
Figures 8–11, it can be seen that the input and output side voltage ripple is less than 1%, and the current
ripple frequency is relatively small, which is beneficial
iL1 to the stable operation of the energy storage unit.
When Q7 shorted, iL4 ripple is only once per cycle, losing the advantage of three levels. However, the overall
performance of the converter remains stable,
(b) Buck modeand the
with input and output
circumferential voltage ripples are low, as shown in
inhibition
Figure 12. Therefore, the BDC has a strong fault tolerance ability, and failure of any one of the arms does not
Figure 9. Left and right arms interleaved 90ºparallel with circumferential inhibition. (a) Boost mode,
affect the operation of other arms.
(b) Buck mode.

(1-D)Ts DTs
S3
UH
Ucf1=0.25UH
iL>0
1 1 1 0 1 1 1 0
1 0 1 1 1 0 1 1
Electronics 2019, 8, x FOR PEER REVIEW 13 of 15

input voltage varies between 150–220 V, the (a)output voltage is stable at 400 V, and the change range
Boost mode
of D is 0.63–0.45. From the experimental results in Figures 8–11, it can be seen that the input and
(1-D)Ts DTs
output side voltage ripple is less than 1%, andS3 the current ripple frequency is relatively small, which
is beneficial to the stable operation of the energy storage UHunit. When Q7 shorted, iL4 ripple is only
Ucf1=0.25UH
once per cycle, losing the advantage of three levels. However, the overall performance of the
1 1 1 0 1 1 1 0
converter remains stable, and the input and output voltage ripples are low, as shown in Figure 12.
1 0 1 1 1 0 1 1
Therefore, the BDC has a strong fault tolerance ability, and failure of any one of the arms does not
iL<0
affect the operation of other arms.
The efficiency is reduced, due to the inherent loss increase with a light load. Since there is a
dead time of 1.5 µ s when the converter is actually running, energy can be transferred from the low
voltage side to the high voltage side through (b) the
BuckIGBT
modebody diode during dead time, as shown in
Figure 13. Thus, the boost mode efficiency is higher than the buck mode. The efficiency curve is
Figure
more than 90%Figure
from 10.10.Two
light Two
loadarms complementary
to heavy
arms series.
load, meeting
complementary (a)
(a) Boost
design
series. mode,
mode,(b)
(b)Buck
requirements.
Boost Buckmode.
mode.

Switch S is turned on at tON, and the supercapacitor charging power is 800 W in buck mode.
UH1
Switch S is turned off at tOFF, and the supercapacitor
Ucf1=0.5Udischarging power is 1200 W in boost mode, as
H1
shown in Figure 11. The dynamic Discharging
responseiL time is less than 20 ms from charging to discharging. The
dynamic response time is 400 ms from discharging to charging in the four-arms mixed modes. The
flying capacitor voltage is always stable, and itheL1=0.5i
DCL bus voltage fluctuation is less than 20 V. The
Charging iL
Discharging Charging Discharging

(a) Two arms parallel

UH
ΔUH<40V Ucf1=0.25UH

Charging iL Discharging iL

Charging Discharging Charging

(b) Two arms series

Figure Transient
11.11.
Figure Transientresponse
responsefor
forbidirectional
bidirectional operation. (a)Two
operation. (a) Twoarms
armsinterleaved
interleaved parallel
parallel transient
transient
response,
response,(b)(b)
Two arms
Two armscomplementary
complementaryseries
series transient response.
transient response.

S3
 (b) Two arms series

Figure 11. Transient response for bidirectional operation. (a) Two arms interleaved parallel transient
response, (b) Two arms complementary series transient response.
Electronics 2019, 8, 774 13 of 15

S3

S7
UL
UH

iL3
iL4

Figure 12. Switch Q7 short circuit experiment.

The efficiency is reduced, due to the inherent loss increase with a light load. Since there is a dead
time of 1.5 µs when the converter is actually running, energy can be transferred from the low voltage
side to the high voltage side through the IGBT body diode during dead time, as shown in Figure 13.
Electronics 2019, 8, x FOR PEER REVIEW 14 of 15
Thus, the boost mode efficiency is higher than the buck mode. The efficiency curve is more than 90%
from light load to heavy load, meeting design
Figure 12. Switchrequirements.
Q7 short circuit experiment.

96
Efficiency (%)

94

92 Boost: UH=400V
Buck: UH=400V
90
100 200 400 600 800 1000 1200
Power (W)
Figure 13.13.The
Figure Theefficiency
efficiency curves.
curves.

6. Conclusions
6. Conclusions
This paper
This paper proposes
proposes a BDCa BDC topology
topology witha amultiplexed
with multiplexed modulation
modulationstrategy
strategyforfor
high-power
high-power
energy storage in bipolar DC microgrids. The parallel arms divide the input side current,can
energy storage in bipolar DC microgrids. The parallel arms divide the input side current, which which
effectivelyovercome
can effectively overcome thethecurrent
currentdifference
difference caused by the
caused inconsistent
by the parasitic
inconsistent parameters
parasitic of the of
parameters
parallel arms. The series arms divide the voltage of the high voltage side, which can effectively
the parallel arms. The series arms divide the voltage of the high voltage side, which can effectively
reduce the voltage stress of the switch and the flying capacitor. The bidirectional transient response
reduce the voltage stress of the switch and the flying capacitor. The bidirectional transient response
is milliseconds, which ensures the dynamic performance and operating efficiency of the converter.
is milliseconds, which ensures the dynamic performance and operating efficiency of the converter.
The BDC has a strong fault tolerance ability, and the failure of any one of the arms does not affect the
The BDC has a strong
operation of otherfault
arms.tolerance ability,BDC
The proposed andtopology
the failure
andofitsany one of thestrategy
modulation arms does not affect the
can effectively
operation
solveofthe
other
issuearms. The proposed
of high-power energyBDC topology
storage andDC
in bipolar itsmicrogrids.
modulation strategy can effectively solve
the issue of high-power energy storage in bipolar DC microgrids.
Author Contributions: P.L. designed the prototype and was responsible for writing the paper. C.Z., S.P. and
L.Z. were responsible for guidance in the experiment and thesis writing process.
Author Contributions: P.L. designed the prototype and was responsible for writing the paper. C.Z., S.P. and L.Z.
were responsible for research
Funding: This guidancewas
in the experiment
supported and
by the thesis writing
National process.
Nature Science Foundation of China under Grants
51477148 and the Science Foundation of Hebei University of Science and technology Grants PYB2019011. This
Funding: This research was supported by the National Nature Science Foundation of China under Grants 51477148
and theresearch
Sciencealso received funding from EEEIC International, Poland.
Foundation of Hebei University of Science and technology Grants PYB2019011. This research also
received funding from EEEIC
Conflicts of Interest: The International,
authors declarePoland.
no potential conflict of interest.
Conflicts of Interest: The authors declare no potential conflict of interest.
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