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BOOT BLOCK FLASH MEMORY

TECHNICAL BOOT BLOCK FLASH

NOTE MEMORY TECHNOLOGY

This article was originally published in 1995. AUTOMATED WRITE AND ERASE
One feature that many current-generation flash
INTRODUCTION devices have is an on-chip state machine that auto-
Flash memory is a programmable, read-only, non- mates WRITE and ERASE. First-generation flash and
volatile memory similar to EPROM and EEPROM. Al- EPROM typically require the host system or program-
though flash memory is a derivative of EPROM and mer to execute complex algorithms to write and erase.
EEPROM, it possesses many advantages that make it a These algorithms are required to write any flash cell,
more attractive nonvolatile memory choice. This tech- but on current-generation flash the algorithms are
nical note describes these advantages, as well as other executed internally by a state machine. This frees the
characteristics inherent to Micron’s boot block flash host system to do other tasks while the state machine
memory technology. writes or erases the flash memory and simplifies design-
in of flash by reducing software overhead necessary to
GENERAL FLASH CHARACTERISTICS write or erase the device.
Although flash shares many characteristics with During a WRITE, the state machine controls the
EPROM and EEPROM, current-generation flash differs WRITE pulse timing to the cell, tracks the number of
in that ERASE operations are done in blocks. Flash, pulses issued, controls the voltages applied to the cell
EPROM and EEPROM all must be erased before being and verifies that the data was written correctly. When
written. When erasing EPROM, the entire chip is erased executing an ERASE, the state machine first writes all
with a UV light source. EEPROM is automatically locations within the block to “0” so that each cell
erased before a WRITE on a byte basis. Flash is either contains uniform charge. The state machine then issues
erased in blocks (boot block or sectored erase block the ERASE pulses to the cells within the block and
flash) or the entire chip at once (bulk erase flash). monitors the ERASE for completion. At any time dur-
Boot block devices have erase blocks that vary in size ing a WRITE or ERASE, the status register may be read
from 4KB to 128KB. A hardware-protected boot block to monitor the WRITE or ERASE in progress or to check
(typically 16KB) provides maximum security for core for the completion of the WRITE or ERASE cycle.
firmware. To write or erase the boot block, the reset pin
must be brought to a super-voltage (VHH = 12V) or the FLASH CELL STRUCTURE
write protect pin (WP#) brought to VIH in addition to Most flash devices share basically the same cell
the normal WRITE or ERASE sequences. Sectored erase structure as the EPROM cell. Both the flash and EPROM
block flash has blocks of equal size, some with no cells are dual polysilicon (poly), floating-gate CMOS
additional hardware protection. This configuration is field effect transistors. The first poly layer is isolated
suited for mass storage or firmware applications. from the control gate by an interpoly dielectric layer
Although flash is erased on a block basis, WRITE and from the substrate by a thin oxide layer.
and READ operations are done on a random byte or
word basis.

Control Gate (Wordline)

Control Gate (Wordline) Interpoly Dielectric
Interpoly Dielectric
Floating Gate (Storage element)
Floating Gate (Storage element)
Tunnel Oxide (~100 A) Oxide (>150 A)

Source n+ n+ Drain (Bitline) Source n+ n+ Drain (Bitline)

Substrate (p-type) Substrate (p-type)

Flash Cell EPROM Cell

Figure 1
Flash Cell vs. EPROM Cell
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FT01.p65 – Rev. 12/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
 TN-28-01
BOOT BLOCK FLASH MEMORY
This isolation allows the first poly layer inversion region to form in the p-type substrate. The
(floating gate) to store charge. The second poly layer is drain voltage is increased to approximately half the
connected to the wordline and functions as the con- control gate voltage (6 volts) while the source is
trol gate. However, there are two main differences grounded (0 volts), increasing the voltage drop be-
between a flash cell and an EPROM cell that allow for tween the drain and source. (See Figure 2.) With the
electrical erase of the flash cell. Flash has a thinner inversion region formed, the current between drain
oxide layer of approximately 100 angstroms to enable and source increases. The resulting high electron flow
Fowler-Nordheim tunneling of electrons from the float- from source to drain increases the kinetic energy of the
ing gate during an ERASE. In addition, flash has a electrons. This causes the electrons to gain enough
deeper source diffusion to further enhance ERASE energy to overcome the oxide barrier and collect on the
performance. Figure 1 compares the two types of floating gate.
memory cells. After the WRITE is completed, the negative charge
on the floating gate raises the cell’s threshold voltage
WRITE (VT) above the wordline logic 1 voltage. When a writ-
Flash and EPROM implement hot electron injection ten cell’s wordline is brought to a logic 1 during a
to place charge on the floating gate during a WRITE. READ, the cell will not turn on. The sense amps detect
During a WRITE, a high programming voltage (VPP = and amplify the cell current and output a “0” for a
12V) is placed on the control gate. This forces an written cell.

VG = VPP

Control Gate (Wordline) Floating Gate (Storage element)

e- e- e- e- e-e-e- e- e-
VD ≈ 6V
e-
e e- e- - e - e -
e - e - ee--e -
e- e-e- -e-
e -e e- - e - e - e -e e - e-
Source n+ e- n+ Drain (Bitline)

Inversion Region

Substrate (p-type)

Figure 2
Flash Cell during a WRITE

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FT01.p65 – Rev. 12/99 2 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
 TN-28-01
BOOT BLOCK FLASH MEMORY

ERASE ARRAY ARCHITECTURE

Flash employs Fowler-Nordheim tunneling to re- Micron’s flash product line implements NOR archi-
move charge from the floating gate to bring it to the tecture for the highest random-access performance.
erased state. Using high-voltage source erase, the source This architecture is optimal for systems requiring
is brought to a high voltage (VPP = 12V), the control updatable firmware storage. See Figure 4 for more
gate grounded (0 volts) and the drain left uncon- detail on the NOR architecture.
nected. (See Figure 3.) The large positive voltage on the
source, as compared to the floating gate, attracts the READING
negatively charged electrons from the floating gate to During a READ of a byte or word of data, the
the source through the thin oxide. Because the drain is addressed row (wordline) is brought to a logic 1 level
not connected, the ERASE function is a much lower (> VT of an erased cell). This condition turns on erased
current-per-cell operation than a WRITE that uses hot cells which allow current to flow from drain to source,
electron injection. while written cells remain in the off state with little
After the ERASE is completed, the lack of charge on current flow from drain to source. The cell current is
the floating gate lowers the cell’s VT below the wordline detected by the sense amps and amplified to the appro-
logic 1 voltage. When an erased cell’s wordline is priate logic level to the outputs. All other wordlines
brought to a logic 1 during a READ, the transistor will within the array remain low. Because only one wordline
turn on and conduct more current than a written cell. needs to be controlled at a time during a READ, the
Some flash devices use Fowler-Nordheim tunneling for decode overhead is minimized. As a result, high
WRITEs as well as ERASEs. random-access READ performance is achieved with
the NOR architecture.

Control Gate (Wordline) Floating Gate (Storage element)

e- e- e- e- VD = No Connection
VS ≈ VPP e- e- e-
e - e - e - e - e - e -e - e-
e-
e -e -ee-e- -
e - e -e -e -
e -ee- -
e-
Source n+ n+ Drain (Bitline)

Substrate (p-type)

Figure 3
Flash Cell During High-Voltage Source ERASE

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FT01.p65 – Rev. 12/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.
 TN-28-01
BOOT BLOCK FLASH MEMORY
WRITING
Similar to READs, WRITEs are also done on a exposed to high voltages, reducing the chance for data
random-access basis. The addressed wordline is brought corruption of other blocks during an ERASE.
to a super-voltage of 12 volts, the bitline (drain) is
brought to approximately 6 volts, while the source SUMMARY
remains at 0 volts. All other wordlines within the array Micron’s boot block flash memory family provides
remain low. designers with secure, updatable firmware storage.
WRITE operations implement hot electron injection
ERASING similar to EPROM, and ERASE operations use Fowler-
ERASE operations are done on a block basis in NOR Nordheim tunneling similar to EEPROM. However, by
flash memory. The source of a cell is common to each automating the write and erase algorithms, the state
cell within a given erase block. During an ERASE, the machine simplifies design-in of flash memory. With
bitlines are left open, all the wordlines are at 0 volts, the NOR architecture, the highest random-access WRITE
and the source is brought to 12 volts, erasing all cells and READ performance is achieved.
within the block. The other blocks in the device are not

BL0 BL1

Source

S S
WL0

D D

WL1

S S

WL2

D D

Figure 4
NOR Flash Cell Array

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TN-28-01
FT01.p65 – Rev. 12/99 4 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1999, Micron Technology, Inc.