EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/

ADRV9009-W/PCBZ User Guide

UG-1378
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Evaluating the ADRV9008-1 Direct Conversion Receiver and the ADRV9008-2 and ADRV9009
Direct Conversion Transceivers

OVERVIEW HARDWARE AND SOFTWARE REQUIREMENTS

The ADRV9008-1, ADRV9008-2, and ADRV9009 demonstration The hardware and software requirements are as follows:
system allows customers to evaluate a device without developing
 The Zynq evaluation platform (Analog Devices, BVAL-
custom software or hardware. The system is comprised of a
TPG-ZYNQ3, Revision 1.2. This evaluation platform is not
radio daughter card, a Zynq® motherboard from Analog Devices,
included in the ADRV9008-1, ADRV9008-2, and ADRV9009
Inc., an SD card with an operating system, two power supplies,
demonstration kit.
and a C#-based evaluation software application. The evaluation
 The ADRV9008-1, ADRV9008-2, and ADRV9009
system uses an Ethernet interface to communicate with the PC.
demonstration system kit.
INITIAL SETUP  The operating system on the controlling PC must be
The ADRV9008-1, ADRV9008-2, and ADRV9009 transceiver Windows® 7 (x86 and x64) or Windows 8 (x86 and x64).
evaluation software (TES) can run with or without evaluation  The PC must have an open Ethernet port with the following
hardware. When the TES runs without the hardware connected, constraints:
the software can be fully configured for a particular operating  If the Ethernet port is occupied by another LAN
mode. If the evaluation hardware is connected, the desired connection, a USB to Ethernet adapter can be used.
operating parameters can be set up with the TES. Then, the  The PC must be able to access the following ports over
software can program the ADRV9008-1, ADRV9008-2, and this dedicated Ethernet connection:
ADRV9009 evaluation hardware. After the device is configured,  22—secure shelf (SSH) protocol.
the evaluation software can be used to transmit waveforms, observe  55555—access to the evaluation software on the
received waveforms, and initiate correction algorithms. An Zynq platform.
initialization sequence in the form of an IronPython script  TES available from the design center landing page.
can be generated and executed using the TES.  The user must have administrative privileges. To run
HARDWARE KIT software automatic updates, the PC must have access to the
The ADRV9008-1, ADRV9008-2, and ADRV9009 demonstration internet. If internet access is restricted, perform a manual
system kit contains the ADRV9008-1, ADRV9008-2, and software update.
ADRV9009 evaluation board in the form of a daughter card HARDWARE SETUP
with a field programmable gate array (FPGA) mezzanine card
The Zynq platform setup requires the following procedure:
(FMC) connector, one 6 V/2 A switching power supply, and one
SD card containing an image of a Linux® operating system with the 1. Ensure that all jumpers are in the positions shown in Figure 1.
required evaluation software. The SD card type is 8 GB size, Type 4. 2. SW11 must be in the positions shown in Figure 1 (Slider 1,
Slider 2, and Slider 5 are in the A position).
3. The SD card included with the evaluation kit must be
placed in the J30 slot of the Zynq platform.
The evaluation hardware setup is shown in Figure 2, Figure 3, and
Figure 4.

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT

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TABLE OF CONTENTS
Overview ............................................................................................ 1 Starting the Transceiver Evaluation Software......................... 10
Initial Setup ....................................................................................... 1 Normal Operation ...................................................................... 12
Hardware Kit ..................................................................................... 1 Other TES Features .................................................................... 27
Hardware and Software Requirements .......................................... 1 Receiver Setup............................................................................. 28
Hardware Setup................................................................................. 1 Transmitter Setup ....................................................................... 30
Revision History ............................................................................... 2 Time Division Duplex (TDD) Mode ........................................... 32
Evaluation Board Photographs ....................................................... 3 LTE TDD Frame Structure ....................................................... 32
Setting up the Evaluation Board ..................................................... 5 ADRV9009 Evaluation Hardware in TDD Mode ...................... 33
Hardware Setup and Operation ...................................................... 6 Setting Up TDD Functionality ................................................. 33
Hardware Setup for External Transmitter LO Leakage TES Interface for TDD Mode ................................................... 35
Calibration ..................................................................................... 6 Scripting ...................................................................................... 38
Hardware Operation .................................................................... 9 Troubleshooting .............................................................................. 40
ADRV9008-1, ADRV9008-2, and ADRV9009 Transceiver Startup .......................................................................................... 40
Evaluation Software (TES)............................................................... 10
Error Handling ........................................................................... 40
Installations ................................................................................. 10

REVISION HISTORY
6/2018—Revision 0: Initial Version

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378

EVALUATION BOARD PHOTOGRAPHS

J68: EXTERNAL Rx TRIGGER

J67: EXTERNAL Tx TRIGGER

LEDs
LED L: Rx LINK B SYNC
LED C: Rx LINK A SYNC
LED R: Tx LINK B SYNC
LED O: Tx LINK A SYNC

17032-195
SW9: SHUTDOWN
SW8: REBOOT

Figure 1. Zynq Evaluation Board with Jumper Settings and Switch Positions Configured to Work with the ADRV9008-1, ADRV9008-2, and ADRV9009 Evaluation Board

ETHERNET
CONNECTION
PC RUNNING
EVALUATION SOFTWARE

SIGNAL GENERATOR

Rx2
EXT LO
Rx1

SIGNAL
SYNTHESIZER

REFERENCE
CLOCK SOURCE
30.72MHz/+5dBm

SD CARD
WITH IMAGE

POWER
12V SWITCH
SWITCHING
SUPPLY

SWITCHING
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POWER
SUPPLY

Figure 2. ADRV9008-1 Receiver Evaluation Board and Zynq Motherboard with Connections Required for Receiver 1 Testing

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ETHERNET
CONNECTION
PC RUNNING
EVALUATION SOFTWARE

SIGNAL GENERATOR
Tx2

ORx2

EXT LO

ORx1
SIGNAL ANALYZER
Tx1
REFERENCE
CLOCK SOURCE
30.72MHz/+5dBm

SD CARD
WITH IMAGE
SIGNAL
SYNTHESIZER

POWER
12V SWITCH
SWITCHING
SUPPLY

SWITCHING

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POWER
SUPPLY

Figure 3. ADRV9008-2 Transmitter Evaluation Board and Zynq Motherboard with Connections Required for Transmitter 2 and Observation Receiver 1 Testing

ETHERNET
CONNECTION
PC RUNNING
EVALUATION SOFTWARE

SIGNAL GENERATOR
Tx2

ORx2
Rx2
EXT LO
Rx1
ORx1
SIGNAL ANALYZER

Tx1
REFERENCE
CLOCK SOURCE
30.72MHz/+5dBm

SD CARD
WITH IMAGE
SIGNAL
SYNTHESIZER

POWER
12V SWITCH
SWITCHING
SUPPLY

SWITCHING
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POWER
SUPPLY

Figure 4. ADRV9009 Time Division Duplex (TDD) Evaluation Board and Zynq Motherboard with Connections Required for Transmitter 2 and Receiver 1 Testing

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SETTING UP THE EVALUATION BOARD

To set up the evaluation board for testing, use the following 5. Connect a 6 V, 2 A power supply, such as the HF-FYD
procedure: FY0602000 (supplied), to the ADRV9008-1, ADRV9008-2,
1. Connect the ADRV9008-1, ADRV9008-2, and ADRV9009 and ADRV9009evaluation board at the P501 header.
evaluation board and the Zynq evaluation platform together 6. Connect a 12 V, 5 A power supply to the Zynq evaluation
as shown in Figure 2, Figure 3, or in Figure 4. Use the high platform at the J22 header.
pin count (HPC) FMC connector (J37). Ensure that the 7. Connect the Zynq evaluation platform to the PC with an
connectors are properly aligned. Ethernet cable, connected to P3. There is no driver
2. Ensure that all jumpers on the Zynq motherboard, as well installation required.
as the SW11 position, match the settings shown in Figure 1 a. In a case where the Ethernet port is already occupied
(Slider 1, Slider 2, and Slider 5 are in the A position). by another connection, use an USB to Ethernet adapter.
3. Insert the SD card included with the ADRV9008-1, b. On an Ethernet connection dedicated to the Zynq
ADRV9008-2, and ADRV9009 evaluation kit into the platform, the user must manually set the IPv4 address to
Zynq SD card slot (J30). 192.168.1.2 and the IPv4 subnet mask to 255.255.255.0
4. On the ADRV9008-1, ADRV9008-2, and ADRV9009 See Figure 5 for more details. Esure that the following ports are
evaluation card, provide a 30.72 MHz clock source (or not blocked by firewall software on the PC:
frequency match the setting selected on the AD9528
 22—SSH protocol.
configuration tab, shown in Figure 31), at a 5 dBm power
level to the J401 connector. This signal drives the reference  55555—access to the evaluation software on the Zynq
clock into the AD9528 clock generation chip on the board. platform.
The REFA pin and the REFA pin of the AD9528 generate the The Zynq IP address is set by default to 192.168.1.10.
device clock for the ADRV9008-1, ADRV9008-2, and
ADRV9009, and the REF_CLK for the FPGA on the
Zynq platform.

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Figure 5. IP Settings for the Ethernet Port Dedicated to the Zynq Platform

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HARDWARE SETUP AND OPERATION

HARDWARE SETUP FOR EXTERNAL TRANSMITTER calibration algorithm. The user must connect a radio frequency
LO LEAKAGE CALIBRATION (RF) splitter at the trans-mitter output. One of the splitter
outputs must be connected to the corresponding ADRV9008-1,
The ADRV9008-1, ADRV9008-2, and ADRV9009 are direct ADRV9008-2, and ADRV9009 observation receiver inputs
conversion transceivers. One drawback of the direct conversion through an RF attenuator (Transmitter 1, Observation Receiver 1,
technique is that the transmitter baseband dc offset and direct Transmitter 2, then Observation Receiver 2). The amount of
coupling of the local oscillator to the transmitter output can attenuation required depends on the attenuation introduced by
cause an undesired continuous wave (CW) emission at the the splitter. For maximum observation receiver gain, the signal
transmitter local oscillator (LO) frequency. The purpose of the level at the observation receiver input must not exceed
transmitter LO leakage (LOL) calibration is to minimize this −16 dBm.
CW emission. The ADRV9008-1, ADRV9008-2, and ADRV9009
evaluation system supports two types of transmitter LOL For external transmitter LOL tracking calibration, both trans-
calibration algorithms. The user can select calibration mitters must be looped back to both observation receivers through
algorithms using the tick boxes shown in the Figure 20. splitters and attenuators. For the best LOL performance when
operating above 4 GHz, use only the Observation Receiver 1
When the user selects internal calibration algorithms LOL input for both Transmitter 1 and Transmitter 2. Use an external
initialization calibration, no external hardware is necessary. In this switch to accomplish this configuration.
case, there is no transmitter LOL tracking calibration available.
Use the following example settings to determine the RF
When the user selects external transmitter LOL initialization attenuator specification:
calibration and external transmitter LOL tracking calibration,
the LOL tracking calibration runs on the evaluation system. For  Transmitter output signal = 7 dBm (CW)
proper operation, external components must be connected to  Maximum observation receiver gain
the ADRV9008-1, ADRV9008-2, and ADRV9009 evaluation  RF splitter attenuation = 3 dB
platform. Figure 6 and Figure 7 show the correct configuration  Maximum observation receiver input = −16 dBm
to demonstrate the performance of the transmitter LOL  RF attenuator = 20 dB (7 dBm – 3 dB – 20 dB = −16 dBm)

Tx2
SPLITTER

ORx2

ATTENUATOR

ORx1

ATTENUATOR

SPLITTER
Tx1
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Figure 6. Demonstration Operation of External Transmitter LOL Calibration on the ADRV9008-2 Transmitter and the Frequency Division Duplex (FDD) Evaluation System

Tx2
SPLITTER

ORx2

ATTENUATOR

ORx1

ATTENUATOR

SPLITTER
Tx1
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Figure 7. Demonstration Operation of External Transmitter LOL Calibration on the ADRV9009 Transmitter and the TDD Evaluation System

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378
COUPLER
Figure 8 and Figure 9 show the configuration in which the Tx2
customer uses the ADRV9008-1, ADRV9008-2, and ADRV9009 –X dB
evaluation system with a desired power amplifier (PA). In this
case, split or couple the signal after the PA to the corresponding ORx2
observation receiver channel through an appropriate attenuator.
The maximum signal level at the observation receiver input must ATTENUATOR

not exceed −16 dBm. The amount of attenuation required must ORx1
be calculated based on the power level after the PA and RF coupler.
COUPLER ATTENUATOR
Tx2
–X dB
–X dB

17032-302
Tx1
COUPLER
ORx2
Figure 9. End User Application of External Transmitter LOL Calibration
(Nonstitching Mode) Using the ADRV9009 Transmitter and the TDD
ATTENUATOR Evaluation System

ORx1 The setup shown in Figure 8 and Figure 9 is used when

nonstitching mode is used. When stitching mode is used (the
ATTENUATOR
observation receiver bandwidth > 200 MHz), use the setup shown
–X dB in Figure 10 and Figure 11.
17032-201

Tx1
COUPLER

Figure 8. End User Application of External Transmitter LOL Calibration

(Nonstitching Mode) Using the ADRV9008-2 Transmitter and the FDD
Evaluation System

Tx2
SPLITTER

SWITCH

ORx1

ATTENUATOR

SPLITTER
Tx1
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Figure 10. Demonstration Operation of the External Transmitter LOL Calibration (Stitching Mode) on the ADRV9008-2 Transmitter and the FDD Evaluation System

Tx2
SPLITTER

SWITCH
ORx1

ATTENUATOR

SPLITTER
Tx1
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Figure 11. Demonstration Operation of the External Transmitter LOL Calibration (Stitching Mode) on the ADRV9009 TDD Evaluation System

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UG-1378 EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide
Figure 12 and Figure 13 show the configuration in which the in Figure 12 and Figure 13 through an appropriate attenuator
customer uses ADRV9008-1, ADRV9008-2, and ADRV9009 and a switch. The maximum signal level at the observation receiver
evaluation system with a desired PA in stitching mode. In this input must not exceed −16 dBm. The amount of attenuation
case, split or couple the signal after the PA to the selected required must be calculated based on the power level after the
observation receiver channel. Observation Receiver 1 is selected PA and the RF coupler.

COUPLER
Tx2
–X dB

ORx2

SWITCH
ORx1

ATTENUATOR

–X dB

17032-203
Tx1
COUPLER
Figure 12. End User Application of External Transmitter LOL Calibration (Stitching Mode) Using the ADRV9008-2 Transmitter and the FDD Evaluation System
COUPLER
Tx2
–X dB

ORx2

SWITCH
ORx1

ATTENUATOR

–X dB
17032-304

Tx1
COUPLER
Figure 13. End User Application of External Transmitter LOL Calibration (Stitching Mode) Using the ADRV9009 Transmitter and the TDD Evaluation System

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378

HARDWARE OPERATION 4. For receiver testing on the ADRV9008-1 and ADRV9009

evaluation board, use a clean signal generator with low
For correct operation of the hardware, use the following phase noise to provide an input signal to the selected RF
procedure: input. Use a shielded RG-58, 50 Ω coaxial cable (1 m or
1. Turn on the evaluation system by switching the Zynq shorter) to connect the signal generator.
board power switch (SW1) to the on position. If the a. To set the input level near the full scale of the receiver,
hardware is connected correctly, two green light emitting set the generator level (for a single-tone signal) to
diodes (LEDs) on the ADRV9008-1, ADRV9008-2, and approximately −15 dBm. This level depends on the
ADRV9009 evaluation board, D501 and D502, are on. input frequency and the gain settings through the
2. The Zynq evaluation system uses a Linux operating system. path. There must be no input signal applied to the
Approximately 30 sec elapse before the system is ready for receiver input when performing an initialization
operation and is ready to accept commands from the PC calibration.
software. The boot status can be observed on the Zynq b. To set the input level near the full scale of the
general-purpose input/output (GPIO) LEDs (L, C, R, and O). observation receiver, set the generator level (for a
The correct sequence of events when the system boots up single-tone signal) to approximately −15 dBm. This
properly is as follows: level depends on the input frequency and the gain
a. After SW1 is turned on, all four LEDs are on for settings through the path.
approximately 15 sec. During this time, the image on 5. For transmitter testing, connect a spectrum analyzer to either
the SD card is copied from the SD card to the FPGA transmitter output on the ADRV9008-2 or ADRV9009
memory. evaluation board. Use a shielded RG-58, 50 Ω coaxial cable
b. Next, the LEDs begin flashing (moving the single on (1 m or shorter) to connect the spectrum analyzer. Both
light), which indicates that the Linux operating system transmitter paths must be terminated, either into spectrum
is booting up. The booting up process takes another analyzers, or if only one transmitter is being checked, the
15 sec. other transmitter must be terminated to 50 Ω. This
c. When the LEDs stop flashing, the system is ready for termination is required because the initial calibrations run
normal operation and awaits connection to the PC over on both channels and can take a long time to complete if a
Ethernet. Establish this connection using the TES. transmitter channel is not correctly terminated.
d. The status of each LED during normal operation is as 6. Power off must be executed using the TES software or the
follows: user must power down the Zynq system using the SW9
push button (see Figure 1) before the user powers down the
 GPIO LED L: Receiver Link B synchronization.
evaluation system by switching SW1 off.
 GPIO LED C: Receiver Link A synchronization.
 GPIO LED R: Transmitter Link B synchronization. It is important to note that the ADRV9008-1, ADRV9008-2,
 GPIO LED O: Transmitter Link A synchronization. and ADRV9009 evaluation system uses a Linux operating
system. Linux requires time to boot up, as well as time to shut
e. When shutdown is executed using the TES, the Linux down before the hardware powers off. Use the software power-
operating system starts the power-down procedure. down feature or press the SW9 button on the Zynq platform
The power-down procedure requires a few seconds to before physically switching the power off using SW1. If this
complete. All four LEDs blinking together indicates sequence is not used, the SD card may be corrupted and the
that the user can safely power off the system using ADRV9008-1, ADRV9008-2, and ADRV9009 evaluation system
SW1 on the Zynq platform. may stop operating.
3. Connect the reference clock signal (30.72 MHz CW tone,
5 dBm maximum) to J401. After the TES is used to program Perform correct shutdown by selecting File > Shutdown Zynq
the system, two LEDs on the ADRV9008-1, ADRV9008-2, platform in the TES, or by pressing the SW9 push button on
and ADRV9009 evaluation board (D401 and D402) are on. the Zynq platform.
Active LEDs indicate that the correct reference clock is After a few seconds, when all four GPIO LEDs on the Zynq
provided and phase-locked loops (PLLs) in the AD9528 platform blink together, the user can safely power off the system
are locked. using SW1 on the Zynq platform.

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ADRV9008-1, ADRV9008-2, AND ADRV9009 TRANSCEIVER EVALUATION SOFTWARE (TES)

INSTALLATIONS
Download the TES directly from the design center landing
page. After the initial software download, copy the software to
the target system and unzip the files (if not already unzipped).
The downloaded .zip file contains an executable file called
ADRV9009 Transceiver Evaluation Software.exe.
Administrator privileges are required to install the TES. After
running an executable file, a standard installation process
follows. Parts of the installation build are Microsoft® .NET
Framework 4.5 (which is mandatory for the software to operate)
and IronPython 2.7.4 (which is optional and recommended).
Figure 14 shows the recommended software installation
configuration.

17032-205
Figure 15. ADRV9009 Transceiver Evaluation Software Shortcut
Configuration

STARTING THE TRANSCEIVER EVALUATION

SOFTWARE
Depending on the shortcut placement selection during the
installation process (see Figure 15), the user can start the
customer software by navigating to Start > All Programs >
Analog Devices > ADRV900x Transceiver Evaluation Software >
ADRV9009 Transceiver Evaluation Software, or by clicking on
the ADRV9009 Transceiver Evaluation Software desktop
shortcut. Figure 16 shows the opening page of the TES
after it is activated.
17032-204

Demonstration Mode
Figure 16 shows the opening page of the TES. In a case when
Figure 14. Software Installation Components
the evaluation hardware is not connected, the user can still use
The last step of the instalation process is to select the shortcut the software in demonstration mode by following this procedure:
configuration (see Figure 15). The user can place the shortcut in 1. Click File > Connect (top left corner of the TES).
the Windows start menu, or on the Windows desktop. 2. The Cannot Connect to Device message appears. Click
OK to proceed.
3. After clicking OK, the software enters demonstration mode,
in which a superset of all transceiver family features is
displayed.
The connection status is indicated at the bottom of the software
window. When the status display reads Disconnected, the TES
operates in demonstration mode (see Figure 17).

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378

17032-206
Figure 16. ADRV9009 TES Interface

17032-207

Figure 17. Project Setup Page of the ADRV9009 TES

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NORMAL OPERATION Figure 18 shows an example of correct connection between a

To start using the complete evaluation system when the hardware is PC and a Zynq system with a daughter card connected to the
connected to a PC, click the File > Connect option in the drop- Zynq system.
down menu at the top left of page to force the TES to establish a Platform Files Update
connection with the Zynq system via Ethernet. When a connection Before continuing, determine if the latest version of the platform
is established, click the DaughterCard position in the device software is installed in the system. After the TES establishes a
tree on the left side of the window (see Figure 18). After selecting connection with the Zynq platform, the TES checks if the latest
DaughterCard, information about the revisions of the different files are present. If the files must be updated, the TES informs
setup blocks appears in the main window. The bottom section the user.
of the window shows that the transfer control protocol (TCP) IP
Update the platform files by navigating to Tools > Update >
address set to 192.168.1.10 and that the port number is set to
Platform Files. The TES automatically updates files on the
55555. Contact Analog Devices if the ADRV9008-1, ADRV9008-2,
Zynq SD card and reboots the ADRV9008-1, ADRV9008-2,
and ADRV9009 evaluation system must operate over a remote
and ADRV9009 evaluation system.
connection and a different IP address for the Zynq platform is
desired. When all updates are installed, the system is ready for normal
operation.

17032-208

Figure 18. Setup Revision Information

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378

Configuring the ADRV9008-2 Transmitter the LO phase to a repeatable value for every change in the RF
PLL frequency. Currently, only initialization and tracking
The TES contains five main user configurable pages (see Figure 19
continuously mode is supported. The RF PLL phase
to Figure 23). After the user selects ADRV900x in the device
synchronization functionality is included at this time for
tree, the Config tab is activated. Contained within this tab are
prototyping and evaluation purposes only. Contact Analog
six sub tabs that contain setup options for the device. The first
Devices for function availability.
one displayed is the Configuration tab. Figure 19 shows the
 Select the desired attenuation for the transmitter channels
initial screen for the ADRV9008-2. In this page, the user can
in dB.
perform the following actions:
 Load the custom stream. This feature assists customers in
 Select the device to be programmed. loading new stream files.
 Select the device clock frequency  Select the digital-to-analog converter (DAC) enabled. This
 Select the number of active transmitter channels section allows the user to either select a low power profile
 Select the profiles for the transmitter and observation or a high power profile. The difference between the two
receiver. profiles is that the DAC is left powered on while the trans-
 Select the observation receiver channel mitter is disabled (for a high power profile), and the DAC
 Select the RF PLL frequency for the transmitter and is disabled while the transmitter is disabled (for a low power
observation receiver. An added feature allows the user to profile). The only trade-off is the higher switching time
enable phase synchronization. This synchronization sets required to turn on the DACs for the low power profile.

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Figure 19. Main Configuration Tab for the ADRV9008-2

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The second user configurable tab is the Calibration tab. The boost mode in which the user can enhance the transmitter LOL
Calibration tab enables the initialization and tracking calibrations. performance. Using this mode, a further 3 dB margin is applied
Figure 20 shows a configuration example. The user can enable between the output signal and the LOL. The status bar at the
or disable initialization calibrations, as well as tracking calibrations. bottom of the TES shows the status of the transmitter QEC tracking
The initial calibrations, transmitter quadrature error correction calibration and indicates whether the radio state is on or off. In
(QEC) and internal transmitter LOL, along with the Transmitter 2 addition, a section on the page allows the setup of receiver gain
LOL, Transmitter 2 QEC, Observation Receiver 1 QEC, and compensation mode, including the floating point options. Refer
Observation Receiver 2 QEC tracking calibrations can be enabled to the ADRV9008-1-W/ADRV9008-2-W/ADRV9009-W
for the ADRV9008-2 device. The user can also enable 3 dB DAC Hardware Reference Manual for more information.

17032-210

Figure 20. Calibration Configuration Tab for the ADRV9008-2

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378
The third user configurable tab is the JESD204b Setup tab. The JESD204B links. The last check box in every framer/deframer is
JESD204b Setup tab is used to set the characteristics of the the option to relink on SYSREF. A feature is available to set the
digital data interface. Figure 21 shows a configuration example JESD204B lane rate as 11 Gbps. The Np parameter is set to 12
for the ADRV9008-2. A subtab exists to select the receiver for 11 Gbps mode. This mode is currently only supported by
framer and the transmitter deframer. The user can set the the Tx 200/300 MHz, IQrate 368.64MHz, Int5, 11G Tx profile
desired JESD204B lane configuration, select scrambling, and and the ORX 300 MHz, IQrate 368.64MHz, Dec5, 12bit, 11G
choose whether to use an internal (free running) or external as ORx profile.
(provided by the AD9528) SYSREF signal to synchronize the

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Figure 21. JESD204b Setup Tab for the ADRV9008-2

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The Tx Summary tab and the ObsRx Summary tab are The TES also provides the capability to export the data plotted
primarily informative and are based on the profile selection in on the graphs to an external file. Perform this export action by
the Configuration tab (see Figure 22 and Figure 23). In each right clicking the graph area and saving the data to a file for
tab, the user can check clock rates at each filter node, as well as later analysis.
filter characteristics and their pass-band flatness. Quick zooming Figure 22 shows an example of the Tx Summary tab with the
capability allows zooming of the pass-band response, as well as resulting composite filter response for the chosen profile.
the ability to restore the full-scale plot.
Figure 23 shows an example of the ObsRx Summary tab.

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Figure 22. Tx Summary Tab

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17032-213
Figure 23. ObsRx Summary Tab

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17032-214
Figure 24. Main Configuration Tab for the ADRV9008-1

Configuring the ADRV9008-1 Receiver  Select RF PLL frequency for the receiver. A feature is available
The TES contains four main user-configurable pages (see Figure 24 that allows the user to enable phase synchronization. This
to Figure 27). After the user selects ADRV9008-1 in the device tree, synchronization sets the LO phase to a repeatable value for
the Config tab is activated. Contained within this tab are six every change in the RF PLL frequency. Currently, only
subtabs that contain setup options for the device. The first subtab initialization and tracking continuously mode is supported.
displayed is the Configuration tab. Figure 24 shows the initial The RF PLL phase synchronization functionality is included at
screen for the ADRV9008-1 receiver. Depending on the device this time for prototyping and evaluation purposes only.
selected, the user can perform the following actions in this page: Consult Analog Devices for function availability.
 Load the custom stream. This feature is added to assist
 Select the device to be programmed.
customers in loading new stream files.
 Select the device clock frequency.
 Select the desired DAC enabled option. This section allows
 Select the number of active receiver channels.
the user to either select a low power profile or a high power
 Select the profile for the receiver. profile. The difference between the two profiles is that the
DAC is left powered on during transmitter disable (for a
high power profile) and is disabled during transmitter
disable (for a low power profile). The only trade-off is the
higher switching time required to turn on the DACs for the
low power profile. This selection does not have any effect
for the ADRV9008-1.

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The second user configurable tab is the Calibration tab. The status of the QEC receiver tracking calibration and indicates if the
Calibration tab is used to enable initialization and tracking radio state is on or off. A new section is available to enable floating
calibrations. Figure 25 shows a configuration example. The user point mode. In addition, a section on the page allows the setup of
can enable or disable initialization calibrations, as well as tracking receiver gain compensation mode, including the floating point
calibrations. The initial calibrations, receiver QEC, along with options. Refer to the ADRV9008-1-W/ADRV9008-2-W/
the Receiver 1 QEC and Receiver 2 QEC tracking calibrations can ADRV9009-W Hardware Reference Manual for more information.
be enabled for the ADRV9008-1 receiver device (see Figure 25). A The user can also enable the 3 dB DAC boost mode, in which
calibration receiver HD2 canceller feature is available. Due to the user can enhance the transmitter LOL performance. Using
conflicting resources required by the receiver QEC and receiver this mode, a further 3 dB margin is applied between the output
HD2, currently only one of the two calibrations can be activated signal and the LOL.
at an instant. The status bar at the bottom of the TES shows the

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Figure 25. Calibration Configuration Tab for the ADRV9008-1

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The third user configurable tab is JESD204b Setup and is used to AD9528) SYSREF to synchronize the JESD204B links. The last
set the characteristics of the digital data interface. Figure 26 shows a check box in each framer/deframer is the option to relink on
configuration example for the ADRV9008-1, ADRV9008-2, and SYSREF. A feature is available to set the JESD204B lane rate as
ADRV9009 receiver. A subtab exists to select the receiver framer 11 Gbps. The Np parameter is set to 12 for 11 Gbps mode. This
and the transmitter deframer. The user can set the desired mode is currently only supported by the Rx 205 MHz, IQrate
JESD204B lane configuration, select scrambling, and whether 368.64MHz, Dec5 receiver profile.
to use an internal (free running) or external (provided by the

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Figure 26. .JESD204b Setup Tab for the ADRV9008-1

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The Rx Summary tab is primarily informative and is based on The receiver uses square wave mixing to downconvert the receive
the profile selection in the Configuration tab (see Figure 27). signal to baseband. Square wave mixing also downconverts signals
In each of these tabs, the user can check clock rates at each filter around the odd harmonics of the receiver LO signal. Spurious
node, as well as filter characteristics and their pass-band signals around odd harmonics of the LO must be filtered to
flatness. Quick zooming capability allows zooming of the pass- prevent interference with the receive signal. Spurious signals
band response, as well as the ability to restore the full-scale plot. that generate harmonics that fall around odd harmonics of the
The TES also provides the capability to export the data plotted LO must also be filtered to prevent spurious harmonics from
on the graphs to an external file. Perform this export by right interfering with the receive signal.
clicking on the graph area and saving the data to a file for later
analysis. Figure 27 shows an example of the Rx Summary tab
with the resulting composite filter response for the chosen profile.

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Figure 27. Rx Summary Tab

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17032-218
Figure 28. Main Configuration Tab for the ADRV9009 TDD

Configuring the ADRV9009 TDD Device  Select RF PLL frequency for the receiver. A feature is available
that allows the user to enable phase synchronization. This
The TES contains five main user-configurable pages (see Figure 22,
synchronization sets the LO phase to a repeatable value for
Figure 23, and Figure 27 to Figure 30). After the user selects the
every change in the RF PLL frequency. Currently, only
ADRV9009 in the device tree, the Config tab is activated.
initialization and tracking continuously mode is supported.
Contained within this tab are subtabs that contain setup options
The RF PLL phase synchronization functionality is included at
for the device. The first subtab displayed is the Configuration
this time for prototyping and evaluation purposes only.
tab. Figure 28 shows the initial screen for the ADRV9009 TDD
Consult Analog Devices for function availability.
device. The user can perform the following actions in this page:
 Select the desired attenuation for the transmitter channels
 Select the device to be programmed. in dB.
 Select the device clock frequency.  Load the custom stream. This feature assists customers in
 Select the number of active transmitter channels. loading new stream files.
 Select the profiles for the transmitter and observation  Select the DAC enabled. This section provides the user the
receiver. capability to either select a low power profile or a high
 Select the observation receiver channel. power profile. The difference between the two profiles is
 Select the number of active receiver channels. that the DAC is left powered on during transmitter disable
 Select the profile for the receiver. (for the high power profile) and is disables during transmitter
disable (for the lower power profile). The only trade-off is
the higher switching time required to turn on the DACs for
the lower power profile.

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The second user configurable tab is the Calibration tab. The performance. Using this mode, a further 3 dB margin is applied
Calibration tab is used to enable the initialization and tracking between the output signal and the LOL. The status bar at the
calibrations. Figure 29 shows a configuration example. The user bottom of the TES shows the status of the transmitter QEC and
can enable or disable initialization calibrations, as well as tracking receiver QEC tracking calibration and indicates whether the
calibrations. The initial calibrations, transmitter QEC, receiver radio state is on or off. A section is available to enable floating
QEC, and internal transmitter LOL, along with the Receiver 1 point mode. In addition, a section on the page allows the setup
QEC, Receiver 2 QEC, Transmitter 2 LOL, Transmitter 2 LOL, of receiver gain compensation mode, including the floating point
Transmitter 2 QEC, Observation Receiver 1 QEC and Observation options. Refer to the ADRV9008-1-W/ADRV9008-2-W/
Receiver 2 QEC tracking calibrations can be enabled for the ADRV9009-W Hardware Reference Manual for more
ADRV9009 (see Figure 29). The user can also enable 3 dB DAC information.
boost mode, in which the user can enhance the transmitter LOL

17032-219

Figure 29. Calibration Configuration Tab for the ADRV9009

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The third user configurable tab is the JESD204b Setup tab. The IQrate 368.64MHz, Dec5 as Rx profile, and the ORX 300 MHz,
JESD204b Setup tab is used to set the characteristics of the IQrate 368.64MHz, Dec5, 12bit, 11G as ORx profile.
digital data interface. Figure 30 shows a configuration example Configure the JESD204B section for ADRV9009 as follows:
for the ADRV9009. A subtab exists to select the receiver framer
and the transmitter deframer. The user can set the desired  The receiver framer selection must be set to Framer A.
JESD204B lane configuration, select scrambling, and whether to  The observation receiver framer selection must be set to
use an internal (free running) or external (provided by the Framer B.
AD9528) SYSREF to synchronize the JESD204B links. The last  The transmitter deframer selection can be set to either
check box in each framer/deframer is the option to relink on Deframer A or Deframer B.
SYSREF. A feature is available to set the JESD204B lane rate as  Ensure that the lane rates for Framer A and Observation
11 Gbps. The Np parameter is set to 12 for 11 Gbps mode. This Receiver Framer B are the same.
mode is currently only supported by the Tx 200/300 MHz,  Ensure that Framer A and Observation Receiver Framer B do
IQrate 368.64MHz, Int5, 11G Tx profile, the Rx 205 MHz, not use the same lanes.

17032-220

Figure 30. JESD204b Setup Tab for the ADRV9009

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The Tx Summary tab, Rx Summary tab, and ObsRx Summary Figure 23 shows an example of the ObsRx Summary tab. Figure 27
tab are primarily informative and are based on the profile shows an example of the Rx Summary tab with the resulting
selection in the Configuration tab (see Figure 28). In each tab, composite filter response for the chosen profile.
the user can check clock rates at each filter node, as well as filter Configuring the AD9528
characteristics and their pass-band flatness. Quick zooming
The daughter card uses the AD9528 clock chip to provide the
capability allows zooming of the pass-band response, as well as
reference clock (REF_CLK), as well as a SYSREF pulse to the
the ability to restore the full-scale plot. The TES also provides
ADRV9008-1, ADRV9008-2, and ADRV9009 and the FPGA via
the capability to export the data plotted on the graphs to an
the FMC connector. The AD9528 can be configured using the
external file. Perform this export by right clicking on the graph
Clock Setup tab, as shown in Figure 31. The input reference
area and saving the data to a file for later analysis. Figure 22
frequency can be selected from a drop-down menu. The user
shows an example of the Tx Summary tab with the resulting
must provide an external reference clock to the J401 SMA
composite filter response for the chosen profile.
connector that matches the frequency selected in the drop-
down menu. The signal amplitude must not exceed 5 dBm.

17032-224

Figure 31. AD9528 Configuration Page

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Programming the Evaluation System When programming completes, the system is ready to operate.
After all tabs are configured, the user must press the Program A progress bar appears at the bottom of the window. Figure 32
button. After pressing the Program button, TES sends a series displays the window with the progress bar and the message that
of API commands that are executed by a dedicated Linux appears after the device is successfully programmed. If an error
application on the Zynq platform. or warning message appears instead, see the Error Handling
section to search for troubleshooting guidelines.

Figure 32. Programming the Device Successfully 17032-225

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OTHER TES FEATURES future use. The TES generates the script in the form of an
Save/Load Profile IronPython (.py) file. This file can then be executed using the
IronPython Script tab shown in Figure 43. There is an option
The TES allows the user to store and load all configuration
to save a MATLAB-based initialization script for the chosen
settings described in the Normal Operation section. To save
setup in the GUI.
software settings, click the File > Save GUI Setup option, shown in
Figure 33. The TES generates a .xml format file with all software API Configuration Structure Initialization
settings recorded. The user can then can load software settings Based on the configuration settings described in the previous
by clicking the File > Load GUI Setup option and selecting the sections, the TES sets up structure member values that are then
saved setup file. The load custom profile function can be used used by API commands. The TES allows the user to create a *.c
to load profiles generated by the ADRV9008-1, ADRV9008-2, file that contains all of these initial values. This file can be imported
and ADRV9009 filter wizard. into a user system that uses the ADRV9008-1, ADRV9008-2, and
ADRV9009 APIs. To generate the *.c files, the user must click
the Tools > Save .c Init Script option. This action opens the
Save As window, requiring the user to name the file and specify
a location for storage. The TES generates files as follows:
 headless.c. This file provides an example file that makes
calls into the ADRV9008-1, ADRV9008-2, and ADRV9009
API to initialize the ADRV9008-1, ADRV9008-2, and
ADRV9009 device.
 headless.h. This file is a header file for headless.c.
17032-226

 user_name.c. This file contains all initialization values for

Figure 33. Configuration Menu Control Buttons the structure members used by the ADRV9008-1,
ADRV9008-2, and ADRV9009 APIs.
ADRV9008-1, ADRV9008-2, and ADRV9009 Initialization
 user_name.h. This file is a header file for user_name.c.
Script
 user_name_ad9528init.c. This file contains all initialization
The TES allows the user to create a script with all API initialization
values for the structures used by the AD9528 (clock IC) APIs.
calls in the form of IronPython functions. When the user clicks
the Tools > Save Python Script option, the script can be given a
file name and stored in a location (chosen by the user) for

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17032-227
Figure 34. Receive Data Tab

RECEIVER SETUP The receiver trigger drop-down menu can be used to select an
immediate trigger, an external trigger, or a TDD state machine
Receiver Signal Chain
pulse. The drop-down menu options are as follows:
After configuring software using the Config tab and selecting
 The IMMEDIATE option starts the capture as soon as the
Program, the system is ready for normal operation. Selecting
SPI command is received to initiate a capture operation.
the Receive Data tab opens a page as shown in Figure 34. After
the Receive Data tab is open, the user can enter the RF receiver  The EXT_SMA option starts the capture when a high level
center frequency in MHz. The receiver gain can be set by entering is present at Connector J68 on the Zynq platform.
the desired gain index for each receiver channel. The gain index  The TDD_SM_PULSE option starts the capture,
refers to the value in the programmable gain index table. Refer depending on the current state of the TDD state machine.
to the ADRV9008-1-W/ADRV9008-2-W/ADRV9009-W The received data can be saved to a file by clicking the floppy
Hardware Reference Manual for gain index table specifics. disk icon. Selecting this option displays a window allowing the
By pressing the play symbol in the Receiver Data tab, the user to select the format for the exported data. If the file type is
transceiver moves to the receive state and graphs received data in specified to be Agilent© data, the TES adds a header to the
both frequency and time domains. An example of a captured saved file that allows Agilent vector signal analyzer (VSA) software
waveform is shown in Figure 34. The upper plot displays the to use the header to read and demodulate the data. The header
FFT result and the lower plot shows the time domain waveform. is followed by data stored in I/Q format. Other formats supported
If the FFT analysis is selected (by clicking the multicolored pie by software are I Q (no header information) or I, Q (no header
chart symbol), basic analysis information from the FFT is information). The number of points saved to the file is determined
displayed on the left side of the screen. The status bar at the by the number of samples selected in the # Samples box.
bottom of the TES shows the status of the receiver QEC and
indicates whether the radio state is on or off.

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The TES allows the user to obtain the FFT of a particular time After pressing the play symbol in the ObsRx Data tab, the
slot by using the FFT Sliding Window Start Time (us) box and ADRV9008-2 or ADRV9009 moves to the receive state and
the FFT Sliding Window End Time (us) box. These functions graphs the output data. An example of a captured waveform is
allow the FFT to be calculated only for the selected time slot. shown in Figure 35.
The FFT Sliding Window Start Time (us) box denotes the The received data can be saved to a file by clicking the floppy
start time of the FFT sliding window, whereas the FFT Sliding disk icon. Selecting this option displays a window allowing the
Window End Time (us) box denotes the end time of the FFT selection of the format for the exported data. If the file type is
sliding window. The FFT sliding window start time must be specified to be Agilent data, the TES adds a header to the saved
greater than zero and less than the FFT sliding window end file that can be read by the Agilent VSA software and used to
time. The FFT sliding window end time must be less than the demodulate the data. The header is followed by data stored in I
maximum time shown in the time domain graph of the TES. <TAB> Q [new_line] format. Other formats supported by
The user can also rerun initial receiver calibrations by pressing software are I <TAB> Q [new_line] (no header information) or
the Rx Init Cals button. When calibrations are finished, the I,Q [new_line] (no header information). The number of points
button changes appearance to display a stopped condition. Note saved to the file is determined by the number of samples
that there must be no input signal applied to the receiver input selected in the # Samples box.
when performing an initialization calibration. Use initialization The TES allows the user to obtain the FFT of a particular time
calibrations when the image rejection must be high. slot by using the FFT Sliding Window Start Time (us) box and
The user can also enable or disable QEC tracking calibrations. the FFT Sliding Window End Time (us) box. These functions
The Rx1 QEC Tracking tick box enables calibration for the allow the FFT to be calculated only for the selected time slot.
Receiver 1 path and the Rx2 QEC Tracking tick box enables The FFT Sliding Window Start Time (us) box denotes the
calibration for the Receiver 2 path. Tracking calibrations start time of the FFT sliding window, whereas the FFT Sliding
operate when a receiver signal path receives real data. Window End Time (us) box denotes the end time of the FFT
Observation Receiver Signal Chain sliding window. The FFT sliding window start time must be
greater than zero and less than the FFT sliding window end
Selecting the ObsRx Data tab opens a page as shown in Figure 35.
time. The FFT sliding window end time must be less than the
The observation receiver gain can be set by entering the desired maximum time shown in the time domain graph of the TES.
gain index. The gain index refers to the value in the programmable
gain index table. Refer to the ADRV9008-1-W/ADRV9008-2-W/ To start operation of the observation receiver signal path, the
ADRV9009-W Hardware Reference Manual for gain index table Radio On button must be enabled.
specifics.

17032-228

Figure 35. ObsRx Data Tab

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TRANSMITTER SETUP After the Transmit Data tab is open, the user can enter the RF
transmitter center frequency in MHz, change the attenuation
Selecting the Transmit Data tab opens a page as shown in level, enable different calibrations, control data scaling, and
Figure 36. The upper plot displays the FFT of the digital input transmit CW tones. The status bar at the bottom of the TES
data, and the lower plot shows the time domain waveform. shows the status of the transmitter QEC and indicates whether
When the Transmitter 2 outputs are enabled, the user can select the radio state is on or off.
the Transmitter 2 data to be displayed in the spectrum plot. In
the time domain plot, the user can select Transmitter 2, I, or Q
data to be displayed.

17032-229

Figure 36. Transmit Data Tab

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17032-230
Figure 37. Transmitter Tone Parameters Setup Menu

Transmitter Data Options The Tx2 Attenuation (dB) input allows the user to control the
The TES provides the following options for inputting analog attenuation in the Transmitter 2 channel. This input
transmitter data: provides 0.05 dB of attenuation control accuracy. The Tx1
Attenuation (dB) input performs the same operation on the
 A single tone or two tones can be generated by the Transmitter 1channel.
evaluation system using the ToneParameters menu shown
in Figure 37. In this window, the user can select the The Tx2 LOL Tracking tick box enables a transmitter LOL
number of tones (1 or 2) to be transmitted on the selected calibration. This calibration improves the LOL performance
transmitter output. The user has control over the tone on the Transmitter 2 channel. The Tx1 LOL Tracking tick box
frequency offset with respect to the LO frequency and tone performs the same operation on the Transmitter 1 channel.
amplitude in dBFS. The user can store these signals in the To perform transmitter LOL tracking calibrations, external
form of test files by selecting the Save Tx Raw Data into a circuitry is required to route transmitter signals back through
File option. Note that the play button must be pressed an observation receiver input. For more details, refer to the
before data is populated in these files. Hardware Setup for External Transmitter LO Leakage
Calibration section. Note that, for external transmitter LOL
 User generated data files can be selected using the Load
tracking calibration, both transmitters must be looped back to
Tx2 button and the Load Tx2 button. Format the data files
both observation receivers through splitters and attenuators.
as one I sample and one Q sample per line. Each I or Q
sample must be in the range from +32767 to −32768. If the The Tx2 QEC Tracking tick box enables a transmitter QEC
I and Q samples are smaller than this range, the software calibration on the Transmitter 2 channel. This calibration
scale them up to numbers in the correct range. The file size improves the QEC performance. The Tx1 QEC Tracking tick
is limited to four mega samples (MS) for each channel (I box performs the same operation on the Transmitter 1 channel.
data = 4 MS maximum, and Q data = 4 MS maximum). The Tx2 Routed to Orx1 tick box advises the software that the
Pressing the play symbol moves the ADRV9008-2 or ADRV9009 user has configured an external loopback path from the
to the transmit state and starts a process where the generated Transmitter 2 output to Observation Receiver 1. The Tx1
CW data or the I/Q data in the Transmitter 2 files are sent to the Routed to Orx2 tick box performs the same operation for the
transceiver. The data is stored on the Zynq motherboard RAM and Transmitter 1 channel.
the RAM pointer loops through the data continuously until the The Tx Init External LOL button runs an external LOL initial
stop button is pressed. calibration.

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TIME DIVISION DUPLEX (TDD) MODE

The ADRV9009 transceiver evaluation hardware, together with  U denotes which subframe is reserved for uplink
TES, provides the capability to demonstrate TDD operation. transmissions.
LTE TDD FRAME STRUCTURE  S denotes a special subframe with the following three
fields: downlink pilot time slot (DwPTS), guard period
Preset configurations provided in the TES follow 3GPP
(GP), and uplink pilot time slot (UpPTS)
specifications, in which Frame Structure Type 2 is used for
TDD operation. In this configuration, each 10 ms radio frame The TES provides preset configurations for all uplink and
consists of two 5 ms half frames. Each half frame consists of five downlink configurations, with both 5 ms and 10 ms downlink
1 ms subframes. The supported uplink and downlink config- to uplink switch point periodicity. All preset configurations are
urations are listed in Table 1, where the following parameters shown in Figure 38. In the case of a 5 ms downlink to uplink
are described for each subframe in a radio frame: switch point periodicity, the special subframe exists in both half
frames. In the case of a 10 ms downlink to uplink switch point
 D denotes which subframe is reserved for downlink
periodicity, the special subframe exists in the first half frame only.
transmissions.

Table 1. Uplink and Downlink Configurations

Subframe Number1
Uplink/Downlink Configuration No. Downlink/Uplink Switch Point Periodicity (ms) 0 1 2 3 4 5 6 7 8 9
0 5 D S U U U D S U U U
1 5 D S U U D D S U U D
2 5 D S U D D D S U D D
3 10 D S U U U D D D D D
4 10 D S U U D D D D D D
5 10 D S U D D D D D D D
6 5 D S U U U D S U U D
1
D means a downlink subframe, S means a special switching subframe, and U means an uplink subframe.

1 FRAME = 10ms
1 SUBFRAME = 1ms

0 DL SS UL UL UL DL SS UL UL UL

1 DL SS UL UL DL DL SS UL UL DL

2 DL SS UL DL DL DL SS UL DL DL

3 DL SS UL UL UL DL DL DL DL DL

4 DL SS UL UL DL DL DL DL DL DL

5 DL SS UL DL DL DL DL DL DL DL

6 DL SS UL UL UL DL SS UL UL DL
17032-231

DL = DOWNLINK SUBFRAME
UL = UPLINK SUBFRAME
SS = SPECIAL SWITCHING SUBFRAME

Figure 38. Graphical Representation of Uplink and Downlink Configurations in the TDD Frame

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ADRV9009 EVALUATION HARDWARE IN TDD MODE The ADRV9009 evaluation system provides a synchronization
For TDD operation, the initialization calibrations are run just as pulse on the Zynq motherboard SMA connector, J67. The user
they are for FDD mode. After the initialization calibrations are can use this pulse to synchronize external measurement
complete, the TDD command is used to place the device in equipment. Fine tune this signal using the TES interface
TDD mode. TDD mode works only when configuring the GUI described in the TES Interface for TDD Mode section. After all
for the ADRV9009 hardware. hardware is connected properly, the user can start configuring
the software.
The FPGA on the Zynq platform contains a configurable TDD
state machine that can be used to control the TX_ENABLE, For successful TDD operation, ensure that the following setup is
RX_ENABLE, and GPIO signals provided to the transceiver. available:
The TDD/FDD Switching tab in the TES allows enabling and  TES Version 1.0.25.0 or above
disabling of the TDD state machine and configuration of the  Dynamic link library (DLL) Version 1.0.29.20 or above
transmitter and receiver regions in the TDD frame pulse to  Command Server Version 1.0.29.20 or above
either a preset LTE TDD configuration, or a user-defined  FPGA Version 4E000101 or above
configuration.  Arm Version 0.07.04 or above
The ARM processor insideADRV9009 uses the RX_ENABLE,  Stream Version 0.00.01 or above
TX_ENABLE, and GPIO signals controlled by the Zynq FPGA
TES Configuration
to determine when the device is in the receiver state, transmitter
state, observation receiver state, and so on. Figure 39 is a timing Perform the following procedure before enabling TDD mode
diagram of the TX_ENABLE and RX_ENABLE signals during using the TES:
the LTE Configuration 0 type frame. The ADRV9009 respond 1. Using the TES interface described in the Configuring the
based on the level of the TX_ENABLE and RX_ENABLE signals. ADRV9008-2 Transmitter section, select profiles for the
Note that the minimum duration for RX_ENABLE or TX_ receiver channels, transmitter channels, and observation
ENABLE is 500 μs for proper calibration operation. receiver channels as follows:
GP 1ms
 Receiver = 200 MHz, I/Q rate = 245.76 MHz
LTE UL-DL CONFIG 0 D S U U U D S U U U  Transmitter = 200 MHz/450 MHz, I/Q rate =
491.52 MHz
TX_ENABLE
 Observation receiver = 450 MHz, I/Q rate =
491.52 MHz
OVERLAP
17032-232

RX_ENABLE 2. Configure the JESD204B section of the TES as follows

(Figure 40 shows a typical setup for JESD204B in the TES):
Figure 39. Timing Diagram Showing Example RX_ENABLE/TX_ENABLE
Signaling for LTE Uplink/Downlink Configuration 0  Set the receiver framer selection to Framer A.
SETTING UP TDD FUNCTIONALITY  Set the observation receiver framer selection to
Framer B.
To operate the ADRV9009 evaluation system and TES in TDD
 Set the transmitter deframer selection to either
mode, the user must perform the steps described in the
Deframer A or Deframer B.
following sections.
 Ensure that the lane rates for Framer A and
Hardware Configuration Observation Receiver Framer B are the same.
Follow the description of hardware configuration in the  Ensure that Framer A and Observation Receiver
Hardware Setup section. Framer B do not use the same lanes.

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17032-233
Figure 40. Typical JESD204B Setup for TDD Operation in the TES

3. Using the calibration page described in the Configuring 7. After theADRV9009 evaluation system is programmed,
the ADRV9008-2 Transmitter section, enable the desired move to the ObsRx Data tab show in Figure 35. In this tab,
calibrations. a. Set the receiver trigger to TDD_SM_PULSE.
4. After all configuration is complete, program the b. Set the sample time to be at least 1 frame length (10 ms
ADRV9009 evaluation system by clicking the Program for standard LTE TDD Type 2 frame structures,
button. described in the LTE TDD Frame Structure section).
5. After theADRV9009 evaluation system is programmed, move c. Click the play button.
to the Receiver Data tab show in Figure 34. In this tab, 8. The final step requires the user to select the desired TDD
a. Set the receiver trigger to TDD_SM_PULSE. timing profile using the TES TDD/FDD Switching tab
b. Set the sample time to be at least 1 frame length shown in Figure 41. See the TES Interface for TDD Mode
(10 ms for standard LTE TDD Type 2 frame structures, section for a detailed description of this tab. After all
described in the LTE TDD Frame Structure section). timing settings are configured,
c. Click on play button. a. Click the SetUp TDD Timings button.
6. Next, click on the Transmit Data tab shown in Figure 36. In b. Click the Enable Tx Data Transmit button.
this tab,
If the user does not follow this sequence, the TES software
a. Load data files that are time aligned with the desired
provides real-time pop-up warning messages. These messages
LTE TDD Type 2 frame structure. The TES provides
inform the user about possible misconfigured settings.
an example data file that can be used with the LTE
TDD 0 Type 2 frame structure. For more information,
see the TES Interface for TDD Mode section.
b. Click the play button.

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378

TES INTERFACE FOR TDD MODE parameters described are allowed to configure the desired
If the device is programmed successfully, the TDD/FDD RF paths with user specific timing. The TES also provides a
Switching tab in the TES becomes active. Figure 41 shows the special mode called custom LTE TDD0. This mode configures
TES TDD interface tab. The parameters available to the user in the ADRV9009 hardware and software with LTE TDD 0
this tab are as follows: frame timing optimized specifically to suit the evaluation
platform. The TES also provides transmitter data files with
 Preset allows the user to select one of seven LTE TDD timing optimized for this particular mode. Users can find
Type 2 frame structures (see the LTE TDD Frame Structure these files in the Resources subfolder, located inside the
section) and provides options for user specific TDD frame TES installation folder. The name of the file is TDD_
timing. If the user selects one of seven LTE TDD Type 2 491p52MSPS_20M_TM3p1_Cfg0.txt.
frame structures, then all the following parameters provide  The Total Frame Time[μs] field determines the total
detailed timing information for enabling and disabling the length of a single TDD frame in microseconds.
RF signal paths. If the user selects custom mode, then all

17032-234

Figure 41. TES TDD Interface Tab

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UG-1378 EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide

FIRST SECOND
STOP TIME STOP TIME

FIRST SECOND
START TIME START TIME

FIRST SECOND
STOP TIME STOP TIME

17032-235
SECOND FIRST
START TIME START TIME

Figure 42. Naming Convention Used for TDD Start/Stop Description in TES

A section of TDD parameters, Transmit Path, allows the user  If more than one Receiver 2 subframe (or group of subframes)
to control the following fields: is used, then the Second Rx2 Time[μs] field determines
 The First Tx2 Time[μs] field determines the beginning the beginning and end of the second Receiver 2 subframe
and end of the first Transmitter 2 subframes (or group of (or group of subframes).
subframes). The Start Time (μs) column determines the A section of TDD parameters called Orx Path allows the user to
beginning of a subframe (or group of subframes) in a control the following fields:
single frame. The Stop Time (μs) column determines the
 The First Orx1 Time[μs] field determines the beginning
end of a subframe (or group of subframes) in a single
and end of the first Observation Receiver 1 subframe (or
frame. The TES TDD interface follows the convention
group of subframes).
where a subframe (or group of subframes) is enabled at the
end and at the beginning of a frame border, and then the  The First Orx2 Time[μs] field determines the beginning
start is marked at the end of a single frame. Figure 42 provides and end of the first Observation Receiver 2 subframe (or
a graphical explanation of the naming conventions used in group of subframes).
the TES.  If more than one Observation Receiver 1 subframe (or
 The First Tx2 Time[μs] field determines the beginning group of subframes) is used, then the Second Orx1
and end of the first Transmitter 2 subframe (or group of Time[μs] field determines the beginning and end of the
subframes). second Observation Receiver 1 subframe (or group of
subframes).
 If more than one Transmitter 2 subframe (or group of
subframes) is used, then the Second Tx2 Time[μs] field  If more than one Observation Receiver 2 subframe (or
determines the beginning and end of the second group of subframes) is used, then the Second Orx2
Transmitter 2 subframe (or group of subframes). Time[μs] field determines the beginning and end of the
second Observation Receiver 2 subframes (or group of
 If more than one Transmitter 2 subframe (or group of
subframes).
subframes) is used, then the Second Tx2 Time[μs] field
determines the beginning and end of the second A section of TDD parameters called Tx to Orx Path allows the user
Transmitter 2 subframe (or group of subframes). to control external signal routing for external LOL initialization
calibrations and tracking calibrations using the following fields:
A section of TDD parameters called Receive Path allows the
user to control the following fields:  The First Tx2 to Orx1 Time[us] field determines the
beginning and end of the first Transmitter 2 to Observation
 The First Rx1 Time[μs] field determines the beginning
Receiver 1 subframe (or group of subframes).
and end of the first Receiver 1 subframe (or group of
subframes).  The First Tx2 to Orx2 Time[us] field determines the
beginning and end of the first Transmitter 2 to Observation
 The First Rx2 Time[μs] field determines the beginning
Receiver 2 subframe (or group of subframes).
and end of the first Receiver 2 subframe (or group of
subframes).
 If more than one Receiver 1 subframe (or group of
subframes) is used, then the Second Rx1 Time[μs] field
determines the beginning and end of the second Receiver 1
subframe (or group of subframes).

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378
 If more than one Transmitter 2 to Observation Receiver 1  In TDD mode, the ADRV9008-1, ADRV9008-2, and
subframe (or group of subframes) is used, then the Second ADRV9009 evaluation hardware generates a pulse on SMA
Tx2 to Orx1 Time[us] field determines the beginning and Connector J67, located on the Zynq platform. The External
end of the second Transmitter 2 to Observation Receiver 1 Trigger [μs] parameter allows the user to control the position
subframe (or group of subframes). and the width of this pulse in reference to the start of the
 If more than one Transmitter 2 to Observation Receiver 2 TDD frame.
subframe (or group of subframes) is used, then the Second  The Loop N Times option allows user to control the
Tx2 to Orx2 Time[us] field determines the beginning and number of loop repetitions. The allowable range is from 1
end of the second Transmitter 2 to Observation Receiver 2 to 15, or the loop repetition continues until stopped.
subframe (or group of subframes).
The bottom part of the TDD/FDD Switching tab in the TES
 The First Tx2 to Orx1 Time[us] field determines the
provides a diagram with a graphical representation of the timing
beginning and end of the first Transmitter 2 to Observation
parameters entered in the table above. This feature allows the
Receiver 1 subframe (or group of subframes).
user to visually represent activities on the receiver and
 The First Tx2 to Orx2 Time[us] field determines the transmitter datapaths.
beginning and end of the first Transmitter 2 to Observation
Receiver 2 subframe (or group of subframes). The TDD page also contains four buttons to interact with the
 If more than one Transmitter 2 to Observation Receiver 1 user. These buttons include
subframe (or group of subframes) is used, then the Second  SetUp TDD Timing. Pressing this button causes the current
Tx2 to Orx1 Time[us] field determines the beginning and TDD configuration stop/start parameters from the table to
end of the second Transmitter 2 to Observation Receiver 1 be written into the FPGA and sets up the state machine for
subframes (or group of subframes). operation. This button also zeroes the transmitter datapath,
 If more than one Transmitter 2 to Observation Receiver 2 resets the transmitter RAM pointer to the start address of
subframe (or group of subframes) is used, then the Second the data, and then reconnects the transmitter RAM to the
Tx2 to Orx2 Time[us] field determines the beginning and transmitter datapath. Finally, this button enables the TDD
end of the second Transmitter 2 to Observation Receiver 2 state machine and starts the data. After the evaluation system
subframe (or group of subframes). is in the TDD state, this button changes its name to Disable
TDD. Pressing this button stops the TDD state machine.
If the user programmed ADRV9009 using Observation Channel 1,
 Enable Tx Data Transmit. After the user sets up TDD
then an error message appears if the user attempts to set up the
mode and presses the SetUp TDD Timing button, the
TDD timings and enters values in the Tx2 to Orx2 field. A further
ADRV9009 evaluation system enables the TDD state
requirement of the observation receiver path assignment relates to
machine and TDD mode becomes operational. There is no
the minimum duration of an ARM tracking calibration in any
data present at the transmitter output until the user presses
one instance. This duration is 500 μs. This requirement is due to
the Enable Tx Data Transmit button. This button enables
the tracking calibrations needing at least 500 μs of data
the data transfer in the FPGA. The transmitter datapath is
to perform a meaningful observation.
zeroed until the Enable Tx Data Transmit button is
The section of TDD parameters named Misc allows the user to pressed (data does not start until the Enable Tx Data
control the following fields: Transmit button is pressed). After entering TDD mode,
 The Tx Path Delay (+/-μs) field allows the user to delay the transmitter data is sent continuously to the device
data sent to the transmitter path over the JESD204B through the JESD204B link (which is not gated by the
interface in reference to the TX_ENABLE signal. TX_ENABLE signal). Therefore, the TDD transmitter data
 The Rx Path Delay (+/-μs) field allows the user to delay files must be properly time aligned to the TDD state
data received from the receiver path over the JESD204B machine signals.
interface in reference to the RX_ENABLE signal.  The Save TDD Frame Timing button allows the user to
 The Obs Rx Path Delay (+/-μs) field allows the user to save a TDD timing to the file in a text readable format.
delay data received from the observation receiver path  The Load TDD Frame Timing button allows the user to
over the JESD204B interface in reference to the ORX_ load TDD timing information from the previously saved
ENABLE signal. TDD timing file.

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UG-1378 EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide

SCRIPTING The Iron Python Script tab allows the user to use IronPython
After the user configures the device to the desired profile, a language to write a unique sequence of events and then execute
script can be generated with all API initialization calls in the them using an evaluation system.
form of IronPython functions. Use the Tools > Create Script > Scripts generated using the Save Python Script button can be
Python button to accomplish this task. This button is located loaded, modified if needed, and run in the Iron Python Script
on top of the Config tab. tab. Figure 43 shows the Iron Python Script tab after executing
the new script function. The top part of the window contains
IronPython commands, and the bottom part of the window
displays the script output.

17032-236

Figure 43. Iron Python Script Tab

IronPython Script Example

The following example, which is generated after selecting the New button in the Iron Python Script tab, returns the version of command
interpreter software running on the Zynq platform:

#Import Reference to the DLL

import clr
clr.AddReferenceToFileAndPath("C:\\Program Files (x86)\\Analog Devices\\ADRV900x Transceiver
Evaluation Software\\AdiCmdServerClient.dll")
from AdiCmdServerClient import AdiCommandServerClient
from AdiCmdServerClient import Talise

#Create an Instance of the Class

Link = AdiCommandServerClient.Instance

#Connect to the Zynq Platform

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378
if(Link.hw.Connected == 1):
Connect = 0
else:
Connect = 1
Link.hw.Connect("192.168.1.10", 55555)

#Read the Version

print Link.Version()

#Disconnect from the Zynq Platform

if(Connect == 1):
Link.hw.Disconnect()
When using the Iron Python window, the user can execute any API command.
A list of all API commands is provided in the TES in Help > API Help. All ADRV9008-1, ADRV9008-2, and ADRV9009 API functions,
when called in the Iron Python window, must be renamed to reflect the following IronPython mnemonic:
ADRV900X -> Talise.
Add a header with a new class instance for a new connection. For example, after calling
#Create an Instance of the Class
Link = AdiCommandServerClient.Instance
the new class instance for the ADRV9008-1, ADRV9008-2, and ADRV9009 evaluation hardware is
Link.
An example of an API function call using Iron Python is as follows (if the user wants to check the gain index for Receiver 1 using the
following ADRV9008-1, ADRV9008-2, and ADRV9009 API function):
TALISE_GetRxGain
Then, the user calls the IronPython function that follows (assuming the platform is initialized using the example code previously described):
print Link.Talise.GetRxGain(Link.Talise.RxChannel.Rx1, 0)
For a complete list of available script commands, refer to the Talise_TCPIP_Client_Library.chm file located in the Resources folder of the
TES.

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UG-1378 EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide

TROUBLESHOOTING
The following section is a quick help guide describing what to LEDs Active, Hardware Not Connected
do if the system is not operational. This guide assumes that the If the LEDs are active, but the TES reports that the hardware is
user follows the instructions and the hardware configuration not connected,
described in this user guide.
1. Check if the Ethernet cable is properly connected between
STARTUP the PC used to run the TES and the Zynq platform. The
No LED Activity LEDs on the Zynq platform next to the Ethernet socket
If there is no LED activity at startup, flash when the connection is active.
2. If the cable is properly connected, check if the Windows
1. Check if the board is properly powered. There must be 12 V operating system is able to communicate over the Ethernet
present at the J22 input, and after powering the Zynq port with the Zynq platform. Check if the IP number
platform on (SW1 is turned on), the following must be true: and the open ports for the Ethernet connection used to
 The fan on the Zynq platform is activated. communicate with the Zynq platform follow the guidelines
 A number of green LEDs on the Zynq platform near described in the Hardware Setup section.
SW1 are on with no red LEDs active on the Zynq 3. Run cmd.exe and then type ping 192.168.1.10. The can
platform. then see a reply from the Zynq platform. If no reply is
 The Zynq GPIO LEDs follow the sequence described received, connection with the Zynq platform must be
in the Hardware Operation section. re-examined.
4. If connection with the Zynq platform is established but the
2. If the LED sequence does not follow the sequence TES still reports that hardware is not available, ensure that
described, check the jumper settings and the SW11 Port 22 (SSH) and Port 55555 (evaluation software) are not
positions on the Zynq platform. If these settings and blocked by firewall software on the Ethernet connection used
positions are correct, check if the SD card is correct and to communicate with the Zynq platform. Both ports are
properly inserted in the J30 socket. Use the SD card required to be open for normal operation.
supplied with the evaluation kit.
ERROR HANDLING
If there is still a problem and the user is certain that the Zynq
The TES provides the user a number of error messages in the
platform is operational, contact an Analog Devices representative
event of problems with hardware or software configuration. The
for help.
error messages displayed by the TES are listed in Table 2. For
each error, the table contains an explanation of how to interpret
the reason for the error message and what action must be
performed to solve potential problems.

Table 2. Error Messages and Possible Solutions

Error Message Description
A connection attempt failed because the These messages indicate that the user attempted to establish connection before readying
connected party did not properly respond the hardware. To solve this problem, perform a power cycle of the Zynq platform and
after a period of time, or established wait until the hardware is fully booted up. The LED indication that system is ready is
connection failed because connected hose described in the Hardware Operation section.
tailed to respond
An established connection was aborted by the
software in your host machine
Connection was terminated by remote host These messages are shown when the Ethernet cable is disconnected or when the Zynq
board loses power. To resolve this issue, check if all hardware connections are correct,
and that the Zynq motherboard and ADRV9008-1, ADRV9008-2, and ADRV9009 daughter
card are powered. Also, restart the ADRV9008-1, ADRV9008-2, and ADRV9009
transceiver evaluation software.
An existing connection was forcibly closed by
the remote host
Cannot connect to device This message is shown when power to the ADRV9008-1, ADRV9008-2, and ADRV9009
daughter card is lost. Ensure that ADRV9008-1, ADRV9008-2, and ADRV9009 daughter
card is connected to J37 on the Zynq board and that the 6 V supply is adequately
connected. The Hardware Operation section describes the correct status of the LEDs on
the ADRV9008-1, ADRV9008-2, and ADRV9009 daughter card.

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EVAL-ADRV9008-1-W/PCBZ/ADRV9008-2-W/PCBZ/ADRV9009-W/PCBZ User Guide UG-1378
Error Message Description
AD9528 REFCLK not detected or PLLs not locked This message indicates that clock chip is not able to lock to the reference signal.
Potential problems in this scenario include a lack of reference signal, incorrect
amplitude, or incorrect frequency. Ensure that external reference clock is connected to
the J401 SYSREF_IN SMA connector at the ADRV9008-1, ADRV9008-2, and ADRV9009
daughter card as shown in Figure 2. The reference frequency must match the frequency
selected in the AD9528 configuration tab, as shown in Figure 31. The amplitude of the
reference signal must not exceed 5 dBm. Correct hardware and software configuration
of the reference clock is indicated by the LED status on the ADRV9008-1, ADRV9008-2,
and ADRV9009 daughter card as described in the Hardware Operation section.
All lane rates are 0 Gbps (disabled) This message indicates that all the transmitter and receiver paths are disabled. At least
one of the paths must be enable when programming the transceiver.
No Rx lanes enabled. Please check selection of Rx This message is related to the JESD204B interface configuration. If the receiver path is
lanes enabled and there are no receiver lanes on the JESD204B interface assigned to the
receiver path, then this error message appears. Select the appropriate lanes for the
receiver using the TES tab shown in Figure 26. Similarly, this error message is shown for
the transmitter or observation receiver JESD204B setup.
Rx lane rate too high. Please check selection of These messages relate to the JESD204B interface configuration. Ensure that the lane rates for
Rx lanes the receiver framer, observation receiver framer, and transmitter deframer match.
Invalid Tx K value
Error during ADRV900x RF PLL frequency setup: This message appears when the user uses the external LO frequency, but the frequency
ERROR:34 setRFPllFrequency is different than expected.
Error during setting of ADRV900x ENSM state: These messages are generated when system is in invalid state. To resolve the problem
ERROR:5 setEnsmState please restart the TES and power cycle the Zynq platform.
Synchronization error. Please power cycle TES
and Zynq Platform
No hardware connection

ESD Caution
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection
circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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UG17032-0-6/18(0)

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