Chapter Four.

Interfacing

Microcomputer And Interfacing

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Outline of the chapter

✔ Basic Input/output Interfacing

✔ Memory Interfacing
✔ 8255 PPI interfacing
✔ Stepper motor interfacing

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 I/O Instructions
• Two types:
• Transfer data between the processor accumulator (AL, AX, EAX) register and I/O
device: IN and OUT
• - Transfer string data between memory and I/O device directly: INS and OUTS
(for processors above 8086)
• The IN instruction (I/O Read): Inputs data from an external I/O device to the
accumulator.
• The OUT instruction (I/O Write): Copies the contents of the accumulator out to an
external I/O device.
• The accumulator is:
• - AL (for 8-bit I/O),
• - AX (for 16-bit I/O),
• - EAX (for 32-bit I/O).

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 I/O Address
• As with memory, I/O devices have I/O addresses (addresses for the I/O port)
• Up to 64K I/O bytes can be addressed
• The 16-bit port address appears on address bus bits A15-A0
This allows I/O devices at addresses 0000H-FFFFH
• Two ways to specify an I/O port address:
• An 8-bit immediate (fixed) address (specified as a byte in the instruction):
• e.g. IN AX, p8 ; Reads a word from port p8
• 0000H-00FFH (can only see the first 256 addresses)
• A 16-bit address located in register DX (can be easily varied):
• e.g. OUT DX, AL; outputs the byte in AL to the port whose address is in DX
• 0000H-FFFFH (upto 16 bit addresses). i.e. high port addresses are
DX
• accessible only through DX addressing 00FF

Immediate
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 I/O Data widths
•As with memory, I/O ports are also organized as bytes
•A port can be 1, 2, or 4 bytes wide (not 8 bytes wide on the
Pentium)

Low Endian scheme:

Low address byte contains
low end (LS) part of data

Port is 4 bytes wide

00F3H

00F2H E
A Port is 2 bytes wide
00F1H X
AX Port is 1 byte wide
A
Port Address p8 00F0H LS byte L 5
 INS and OUTS I/O instructions
• They address I/O port using register DX

• Transfer string data between port and memory

• - INS: Moves string data to the Extra Segment; ES:DI

• - OUTS: Moves data from the Data Segment; DS:SI

• As with other string instructions, DI and SI can be automatically incremented or

decremented depending on the state of the DF (direction flag) bit

• Data width of transfer specified by using INSB, INSW, and INSD for byte, word, and
double word

• Can be prefixed with REP to repeat the instruction for a number of times stored in CX
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(Note corrections)

a d
Re
I/O
DX

r i t e
W
I/O
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 Isolated vs. Memory Mapped
• I/O can be either:

• - Isolated, or Memory mapped

• Isolated I/O: uses the dedicated I/O instructions (IN, OUT and INS, OUTS) and has its own
address space for I/O ports (0000H-FFFFH)- isolated from the memory address space

• Memory mapped I/O: uses memory reference instructions , e.g. MOV, and a region of the
memory address map. So address space is shared between memory and I/O

• Both techniques can be used with Intel processors

• But most Intel-based systems e.g. the PC, use isolated I/O

• Some other processors do not have dedicated I/O instructions and therefore use only
memory-mapped I/O addressing, e.g. the PowerPC microprocessor (Macintosh computers)

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Basic Input/ Output Interfacing

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Memory and I/O address
Maps for the 8086/8088
Memory: I/O Port specified
in DX, either explicitly or implicitly
MOV

a. Isolated I/O I/O:

Using dedicated I/O IN 64 K
instructions e.g. IN, OUT I/O bytes
00FF

Port specified immediately

as a byte in the I/O instruction

MOV

Range of memory addresses

b. Memory-mapped I/O assigned for I/O transfers
Using ordinary memory
transfer instructions Memory
e.g. MOV

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IN (I/O Read)
• The IN instruction primarily takes the following forms:
Data from the Input port addressed
is put on the data bus for the processor to read
• into the A register
• IN AL,23H ;immediate
• IN AL,DX ;DX holds address
• IN AX,44H
• IN AX,DX
• IN EAX,2AH
• IN EAX,DX

Size of data transferred in each case?

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OUT (I/O Write)
• The OUT instruction primarily takes the following
forms:
Data from the AL register is put on the data bus for
latching into the Output port addressed
• OUT 23H,AL ;immediate
• OUT DX,AL ;DX holds port
• OUT 4CH,AX
• OUT DX,AX
• OUT 1EH,EAX
• OUT DX,EAX

Size of data transferred in each case?

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Basic Input Port (for I/O Reads)
• The basic input port connects an external set of bits to the μP data bus
whenever the μP executes the correct IN instruction with the correct I/O port
address

• External device puts data on the μP data bus

• Must include a 3-state (Tri-State) buffer to limit access to the processor

data bus to the duration of executing the I/O instruction only

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 Basic 8-bit Input Interface:
Reads the status of 8 toggle
Switches (a byte read)

Pull-up
Resistors To μP
Gate

Outputs:
0 1 Normally Hi-Z
Toggle switches Unless device is
Selected
3-state buffer (both G1 and G2 low)
The SEL signal is generated (active low)
By decoding: Circuit can be expanded for
- The address for the I/O port 16-bit (word) or 32-bit (DWord)
- The I/O READ operation interfaces 14
 Basic Output Port (for I/O Writes)
• The basic output port writes data from the mP data bus to an output port whenever the mP

executes the correct OUT instruction with the correct I/O port address

• Must latch the processor data put on the bus during the I/O instruction to make it

available indefinitely for the port

• No need for 3-state (Tri-State) buffers as the data bus is at the input side of the latch

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 Basic 8-bit Output Interface:
Controls 8 LEDs (1: OFF, 0: ON)

Circuit can be expanded for

16-bit (word) or 32-bit (DWord)
interfaces

From μP
Edge-triggered
latch

OE
No HiZ. Data is latched and remains here until the next OUT
O/P always
instruction to this port is executed
enabled
The SEL is generated (for + ive edge triggering) by decoding:
- The address for the I/O port
- The I/O WRITE operation 16
 Parallel Port
• The parallel port is an example of interfacing slow devices, e.g. a printer, to the processor

• A printer can print say 100’s of characters per sec (CPS), but the processor can output as
many as 1000’s of CPS

• To achieve ‘flow control’ and proper operation we use a technique called handshaking

• Handshaking regulates the flow of data from the processor to a slower peripheral device
to ensure correct operation

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 Interfacing
When connecting external input and output devices to the processor, we must take into account the
DC characteristics and drive capabilities of the mP pins.

(Fan-out considerations
For outputs before)

Input Devices, e.g. Output Devices, e.g.

μP
Switches LEDs

μP Input μP Output

Source Sink

Sink Source

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 Port Address Decoders
• As with memory addresses, port addresses must also be decoded to select an I/O device for a
particular port number.

• Memory mapped I/O is identical to memory access (with IO/#M = 0)

• Will consider here only isolated I/O (using dedicated instructions: IN, OUT, etc.)

• Most embedded systems use only fixed I/O addressing:

• - i.e. Only the least significant eight address bits A7-A0 are decoded. Limits number of I/O
ports to 256 (enough)

• PC systems used fixed/variable I/O addressing:

• - All 16-bits of the I/O address A15-A0 are decoded, allowing the use of up to 64K ports

• Decoding is simpler than for memory- smaller # of address lines

• Isolated I/O transfers are activated using (depending on processor and mode):

• - IO/#M = 1, M/#IO = 0, #IORC, #IOWC, #RD, #WR, W/#R

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BUS
BUFFERING
AND
LATCHING

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BUS
BUFFERING
AND
LATCHING

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BUS
BUFFERING
AND
LATCHING

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❑ Basic Bus Operation
• The three buses of 8086/8088 function the same way as any other microprocessor.
• If data are written to memory the processor:
• outputs the memory address on the address bus
• outputs the data to be written on the data bus
• issues a write (WR) to memory
• and IO/M= 0 for 8088 and IO/M = 1 for 8086
• Strobe Width
• The other timing factor to affect memory operation is the width of the RD strobe.
• The time for this strobe at a 5 MHz clock rate is 325 ns.
• This is wide enough for almost all memory devices manufactured with an access
time of 400 ns or less.

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Chapter Four: Interfacing
Programmable Peripheral Interface (8255A)

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Outline of the topic

✔ Pin diagram
✔ Block diagram
✔ Interfacing the 8255
✔ Programming the 8255
• Mode 0
• Mode 1
• Mode 2

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

❑ Pin diagram:

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Programmable Peripheral Interface (8255)

❑ Block diagram:

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29
 Programmable Peripheral Interface (8255)

❑ Block diagram:
• Data Bus Buffer
• This tri-state bidirectional buffer is used to interface the internal data bus of 8255 to
the system data bus.

• Input or Output instructions executed 'by the CPU either Read data from, or Write data
into the buffer.

• Output data from the CPU to the ports or control register, and input data to the CPU
from the ports or status register are all passed through the buffer.

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Programmable Peripheral Interface (8255)

❑ Block diagram:
• Control Logic
• The control logic block accepts control bus signals as well as inputs from the address
bus, and issues commands to the individual group control blocks (Group A control
and Group B control).

• It issues appropriate enabling signals to access the required data/control words or

status word.

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Programmable Peripheral Interface (8255)

❑ Block diagram:
• Group A and Group B Controls
• Each of the Group A and Group B control blocks receives control words from the
CPU and issues appropriate commands to the ports associated with it.

• The Group A control block controls Port A and PC7-PC4 while the Group B control
block controls Port B and PC3-PC0.

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Programmable Peripheral Interface (8255)

❑ Block diagram:
• Group A and Group B Controls
• Port A: This has an 8-bit latched and buffered output and an 8-bit input latch. It can be
programmed in three modes: mode 0, mode 1 and mode 2.
• Port B: This has an 8-bit data I/O latch/ buffer and an 8-bit data input buffer. It can be
programmed in mode 0 and mode 1.
• Port C: This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer. Port C can
be split into two parts and each can be used as control signals for ports A and B in the
handshake mode. It can be programmed for bit set/reset operation.

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

❑ Interfacing the 8255

✔ Figure 4-44 shows a diagram of the 8255 and its I/O and
control signals.

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Programmable Peripheral Interface (8255)
❑ Interfacing the 8255
✔ When the address bus contains one of these four port addresses during an I/O access, (CS) ̅ will
be pulled low. The 8255 will internally decode the states of A0 and A1 and determine which
port to access.

✔ In this example, port A has port address A0H, Ports B and C are accessed through ports A1H
and A2H, respectively, and the control port is at A3H.

✔ The nicest feature of the 8255 is that different hardware circuits can be connected to ports A, B,
and C, with the direction (input or output) of each port configured with initial programming.

✔ This allows an 8088/86-based system with an 8255 in it to be used for many different purposes.

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Programmable Peripheral Interface (8255)

❑ Programming the 8255

▪ The 8255 can be programmed to operate in three I/O modes of operation and BSR.
✔ Mode 0 operation (basic input/output):

✔ Mode 1 operation (strobed input/output)

✔ Mode 2 operation (strobed bidirectional I/O)

✔ Bit set or reset (BSR)

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Programmable Peripheral Interface (8255)

❑ Programming the 8255

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Programmable Peripheral Interface (8255)

• The first is mode 0: basic input/output.

• In this mode, ports A, B, and C can be individually programmed as input or output ports.
• Port C is divided into two 4-bit halves, directionally independent from each other.

Example 4-5: Find the control(mode) word if PA=out, PB=in, PC0-PC3=in and PC4-PC7=out.
And program the 8255 to get data from port B and send it to port A.
In addition, data from PCL is sent out to the PCU
Use port addresses of 300H-303H for the 8255 chip

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

❑ Mode 1 Operation:
✔ Port B operates in the same way, using PC2 and PC1 as handshaking signals.

✔ Both ports have the capability of causing an interrupt when data is strobed into them.

✔ The INTR output will go high when IBF goes high and the internal interrupt-enable bit
is set.

✔ PC4 and PC2 make up the interrupt-enable bits for ports A and B. Setting PC4 will
cause INTRa to go high when data is strobed into port A.

✔ Reading the input port will clear the interrupt request. This interrupt mechanism is a
useful alternative to using software to constantly poll the input port.

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Programmable Peripheral Interface (8255)

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Programmable Peripheral Interface (8255)

❑ Mode 1 Operation:

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Programmable Peripheral Interface (8255)

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 Programmable Peripheral Interface (8255)
❑ Mode2 Operation
❑ Reading Assignment

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 Programmable Peripheral Interface (8255)

❑ BSR/Bit Set-Reset/ mode Operation:

✔ This mode is concerned only with the 8 bits of port C which can be set
or reset by writing appropriate control word into the control register.

✔ BSR control word has D7 = 0;

✔ BSR control word does not affect any previously transmitted I/O control
word with D7 = 1.

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 Programmable Peripheral Interface (8255)

❑ BSR mode Operation:

✔ BSR control word :This is shown in Figure 4-49. it sets or resets port C bits,
one bit at a time.

✔ In this mode, individual bits of port C can be used for applications such as an
On/Off switch.

✔ The BSR word can also be used for enabling or disabling interrupt signals
generated by Port C when the 8255 is programmed for Mode 1 or 2 operation.

✔ This is done by setting or resetting the associated bits of the interrupts.

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 Programmable Peripheral Interface (8255)

❑ BSR mode Operation:

✔

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 Programmable Peripheral Interface (8255)

❑ BSR mode Operation:

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54
•Applied Control Systems

• Stepper Motors

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