3328 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO.

3, MARCH 2023

A Family of Bipolar High Step-Up Zeta–Buck–Boost

Converter Based on “Coat Circuit”
BinXin Zhu , Senior Member, IEEE, Yu Liu , Shubo Zhi, Kaihong Wang , and Jiaxin Liu

Abstract—A family of bipolar high step-up zeta–buck–boost con-

verters based on the “coat circuit” is proposed, which can be used to
connect a low-voltage dc source and a bipolar dc bus. Like the basic
zeta or buck–boost converter, it contains only one active switch,
so its control method and drive circuit are simple to achieve. The
conversion ratio of the proposed converter is effectively increased
through a “coat circuit,” and the voltage stress of the devices is
reduced. In addition, the positive and negative voltages of the
bipolar output voltage of the converter can be automatically equal-
ized. Working principle and performance analysis of the proposed
converter has been given in this article in detail, and a 400 W
experimental prototype has been built to verify the correctness and Fig. 1. Bipolar dc link in data center.
effectiveness of the theoretical analysis.
Index Terms—Beta, bipolar, buck–boost, high step-up.

I. INTRODUCTION
HE bipolar dc bus can realize a high-efficiency, low-cost,
T and high-reliability connection between the distributed
renewable energy units and data centers which have developed
rapidly in recent years [1], [2], [3], as shown in Fig. 1. In the
data center, the common voltage levels are ±190 and ±200 V
[3], [4], [5], [6], [7], [8], [9], [10]. There are three common ways
to connect renewable energy units with bipolar dc bus as shown
in Fig. 2. Fig. 2. Conventional methods to connect renewable energy units with bipolar
In the first structure as shown in Fig. 2(a), at least two con- dc bus. (a) Parallel DC converter. (b) DC converter with voltage balancer. (c)
Neutral clamp converter.
verters are needed, and their input-ports are connected in parallel
while output-ports are connected in series [5], [11], [12]. This
structure uses two independent converters with two independent the working environment of important loads, but the voltage
power flows. Therefore, it works very stable, even if one side of balancer needs to monitor the line voltage in real time to adjust
the converter is damaged, the other side can still work normally. its own mode, and the control method is complicated. The third
But two sets of converters need to spend too much cost. The structure is to directly convert the renewable energy to the bipolar
second structure needs one converter and a voltage balancer as dc network through a bipolar output dc/dc converter as shown
shown in Fig. 2(b) [7], [13], [14], the voltage balancer can ensure in Fig. 2(c) [15], [16], [17], [18].
Compared with the above two structures, the use of bipolar
Manuscript received 24 May 2022; revised 13 September 2022 and 1 Novem- output dc/dc converter has the advantages of a simpler structure
ber 2022; accepted 9 November 2022. Date of publication 14 November 2022; and lower cost. Some dc/dc converters with bipolar output capa-
date of current version 26 December 2022. This work was supported in part by the
National Natural Science Foundation of China under Grant 51707103 and in part bilities have been proposed in [17], [18], [19], [20], [21], [22].
by the Natural Science Foundation of Hubei Province under Grant 2020CFB754. The converter proposed in [20], [21], and [22] uses transformers
Recommended for publication by Associate Editor G. Moschopoulos. (Corre- to achieve bipolar outputs, but the use of transformer would in-
sponding authors: Yu Liu; Kaihong Wang.)
BinXin Zhu, Yu Liu, Kaihong Wang, and Jiaxin Liu are with the College of crease the overall size and cost of the system in a situation where
Electrical Engineering and New Energy (Hubei Provincial Research Center on isolation is not required. The converter proposed in [17] has low
Microgrid Engineering Technology), China Three Gorges University, Yichang component counts, which can transfer power between output
443002, China (e-mail: [email protected]; [email protected]; wangkai-
[email protected]; [email protected]). terminals and also operates bidirectionally. However, the duty
Shubo Zhi is with the Beijing Spacecrafts, Beijing 100094, China (e-mail: cycle of the converter is limited, and its input and output voltage
[email protected]). are not in common ground. The converter in [18] can work
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TPEL.2022.3221781. in synchronous rectification mode and zero-voltage-switching
Digital Object Identifier 10.1109/TPEL.2022.3221781 (ZVS) of the power MOSFETs can be realized, but the driver and
0885-8993 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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ZHU et al.: FAMILY OF BIPOLAR HIGH STEP-UP ZBB CONVERTER BASED ON “COAT CIRCUIT” 3329

Fig. 3. Topology derivation. (a) Zeta and buck–boost converter. (b) Zeta and buck–boost converter. (c) Zeta and buck–boost converter. (d) Buck–boost with coat
circuit. (e) ZBB-I. (f) ZBB-II. (g) ZBB-II. (h) ZBB-IV.

control circuit of this converter are complex and expensive. A Section V. The experimental result and closed-loop control are
Sepic-Cuk-integrated converter proposed in [19] only contains given in Section VI.
one active switch, and its drive and control circuit are simple
as the Sepic or Cuk converter, but the boost capability of this
converter is lower, and the structure of the topology is fixed. II. TOPOLOGY DERIVATION
In this article, a family of bipolar high step-up zeta–buck– As shown in Fig. 3(a), the zeta and buck–boost converters
boost (ZBB) converters based on the “coat circuit” is proposed, have the same input port, and they can be combined into one
which can not only achieve high voltage conversion gain and circuit as shown in Fig. 3(b). To improve its voltage conversion
bipolar output, but also does not contain an additional active gain, the “coat circuit” proposed in [23] can be introduced, then
switch. The topology derivation of the bipolar output voltage ZBB-I (zeta–buck–boost integrated converter with “coat” circuit
of the proposed converter is discussed in Section II. Operation I) can be obtained as shown in Fig. 3(e).
principle and performance analysis of the converter is described In Fig. 3(e), the topology overcomes the problem of low
in Sections III and IV. The design consideration is given in efficiency caused by parasitic parameters of the conventional

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3330 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 3, MARCH 2023

Fig. 4. Proposed ZBB-IV circuit with one negative cell and two positive cells. Fig. 5. Key waveforms of the proposed converter.

converters when the voltage gain is high. However, in this

converter, the voltage stresses of the capacitors are increasing Mode 1 [t0 –t1 ] shown in Fig. 6(a): Switch S1 is turned ON
step by step among capacitors CN12 , CN22 , …, CNm2 and CP12 , and all diodes work in the OFF-state. During this stage, L, LP2 ,
CP22 , …, CPn2 placed horizontally. And the current stresses LN1 , and LN2 are charged by CP21 , CN11 , CN21, and input
flowing through CN21 , CN31 , …, CNm1 and CN11 , CN21 , …, voltage source, all inductor currents are increased linearly. In
CNn1 placed longitudinally gradually increase, which affects this interval, CP21 , CN11 , and CN21 are discharged while CP12 ,
the flexibility and applicability of the converter. By adjusting CP22 , CN12 , and CN22 are charged as
the position of each capacitor in the “coat circuit,” the voltage
⎧
stress and current stress on these capacitors can be optimized, ⎪
⎪ uL = uin
as shown in Fig. 3(f)–(h). ⎪
⎪
⎨uLN 2 = uCN 21 + uin + uCN 11
The current stress on capacitors of the ZBB-II converter . (1)
shown in Fig. 3(f) is relatively consistent and low. The voltage ⎪
⎪ u = u + u − u
⎪
⎪
LP 1 CP 11 in CP 12
⎩
stress on capacitors of the ZBB-III converter shown in Fig. 3(g) is uLP 1 = uCP 21 + uin − uCP 12 − uCP 22
relatively consistent and low. The current stress on CN21 , CN31 ,
…, CNm1 , CP11 , CP21 , …, CPn1 and the voltage stress on CN12 ,
CN22 , …, CNm2 , CP12 , CP22 , …, CPn2 in the ZBB-IV converter Mode 2 [t1 –t2 ] shown in Fig. 6(b): Switch S1 is turned OFF
shown in Fig. 3(h) is relatively consistent and low. and all diodes work in the ON-state. The inductor current of L1
branches off through four paths; first through DN1 , CN12 , and
III. WORKING PRINCIPLE second through CN11 , DN2 , CN22 , CN12 ; and third through CP11 ,
DP1 ; and fourth through CP21 , DP2 , CP12 . The inductor current
To simplify the analysis process, the proposed ZBB-IV con- of LN2 through DN2 , CN12 , the inductor current of LP1 through
verter with one positive and two negative cells is taken as an DP1 , CP12 , the inductor current of LP2 through DP2 , CP22 , and
example as shown in Fig. 4, and some assumptions are given as output stage (CP12 +CP22 //RPL ), and all inductor voltages are
follows. decreased as
1) All components are considered ideal and all effects of
parasitic parameters are neglected. ⎧
2) The capacitance of all capacitors is larger enough and the ⎪uL = uCN 12
⎪
⎪
⎪
⎨uLN 2 = uCN 22
influence of a capacitor voltage ripple is negligible.
. (2)
3) The converter works in continuous conduction mode ⎪
⎪ uLP 1 = uCP 12
⎪
⎪
(CCM). ⎩
uLP 2 = uCP 22
Fig. 5 shows the key waveforms of the proposed circuit during
one switching period. Similar to the buck–boost or zeta con-
verter, there are two modes when the proposed circuit operates The working principle and analysis process of other convert-
in CCM as shown in Fig. 6. The detailed working process of the ers are similar to the above analysis of ZBB-IV and as such they
converter is presented as follows. are not discussed here.

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ZHU et al.: FAMILY OF BIPOLAR HIGH STEP-UP ZBB CONVERTER BASED ON “COAT CIRCUIT” 3331

Fig. 7. Closed-loop control system of the proposed converter.

Based on (3), the voltage conversion ratio (MP and MN ) can

be obtained as follows:
 up
MP = uin = 1−D
2D
. (4)
MN = uuinn
= − 1−D
2D

Extending the above analysis to a converter with (n-1) nega-

tive cells and m positive cells
⎧
⎪
⎪ uCP 12 = uCP 22 = · · · = uCP m2 = u1−D in D
⎪
⎪
⎪uCN 12 = uCN 22 = · · · = uCN n2 = in D
⎪ u
⎪
⎪ 1−D
⎨u
CN m1 = uCN (m−1)1 + 1−D = uCN (m−2)1 + 2 1−D
uin D uin D

⎪
⎪ = · · · = uCN 11 + (m − 1) u1−Din D
= (m − 1) 1−DD
uin
⎪
⎪
⎪
⎪ u = u − uin D
= u − 2 uin D
⎪
⎪
CP n1 CP (n−1)1 1−D CP (n−2)1 1−D
⎩= · · · = u
CP 11 − (n − 1) 1−D = − 1−D uin
uin D nD

(5)

MP = uuin P
= 1−D
mD
. (6)
MN = uuin N
= − 1−D
nD

As shown in (5) and (6), the voltage gain of ZBB-IV can be

changed by adjusting the number of expansions cells.

B. Voltage and Current Stress of Components

Based on (3), the voltage stresses of switch S1 , diodes DN1 ,
DN2 , DP1 , and DP2 shown in Fig. 6 can be expressed as uS1 ,
uDN1 , uDN2 , uDP1, and uDP2 shown in (7), respectively.
When the converter is extended to (n-1) negative cells and m
positive cells, the voltage stress of the diodes can be obtained
as (8)
⎧
⎪
⎪ uS1 = uDN 1 = uin + uCN 12 = 1−D uin
⎨u
DN 2 = uCN 21 +uin + uCN 12 + uCN 22 = 1−D
uin
Fig. 6. Equivalent circuits of the proposed converter working in CCM. (7)
⎪
⎪ uDP 1 = uCP 11 + uin = 1−Duin
⎩
uDP 2 = uCP 21 + uin − uCP 12 = 1−D uin

IV. PERFORMANCE CHARACTERISTICS 

uS1 = uDP 1 = uDP 2 = · · · = uDP n = 1−D uin
= nD
uP
A. Voltage Conversion Ratio .
uS1 = uDN 1 = uDN 2 = · · · = uDN m = 1−D = − mD
uin uN

By the volt-second balance of the inductor L1 , LN2 , LP1 , and (8)

LP2 given in (1) and (2), the following formula can be obtained:
⎧ Apparently, both the voltage stresses on diodes and switches
⎪
⎪ uCN 21 = − 1−D D
uin are lower than that of a basic buck–boost or zeta converter.
⎪
⎪
⎪ To simplify the calculation of current stress, the current ripples
⎨uCP 11 = 1−D uin
D
⎪
on L, LP1 , LP2 , LN2 , RP , and RN are all ignored. The average
uCP 21 = 1−D2D
uin . (3)
⎪
⎪ current of the above devices is represented, respectively, by IL ,
⎪
⎪uN = − 1−D uin
2D
⎪
⎪ ILP1 , ILP2 , ILN2 , IP , and IN . Based on capacitor charge balance
⎩
uP = 1−D2D
uin requirements of CP11 , CP12 , CP21 , CP22 , CN11 , CN12 , CN21, and
CN22 , the currents flowing through the diodes DP1 , DP2 and the

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3332 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 3, MARCH 2023

TABLE I
PERFORMANCE CHARACTERISTICS OF PROPOSED CIRCUITS

TABLE II
COMPARISON OF THE PROPOSED ZBB-IV WITH OTHER TOPOLOGIES

inductors LP1 , LP2 are equal to the output current IP ; the currents TABLE III
SPECIFICATIONS OF THE EXPERIMENTAL PROTOTYPE
flowing through diodes DN1 and DN2 and the inductors LN1 and
LN2 are equal to the output current IN

IDP 1 = IDP 2 = ILP 1 = ILP 2 = IP
. (9)
IDN 1 = IDN 2 = ILN 1 = ILN 2 = IN
When the efficiency of the converter is assumed to be 100%,
the input average current IL is
2DIP + (1 + D)IN
IL = . (10)
1−D
As shown in Fig. 6(a), the average current and RMS current
flowing through the switch S1 is as

IS1 = IL + ILP 1 + ILP 2 +√ILN 2 = (IP + IN ) 1−D 2
.
IS1−RMS = (IP + IN ) 1−D D
2 and the current stresses of the capacitors CNj2 and CPk2 are
(11) ⎧
When extending the analysis to the converter with (n-1) ⎪
⎪ ILP 1 = ILP 2 = · · · = ILP m = IP
⎪
⎪
negative cells and m positive cells, (12) can be obtained. ⎪
⎪ I LN 2 = · · · = ILN n = IN
⎨
Detailed current and voltage stresses of capacitors in the IL = IN +(n−1)DI N +mDIN
1−D (12)
proposed ZBB-I, ZBB-II, ZBB-III, and ZBB-IV converter are ⎪
⎪
⎪
⎪IS1 = 1−D
nIN
+ mI P
given in Table I. For the ZBB-I converter, the voltage stress of ⎪
⎪  1−D
√
⎩
the capacitors CNj1 and CPk1 is relatively consistent and lower, IS1−RMS = 1−D nIN
+ mIP
1−D D

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ZHU et al.: FAMILY OF BIPOLAR HIGH STEP-UP ZBB CONVERTER BASED ON “COAT CIRCUIT” 3333

Fig. 9. Input voltage and loads variation of the prototype. (a) Input voltage
change from 48 to 38 V. (b) Input voltage change from 38 to 48 V. (c)
Fig. 8. Experimental waveforms of the prototype when the input voltage is Negative load change from 400 to 200 Ω. (d) Negative load change from 200 to
48 V with 400 and 200 Ω unbalanced bipolar load. (a) Voltage across S1 , input 400 Ω.
voltage, positive output voltage, and negative output voltage. (b) Voltage across
diodes. (c) and (d) Voltage across capacitors. (e) Inductor currents.

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3334 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 3, MARCH 2023

Fig. 11. Efficiency waveforms of the converter.

Fig. 10. Output voltage difference under different loads. (a) Actual voltage
deviation rate. (b) Theoretical voltage deviation rate. of the converter proposed in [19] are as simple as the zeta and
buck–boost converters and also have the ability to operate in
either step-up or step-down mode. However, the voltage gain is
relatively consistent and lower, jࢠ[2,m], kࢠ[1,n]). For the ZBB- not adjustable, and the above converters cannot output bipolar
II converter, the current stresses of capacitors CNj1 and CPk1 voltage. The converter in [24] uses a switch capacitor which
are relatively consistent and lower, and the voltage stresses of can increase the voltage gain and decrease duty cycle and ripple
capacitors CNj2 and CPk2 are relatively consistent and lower, current. However, the voltage difference of capacitors may cause
jࢠ[2,m], kࢠ[1,n]; For ZBB-III converter, the current stresses a large current pulse. The converter proposed in [25] is an
of the capacitors CNj1 , CNj2 , CPk1 , and CPk2 are relatively improved coupled inductor-based topology that has a low ratio
consistent and lower, jࢠ[2,m], kࢠ[1,n]; for ZBB-IV converter, of switch voltage to the high voltage dc bus value. However, the
the current stresses of the capacitors CNj1 , CPk1 are relatively voltage stress of devices compared to converter proposed in this
consistent and lower, and the voltage stresses of capacitors CNj2 , article is much higher. In [26], a soft-switched boost-integrated
CPk2 are relatively consistent and lower, jࢠ[2,m], kࢠ[1,n]; these flyback converter is proposed, a bidirectional boost converter
four bipolar topologies achieve different voltage and current is stacked with a flyback converter which bypasses the leakage
stress characteristics of capacitors through different topology energy to the output capacitor and thus increases the voltage
structures and meet the requirements of different occasions. gain and provides ZVS turn-on of switches, but it contains a
Design requirements and specific characteristics are shown in transformer and two active switches which increase the size of
Table I. converter and the complexity of control.

C. Comparison of the Proposed ZBB-IV With Other

V. DESIGN CONSIDERATIONS
Topologies
Table II shows the performance comparison of several other A. Component Design
bipolar dc/dc converters, high step-up converters, and the To verify the performance of the proposed converter accu-
converter proposed in this article. The converters proposed in rately in the experiment, some design considerations need to be
[17] and [18] can also output bipolar voltage, but using two discussed. The proposed ZBB-IV converter with one positive
active switches, the voltage gain cannot be changed, and the and two negative cells is designed to operate in CCM operation,
duty cycle is limited in [17]. The control and the drive circuit and the detailed designs of all components are as follows.

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ZHU et al.: FAMILY OF BIPOLAR HIGH STEP-UP ZBB CONVERTER BASED ON “COAT CIRCUIT” 3335

1) Selection of duty cycle: According to the voltage gain in

CCM (4), the selection of duty cycle is given by
MP MN
D= = . (13)
MP + 2 MN − 2
2) Inductors design: The inductor current ripple iL can be
written as
Vin D VP (1 − D) VN (1 − D)
ΔiL = = =− (14)
L1 f s 2DLfs 2DLfs
where fs is the switching frequency.
The inductor values of L1 and L2 are given by
⎧
⎪
⎪
VP (1−D)
L ≥ 2DΔi VN (1−D)
= − 2DΔi
⎨ 1 L1 fs L1 fs
VP (1−D)
LP1 = LP2 ≥ 2DΔi . (15)
⎪
⎪ P fs
⎩L ≥ − N V (1−D)
N2 2DΔiN fs

3) Capacitors design: According to the theoretical analysis

in Section III, the capacitor’s voltage stresses are given by
(5). According to Fig. 6(a), during the conduction period
of the switch S1 , the current flowing through the capacitor
CN21 is equal to the current of the inductor LN2 , the current
flowing through the capacitor CP11 is equal to the current
of the inductor LP1 , and the current flowing through the
capacitor CP21 is equal to the current of the inductor LP2 ,
the current flowing through the capacitor CP22 is equal to
the negative output current IN , the current flowing through
the capacitor CP21 is equal to the sum of the iLN2 and
IN . The current through the capacitor CP12 is the current
ripple of iLP2 . In order to simplify the calculation of the
CP12 , the current of CP22 can be neglected, and the current
flowing through the capacitor CP12 is equal to iLP1 . The
values of capacitors can be given by
⎧
LN 2 ·Ts
⎪
⎪ CN21 ≥ D·i 2ΔuCN 21 = 2ΔuCN 21 ·fs
D·IN
⎪
⎪
⎪
⎪ D·iCP 11 ·Ts
⎪CP11 ≥ 2Δu
⎪ = 2ΔuD·I P
CP 11 ·fs
⎪
⎪
CP 11
⎪CP21 ≥ D·iCP 21 ·Ts =
⎪ D·IP
Fig. 12. Loss distribution and images of the prototype. (a) Loss distribution
⎪
⎨ 2ΔuCP 21 2ΔuCP 21 ·fs
LN 2 ·Ts
of the converter. (b) Thermal image. (c) Prototype image. CN22 ≥ D·i 2ΔuCN 22 = 2ΔuCN 22 ·fs
D·IN
(16)
⎪
⎪
⎪
⎪CN12 ≥ D·(iN +iLN 2 )·Ts
= ΔuCN 12 ·fs
D·I N
⎪
⎪
⎪
⎪
2ΔuCN 12
⎪
⎪ C D·iLP 1 ·Ts
≥ 2ΔuCN 22 = 2ΔuD·I P
⎪
⎪ P12 CN 22 ·fs
⎪
⎩C ΔiLP 2 ·Ts
P22 ≥ 8ΔuCP 22 = 8ΔuCP 22 ·fs
ΔiLP 2

where ΔuCN12,21&22 and ΔuCP11,12,21&22 are capacitor’s

voltage ripples. ΔiLP2 is the current ripple of the inductor LP2 .
4) Selection of power components: The voltage and current
stresses on power components are discussed in Section IV-
B. Therefore, power components can be selected accord-
ing to (7)–(11).
Based on the above analysis, the specifications of the proto-
type are shown in Table III.

B. Control Design
The averaged switch model of the proposed ZBB can be
obtained by using the circuit averaging method proposed in [27]
Fig. 13. Average switch model of the proposed converter.
which is analyzed in Appendix B.

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3336 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 3, MARCH 2023

When averaging inductor’s current and capacitor’s voltage is 250%, the maximum voltage deviation rate of the converter
waveforms in a period, the small ripples of devices can be is 1.9%. Based on the correlation between voltage deviation
averaged out. Small signal perturbation is introduced into the rate and resistance deviation, the theoretical voltage deviation
current iS1 (t), iD1 (t), iD11 (t), and iD21 (t) to establish the equiv- rate can be obtained by calculating the efficiency as shown in
alent small signal ac model. The specific condition with small Fig. 10(b)
signal perturbation are as follows:
⎧ VP − VN
uS (t)Ts = US + ûS (t) Devrate = × 100%. (19)
⎪
⎪ (VP + VN )
⎪i (t) = I + î (t)
⎪
⎨ S Ts S S
uDN 1,2&DP 1,2 (t)Ts = UDN 1,2&DP 1,2 + ûDN 1,2&DP 1,2 (t) . The efficiency waveform of the converter under different
⎪
⎪
⎪
⎪ i (t)Ts = IDN 1,2&DP 1,2 + îDN 1,2&DP 1,2 (t) input voltages, rated duty cycle, and bipolar loads (200/200
⎩ DN 1,2&DP 1,2
d(t) = D + d(t)ˆ ⇒ d (t) = D − d(t) ˆ Ω) is shown in Fig. 11(a). When the output voltage is ±100V,
(17) the maximum efficiency of the converter is near 95.1%. The
The symbol (^) shows the dynamic changes of the parameters efficiency waveform of the converter under different loading
as shown in (17) and (18). Tp is transformer primary winding, condition is shown in Fig. 11(b). When the output power is 150
TSN1 , TSN2 , TSP1 , and TSP2 are transformer secondary windings W, the maximum efficiency of the converter is nearly to 94.1%.
(the transformer windings represent the active switch and diode The efficiency waveform of the converter under different input
operation in the average switched model) voltage, same output voltage (400 V), and rated power is shown
 in Fig. 11(c). As the input voltage increases, the converter’s
ˆ · Uin 
u1 = d(t) D·D . (18) efficiency gradually increases.
ˆ · IDN 1,DN 2,DP
iN 1,N 2,P 1,P 2 = d(t) 1,DP 2
D·D  The calculated loss distribution of the experimental prototype
is shown in Fig. 12(a). When the output voltage is ±200V and
According to the established average switching model, a ZBB
the loads are both 200 Ω, the main losses are on switch, diodes,
converter control system with one negative cell and two positive
and inductors, which are close to 6.48, 5.6, and 6.65 W. Under
cells is designed, as shown in Fig. 7.
the same working conditions, the thermal image of the prototype
is given in Fig. 12(b). The ambient temperature is 18.2 °C, and
VI. EXPERIMENTAL RESULTS
the maximum temperature of the converter is about 52.2 °C. The
An experimental prototype has been built to verify the accu- thermal image also proves the validity of the calculation results.
racy of the above theoretical analysis. An unbalanced bipolar The size of prototype is 9.8 × 8.6 × 6.8 cm (L/W/H) as shown
load is connected between positive and negative outputs, 400 in Fig. 12(c). The power density of the prototype is about 0.698
Ω(RN ) and 200 Ω(RP ), respectively. Fig. 8(a) shows the wave- W/cm3 .
forms of uds , uin , uP, and uN , the output voltages of positive and
negative polarity are almost the same, and the voltage conversion VII. CONCLUSION
gains are both 4.167 when the duty cycle is near 0.678, which
is near to (6). Voltage waveforms across DN1 , DN2 , DP1, and A family of bipolar buck–boost converters based on the “coat
DP2 are shown inFig. 8(b), and the voltage stresses of the above circuit” is proposed to improve the voltage conversion ratio in
diodes and S1 are approximately 149.1 V, which is consistent this article. Theoretical analysis and experimental results show
with (7). Fig. 8(c) and (d) show the voltage across the capacitors, that the proposed circuits have the following advantages.
the average value of CN21 , CP11, and CP21 is about 100, -100, 1) Since the proposed bipolar topologies do not contain
-200 V, and the average value of CP12 , CP22 , CN12 , and CN22 is additional active switches, the control method and drive
approximately 100 V, which is near to (6). Fig. 8(e) shows the circuits of the proposed converter are consistent with the
current waveforms of L, LN1 , LP1, and LP2 . The dc value of iL basic converter.
is about 6.25 A, the dc value of iLN2 is about 0.5 A and the dc 2) The introduction of “coat circuit” can reduce the voltage
values of iLP1 and iLP2 are about 1 A, which is consistent with stress of semiconductor devices, so it can reduce cost and
(9) and (10). the selection requirements of devices.
A digital control closed-loop system based on 3) The duty cycle and voltage conversion ratio of the con-
TMS320F28335 is built to test the dynamic characteristics verter are not limited, which is suitable for wide in-
of the prototype, as shown in Fig. 9. Input voltage variations put/output voltage occasions.
from 38 to 48 V and 48 to 38 V are shown in Fig. 9(a) and (b). 4) The number of positive and negative extension cells in
As indicated in Fig. 9(c) and (d), negative load (RN ) is variated the topology can be expanded according to the needs of
from 400 to 200 Ω and 200 to 400 Ω. applications, which makes its application range-wide.
To judge whether the output voltage of the converter is bal-
anced under different loads. The actual and theoretical three- APPENDIX
dimensional diagrams of the voltage deviation rate are drawn in
A. Loss Calculation
Fig. 10(a). The test method is to fix the input at 48 V and the
duty cycle at 0.678, change the resistance of the bipolar loads, This article takes the unbalance bipolar load (RPL = 400 Ω,
then test each output voltage and calculate the deviation rate as RNL = 200 Ω) as an example for analysis. All the analyses are
shown in (19). It can be seen that when the resistance deviation as follows.
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ZHU et al.: FAMILY OF BIPOLAR HIGH STEP-UP ZBB CONVERTER BASED ON “COAT CIRCUIT” 3337

The power loss in MOSFET: The loss of MOSFET is mainly B. Small Signal Model
divided into switching loss and conduction loss. The conduction
To simplify the listing of state space equations, the following
loss is determined by the conduction resistance of the MOSFET assumptions are made:
and the current flowing through it. Therefore, the conduction
1) The converter works under CCM condition.
loss of the MOSFET can be given by
2) The converter contains one negative cell and two positive
PCON = IDS 2
RDS(on) D = (9.25)2 × 0.011 × 0.678 = 0.638 W. cells.
(A1) 3) The influence of parasitic parameters of converter ele-
The switching loss is due to the overlap of voltage and current ments is ignored except for the forward voltage of diodes.
across the MOSFET during turn-OFF state. The switching loss can Mode 1, the switch S1 is ON-state and all diodes are OFF-state.
be expressed as follows: The state equations can be given by
 ⎧
⎪
⎪ uS1 (t) = 0
PSW = IDS VDS f2(ton +toff ) ⎪
⎪
. (A2) ⎪
⎪ uDN 2 = uCN 21 + uin + uCN 12 + uCN 22 ≈ uin + uCN 12
3 −9
= 9.25×148×100×102 ×(18+41)×10 = 4.04 W ⎪
⎪
⎨uDN 1 = uin + uCN 12
uDP 1 = uCP 11 + uin .
The power loss in diodes: The loss of the diode is mainly ⎪
⎪
⎪
⎪ u DP 2 = u CP 21 + u in − u CP 12 ≈ u in + u CN 12
concentrated on the conduction loss, which is caused by the ⎪
⎪
⎪
⎪ iS1 (t) = iL (t) + iLN 2 (t) + iLP 1 (t) + iLP 2 (t)
forward voltage drop (Vd ) of the diode in the conduction device. ⎩
The average current of DP1 and DP2 is equal to the average iDN 2 (t) = iDN 1 (t) = iDP 1 (t) = iDP 2 (t) = 0
(A8)
positive output current IP , while the average current of DN1 and
Mode 2, the switch S1 is turned OFF and all diodes are turned
DN2 is equal to the average negative output current IN
ON. The state equations are
⎧
⎪ PDP 1 = PDP 2 = IP Vd = 0.5 × 1.4 = 0.7 W ⎧
⎪
⎪ ⎪ uS1 (t) = uin + uCN 12
⎪
⎨PDN 1 = PDN 2 = IN Vd = 1 × 1.4 = 1.4 W ⎪
⎨
uDN 2 = uDN 1 = uDP 1 = uDP 2 = 0
PDP = PDP 1 + PDP 2 = 1.4 W . (A3) iS1 (t) = 0
. (A9)
⎪
⎪ ⎪
⎪
⎪
⎪ P = P + P = 2.8 W ⎩
⎩
DN DN 1 DN 2 iDN 1,2&DP 1,2 (t) = 4 IL + 4 ILN 2,2&LP 1,2
1 3
PD = PDP + PDN = 4.2 W
The low-frequency average of the inductor voltages and cur-
The power loss in inductors: Inductance loss can be divided rents are found by evaluation of (A8) and (A9), given as
into copper loss and iron loss, the resistance of the main inductor ⎧
⎪ uS (t)Ts = d (t)(uin (t)Ts + uCN 12 (t)Ts )
L is 49 mΩ, the resistance of the LP1 , LP2, and LN2 is 110 mΩ. ⎪
⎪
⎪
⎪ uDN 1,2&DP 1,2 (t)Ts = d(t)(uin (t)Ts + uCN 12 (t)Ts )
Therefore, the copper loss of the inductor is ⎪
⎪
⎧ ⎪
⎨i 
DN1,2 (t)Ts = d (t)( 4 iL (t)Ts + 4 iLN 2 (t) Ts )
1 3
⎪
⎨PL−dc = IL RL1 = 7.25 × 0.05 = 2.63 W
2 2
.
PLP 1−dc = PLP 2−dc = IP2 × RL2 = 0.52 × 0.11 = 0.03 W . ⎪ 
⎪iDP 1,2 (t)Ts = d (t)( 4 iL (t)Ts + 4 iLP 1,2 (t) Ts )
1 3
⎪ ⎪
⎪
⎩P ⎪
⎪iS (t)Ts = d(t)(iL (t)Ts + iLN 2 (t)Ts
LN 2−dc = IN × RL2 = 1 × 0.11 = 0.11 W
2 2 ⎪
⎪
⎩
(A4) +iLP 1 (t)Ts + iLP 2 (t)Ts )
The core loss can be calculated from the datasheet of the (A10)
magnetic core, and its power is related to magnetic flux density
and frequency. Calculated as follows: When averaging the inductor currents and capacitor wave-
⎧ forms in one period, their small ripple can be averaged out. In
⎪ ΔB11.928 f 6.09
⎨PL−CORE = 2.059
⎪ 1000 = 0.52 W the above equation, <x(t)>Ts is the average value of the variable
1.928 6.09
PLP 1−CORE = PLP 2−CORE = 0.4379 ΔB2 1000f = 0.56 W . x(t) in one period. By simplifying (A10), it can be obtained as
⎪
⎪
⎩ ΔB31.928 f 6.09 follows:
PLN 2−CORE = 0.4379 1000 = 0.51 W  
(A5) uS (t)Ts = dd(t) (t)
uDN 1,2&DP 1,2 (t)Ts
.
The loss of inductors can be shown as follows: iS (t)Ts = i=1 ( dd(t)
2 d(t)
 (t) iDN i (t)Ts + d (t) iDP i (t)Ts )
⎧
⎪
⎪ PLP = PLP 1−dc +PLP 1−CORE +PLP 2−dc (A11)
⎪
⎨ Small signal disturbance is introduced into current iS1 (t),
+PLP 2−CORE = 3.11 W
. iD1 (t), iD11 (t), iD21 (t) and other variables to establish an equiv-
⎪
⎪ PLN = PL−dc +PL−CORE +PLN 2−dc +PLN 2−CORE = 1.18 W
⎪
⎩ alent small signal ac model. The specific conditions for adding
PL = PLP + PLN = 4.29 W small signal disturbance are as follow:
(A6) ⎧
The capacitance loss and other losses of the total converter ⎪ uS (t)Ts = US + ûS (t)
⎪
⎪
are approximately 2 W. In this case, the total efficiency of the ⎪uDN 1,2& DP 1, 2(t)Ts = UDN 1,2&DP 1,2 + ûDN 1,2&DP 12 (t)
⎨
converter can be given by iS (t)Ts = IS + îS (t) .
⎪
⎪
⎪
⎪ i DP 1, 2(t) = I + î (t)
η=
P
= 95.19%. ⎩ DN 1,2& Ts DN 1,2&DP 1,2 DN 1,2&DP 12
d(t) = D + d(t) ˆ ⇒ d (t) = D − d(t) ˆ
P + PCON + PSW + PD + PL + Pother
(A7) (A12)

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3338 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 38, NO. 3, MARCH 2023

Gud (s) =
1.56472 × 10−25 s5 − 3.78302 × 10−21 s4 + 6.52670×10−17 s3 −4.03956 × 10−13 s2 + 4.153553 × 10−9 s + 5.27819 × 10−21
−2.93824 × 10−26 s5 +3.70775 × 10−22 s4 − 4.04260 × 10−18 s3 + 1.34817 × 10−16 s2 − 4.15977 × 10−12 s
(A17)
5.14737 × 10−24 s2 + 5.98400 × 10−22 s − 8.27310 × 10−33
Gid (s) = . (A18)
8.70163 × 10−30 s3 + 5.37501 × 10−28 s2 +8.96998 × 10−24 s

The symbol (^) shows the dynamic changes in the parameters. The experimental parameters are shown in Table III. The
Combining (A11) and (A12), ignoring the dc component and the output current Io is 1 A and the duty cycle D is 0.678 which
second-order ac term, the equivalent equation after linearization can be calculated based on the above parameters. Substitute
can be obtained as follows: the above parameters into (A15) and (A16), simplify and solve
⎧ the output voltage transfer function Gud (s) and input cur-
 Uin ˆ
⎪
⎪ û (t) = D D ûDN 1,2&DP 1,2 (t) − DD  d(t)
⎨ s rent transfer function Gid (s) with Mathematica and MATLAB
 Uin ˆ
=D D ûDN 1,2&DP (t) − DD  d(t)
⎪ 1,2  . given by (A17) and (A18), shown at the top of this page,
⎪
⎩D îS (t) = 2 D îDN i&DP i (t) + IDN i&DP i ˆ respectively
i=1  d(t) DD
(A13)
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ZHU et al.: FAMILY OF BIPOLAR HIGH STEP-UP ZBB CONVERTER BASED ON “COAT CIRCUIT” 3339

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BinXin Zhu (Senior Member, IEEE) was born in

Anhui, China, in 1986. He received the B.S. de-
gree from the Hefei University of Technology, Hefei,
China, in 2008, and the Ph.D. degree from Chongqing Jiaxin Liu received the bachelor’s degree in electrical
engineering and antimotivation in 2020 from China
University, Chongqing, China, in 2013, respectively,
Three Gorges University, Hubei, China, where she
both in electrical engineering.
is currently working toward the master’s degree in
In 2014, he joined as a Lecturer the College of
Electrical Engineering and New Energy, China Three electrical engineering.
Her research focuses on high-reliability and high
Gorges University, Yichang, China, where he became
step-up dc–dc converters.
an Associate Professor and a Group Leader of the
Power Electronics Group in 2016, and has been a
Professor since 2022. His research focuses on high-efficiency and high step-up
dc–dc converters.

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