Frequenz 2022; 76(5-6): 337–344

Frank Herzel*, Thomas Mausolf and Gunter Fischer

A Novel architecture for low-jitter multi-GHz

frequency synthesis
https://doi.org/10.1515/freq-2021-0188 embedded in a PLL to stabilize its output frequency by
Received August 9, 2021; accepted January 13, 2022; using a spectrally pure low-frequency input signal with a
published online February 16, 2022
frequency fin . The PLL output frequency, fout , is larger by a
factor M(N + α), where M is the prescaler division ratio
Abstract: A phase-locked loop (PLL) cascade driven by a
(typically 2 or 4), N is the integer part of the programmable
crystal oscillator and a free running dielectric resonator
divider ratio, and α is its fractional part, where 0 ≤ α < 1. The
oscillator (DRO) is proposed. For minimizing phase noise,
PN of mmW VCOs is typically quite high, mainly due to the
spurious tones and jitter, a programmable PLL1 in the
low Q-factor of the integrated variable capacitor (varactor).
lower GHz range is used to drive a millimeter-wave (mmW)
In order to reduce VCO PN and in-band PN, a high fin and a
PLL2 with a fixed frequency multiplication factor. The
large loop bandwidth, fL , are usually mandatory. Since in
phase noise analysis results in two optimum bandwidths of
an integer-N PLL the spacing of the output frequencies is as
the two PLLs for the lowest output jitter of the cascade.
Phase noise and spurious tones (spurs) in PLL1 are further large as Mfin , a fractional-N PLL (α > 0) is often required for
reduced by dividing the output frequency of PLL1 and up- programming fout . Here, the in-band PN and in-band spurs
converting it by means of a single-sideband (SSB) mixer may become excessive for small α, especially, for a large fL
driven by the DRO. By including the SSB mixer in the [2]. Unfortunately, a large fL is required for VCO noise
feedback loop of PLL1 manual tuning of the DRO is avoi- suppression. Therefore, a simple fractional-N PLL is not
ded, and a low-noise free running DRO can be employed. capable of combining efficient VCO PN suppression with a
An exemplary design in SiGe BiCMOS technology is low level of in-band noise. If a low-frequency PLL1 with a
presented. low-noise VCO is available, it can be used to drive a mmW
PLL, named PLL2 in this paper. In order to save DC power,
Keywords: dielectric resonator oscillator; frequency syn- the feedback divider ratio in PLL2 should have a simple
thesizer; low-jitter clock; phase noise; phase-locked loop. value, preferably a power of two. The loop bandwidth of
PLL1, fL, 1 , should be much smaller than the loop band-
width of PLL2, fL, 2 . In such a PLL cascade, a relatively low
1 Introduction level of in-band PN and spurs can be combined with a
significant reduction of the VCO PN in PLL2 [3]. PLL cas-
Phase noise and jitter of PLLs are critical in communication cades are especially useful in phased-array systems, where
systems and data converters [1]. Jitter describes the devia- a common reference signal in a few-gigahertz range is
tion of the zero-crossings of the output signal from the distributed to a set of local mmW PLLs located at each
expected points in time, whereas phase noise (PN) is the antenna element [4].
corresponding frequency-domain equivalent. Minimiza- Further reduction of the output jitter requires a high-
tion of jitter implies a minimization of the PN spectrum and Q device in PLL1 in addition to the crystal oscillator. For
spurs. This is important for high-speed wireline trans- achieving a low phase noise in the kHz offset region of the
ceivers, wireless transceivers in 5G radios, and high-speed, phase noise spectrum, opto-electronic oscillators (OEO)
high-resolution analog-to-digital converters (ADCs). and DROs are promising [5]. A DRO is based on ceramic
Integrated millimeter-wave (mmW) frequency synthe- material to function as a resonator for radio waves,
sizers usually employ a voltage-controlled oscillator (VCO) generally in the microwave bands. The unloaded Q factor
of the resonator is typically on the order of 10000s. As a
result, the PN of DROs is much lower than that of
*Corresponding author: Frank Herzel, IHP - Leibniz-Institut für PLL-based frequency synthesizers. In [6] a 19 GHz DRO
innovative Mikroelektronik, Im Technologiepark 25, 15236 Frankfurt
was used to down-convert a radar signal around 18 GHz to
(Oder), Germany, E-mail: [email protected]
Thomas Mausolf and Gunter Fischer, IHP - Leibniz-Institut für
a frequency of about 1 GHz for use in a 77 GHz automotive
innovative Mikroelektronik, Im Technologiepark 25, 15236 Frankfurt radar frontend. Unfortunately, the thermal stability of the
(Oder), Germany DRO frequency is much worse than for a crystal oscillator,
Open Access. © 2022 Frank Herzel et al., published by De Gruyter. This work is licensed under the Creative Commons Attribution 4.0
International License.
338 F. Herzel et al.: A Novel architecture for low-jitter multi-GHz frequency synthesis

especially, if a low-cost DRO is employed. This problem typically k = 1–2. The DTCs deliver accurate quadrature
can be solved by using a voltage-controlled DRO and lock signals (I and Q) which are needed for single-sideband
it to a crystal reference in a PLL. However, this raises the mixing. As long as the signals stay on the same chip, the
DRO phase noise, mainly due to varactor pulling. More- accuracy of this method is high over a wide frequency
over, the electronic tuning range of DROs is quite limited, range. In [7] the measured static phase error was as low as
and manual tuning is usually required, which raises the 0.16° for an output frequency of 20 GHz, corresponding to a
system cost significantly. A solution based on a free sideband suppression of 57 dB. Each DTC reduces the
running DRO is, therefore, highly desirable to avoid phase noise by 6 dB, assuming that the divider noise can be
electrical and mechanical DRO tuning. neglected.
This paper proposes a method to lower the PN of mmW For illustration, we assume that a low-noise 4.4 GHz
PLLs by combining a PLL cascade with a free running DRO. DRO and a high-noise PLL1 at 2 GHz are available. A fre-
The low PN is achieved by dividing the output frequency of quency division by i DTCs will reduce the PLL PN by
the VCO in PLL1 and up-converting the result by means of a i × 6 dB, and the division of the DRO frequency by k DTCs
single-sideband (SSB) mixer driven by the DRO. The pre- will reduce its PN by k × 6 dB. These two low-noise signals
sented circuit architecture requires no manual or electrical are then mixed, where their PN is added to a level, which is
tuning of the DRO and compensates its frequency drift due still much lower than that of PLL1. Figure 2 illustrates this
to temperature changes and aging. effect for i = 3 and k = 1, where the PN level is much
exaggerated.
The divided outputs are multiplied in a single-
sideband (SSB) mixer. The PN reduction is reflected in
2 Architecture the narrower line at the mixer output (violet curve)
compared to the broader line of PLL1 (dark blue curve).
In a first step, we assume that a calibrated low-noise DRO in
Assuming a perfect DRO output signal and a noiseless
the lower GHz range is available. A frequency division of a
mixer, the mixing operation will neither change the shape
PLL output signal using a cascade of i divide-by-two cir-
of the PN spectrum nor the level of spurs. Neglecting the
cuits (DTC) will reduce the PN of a signal by i × 6 dB. An
noise of the DRO, the dividers and the SSB mixer for a
up-conversion of the divided signal by an SSB mixer will
moment, the overall PN reduction of PLL1 is as large as
leave this low PN basically unchanged. The combination of
18 dB with similar center frequencies of PLL1 and SSB
these two operations leads us to the brute force approach
mixer output.
depicted in Figure 1.
The architecture in Figure 1 was named ‘uncompen-
Here, a PLL in the lower GHz range (PLL1) generates an
sated’, since any deviation of the DRO frequency from the
output frequency from a crystal oscillator, preferably an
nominal value will appear at the output of the cascade.
oven-controlled crystal oscillator (OCXO). The multiplica-
This requires manual tuning of the DRO, which raises the
tion factor can be an integer number, i.e. α = 0, or a frac-
total system cost. A tunable DRO has also a higher phase
tional number (α > 0). In order to reduce the PN and the
spurious tones (spurs) in the output spectrum, the output
signal is divided by a cascade of i DTCs, typically i = 2–4.
The DRO signal is also divided by a cascade of k DTCs,

Figure 2: Single-sideband phase noise spectrum at different

Figure 1: Uncompensated low-jitter PLL cascade using a single- locations in the circuit. The phase noise level is exaggerated for
sideband mixer driven by a dielectric resonator oscillator. better visibility.
 F. Herzel et al.: A Novel architecture for low-jitter multi-GHz frequency synthesis 339

noise compared to a free-running DRO. Moreover, the 3.2 Phase noise spectrum
change of the DRO frequency with temperature is typically
larger than for a crystal oscillator, which may require phase A more severe problem is PN. Let us assume a PN
locking with the crystal as reference. In order to solve these of −110 dBc/Hz at 100 kHz offset from the 4.6 GHz carrier.
problems, the SSB mixer should be included in the feed- After the 1:16 frequency divider this corresponds to a PN
back loop of PLL1 as depicted in Figure 3. of −134 dBc/Hz. The PN of DROs is much lower than that of
Some exemplary numbers are given related to a silicon-based integrated VCOs. In [8] a PN of −125 dBc/Hz
possible application in the 122 GHz ISM band. The divided was specified at 100 kHz offset from the 8.8 GHz carrier. We
VCO signal is compared with an 80 MHz input signal in the assume a little more conservatively a PN of −122 dBc/Hz at
phase detector. Here, the term ‘phase detector’ includes all 8.8 GHz and obtain −134 dBc/Hz after the 1:4 frequency
circuitry to derive the VCO control voltage(s) from the divider shown in Figure 3. As a result, we expect a PN
incoming signals, typically a phase-frequency detector of −131 dBc/Hz at 100 kHz offset from the 1.9 GHz mixer
(PFD), one or two charge pumps (CP), and one or two low- output, and −95 dBc/Hz in the 122 GHz ISM band. This is
pass filters (LPF). If the output frequency of the DRO is much lower than for typical mmW PLLs [9]. Note that the
modified due to temperature change or aging, the feedback PN contributions of frequency dividers, SSB mixer and
loop will change the VCO tuning voltage such that the SSB frequency doubler were disregarded in this simplified
mixer output frequency remains at the nominal value, consideration. Nonetheless, it is evident that PN and spurs
defined as the crystal oscillator frequency multiplied by the in a PLL can be reduced significantly by combining fre-
feedback divider ratio N 1 . quency division and SSB mixing, provided that a low-noise
frequency source such as a DRO or an OEO is available.

3 Spectral purity considerations

3.3 Jitter minimization
3.1 Sideband suppression
For a rough jitter estimation, the power spectral density
In an SSB mixer unwanted sidebands appear due to delay (PSD) of the PLL output phase can be described in the
mismatches between the I and the Q paths. In the case of framework of an overdamped second-order PLL model [10].
the 122 GHz ISM band synthesizer, they will occur at the Here, the low-pass filtered in-band PN floor adds to the
sum of the two input frequencies of about 2.5 GHz. After high-pass filtered VCO PN spectrum according to
multiplication by 64 this corresponds to frequencies
Sϕ (f ) = Sfloor H LPF (f ) + SVCO (f ) H HPF (f ). (1)
around 160 GHz. Sidebands at these frequencies are well
suppressed by the antenna filter of a system working in the The rms timing jitter at the PLL output is given by
122 GHz ISM band.
1 √̅̅̅̅̅̅̅̅̅̅̅
∞
σt = ∫0 2 Sϕ (f ) df (2)
2πfout

where Sϕ (f ) = 10£( f )/10 is the two-sided PN spectrum. The

jitter minimization for the PLL cascade implies the opti-
mization of two loop bandwidths. According to (3) in [11],
the jitter-optimum loop bandwidth for each of the two PLLs
is approximately given by
√̅̅̅̅̅̅̅̅̅
fLopt [MHz] = SVCO /Sfloor (3)

where SVCO = 10£VCO /10 is the VCO PN at 1 MHz offset, and

Sfloor = 10£floor /10 is the in-band PN floor of the PLL. The
corresponding minimum timing jitter in seconds reads
√̅̅̅̅̅
1 1 MHz 1/4
σt =
min
(SVCO Sfloor ) (4)
fout 2π

Figure 3: Compensated low-jitter PLL cascade for the 122 GHz ISM where fout is the PLL output frequency. Note that 1/f noise
band. was disregarded in (3) and (4).
340 F. Herzel et al.: A Novel architecture for low-jitter multi-GHz frequency synthesis

Figure 4: Modelled PN spectrum at the output of the 60 GHz PLL Figure 6: Block diagram of PLL2.
from Figure 3 for three different loop bandwidths fL, 2 .

As an illustration, we assume a PN of −94 dBc/Hz for

4 Design example
VCO2 at 1 MHz offset and an in-band noise floor
We have designed an exemplary circuit in a 130 nm SiGe
of −104 dBc/Hz for PLL2. From (3) we obtain an optimum
√̅̅ BiCMOS technology featuring SiGe HBTs with fT /fmax of
loop bandwidth of 10 MHz ≈ 3.16 MHz for PLL2. Figure 4
240/330 GHz [12].
shows the modelled PN spectrum for three different loop
bandwidths of PLL2.
The red curve has a loop bandwidth close to the opti- 4.1 PLL architecture
mum value according to (3).
In order to see the effect of the post-synthesis divider The basic design of the PLLs is similar to the PLL described
and the SSB mixer, we calculated the spectrum for in [13]. Figure 6 shows a simplified block diagram of PLL2.
fL, 2 = 3 MHz also for a simple cascade composed of PLL1 A fast fine tuning loop and a slow coarse tuning loop
and PLL2 (i = 0) and for different numbers of DTCs after the are used in parallel and are permanently working together.
VCO. As evident from Figure 5, the improved cascade has a The task of the coarse tuning loop is the compensation of
significantly lower PN in the kHz region. device parameters with process, supply voltage and tem-
The PN in the kHz range can be reduced even more, if perature (PVT), whereas the fine tuning loop defines the
the division ratio of the post-synthesis divider is increased small-signal dynamics and the PN behavior. The output of
from 16 to 32 or 64. Even though this does not significantly the CMOS CP in the coarse tuning loop is loaded only with
reduce the overall rms jitter, such a phase noise reduction in an on-chip capacitor to ground in parallel with a large
the lower kHz region may significantly improve detection external capacitor C COARSE . Unlike in [13], we neither use a
and tracking performance of mmW FMCW radar systems [9]. CMOS PFD nor a CP in the fine tuning loop of PLL2. Rather,
a bipolar PFD followed by a differential bipolar amplifier is
employed. The high speed of the SiGe-HBTs allows the
input frequency to the PFD to be as large as several GHz. By
using two 1:16 frequency dividers, the input frequency to
the CMOS PFD is reduced to about 125 MHz, a convenient
frequency for the thick-oxide MOSFETs used for CMOS PFD
and CP.

4.2 Design of VCO and frequency dividers

The VCO represents a differential Colpitts oscillator shown

in Figure 7.
Figure 5: Modelled phase noise spectrum at the output of the The VCO uses four digital inputs to generate 16 sub-
60 GHz PLL for the simple PLL cascade (black), and the PLL cascade bands, where the highest bit is realized by inductor
including SSB mixer and i post-synthesis DTCs after the VCO. switching. In addition, the analog control input Vctr used
 F. Herzel et al.: A Novel architecture for low-jitter multi-GHz frequency synthesis 341

Figure 9: Schematic of D-latch.

Figure 7: Schematic of voltage-controlled oscillator taken from [14].

in [14] is split into two control inputs for coarse and fine
tuning according to Figure 6. The output frequency of the
VCO is doubled by using a SiGe-based Gilbert mixer.
All dividers in PLL2 are cascades of DTCs to simplify
the design and to minimize DC power consumption.
Figure 8 shows the schematic of a DTC composed of two
latches in a feedback loop, and Figure 9 shows the sche-
matic of the latch.
The internal divider circuit uses only one emitter fol-
lower. The second emitter follower is used for driving
Figure 10: Schematic of phase-frequency detector.
external loads.

configuration with an additional reset input was used for

4.3 Design of phase-frequency detector the ECL flipflops. All signals are differential, but only the
positive branches are shown in Figure 10. The delay
Figure 10 shows the schematic of the bipolar PFD. element in the reset path minimizes the dead-zone effect.
It consists of two edge-triggered resettable D-flipflops As usual, the resettable D-flipflop is composed of two
designed with SiGe-HBTs for a high speed. Their D inputs latches. Figure 11 shows the schematic of the resettable
are connected to logical ONE. A standard master-slave D-latch consisting of five differential pairs.

Figure 8: Schematic of divide-by-two circuit. Figure 11: Schematic of resettable D-latch.

342 F. Herzel et al.: A Novel architecture for low-jitter multi-GHz frequency synthesis

The lowest pair receives the differential clock signal and

is biased by a current mirror. If the differential reset signal is
LOW, then the current flows through the inner pairs, and the
latch behaves like a classical D-latch. If the reset signal R
goes HIGH, the current flows through the outer differential
pairs and from there through the load resistor RC connected
to the positive output node “out”. In other words, the dif-
ferential output signal is LOW in this case, as desired.

4.4 Design of active filter

An active loop filter as in [15] was used to avoid any

MOSFET in the fine tuning loop. Figure 12 shows the Figure 13: Schematic of SSB mixer.

schematic of the active loop filter.

Unlike in [15], our filter is completely integrated and is
designed for a large loop bandwidth. The amplifier is a two-
stage differential bipolar amplifier. Its shot noise contribu-
tion to the phase noise spectrum is minimized by using a
small VCO fine tuning gain. The output of the amplifier is
softly biased close to the middle of the rails. As discussed in
[13], such a biasing keeps the VCO fine tuning gain and the
phase noise spectrum constant, regardless of PVT variations.

4.5 Design of SSB mixer

Figure 13 shows the schematic of the SSB mixer.

It consists of two Gilbert mixers with connected outputs.
The differential output is loaded with a capacitor for high-
pass filtering. Figure 14 shows the layout of the SSB mixer Figure 14: Layout of SSB mixer preceded by 1:2 and 1:8 frequency
divider at first and second input, respectively.
including 1:2 and 1:8 frequency dividers at the inputs.
The layout of the whole circuit is depicted in Figure 15.
With a reference input of 80 MHz and an 8.8 GHz DRO 5 Simulation results
input a default frequency of 61.44 GHz is generated.
Another output at the divided VCO frequency (7.68 GHz) We have simulated both PLLs on transistor level. Figure 16
can be used for phase noise measurements. shows the simulated settling behavior of PLL2.

Figure 15: Layout of PLL cascade including post-synthesis dividers

Figure 12: Schematic of active loop filter. and single-sideband mixer.
 F. Herzel et al.: A Novel architecture for low-jitter multi-GHz frequency synthesis 343

results in a low clock jitter, provided that the mixer is

driven by a spectrally pure signal. A free running DRO can
be employed for this purpose which avoids manual tun-
ing. An exemplary design in BiCMOS technology was
analyzed and simulated on transistor level. It employs a
high-speed PFD using SiGe-HBTs to achieve a low in-band
noise floor of the second PLL. The presented circuit ar-
chitecture can be used for generating a low-cost, sta-
ble, mmW local oscillator source for terrestrial and
satellite communications.

Author contribution: All the authors have accepted respon-

sibility for the entire content of this submitted manuscript
Figure 16: Simulated settling of VCO control voltages in PLL2. and approved submission.
Research funding: None declared.
During the first 10 μs the loop filter capacitances are Conflict of interest statement: The authors declare no
loaded and the tuning voltages oscillate. After that period, conflicts of interest regarding this article.
the tuning voltages converge exponentially towards the
final values. The time constant is below 1 µs, corresponding
to a large loop bandwidth of PLL2. Figure 17 shows the
simulated PFD output signals close to the steady state. The References
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