Accepted Manuscript

4H-SiC superjunction trench MOSFET with reduced saturation current

Qingyuan He, Xiaorong Luo, Tian Liao, Jie Wei, Gaoqiang Deng, Tao Sun, Jian Fang,
Fei Yang

PII: S0749-6036(18)31665-3
DOI: 10.1016/j.spmi.2018.10.016
Reference: YSPMI 5928

To appear in: Superlattices and Microstructures

Received Date: 12 August 2018

Revised Date: 17 September 2018
Accepted Date: 16 October 2018

Please cite this article as: Q. He, X. Luo, T. Liao, J. Wei, G. Deng, T. Sun, J. Fang, F. Yang, 4H-SiC
superjunction trench MOSFET with reduced saturation current, Superlattices and Microstructures
(2018), doi: https://doi.org/10.1016/j.spmi.2018.10.016.

This is a PDF file of an unedited manuscript that has been accepted for publication. As a service to
our customers we are providing this early version of the manuscript. The manuscript will undergo
copyediting, typesetting, and review of the resulting proof before it is published in its final form. Please
note that during the production process errors may be discovered which could affect the content, and all
legal disclaimers that apply to the journal pertain.
 ACCEPTED MANUSCRIPT

4H-SiC Superjunction Trench MOSFET With Reduced

Saturation Current

Qingyuan Hea, Xiaorong Luoa, Tian Liaoa, Jie Weia, Gaoqiang Denga, Tao Suna, Jian

PT
Fanga, Fei Yangb

a
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic

RI
Science and Technology of China, Chengdu 610054, China
b
Global Energy Interconnection Research Institute, Changping District, Beijing 102209, China

SC
Corresponding author. Tel: +86 28 83206788, Fax: +86 28 83207120, Email: [email protected]

Abstract—A novel 4H-SiC superjunction trench metal oxide semiconductor field effect

U
transistor (SJ-TMOS) is proposed in this paper. The device features a grounded P+ buried
layer below the P-body, an oxide trench beneath the gate, and a P-region surrounding the
AN
oxide trench. The P-region, grounded P+ buried layer, and P-body serve as a three-level
buffer (TLB) to lower the saturation current and thus improve the short-circuit ruggedness.
M

Moreover, the P-region, P+ buried layer and N-drift form an SJ structure to decrease the
specific on-resistance (Ron,sp) and increase the breakdown capability. Compared with
D

conventional trench MOSFET (C-TMOS), the saturation current for SJ-TMOS is drastically
lowered and thus the short-circuit time (tsc) extends by 175%. Meanwhile, the Ron,sp decreases
TE

by 45% and the breakdown voltage increases by 10%. In addition, the SJ-TMOS exhibits a
low gate-to-drain charge (Qgd) due to the low permittivity of oxide trench and the
EP

nonlinearity in SJ capacitance characteristics.

Keywords: 4H-SiC, superjunction (SJ), saturation current, on-resistance, breakdown
C

capability.
AC

INTRODUCTION

Silicon carbide MOSFETs, as a potential candidate for the next generation power
switching device, are developing toward lower specific on-resistance (Ron,sp), lower switching
loss, higher breakdown capability, and better short-circuit ruggedness [1], [2]. The trench
technology and superjunction (SJ) structure are employed to reduce Ron,sp. The former
optimizes the channel density and scalability, and some shielding structures are joined to
overcome premature breakdown in oxide so as to keep the high breakdown voltage (BV)
 ACCEPTED MANUSCRIPT

[3]-[5]. The latter allows drift region heavily doped and modifies the electric field
distribution, realizing high BV and low Ron,sp [6]-[8]. Reducing the Ron,sp often leads to higher
saturation current and thus degrades the short-circuit ruggedness. To lower saturation current,
one typical way is to increase the JFET resistance, while the Ron,sp inevitably increases [9],
[10]. In terms of improving the high frequency characteristics, shrinking the gate-to-drain
overlapped area and thickening the bottom oxide are common methods in [11]-[13].

PT
The 4H-SiC superjunction trench MOSFET (SJ-TMOS) is proposed to optimize the
trade-off relationship between Ron,sp and short-circuit ruggedness, simultaneously improves

RI
dynamic performance and BV. The three-level buffer (TLB) reduces the saturation current
(Idsat). The SJ structure reduces Ron,sp and improves BV. The switching loss is decreased

SC
because of the reduced gate-to-drain capacitance (Cgd). Simulation based on Sentaurus TCAD
is carried out to investigate the static and dynamic characteristics. Shockley-Read-Hall
recombination, Auger recombination, Okuto avalanche, incomplete dopant ionization

U
mobility, doping dependence mobility, and high field saturation mobility are used in
AN
simulation. The thermodynamic model is covered in simulation of short-circuit test and an
appropriate heat resistance is attached to the drain contact.
M

DEVICE STRUCTURE AND MECHANISM

D

Figure 1 shows the schematic cross-sectional structures of the proposed SJ-TMOS, the
TE

conventional trench MOS (C-TMOS) and the double-trench MOS (trench source and trench
gate, DT-MOS). The gate structure of SJ-TMOS includes a shallow trench and a deep trench.
The shallow trench is wider and filled with polysilicon. The gate oxide thickness is 50nm.
EP

The deep trench is filled with SiO2 to form an oxide trench. A P-region surrounding the oxide
trench relieves the electric field (E-field) at its bottom and corner. A grounded P+ buried layer
C

touches the shallow trench to reduce the high E-field at its corner. The P-region, the grounded
AC

P+ buried layer and the P-body make up the TLB to drastically lower the Idsat. The P-region
assists in depleting the N-drift and thus the Nd is increased. The oxide trench can withstand
high voltage and reduce the Cgd owing to the low permittivity. The nonlinearity in SJ
capacitance characteristics further lowers Cgd.
In simulation of this paper, the channel length is 0.3µm, and an electron mobility of
20cm2/V·s. The doping concentration of P-body is 2×1017cm-3. The doping profile of P+
buried layer for SJ-TMOS and C-TMOS exhibits Gauss distribution, with surface
concentration of 1×1019cm-3 and junction depth of 0.3µm. The doping concentration of drift
region and the P-region are represented by Nd and Np, respectively. The distance between
 ACCEPTED MANUSCRIPT

P-body and P+ buried (w1) and the distance from P+ buried to the central of JFET region (w2)
influence the saturation current.
2.25µm 1.75µm 1.75µm
Source Gate Source Gate Source Gate

N+ N+ N+
P Poly P Poly P Poly
w1
1.2µm P 1µm Metal P
CSL Lm
P+ (2 ×1016cm-3)
P+ P+
w2
0.4 SiO2
µm SiO2 0.5µm
7µm

PT
10µm
1µm
N-drift N-drift N-drift
(N d) ×1015cm -3)
( 6.5× ×1015cm-3)
( 6.5×
P (Np)

RI
N+ N+ N+

Drain Drain Drain

SC
(a) SJ-TMOS (b) C-TMOS (c) DT-MOS
Fig.1. Schematic cross-sectional structures of (a) proposed superjunction trench MOSFET (SJ-TMOS), (b)
the conventional trench MOSFET (C-TMOS) and (c) DT-MOS.

U
Figure 2 shows the off-state E-field contours. At the drain voltage of 1200V, the maximum
AN
E-field in oxide (Eox-max) of 1.77MV/cm for the SJ-TMOS is far below those of the other
devices. Even though the breakdown occurs at 1633V, the Eox-max for the SJ-TMOS is in the
safe area. Figure 3 (a) shows the depletion boundary of the three-level buffer (TLB) at the
M

on-state. The depletion caused by TLB narrows the current and thus the out-put current is apt
to saturate. Figure 3 (b) shows the assistant depletion effect of the P-region and the P+ buried
D

layer on the N drift region and the JFET region at off-state, and thus the higher optimum Nd is
TE

allowed.
EP

EOX=2.74MV/cm
EOX=3.07MV/cm Electric Field(MV/cm)

3.0

ESiC=3.19MV/cm ESiC =3.88MV/cm ESiC=3.87MV/cm

Oxide Oxide 2.5
C

Trench Trench ESiC=3.7MV/cm

2.0

1.5
AC

1.0

0.5
EOX=1.77MV/cm EOX=2.68MV/cm
0.0

(a) (b) (c) (d)

Fig.2. OFF-state E-field contours for the (a) SJ-TMOS at Vds=1200V, (b) SJ-TMOS at Vds=BV=1633V (c)
C-TMOS at Vds=1200V and (d) DT-MOS at Vds=1200V.
 ACCEPTED MANUSCRIPT

N+
P-body
Poly Poly Poly Poly
3rd

2nd P+

SiO
SiO2 SiO2
SiO SiO2
SiO SiO2
SiO
2 1st 2 2 2

P P
N-drift

PT
Depletion boundary

(a) (b)

RI
Fig.3. (a) In the on-state, the mechanism of three-level buffer to lower the saturation current. (b) In the

OFF-state, the P-region and the P+ buried layer assist to deplete the N-drift.

SC
RESULTS AND DISCUSSION

U
Figure 4 (a) shows the breakdown characteristic curves. The SJ-TMOS has the highest BV
AN
of 1663V, and the equipotential lines distribution is more uniform than those of C-TMOS and
DT-MOS. Figure 4 (b) shows the vertical electric field distributions. Because of the mutual
depletion effect of the P- and N- pillar in the SJ, the E-field distribution for the SJ-TMOS at
M

the P/N interface is uniform and thus its BV is higher than those of C-TMOS and DT-MOS.
Figure 5 (a) shows the relationship between BV and Nd, Np for SJ-TMOS. For each Nd, there
D

is an optimum Np correspondingly. As Nd increases, Np must be increased to realize the

TE

charge balance, while the BV will degrade owing to the increase in lateral electric field.
Figure 5 (b) shows the impacts of Nd on the BV, Ron,sp and the figure of merit
(FoM=BV2/Ron,sp). The proposed structure without the P-region of SJ is as a comparison with
EP

the proposed SJ-TMOS, the optimum Nd for the SJ-TMOS of 9.5×1016 cm-3 is far higher than
1.2×1016 cm-3 for the comparison structure, and the FoM is 2× high. Figure 6 shows the
C

trade-off relationship between Ron,sp and Eox-max for these three devices. The SJ-TMOS
AC

exhibits a great advantage in reducing Eox-max- and Ron,sp over the other two devices. For the
DT-MOS, the Eox-max decreases and the Ron,sp increases as the length of mesa (Lm, see figure
1(c)) reduces.
 ACCEPTED MANUSCRIPT

100 4
SJ-TMOS BV=1633V SJ-TMOS C-TMOS DT-MOS
C-TMOS BV=1486V
DT-MOS BV=1554V
µ A/cm2) Electric Potential (V)
10-1 3

E (MV/cm)
Flat Electric Field
1600

1200
10-2
Ids (µ

800 2
400

10-3 0
1
SJ-TMOS C-TMOS DT-MOS

10-4

PT
0
0 400 800 1200 1600 0 2 4 6 8 10
Vds (V) y (µm)

(a) (b)

RI
Fig.4. (a) Blocking I-V curves, the breakdown voltages are 1633V, 1486V, 1554V, respectively. The inset
figures are electric potential contours. (b) Electric field distributions in the vertical direction.

SC
2000 3000
BV (V) , FoM (MW/cm2) with P-region w/o P-region
×1016cm-3
Nd= 6.5× ×1016cm-3
Nd= 8× 3.0
BV
1800 ×1016cm-3
Nd= 9.5× ×1016cm-3
Nd= 11× Ron,sp Optimum
2500
FoM

Ω⋅cm2)
2.5
1600
BV (V)

U
2000
Optimum

Ron,sp (mΩ
1400 2.0
1500
AN
1200
1.5
1000
1000
1.0
800 500
0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.5 1.0 1.5 2.0 6 8 10 12 14
M

Np /1017 (cm-3) Nd /1016 (cm-3)

(a) (b)
D

Fig.5. (a) Relationship between BV and Np with different Nd for the SJ-TMOS. (b) Relationship between FoM
and the Ron,sp for the proposed SJ-TMOS and the proposed structure without the P-region of SJ.
TE

6 Lm(µm)=1
Eox-max (MV/cm)

5
EP

0.9

DT-MOS 0.8
4

Ron,sp : 45% 0.7

C

3
0.6
Eox-max : 42% C-TMOS
AC

2
SJ-TMOS
1
1.2 1.4 1.6 1.8 2.0 2.2 2.4
2
Ω⋅cm
Ron,sp (mΩ )
Fig.6. Ron,sp verse Eox for SJ-TMOS, C-TMOS and DT-MOS. The Lmesa of DT-MOS is from 1µm to 0.6µm
with the step of 0.1µm.

Figure 7 shows the I-V characteristic curves of the three structures at different Vgs. The
SJ-TMOS has the lowest both Ron,sp and Idsat among the three devices. It’s worth noting that
the ST-TMOS works in the saturated state around Vds = 5V, but the output currents for the
 ACCEPTED MANUSCRIPT

C-TMOS and the DT-MOS are still unsaturated at Vds = 15V.

The trade-off relationships between the Idsat and the Ron,sp for the SJ-TMOS are shown in
figure 8. As w1 and w2 reduce, the Idsat decreases while the Ron,sp increases. If the value of w1
or w2 is too small (w1 = 0.4µm or w2 = 0.2µm), the current paths have pinched off owing to
the depletion of PN junction, so the Ron,sp is large. When the value of w1 is too large (e.g. w1 =
0.8µm), w2 pays a critical impact on Idsat. As w1 reduces, the impact of w2 on Idsat is decreased.

PT
When w1 ≥ 0.5µm, the change range of Ron,sp is relatively narrow, but the Idsat increase 3×
from w1 = 0.5µm to w1 = 0.8µm, The value of 0.5µm is thus chosen for the optimum value of

RI
w 1.
5
Vgs = 15V 20V 25V

SC
SJ-TMOS
4 C-TMOS
DT-MOS
2
)
Ids (kA/cm

U
AN
1
M

0
2 4 6 8 10 12 14
Vds (V)

Fig.7. Output characteristic curves at Vgs = 15V/20V /25V.

D

8
TE

w1=0.8µm µm
w2=0.2µ
µm
w2=0.3µ
6
µm
)

w2=0.4µ
2
Isat (kA/cm

µm
w2=0.5µ
EP

4
w1 from 0.8µm to 0.4µm, step 0.1µm
w1=0.8µm
2
0.5µm
C

w1=0.4µm

0
AC

w1=0.4µm

1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
2
Ω⋅cm
Ron,sp (mΩ )

Fig.8. Tradeoff between Ron,sp and Idsat for the SJ-TMOS as the functions of w1 and w2.

Figure 9 gives the short-circuit waveforms for the SJ-TMOS, the C-TMOS and the
DT-MOS at the bus voltage of 600V. The gate resistance and the stray inductance are set to
be 5Ω and 10nH, respectively. The gate turns on at 5µs. The short-circuit current for
SJ-TMOS is the lowest due to its lowest saturation current as mentioned above. The
 ACCEPTED MANUSCRIPT

short-circuit duration time for SJ-TMOS, C-TMOS and DTMOS is set to 11µs, 5µs and 8µs,
respectively. The failure for C-TMOS and DT-MOS is detected after the gate turns off as
shown within the blue and green lines, because the high heat produced during short-circuit is
stored and it can’t give away. Consequently, the short-circuit withstanding time (tsc) for
C-TMOS and DT-MOS is less than 5µs and 8µs, respectively. For the SJ-TMOS, thanks to
the low saturation current, the heat produced during short-circuit doesn’t reach the critical

PT
value and thus the SJ-TMOS is found no failure.

1000

RI
800
Vds(V)

600

400

SC
20
600V
15
10n H
Vgs (V)

10 5µs 5Ω
5 8µs DUT

U
0 11µs
-5
-10
AN
6
Ids (kA/cm )
2

SJ-TMOS
4 C-TMOS
DT-MOS
2
M

0
0 5 10 15 20 50 75 100 125 150
t (µs)
D

Fig.9. Output currents and gate voltages at room temperature with the short-circuit time of 11µs, 5µs
TE

and 8µs, respectively. The inserted figure is the test circuit of short-circuit for simulation.

The reverse transfer capacitance (Crss = Cgd) and the output capacitance (Coss) play critical
roles on reducing the switching losses. As shown in figure 10 (a), the capacitance
EP

characteristic for the SJ-TMOS is strongly nonlinear. This phenomenon in SJ devices has
been discussed in [14]-[16]. The equivalent capacitance for SJ-TMOS at Vds < Vc (see figure
C

10(a)) and Vds > Vc are potted in figure 10 (b), When Vds < Vc, the Crss is small because the
AC

neutral region of the P-region connects to the source, which shields Cgd. Therefore, the
capacitance at the bottom of the trench is gate-to-source (Cgs). As Vds increases beyond Vc, the
Crss increases due to the weakened shielding effect with the shrinking P-neutral region. Gate
charges of these three structures are tested with the circuit in the inset of figure 10 (c). All the
device areas are set to be 1 cm2, the dc voltage of 600V is applied, and the currents of load
and gate are 100A and 200mA, respectively. A SiC JBS diode is used to provide a
freewheeling path. As shown in figure 10 (b), the Qgd for the SJ-TMOS, the C-TMOS and
DT-MOS is 162nC/cm2, 211nC/cm2 and 304 nC/cm2. The lowest Qgd for the SJ-TMOS
 ACCEPTED MANUSCRIPT

exhibits the lowest switching losses.

15
10-7 SJ-TMOS C-TMOS DT-MOS Qgd (nC/cm2)
SJ-TMOS 162
-8 C-TMOS 211
10 600V
DT-MOS 304
10
C (F/cm )

-9

Vg (V)
2

10
Coss Cgs SiC
100A
JBS
10-10
5 200mA
Crss DUT
10-11 Qgd

PT
10-12 Cgd
depletion boundary 0
0 Vc=60V 200 400 600 0 200 400 600 800 1000
2
Vds (V) Vds < Vc Vds > Vc Qg (nC/cm )

RI
(a) (b) (c)
Fig.10. (a) Terminal capacitances of SJ-TMOS, C-TMOS and DT-MOS. (b) the equivalent capacitances are

SC
plotted in the SJ-TMOS for Vds < Vc and Vds > Vc. (c) Specific gate charge characteristic curves. The extracted
Qgd is 162, 211, and 304nC/cm2, respectively. The inserted figure is the text circuit.

Table I summarizes the simulation results of SJ-TMOS, C-TMOS and DT-MOS. The FoM

U
BV2/Ron,sp for the SJ-TMOS increases by more than 100%, and the FoM Ron,sp×Qgd decreases
AN
by more than 50% compared with those of the other two devices. The larger value of
BV2/Ron,sp and the smaller value of Ron,sp × Qgd exhibit the better static and dynamic
performance, respectively. As can be seen from figure 11, the result of the proposed
M

SJ-TMOS is closed to the theoretical 1-D limit of 4H-SiC unipolar devices. With the
advancement of fabrication process technology, the SiC SJ technology can be extended to
D

higher level of voltages, such as 3.3kV, 6.5kV, and the advantages would be more
TE

outstanding.
TABLE I.
CHARACTERISTICS OF SJ-TMOS, C-TMOS AND DT-MOS
BV2/ Ron,sp Ron,sp×Qgd tsc
EP

Device BV Eox-max Ron,sp Qgd

2
Type (V) (MV/cm) (mΩ·cm ) (nC/cm2) (MW/cm2) (mΩ·nC) (µs)
SJ-TMOS 1633 1.77 1.14 162 2339 185 11
C

C-TMOS 1486 2.74 2.11 211 1046 445 4

DT-MOS 1554 3.07 2.07 304 1167 629 7
AC

Eox-max at Vgs=0V, Vds=1200V.

 ACCEPTED MANUSCRIPT
100

7]
[1
it
lim

8]
)

[1
2
Ω⋅cm

it
10

la r

im
ip o

rl
Ron,sp (mΩ
[5]

ola
un
[11]

ip
[10]

Si

un
[4]

iC
1 [4]

-S
4H
[6] [7]

PT
This work

0.1
100 1000 10000
BV (V)

RI
Fig.11. Tradeoff between the breakdown voltage and the specific on-resistance in recent 4H-SiC
simulation reports and research samples.

SC
A feasible fabrication procedure is shown in figure 12. The deep trench is formed by ICP
etching after the shallow trench in (e). A metal with high etching selectivity to 4H-SiC is
selected for the mask layer, and it can be used for next three steps from (f) to (h). Figure 13 (a)

U
shows the 3-D layout of SJ-TMOS, the P+ source is located in the z-direction, and it is
AN
protruded over the P-body to contact on the P+ buried layer. The schematic cross section of
the face ABCD and A’B’C’D’ are plotted in figure13 (b) and (c). The P+ buried layer is well
grounded by the P+ source.
M
D
TE

SUB SUB SUB SUB SUB

(a) (b) (c) (d) (e)

EP

METEL
G
C
AC

SUB SUB SUB SUB SUB

(j) (i) (h) (g) (f)

Fig.12. key fabrication process flows for the SJ-TMOS: (a) Form the P+ buried layer, (b) n-type epitaxial
growth (c) form the P+, N+ sources and the P-body, (d) ICP etch to form the shallow trench, (e) ICP etch to
form the deep trench, (f) vertical implantation to form the P-region at the bottom of trench, (g) tilted
implantation to form the P-region along the sidewall of trench (h) fill the deep trench with SiO2, (i) thermal
oxidation to form the gate oxide, (j) deposition the poly silicon and form electrodes.
 ACCEPTED MANUSCRIPT
z
A’
’ B’
’
x
A B B’
P+ A’
’ ’
N+ A B
y Poly P
N+
C Poly P P+
D P+

SiO
SiO22
SiO2
SiO2

SiO2 P+ Contact SiO2

PT
N-drift
D’
’ C’
’
N+
D C

(a) (b) (c)

RI
Fig.13. (a) 3-D view of SJ-TMOS. (b) Schematic cross section of the face ABCD (c) Schematic cross
section of the face A’B’C’D’.

SC
CONCLUSION

U
AN
A 1200-class 4H-SiC SJ-TMOS is proposed in this paper. The TLB effectively lowers the
saturation current by more than 50%, leading to the lengthened tsc of 11µs. The SJ structure
reduces the on-resistance and improve the breakdown capability. The electric field in oxide is
M

low owing to the shielding effect of the P-region and the grounded P+ buried layer. In
addition, the SJ-TMOS also exhibits a good dynamic performance because of the low Qgd.
D

The SJ-TMOS is more attractive and promising for the high frequency and high power
TE

application.

REFERENCES
EP

[1] S. Ji, Z. Zhang, F. Wang. "Overview of high voltage sic power semiconductor devices:
C

development and application." CES Transactions on Electrical Machines and Systems, 2017,
1(3): 254-264.
AC

[2] X, Li, X. Tong, A. Q. Huang, et al. "SiC Trench MOSFET With Integrated
Self-Assembled Three-Level Protection Schottky Barrier Diode." IEEE Transactions on
Electron Devices 65.1 (2018): 347-351.
[3] J. Tan, J. A. Cooper, and M. R. Melloch. "High-voltage accumulation-layer UMOSFET's
in 4H-SiC." IEEE Electron Device Letters 19.12 (1998): 487-489.
[4] T. Nakamura, Y. Nakano, M. Aketa, R. Nakamura, S. Mitani, H. Sakairi, Y. Yokotsuji, et al.
"High performance SiC trench devices with ultra-low ron." Electron Devices Meeting
(IEDM), 2011 IEEE International. IEEE, 2011.
 ACCEPTED MANUSCRIPT

[5] X. Zhou, R. Yue, J. Zhang, G. Dai, J. Li, and Y. Wang. "4H-SiC Trench MOSFET With
Floating/Grounded Junction Barrier-controlled Gate Structure." IEEE Transactions on
Electron Devices 64.11 (2017): 4568-4574.
[6] T. Masuda, K. Ryoji, and H. Toru. "0.97 mΩ·cm2/820 V 4H-SiC Super Junction V-Groove
Trench MOSFET." Materials Science Forum. Vol. 897. Trans Tech Publications, 2017.
[7] X. Zhong, B. Wang, J. Wang, and K. Sheng. "Experimental Demonstration and Analysis

PT
of a 1.35-kV 0.92-mΩ·cm² SiC Superjunction Schottky Diode." IEEE Transactions on
Electron Devices (2018).

RI
[8] K. Ryoji, Y. Sakuma1, K. Kojima, et al. "First experimental demonstration of SiC
super-junction (SJ) structure by multi-epitaxial growth method." Power Semiconductor

SC
Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on. IEEE, 2014.
[9] D. Peters, R. Siemieniec, T. Aichinger, T. Basler, R. Esteve, W. Bergner, and D. Kueck
"Performance and ruggedness of 1200V SiC-Trench-MOSFET." Power Semiconductor

U
Devices and IC's (ISPSD), 2017 29th International Symposium on. IEEE, 2017.
AN
[10] M. Zhang, J. Wei, H. Jiang, K. J. Chen, and C. H. Cheng et al. "A New SiC Trench
MOSFET Structure with Protruded p-Base for Low Oxide Field and Enhanced Switching
Performance." IEEE Transactions on Device and Materials Reliability 17.2 (2017): 432-437.
M

[11] H. Jiang, J. Wei, X. Dai, M. Ke, I. Deviny, and P. Mawby. "SiC trench MOSFET with
shielded fin-shaped gate to reduce oxide field and switching loss." IEEE Electron Device
D

Letters 37.10 (2016): 1324-1327.

TE

[12] K. Han, B. J. Baliga, and W. Sung. "Split-Gate 1.2-kV 4H-SiC MOSFET: Analysis and
Experimental Validation." IEEE Electron Device Letters 38.10 (2017): 1437-1440.
[13] H. Takaya, J. Morimoto, K. Hamada, T. Yamamoto, J. Sakakibara, Y. Watanabe, and N.
EP

Soejima. "A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics."
Power Semiconductor Devices and ICs (ISPSD), 2013 25th International Symposium on.
C

IEEE, 2013.
AC

[14] F. Udrea, G. Deboy, and T. Fujihira. "Superjunction power devices, history, development,
and future prospects." IEEE Transactions on Electron Devices 64.3 (2017): 720-734.
[15] H. Kapels. "Superjunction MOS devices—From device development towards system
optimization." Power Electronics and Applications, 2009. EPE'09. 13th European
Conference on. IEEE, 2009.
[16] I. Castro, J. Roig, R. Gelagaev, B. Vlachakis, F. Bauwens, D. G. Lamar, and J. Driesen.
"Analytical switching loss model for superjunction MOSFET with capacitive nonlinearities
and displacement currents for DC–DC power converters." IEEE Transactions on Power
 ACCEPTED MANUSCRIPT

Electronics 31.3 (2016): 2485-2495.

[17] B. J. Baliga. "Power semiconductor device figure of merit for high-frequency
applications". IEEE Electron Device Letters, 10.10 (1989): 455-457.
[18] D. T. Morisette. "Development of robust power Schottky barrier diodes in silicon
carbide." (2001).

PT
RI
U SC
AN
M
D
TE
C EP
AC
 ACCEPTED MANUSCRIPT

● The three-level buffer of the proposed device lowers the saturation current and thus improves the
short-circuit ruggedness.
● the superjunction structure reduces the specific on-resistance and improves the breakdown voltage.
● The P-region and the grounded P+ buried layer shield the trench and thus reduce the electric field in
oxide.
● The low switching loss is caused by the low gate-to-drain charge.

PT
RI
U SC
AN
M
D
TE
C EP
AC