Materials Science Forum Submitted: 2016-09-19

ISSN: 1662-9752, Vol. 897, pp 483-488 Revised: 2017-01-10

doi:10.4028/www.scientific.net/MSF.897.483 Accepted: 2017-01-10
© 2017 Trans Tech Publications, Switzerland Online: 2017-05-15

0.97 mΩcm2/820 V 4H-SiC Super Junction V-Groove Trench MOSFET

T. Masuda 1, a*, R. Kosugi1, b, T. Hiyoshi2, c
1
Nation Institute of Advanced Industrial Science and Technology,
16-1 Onogawa, Tsukuba, Ibaraki, 303-8564 Japan
2
Sumitomo Electric Industries, Ltd.,
1-1-3 Shimaya, Konohana, Osaka 554-0024, Japan
a
[email protected], [email protected], [email protected]

Keywords: 4H-SiC trench MOSFET, V-groove, (0-33-8) face, Super Junction.

Abstract. We have fabricated Super Junction (SJ) V-groove trench MOSFETs (VMOSFETs),
demonstrated a low specific on-resistance (RonA) of 0.97 mΩcm2 and a blocking voltage (VB) of
820 V. In the first trial, SJ structure in 4H-SiC have proved to be a good combination with MOS
interface on (0-33-8) faces which keep high channel mobility in high doping concentration. We
designed a protection structure called “upper p-pillar region” and demonstrated that VB lowering
appeared according to its width.

Introduction
In recent years, there has been more development in 4H-SiC trench MOSFETs in order to reduce a
specific on-resistance (RonA) [1]. However, gate oxide reliability at the trench bottom and damaged
surfaces on the trench sidewall (resulting in low channel mobility) remain issues. The 1.2kV-class
VMOSFETs using the 4H-SiC (0-33-8) face on the channel region were reported in previous
conference [2-4]. In order to protect the trench bottom, the VMOSFETs have buried p-regions in the
epitaxial layer and a thick bottom oxide in the trench bottom. After the optimization of the device
structure [3], the VMOSFET showed a very low RonA of 2.0 mΩcm2 and a high gate oxide reliability
[4]. The drift resistance is dominant and occupies over 50 % of the RonA in the VMOSFET. The drift
resistance must be reduced in order to further lower RonA. SJ devices are the most promising
candidates for the reduction of the drift resistance. There are a few reports on SiC SJ devices [5, 6],
and the SJ PiN diodes showed a clear advantage in terms of RonA and VB [5]. When SJ structures are
utilized in the conventional 4H-SiC trench MOSFETs, there are important issues related to the
channel doping concentration. The channel of conventional 4H-SiC trench MOSFETs are fabricated
on the (1-100) faces or the (11-20) faces. The channel concentration must remain lower than
approximately 1.0x1017 cm-3 in order to suppress the channel resistance due to low channel mobility.
On the other hand, in the case of low channel concentration, the short channel effect (lower threshold
voltage) or the punch through effect will be happened. However, a VMOSFET using the (0-33-8)
faces is the best solution in the high channel doping concentration because the channel mobility on
(0-33-8) faces can keep 80 cm2/Vs in a high channel doping concentration of 1.0x1018 cm-3 due to a
low trap density at the edge of the conduction band. Thus, we expected to gain a foothold for the
ultimate low on-resistance exceeding the 4H-SiC limit by the first demonstration of trench SiC
MOSFET with SJ structure.

Experiment
Figure 1 shows the schematic cross-sectional view of SJ-VMOSFET. The SJ-VMOSFETs were
fabricated on an n-type 4 ° off axis 4H-SiC (000-1) substrate with an n-type epitaxial layer. The cell
pitch and the active area were 7.0 µm and 1.61x10-4 cm2, respectively. The SJ drift layer consists of p-
and n- type pillar (p-pillar and n-pillar) structures, which were periodically arranged and
synchronized to the V-groove trenches.

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484 Silicon Carbide and Related Materials 2016

The thickness and the doping concentration of the n-drift layer were 6.0 µm and 3.0x1016 cm-3,
respectively. The p-pillars with 3.0 µm deep box profiles with a doping concentration of
3.0x1016 cm-3 were formed with high energy aluminum ion-implantation (~ 9 MeV). In order to
protect the trench bottom oxide, the authors introduced an upper p-pillar with a doping concentration
of 1.0x1018 cm-3.
The 2.0 µm thick epitaxial layer was grown as the V-groove MOSFET layer on the SJ structures.
The source regions and the p-bodies were formed by ion-implantations whose doping concentrations
were 5.0x1016, 2.0x1019 and 1.0x1018 cm-3 respectively. The upper p-pillars were connected between
the p-type source regions and p-pillars around the edge of the active area not shown in Fig. 2. The gap
was located between the trench bottom and the upper p-pillar in order to reduce the RonA of the upper
drift layer due to enhancement of current spreading.
The V-groove trench was formed with Cl2 chemical thermal etching using SiO2 mask [7]. The gate
oxidation was carried out in a dry O2 ambient, followed by nitridation at 1350 °C as post oxidation
annealing. The gate oxide thickness on the channel region was approximately 40 nm. The channel
length and doping concentration were 0.6 µm and 1.0x1018 cm-3 respectively.

Fig. 1. Schematic cross-sectional view of SJ-VMOSFET.

Fig. 2. Transfer characteristic of SJ-VMOSFET.

Results
Figure 1 shows the transfer characteristics of the SJ-VMOSFET on a logarithmic scale. The
threshold voltage (Vth) at the drain current density of 1.0 mA/cm2 was 3.4 V, which was the same Vth
as the reported VMOSFETs [2]. There is no difference between the Vth at the drain voltage of 0.1 and
that of 1.0 V, so it indicates that the short channel effect does not occur in the SJ-VMOSFET.
 Materials Science Forum Vol. 897 485

Figure 3 shows the output characteristics of the SJ-VMOSFET. The RonA was 0.97 mΩcm2
(1.01 mΩcm2) at a gate voltage of 25 V (20 V) and a drain voltage of 1.0 V, which excludes the
measurement probe and stage contact resistance of about 0.3 Ω. Figure 4 depicts the calculated and
experimental RonA compositions of the VMOSFET. The experimental data showed the agreement
with calculated value. The SJ resistance occupied less than 9% of the total. Further, we consider that
there is room for RonA reduction through the n-type drift layer with a higher doping concentration or a
shorter channel length, which is located between the p-pillar region and substrate in Fig. 2 and left as
the buffer layer in order to form pn junctions with a low leakage current in the epitaxial layer. A
proven cell pitch of 7.0 µm in SJ structure was used in this study though the cell pitch of VMOSFETs
can be shortened up to 5.0 µm. It means that the channel resistance can be further reduced by the
increasing of the channel density.

Fig. 1. Output characteristics of SJ-VMOSFET.

Fig. 2. Specific on-resistance analysis for various resistance elements.

Blocking characteristics are shown in Figure 5. The VB obtained at a drain leakage current of
1 mA/cm2 was 820 V. The VB is greater than a theoretical blocking voltage (VB_theory) of 710 V
calculated by the parallel plane model for the conventional drift layer with the same doping
concentration.
486 Silicon Carbide and Related Materials 2016

Fig. 3. Blocking characteristics of SJ-VMOSFET.

Figure 6 depicts the RonA-VB relationship of the previously reported trench MOSFETs and this
work. Although there is still scope for improvement in the RonA by removing the excess n-type drift
layer, substrate grinding, and the reduction in cell pitch, the SJ-VMOSFET displayed one of the
industry-leading levels. The impact of SJ structure clearly appears in 2000 V or higher.

Fig. 4. Trade-off relationship between RonA and VB of various SiC trench MOSFETs.

Discussion
Upper p-pillar region plays an important role for RonA and VB. The upper p-pillar region connects
the p-pillar region to the p-type source region around the active area not shown in Fig. 2. We expect
that the upper p-pillar regions protect the gate oxide at the trench bottom and ground the p-pillars of
the SJ structure.
Figure 7 shows the VB with various Wup with a p-pillar width (Wp) of 2.0 µm. It was found that the
VB tendency is divided into 2 groups. The VB is higher than the VB_theory in a Wup larger than 1.5 µm.
Figure 8 shows the typical drain and gate leakage current density of the 2 groups. Both of the gate
leakage currents are below the level of the measurement limit. It means that the leakage current
between the source and the drain is dominant in each of devices and the gate oxide is protected by the
upper p-pillar. The VB of group B is less than half of VB_theory. The punch through effect can be
 Materials Science Forum Vol. 897 487

considered to occur at the VB in group B with a high doping concentration of the channel region of 1.0
x 1018 cm-3 and group B prevents the punch-through effect due to suppressing the n-pillar region as
the drain current path.

Fig. 7. VB tendency of various Wup with Wp of 2.0.

Fig. 8. Typical drain and gate leakage current of group A (low VB) and B (high VB).

Figure 9 shows the relationship between the Wup and the Wp for RonA. The RonA does not depend on
the Wup because the upper p-pillar region is formed inside the p-pillar region. It indicates that the best
Wup for the tradeoff relationship between the VB and the RonA is 2.0µm which is the maximum width
in this study. Devices represented by dark blue circles in Fig. 9 correspond to those of the Fig. 7. The
RonA of the devices for group B is found to be almost constant despite of the increasing blocking
voltage. It suggests that the upper p-pillar prevents lowering VB due to punch-through effect without
increasing the RonA.
488 Silicon Carbide and Related Materials 2016

Fig. 9. Wup contribution for RonA.

Summary
This is the first demonstration of super-junction MOSFETs with V-groove trenches in 4H-SiC
with an RonA of 0.97 mΩcm2 and a VB of 820 V. It is a reasonable resistance estimated from the
channel resistance [3] and drift resistance [5]. The Vth of SJ-VMOSFET keeps the same level as the
conventional VMOSFET. The upper p-pillar preventing the punch through effect without increasing
the RonA. We accomplished to pave the way for the ultimate low loss SiC device by the first
demonstration of trench SiC MOSFET with SJ structure.

Acknowledgment
This work was supported by Council for Science, Technology and Innovation (CSTI),
Cross-ministerial Strategic Innovation Promotion Program (SIP), “Next-generation power
electronics/Consistent R&D of next-generation SiC power electronics” (funding agency: NEDO).

References
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[4] T. Hiyoshi et al. Proc. of Int Symp. Power Semicond. Devices & ICs (Prague), 39 (2016).
[5] R. Kosugi et al., Proc. of Int Symp. Power Semicond. Devices & ICs (Hawaii), 346 (2014)
[6] X. Zhong, et al., Proc. of Int. Symp. Power Semicond. Devices & ICs (Prague), 231 (2016).
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