Microelectronics Journal 125 (2022) 105432

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Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Device and circuit-level performance comparison of GAA nanosheet FET

with varied geometrical parameters
N. Aruna Kumari *, P. Prithvi
Department of Electronics & Communication Engineering, National Institute of Technology Warangal, Warangal, 506004, Telangana, India

A R T I C L E I N F O A B S T R A C T

Keywords: In this paper, DC and analog/RF figures of merit (FOMs) for different geometrical variations of the Gate all
Nanosheet around (GAA) Nanosheet FET (NSFET) are computationally examined. For each nanosheet, the thickness (NT)
GAA varied from 5 nm to 9 nm and width (NW) varied from 10 nm to 50 nm to analyze the performance variations
SCEs
with the device’s geometry. It is observed that DC metrics like switching ratio, drain induced barrier lowering
Analog and RF FOMs
Sub-7-nm
(DIBL), and subthreshold swing (SS) degrade with increment in geometry of NS. Moreover, the increment in
Verilog-A analog/RF FOMs like transconductance (gm), output conductance (gds), cutoff frequency (fT), transconductance
frequency product (TFP), and gain bandwidth product (GBW) is observed as the width and thickness are increase
towards 50 nm and 9 nm, respectively. However, intrinsic gain, GFP, and GTFP deteriorate as the physical di­
mensions of the NSFET increase. On top of that, inverter and ring oscillator (RO) circuits are designed and the
performance is demonstrated by varying width of the nanosheet. The circuit analysis is performed in Cadence
Virtuoso tool by using look-up table based Verilog-A model. A decrement of 17.6% in the delay of the inverter is
noticed when the width is increased from 10 nm to 50 nm. Also, it is observed that the static current of inverter is
less than pA, which ensures less static power dissipation. Furthermore, an increment of 46.5% in fosc of 3-stage
RO is observed as width increased to 50 nm. According to the various results analyses, NSFET is a promising
device for high performance and high frequency analog/RF applications for sub-7-nm technology nodes.

1. Introduction conventional FETs. In transistors, SCEs lead to an increase in energy loss

and performance deterioration. In order to have control over power
The semiconductor devices have been significantly improved since consumption, in addition to the device dimensions, the supply voltage
1992 when the ITRS started to issue the roadmaps for semiconductor (VDD) also needs to be scaled. To maintain high drive currents, fewer
technology. These roadmaps define the industry trends for their internal electric fields and good performance in short channel transis­
improved productivity and performance. Also, they proclaim the ways tors, the threshold voltage (Vth) also needs to be scaled. However, the
to continue Moore’s law. The miniaturization of the transistors has been decrement in threshold voltage leads to a substantial increment of
following Moore’s law and remarkably leads to high throughput, lower sub-threshold current leakage. The leakage current (IOFF) is affected by
energy consumption, high speed, and higher integration of the transis­ various performance metrics like threshold voltage, doping profile, de­
tors. By downscaling the physical dimensions, the device can be oper­ vice’s physical dimensions, the junction depth of source and drain, the
ated at high speed at higher operating frequencies and consumes less thickness of gate oxide, and VDD. Some of the short channel effects are
power. According to Moore’s Law, there is a two-fold increment in the threshold voltage roll-off, degradation of subthreshold slope (SS), drain
transistors count on a chip for every one and half years. Moreover, induced barrier lowering (DIBL), etc [6]. While scaling down the tran­
downscaling the device leads to easy portability and cost reduction sistor, to keep control of SCEs, the gate oxide thickness also needs to be
[1–4]. In addition to the gate length, device dimensions are also reduced scaled in proportional to the channel length. However, the reduced
for each technological node [5]. In conventional metal oxide semi­ thickness of gate oxide leads to a considerable amount of current flow
conductors because of aggressive scaling tends to various short channel from the gate and destroys the advantageous concept of the infinite
effects (SCEs). The fields from the source/drain start influencing the input impedance of the MOSFETs. To circumvent these SCEs, various
region under the gate, which invites the detrimental SCEs in device engineering and new structures with multiple gates are proposed.

* Corresponding author.
E-mail addresses: [email protected] (N.A. Kumari), [email protected] (P. Prithvi).

https://doi.org/10.1016/j.mejo.2022.105432
Received 5 February 2022; Received in revised form 2 April 2022; Accepted 5 April 2022
Available online 15 April 2022
0026-2692/© 2022 Elsevier Ltd. All rights reserved.
N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 1. (a) Three-dimensional view of NSFET with Nitride spacer, (b) Cross sectional view of NSFET with NT and NW and (c) Three-dimensional view of NSFET with
nanosheet channels.

performance. Nanosheet (NS) and nanowire (NW) are examples of GAA

structures. On the other hand, it is reported that, due to the surface
roughness factor, the nanowire performance is deteriorated [23]. The
GAA nanosheet structures are FinFET successors for sub-7-nm technol­
ogy and beyond, and have emerged as viable challengers for traditional
FinFETs since they offer greater control over the channel region. Robust
leakage control and strong current driving capacity are two advantages
of nanosheet architectures. Due to the tight electrostatic control over the
channel region, NSFETs are resistant to short channel effects [24]. S. D
Kim reported that NSFETs exhibited greater electrostatic performance
on the channel compared to GAA nanowire and FinFET architectures
[25]. By making minimal changes to the fabrication flow of FinFET,
NSFET can be fabricated as shown in Ref. [26]. Also, it is shown that by
using NSFETs instead of FinFETs, 30% higher effective width (Weff) can
be produced on the same footprint. Another remarkable observation is
that single stack nanosheets have been shown to have superior intrinsic
Fig. 2. Validation of simulation models with that of experimental data [27]. performance than FinFETs or stacked nanowires for a given active width
due to lower parasitic capacitance. In a given footprint, nanosheets offer
a higher effective width making them good at driving capacitive loads
By stacking a ferroelectric layer in the gate stack, the Negative Capaci­
[27,28]. Moreover, nanosheet width doesn’t affect by fin pitch which
tance FET (NCFET) can be realized which offers steeper switching slope.
provides greater flexibility in maintaining appropriate Weff. Usage of
The detailed analysis of NCFET and its mixed signal applications are
more stacked nanosheets to maximize the drive current is a better op­
discussed in Refs. [7–11]. Also, advanced multiple gate structures like
tion, but the larger height of the device exacerbates parasitic capaci­
FinFET and Nanosheet/Nanowire structures are proposed to mitigate
tances [29].
SCEs [12–20].
In this paper, the performance of two stack GAA NSFET at 5 nm
Double gate MOSFETs contain two gates, in which gates are present
technology node is designed towards ITRS projections, and various DC
at the bottom and top of the device. By maintaining the two gates, the
and analog/RF design metrics are discussed. Further, high-k dielectric
channel’s electrostatic integrity increases and offers better short channel
material HfO2 is involved in the gate stack to reduce the gate leakage
performance. However, in double gate MOSFETs, the misalignment
current [30]. Although some studies discussed the performance evalu­
problem of the top gate and bottom gate is present, which causes
ation of NSFET with different geometry at the device level [33], the
degradation in on current [21]. In trigate and FinFET devices, the gates
impact of NS width (NW) on the voltage transfer characteristics (VTCs) of
surround the channel in the left, top and right directions and are possible
CMOS inverter, propagation delay (τP), switching current (ISC) and fre­
candidates to replace the orthodox MOSFETs in the semiconductor in­
quency of oscillations (fOSC) of 3 stage ring oscillator circuits still needs
dustry. Moreover, FinFET structures are more immune to SCEs and offer
to be discussed. The efforts are made in this paper to evaluate these
fewer DIBL and SS values for sub-22-nm technology nodes. The semi­
parameters in detail.
conductor companies like TSMC and INTEL have adopted FinFETs into
In order to evaluate the NSFET performance towards circuit appli­
their significant portion of IC fabrication since 2011. However, for
cations, digital circuits like inverter and ring oscillator (RO) are
further scaling of FinFETs, taller and thinner fins are required to get
designed and demonstrated their performance. The paper is organized as
more drive current, which increases the process complication of the
follows. The device physics and parameters are discussed in section 2 of
device. Moreover, maintaining the taller fins on a narrow base may lead
the manuscript. The geometrical dependence on NSFET towards DC, and
to fracture and malfunction of the circuit [22].
analog/RF performance is investigated in section 3. For all the results
To circumvent these problems, researchers came up with the solution
presented in section 3, n-type NSFET is considered. By using both n-type
of GAA configurations. Since the channel in GAA structure is controlled
NSFET (N- NSFET) and p-type NSFET (P- NSFET), circuit level perfor­
in all directions by the gate and hence improves the sub threshold
mance is explored in section 4. Further, section 5 concludes the paper.

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Table 1 for NW are considered. Section 3.1 deals with DC performance depen­
Simulation parameters. dence on geometry by considering various DC performance metrics.
Parameter Value Analog/RF FOMs are discussed in section 3.2.
Thickness of nanosheet (nm) 5–9
Width of nanosheet (nm) 10–50
Length of gate (nm) 16 3.1. Geometry dependence on DC metrics of NSFET
Source/Drain doping (cm− 3) 1020
Doping of the channel (cm− 3) 1015 In this section, the NSFET’s DC metrics are evaluated with various
EOT (TSiO2 +(εSiO2/εHfO2) × THfO2) (nm) 0.78 thickness and width values and are discussed in detail. The major per­
Dielectric of Underlap Nitride
formance characteristics mentioned in this section include ION, IOFF,
Pad length of Drain/Source (nm) 12
Source/Drain underlap length (nm) 5 switching ratio (ION/IOFF), threshold voltage (Vth), DIBL, and SS.
Gate work function (eV) 4.6 The dependence of electron mobility on the channel in ON state is
Height of the gate (nm) 60 depicted in Fig. 3(a). The device exhibits higher mobility in the channel
area due to better gate electrostatics. Fig. 3(b) depicts the electric field
distribution of NSFET. The device exhibits a higher electric field in the
2. NSFET device and simulation parameters
spacer region. However, the impact is lower on the channel. Fig. 3(c)
depicts the potential distribution of NSFET at VDS = VGS = 0.7 V.
The three-dimensional diagram of GAA NSFET is depicted in Fig. 1
The rise in drain current and parasitic capacitance is a trade-off when
(a). 2-D cross sectional view in XZ plane is shown in Fig. 1(b), where NT
using high-k spacers to reduce circuit delay. Enhanced spacer designs
and NW are the thickness and width of each nanosheet respectively. All
will be required to improve circuit and device performance even more
the simulations are performed through the Cogenda 3D TCAD simulator
by lowering parasitic capacitances while maintaining a high drive cur­
[31]. A gate length (LG) of 16 nm is considered for NSFET. A p-type
rent [34]. In our work, the nitride spacer with an optimized thickness of
doping concentration of 1015 cm− 3 and n-type doping concentration of
5 nm is considered, which offers lower degradation of the Ieff/Ceff
1020 cm− 3 for channel and source/drain, respectively used for simula­
electrical performance [27]. The introduction of high-k spacers induces
tion. To overcome the gate oxide tunneling a high-k gate stack with HfO2
field coupling through the fringing effect and enhances switching ratios
of 1.5 nm and interfacial oxide of 0.5 nm, which forms an effective oxide
[35]. By using nitride spacer due to the more distance between channel
thickness (EOT) of 0.78 nm is considered. The metal gate with the work
and drain ensures reduced drain potential over the channel and
function of 4.6 eV is maintained throughout the simulations. To over­
come the direct tunneling a spacer distance of 5 nm is incorporated,
which improves the sub-threshold performance [32].
The device is well calibrated using [27,33], and the ID-VGS charac­
teristics are depicted in Fig. 2. The physical models incorporated for
simulation are considered from Ref. [33] and are as follows. Schenk’s
bandgap narrowing model is used to account for narrow bandgap effects
caused by larger doping levels. The Shockley-Read-Hall (SRH) recom­
bination method is used to assess the consequences of carrier generation
and recombination. The Lombardi mobility model is used to account for
scattering phenomena such as surface roughness. The Selberherr impact
ionization model is used to calculate the electron-hole pair’s generation
rate. The simulation models are validated by using experimental data.
Table 1 provides the values of device parameters that areincluded in the
simulation.

3. Results and discussion

In this section, both DC and analog/RF FOMs are discussed for

NSFET. To investigate the performance dependence on NSFET geome­
Fig. 4. Transfer characteristics of NSFET in linear and log scale for various
try, a lower and upper bound of 5 nm and 9 nm for NT, 10 nm and 50 nm
NW values.

Fig. 3. (a) Electron mobility (b) Electric field distribution (c) Potential of NSFET.

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 5. (a) ION and (b) IOFF as a function of NW for various NT values.

Fig. 6. (a) Switching ratio and (b) Threshold voltage (Vth) variations as a function of NW for various NT values.

Fig. 7. (a) SS and (b) DIBL as a function of NW for various NT values.

minimizes SCEs, as shown in Fig. 3(c). nanosheet’s geometry increases. The highest increment of 286% in ION is
Fig. 4 shows the transfer characteristics NSFET with various widths observed for NT of 5 nm for the NW ranging from 10 nm to 50 nm.
at constant LG of 16 nm and NT of 5 nm. The flow of current in the The OFF current (IOFF) variations are shown in Fig. 5(b) with respect
nanosheet is dependent on the width of the nanosheet. In order to to various width and thickness values of the nanosheet. In addition to
evaluate the impact of ID on NW, the device width is varied from a the increment in ION, IOFF also gets incremented with the increment in
minimum of 10 nm–50 nm. Moreover, the NT is also varied from 5 nm to the geometry of NS and is shown in Fig. 5(b). This phenomenon is
9 nm to see the impact of NT on ID. Fig. 5(a) depicts the ON current (ION) observed because, increment in NW leads to more leakages in the device
of the device at VGS = VDS = 0.7 V, which is a crucial measure for high because of the degraded control of gate over the channel. It is evident
performance applications. Also, the proportionality increment in ION that by using thinner nanosheets, the IOFF is mitigated. In the OFF state,
with respect to effective width gives rise to higher currents when the as the NT increases, the potential barrier height and conduction band

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 8. (a) Transconductance (gm ) and (b) Transconductance generation factor (TGF) values as a function of NW for various NT values.

energy in the channel gets reduced and leads to an increment in leakage

Vtlin − Vtsat
currents. However, as the thickness decreases, the ION decreases DIBL = (2)
VDsat − VDlin
marginally due to mobility degradation caused by increased perpen­
dicular electric field [33]. An increment of 2 orders in IOFF is observed Here, Vtlin is the Vth taken at VDlin = 0.04 V and Vtsat is Vth taken at
with the increment in NW from 10 nm to 50 nm at NT of 9 nm. As NT VDsat = 0.7 V. The Vth is calculated through the constant current method
increases, a large increment in the IOFF is observed due to the degrada­ at 200nA × Weff/LG. The effective width (Weff) is the perimeter of the
tion of electrostatic integrity over the channel. nanosheet [32,33].
Fig. 6(a) depicts ION/IOFF variations with respect to NW for various Fig. 7(b) depicts DIBL values as a function of NW for various NT
values of NT. For better logic applications, the switching ratio of 106 is values. It can be seen that when the dimensions of the nanosheets grow,
feasible. It is observed from Fig. 6(a) that the switching ratio perfor­ the DIBL grows as well. By integrating nanosheets with lesser width and
mance deteriorates as the NW increases due to large increment in IOFF. A thickness, the DIBL can be reduced due to low Vth roll-off. For NW 50 nm,
large increment in the IOFF with a marginal increment in ION tends to the highest increment of 30.6% in DIBL is observed. Also, for NT of 9 nm,
downfall in the ION/IOFF as NW increases. Moreover, the switching ratio the highest increment of 62% in DIBL is noticed. From this, it can be
decreases as the NT increases, which is because of a huge increment in inferred that DIBL is sensitive to higher width and thickness variations.
IOFF due to reduced electrostatic integrity of the gate over the channel.
The highest decrement of 89% in switching ratio is noticed for NT of
9 nm as the NW1 towards 50 nm. Degradation of switching ratio is more 3.2. Geometry influence on Analog/RF response of GAA NSFET
as the NT increases due to weak electrostatic control of gate over the
channel. The aggressive scaling of devices made it possible to build system-on-
Threshold voltage (Vth) variations are shown in Fig. 6(b). The Vth chip (SOC) devices. Analog and RF circuits are embedded on SOC for
gets decrement as the NW increases due to an increment in leakage various applications. Thus, the study of analog and RF metrics of a de­
currents. The same trend is observed as the NT is increased. It is seen that vice is very crucial to estimate the potential of the device towards analog
a downfall of 2.9% and 5.4% in Vth for NW of 10 nm and 50 nm, as the NT and RF applications. In this section, various analog/RF metrics like gm ,
is ranges from 5 to 9 nm. Similarly, a fall of 5.3% and 7.6% in Vth are TGF, gds, intrinsic gain, cut-off frequency, intrinsic delay, TFP, GFP,
observed for the NT of 5 and 9 nm, as the NW is increased. As the NT and GTFP, and GBW are studied for different geometries of NSFET.
NW values are increasing, the Vth roll-off is more since the deterioration Transconductance (gm ) is one of the essential analog metrics which
of gate electrostatics on the channel region. evaluates the change in ID obtained to the corresponding change in VGS.
SS is an essential parameter for the evaluation of subthreshold per­ Inherently gm gives the speed of a device, and better gm indicates that the
formance towards low power applications. SS gives the value of VGS device can operate at high speed for logic operations [36]. Moreover, the
required to get a decade change in ID. Lower SS values are preferred for gate transport efficiency is high for devices which are having high gm .
the good subthreshold operation of the device. The SS takes the Transconductance decides the amplifying capability of the device. A
expression (1). higher amount of gain or amplification can be obtained by having more
gm values for analog applications. gm can be calculated by using equation
SS = (
∂log10 ID −
) 1
(1) (3).
∂VGS
∂ID
SS values as a function NW for various NT values are given in Fig. 7 gm = (3)
∂VGS
(a). The NSFET with geometrical values of NW and NT of 10 nm and 5 nm
performs best with an SS of 62.5 mV/dec, which is close to the optimum Fig .8(a) depicts the gm variations for various NW and NT values. It is
value. noticed that for the lesser nanosheet widths, the value of gm is less.
As the NW is increasing, a maximum increment of 8.6% in SS is found Higher gm values can be obtained by increasing the nanosheet thickness
for NT of 9 nm. As the NT is raised, a maximum growth of 10.6% in SS is and width. Due to the peak electron velocity at the source region and less
noticed for NW of 50 nm. The sub-threshold performance degrades for channel doping in the channel region, higher gm is obtained. As the NW
higher NW and NT values because of higher SS. increasing, the highest increment of 273% in gm is observed for NT of 5
DIBL is another important sub-threshold performance measure, and nm. Also, the highest increment of 32% in gm is observed for NW of 10 nm
low value of DIBL is preferred for optimal device performance. Equation as the NT increases towards upper bound. It is noticed that the
(2) is used to calculate the DIBL. improvement in gm is due to the rise in drain current for larger NT and NW
values.
TGF = gm/ID, is another crucial analog FOM and it estimates the

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Fig. 9. (a) gds and (b) Maximum gain, AV0 values as a function of NW for various NT values.

Fig. 10. (a) Cgg and (b) Cgd versus VGS for various NW values for constant NT of 5 nm.

efficient use of drain current to obtain the agreeable value of gm . It is also

∂ID
taken as accessible gain per unit power dissipation. The device with gds = (4)
∂VDS
more TGF values can be operated at lower voltages without deterio­
rating the performance [37]. Also, TGF is used to estimate the power Fig. 9(a) depicts gds variations for various nanosheet width and
required to achieve high speed [38]. The variations in TGF as a function thickness values. It is clearly seen that for nanosheet width of 10 nm and
NW for various NT values are depicted in Fig. 8(b). As the NT and NW thickness of 5 nm outperforms remaining all the variations, and it can be
values are increase, a reduction in TGF is noticed. In the weak inversion concluded that for higher values of nanosheet’s width and thickness, the
region, higher TGF values are obtained and tend to decrease in the super amplification capacity of the device degrades since gds is increasing.
threshold region due to velocity saturation. In addition to the increase in Moreover, for thicker nanosheets, gds is increasing drastically. The
gm , an increase in ID is noticed when the NW and NT increase due to the highest increment of 431% in gds is noticed for NT 9 nm respectively as
rise in effective width. There is a growth rate of 273% in gm observed the NW is increased from 10 nm to 50 nm. Also, an increment of 101% in
when the NW is increased from 10 nm to 50 nm. However, the growth gds is observed for NW of 50 nm as the NT is increased from 5 to 9 nm.
rate of 286% in ID is observed when the width is increased from 10 nm to Intrinsic gain for various NW and NT variations is shown in Fig. 9(b).
50 nm, which is more than the growth rate of gm . This makes the TGF It is noticed that with the increment in NW, the gain is deteriorating
downfall in spite of the increment in gm . The highest 8.8% in TGF is because of the increased dependency of drain current on drain voltage.
observed for NT of 9 nm as the NW is increased from 10 nm to 50 nm. Similarly, the higher gain is obtained for thinner nanosheets because of
Also, the highest decrement 8.3% in TGF is observed for NW of 50 nm as the decrement in output conductance and enhanced gate electrostatics
the NT is raised from 5 to 9 nm. It can be seen that the deterioration in over the channel. The highest decrement of 13.1% in gain is observed for
TGF is observed for increment in NW and NT values of NSFET. NT of 9 nm as the NW is increased from 10 nm to 50 nm. Also, the highest
Another essential analog/RF figure of merit is output conductance deterioration of 14.6% in gain is observed for NW of 50 nm as the NT is
(gds) and it should be minimum for good performance of the device. increased from 5 to 9 nm. For higher values of NW and NT the gain is
Mostly, the devices incorporated in analog circuit design are operated at deteriorating because of the increment in output conductance.
the saturation region. Ideally, in the saturation region, the drain current Fig. 10(a) and (b) show the Cgg and Cgd variations as a function of VGS
is independent of drain voltage. However, because of short channel ef­ for various NW values at a constant NT of 5 nm. Also, Fig. 11(a) and (b)
fects like DIBL, the variation in drain voltage leads to variations in drain depict the Cgg and Cgd variations with VGS for various NT values of the
current also. To measure the dependency of drain current on drain nanosheet at a constant NW of 10 nm. The gate capacitance is the
voltage in the saturation region, the parameter gds is evaluated, and for summation of both Cgs and Cgd, i.e., Cgg = Cgd + Cgs. It can be deduced
better performance, the gds values should be as minimum as possible. from Figs. 10 and 11 that as the nanosheet dimensions grow, the Cgg and
The gds is given by equation (4). Cgd increase due to the increase in effective area.

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 11. (a) Cgg and (b) Cgd values as a function of VGS for various NT values for constant NW of 10 nm.

Fig. 12. (a) fT (b) Intrinsic delay, τ values with respect to NW for different NT values.

Fig. 13. (a) TFP and (b) GFP values as a function of NW for various NT values.

To analyze a device for its suitability for high frequency applications, gm

it is crucial to consider the Miller capacitance (Cgd) [39]. Miller capac­ fT = (5)
2π(Cgs + Cgd )
itances are capacitances between the output and input that mitigate the
device’s gain performance at high frequencies. The crucial FOMs, which From Fig. 12(a), the variations in fT are observed from different
are dependent on Miller capacitances, are discussed further in this geometrical variations of NSFET. It can be seen that with the raise in NW,
paper. the fT followed an increasing manner. As the NW and NT increase, the
Cut-off frequency (fT) is another important characteristic to consider transconductance, effective width and capacitance values increase and
when evaluating the device’s analog/RF performance. Usually, the fT is cause an increase in cut-off frequency. The maximum increment of
derived by taking into account of the frequency at which the magnitude 24.6%, in cut-off frequency, is obtained for NT of 7 nm NW increases
of current gain is equal to one. The cut-off frequency is defined as [40]. from lower to upper bound. Also, the highest increment of 10.8% in fT is
observed for NW of 20 nm as NT is increased from lower to upper bound.

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Fig. 14. (a) GTFP and (b) GBW values as a function of NW for various NT values.

capacitance is less. Thus, there is a downfall in τ as the NW ranges from

Table 2 10 nm to 50 nm. It is noticed that the lowest delay characteristics are
Comparison of DC and analog/RF metrics with existing literature. obtained for an NW of 50 nm. The decrement of 22.5% and 26.5% in τ is
Reference ION (A) IOFF (A) ION/ SS DIBL gm fT observed for NT values of 5 nm and 9 nm, respectively, as the NW raised
IOFF (mV/ (mV/ (S) (GHz) from 10 nm to 50 nm. Also, the decrement of 12.7% and 17.3% in the τ is
dec) V) observed for NW of 10 nm and 50 nm, respectively, as the NT is increased
[33] 6.8 × 6.7 × 2.3 × 71 22.8 – 404 from 5 to 9 nm.
10− 5 A 10− 12 A 107 The TFP is shown in Fig. 13(a). TFP is another important analog/RF
[46] 16.6 × – – – 32 78 × 607 figure of merit and is obtained by taking the product of trans­
10− 5 A 10− 5
[47] 2.37 × 1.15 × 2× 70.89 – 5.4 3790
conductance and cut-off frequency, given by equation (7) [43].
10− 5 10− 10 105 × gm
A/μm A/μm 10− 5 TFP = × fT (7)
ID
[48] 832 13.3 6.3 × 74 – – –
μA/μm nA/μm 104 TFP gives the trade-off between bandwidth and power and is used in
This work 2.45 × 1.24 × 1.98 62.48 31.81 2E-4 300
medium and high-speed circuit applications [44]. From Fig. 13(a), it can
10− 5 A 10− 14 A × 109
be observed that TFP is more for higher NT and NW values because of an
increment in cut-off frequency. The highest increment of 17.9% and the
The intrinsic delay, τ is shown in Fig. 12(b). Basically, τ can be ob­ lowest increment of 14.11% are observed as the NW is varied from 10 nm
tained by taking the product of total resistance and total capacitances to 50 nm for NT of 5 nm and 9 nm, respectively. Also, the maximum
[41]. τ is very important FOM to evaluate the device’s practicality in increment of 5.8% and minimum increment of 2.4% in TFP are noticed
SOC applications [42]. The intrinsic delay is given by the expression (6) for NW of 10 nm and 50 nm, respectively, as the NT is increased from 5
nm to 9 nm.
Cgg VDD
τ= (6) Gain frequency product (GFP) is another crucial analog/RF figure of
ION
merit [45], given by
From equation (6), it can be seen that, τ is proportional to the total gm
capacitance Cgg and power supply and is inversely proportional to the GFP = × fT (8)
gds
ION of the device. It is obvious that as the effective width of the nano­
sheet increases, both on current and gate capacitance of the device are As the intrinsic gain is the most important parameter for operational
boosted up. As the NW is increased from 10 nm to 50 nm, there is an amplifiers, GFP is depicted in Fig. 13(b) is used to estimate the perfor­
enhancement of 4x in ION and 2x in Cgg for a fixed NT of 5 nm. So mance of operational amplifiers in high frequency circuit implementa­
compared to the improvement in on current, the increment in the gate tions. There is a decrement in GFP observed for increment in NW and NT
values. The decrement of 5.5% and of 21% in GFP were observed as the

Fig. 15. Flow chart of verilog- A model creation and SPICE simulation.

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 16. Look up table format (left) and Verilog-A code for symbol creation (right).

Fig. 17. (a) Inverter schematic diagram (b) transient response of inverter for NW = 10 nm and NT = 5 nm.

NW varies from 10 nm to 50 nm for NT of 5 nm and 9 nm, respectively. gm gm

Also, the decrement of 21% and 34% in GFP are observed for NW of 10 GTFP = AV0 × TFP = × × fT (9)
gds ID
nm and 50 nm, respectively, as the NT is increased from 5 nm to 9 nm.
More deterioration in GFP is observed for higher NT and NW values since The GTFP as a function of nanosheet width for various nanosheet
there is an increment in the gds. thickness values is depicted in Fig. 14(a). It can be seen that by using less
The gain transconductance frequency product (GTFP) is very much NW and NT for nanosheet, higher GTFP can be achieved. For NT of 5 nm
useful for circuit designers. GTFP allows the designers to identify the and 9 nm, respectively, the decrement of 10% and 28% in GTFP were
optimum region achieving a good trade-off among parameters like found when the NW varied from 10 nm to 50 nm. Also, the decrement of
transconductance, speed, and gain of the device [44]. GTFP is given by 24% and of 40% in GTFP is observed for NW of 10 nm and 50 nm
(9) respectively as the NT is increased from 5 nm to 9 nm.

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 18. (a) Propagation delay (τP), EDP and (b) Switching current of inverter for different NW at constant NT of 5 nm.

Fig. 19. (a) Transfer characteristics of inverter for various VDD values (b) NM as a function of NW at VDD = 1 V.

observed for thickness values of 6 nm and 9 nm respectively as the NW is

increased from 10 to 50 nm. Moreover, an increment of 10.93% and
12.2% in GBW is observed for NW of 30 nm and 40 nm, respectively, as
the NT is increased from 5 to 9 nm. The comparison of DC and analog/RF
metrics with existing literature is given Table .2.

4. Circuit analysis

In this section, the impact of nanosheet width on inverter and ring

oscillator’s performance is analysed by performing the SPICE simulation
using the look up table-based Verilog-A model [39]. The flow of the
SPICE simulation is shown in Fig. 15.
Initially, the device is designed using the Visual TCAD tool [31]. On
top of that, the DC and AC characteristics are obtained using the Visual
Fab parallel simulation platform. From the obtained characteristics, the
look up tables are prepared using the format shown in Fig. 16. By using
the look up tables and Verilog -A model, the symbol is created in the
Fig. 20. 3- stage ring oscillator (RO).
Cadence Virtuoso tool [50] and is further used in schematic diagrams.
Fig. 17 (a) depicts the schematic of the inverter diagram. In the inverter
Another crucial analog/RF FOM is gain bandwidth product (GBW) diagram, VDD is the supply voltage, Vin and Vout are the input and output
and is used to evaluate device efficiency in high frequency applications. voltages, respectively. The transient response for NW of 10 nm is shown
GBW can be calculated by the following equation [45]. in Fig. 17(b). For digital applications, it is important to evaluate the
gm parameters like propagation delay (τP), energy delay product (EDP),
GBW = (11)
20π Cgd switching current, and noise margins to estimate the digital performance
of the device. For the designed inverter, these parameters are calculated
From Fig. 14(b), it can be seen that as the width and thickness in­
and compared the performance variations for NW of 10 nm and 50 nm at
crease, the increment in GBW is observed since it is proportional to
a constant NT of 5 nm.
transconductance (gm). Miller capacitance or gate to drain capacitance
Various transient and dc responses of the inverter are simulated
(Cgd) increases with increment in width and thickness values. However,
using the Cadence Virtuoso platform. The load capacitance CL is taken as
the improvement in GBW is observed because of a large improvement in
the sum of Cgg of both N-NSFET and P-NSFET [49]. The transient
gm compared to Cgd. An increment of 23.8% and 24.7%, in GBW is
response of the inverter is shown in Fig. 17(b) for the time of 5 μs.

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N.A. Kumari and P. Prithvi Microelectronics Journal 125 (2022) 105432

Fig. 21. 3- stage ring oscillator’s transient response for (a) NW of 10 nm and (b) NW of 50 nm.

There is an increment of 46.5% observed for NW increment from 10 nm

Table 3 to 50 nm due to higher ION. As a result of the foregoing research, greater
Comparison of fosc with existing literature. widths assure device flexibility for high-speed applications. The com­
Reference Number of stages fosc (GHz) Technology node parison of fosc with existing literature is shown in Table 3.
[54] 3 52.44 22
[55] 3 6.02 90 5. Conclusion
[56] 3 41.10 30
[57] 3 2.45 180 The DC and analog/RF performance of NSFET is investigated in this
[58] 9 9 50
research by altering the geometry of each nanosheet at the 5 nm tech­
This work (NW = 10 nm) 3 36.77 5
This work (NW = 50 nm) 3 53.86 5 nology node. As the NT and NW are raised, there is an increase in both ION
and IOFF. The optimum values for switching ratio, DIBL, and SS are ob­
tained for lower values of NW and NT. However, analog/RF FOMs like
Fig. 18(a) shows the propagation delay of the inverter for NW of 10 gm, gds, fT, TFP, and GBW are more for higher NW and NT values of NS.
nm and 50 nm. The overall propagation delay (τP) was obtained by These results will give an understanding of DC and analog/RF perfor­
considering the formula shown in Fig. 18(a) [51]. Where CL is the load mance of NSFET with geometrical variations of the device. Moreover,
capacitance, I is the average current in the circuit. As τP α CL × (1/ION (N the circuit performance was assessed for circuits like inverter and 3-
NSFET) + 1/ION (P NSFET)), with the increment in NW, both I and CL will stage RO and found that with the increment in width, the propagation
increase. However, the relative increment in I is higher than that of CL delay gets decremented, and fosc increases. These results will give per­
and causes a decrement in τP. From the result analysis, it is noticed that formance insights of GAA NSFET at both device and circuit levels.
as the NW increases from lower to upper bound, the τp decreases by 37%.
Fig. 18(a) also shows EDP of the inverter for different NW values. An
increment of 2.5x is noticed in EDP as the NW increases towards its upper Declaration of competing interest
bound.
Fig. 18(b) depicts the switching current (ISC) of inverters for NW The authors declare that they have no known competing financial
values 10 nm and 50 nm. The inverter with higher NW is delivering more interests or personal relationships that could have appeared to influence
switching current, and an increment of 4.73x is observed in peak the work reported in this paper.
switching current with NW of 50 nm. Also, the static current (at Vin = 0
V, Vin = VDD) is less than 10 pA and offers much lower static power References
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