Dell Latitude E4200 Compal LA-4291P Rev 0.1 Schematic
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aoa.crioDell Latitude E4200 Compal LA-4291P Rev 0.1 Schematic
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COMPAL CONFIDENTIAL
MODEL NAME : JAZ00
PCB NO : LA-4291P
D
BOM P/N : 46155331L01 D
MINICOOPER
C uFCBGA Mobile Penryn SFF ULV C
Intel Cantiga GS(High Performance) + ICH9M SFF
12-07-2007
REV : 0.1(X00)
B
@ : Nopop Component B
1@ : TAA board Used only
2@ : Without TAA board Used only
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cover sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 1 of 49
5 4 3 2 1
A B C D E
Compal confidential On Audio/B
CK505 Clock GEN CPU ITP Port FAN GUARDIAN III
INTEL
Block Diagram CRT CONN. Penryn-3MB SFF ULV SILEGO SLG8LP554BV EMC4002
Model : JAZ00 uFCBGA CPU +3.3V_M page 6 +1.05V_VCCP page 7 +FAN1_VOUT page 19 +3.3V_M page 19
+5V_RUN +1.5V_RUN
+1.05V_VCCP
RGB +VCC_CORE 956pin page 7,8,9
1
DAI RGB 1GB on Board 1
E-Family Vedio Switch H_A#(3..35) System Bus H_D#(0..63) (128Mx8)*8pcs page 16,17
USB8/USB9 FSB 800 MHz
SATA5 TS3DV520ERHUR RGB 800 MHz
DOCKING
DOCK LPC BUS +3.3V_RUN page 20 INTEL DDRIII-DIMM X1
Memory BUS DDR3 page 18
page 31 DPB/DPC Cantiga GS-High Performance +1.5V_MEM
+3.3V_RUN
CHA for memory down +V_DDR_MCH_REF
1363pin BGA CHB for SO-DIMM
+1.5V_MEM +0.75V_DDR_VTT
LVDS +1.5V_RUN On Audio/B
LVDS CONN. 2:1 LVDS MUX GFX Frequency 457/533 MHz
+1.05V_M SATA4 BKT_Audio
MAXIM MAX4889 +1.05V_VCCP
+LCDVDD page 20 +3.3V_RUN_BKT_PWR page 20 +VCC_GFXCORE page 10,11,12,13,14,15 On BT/B On IO/B
E-SATA
On IO/B USB Port Inverting Buffer & Driver
BKT_LVDS BLUETOOTH
+1.5V_RUN/100MHz HDA X1 USB Port X1 TI SN74HC368PWR
Memory Card &1394 DMI*4 page30 page35 page35
1394 CONN. +3.3V_RUN_BKT_PWR page26
Controller
2
RICOH R5C833 PCI BUS USB 2.0 USB[6] USB[0] USB[3] 2
SD/MMC CONN. INTEL
+3.3V_RUN page29
ICH9M SFF HDA
+1.5V_RUN Azalia Codec Headphone AMP.
PCI Express BUS 569pin BGA GLCI/LCI IDT 92HD71B7 ADI SSM2602
+RTC_CELL
Intel Boazman +VDDA
PCIE3 PCIE2 PCIE1 +3.3V_RUN +3.3V_RUN_BKT_PWR page26
82567LM +3.3V_RUN page26
+1.05V_VCCP SATA0
+1V_LAN_M
EXPRESS Card WLAN WWAN +3.3V_ALW_ICH page 22,23,24,25
+1.8V_LAN_M
+3.3V_SUS Mini Card1 Mini Card 2 On MIC/B
+3.3V_LAN page28
+1.5V_RUN +1.5V_RUN +1.5V_RUN 1.8" SATA Dock
+3.3V_RUN page35 +3.3V_WLAN page30 +3.3V_RUN_WWAN_PWR page30 USB[10] SSD CONN. Dig. MIC
+3.3V_RUN page35
USB[7] USB[4] LPC BUS Broadcom USH LAN Switch
WWAN_USB
BCM5880KFBG PI3L500-AZFEX On Audio/B
SIM/UIM SPI
2:1 MUX Card +3.3V_RUN page32 +3.3V_LAN page28 MIC
+3.3V_RUN_BKT_PWR page21 page30 HeadPhone
3 BKT_USBBIO On IO/B & MIC Jack 3
USB[5] 32M 4K section
USBH TERIDIAN
73S8009CN Dock
3V/5V BKT_USBH +3.3V_RUN page32 Transformer HP
page41 W25X32VSSIG
2:1 MUX +LOM_VCT Audio AMP.
+3.3V_LAN page24 +3.3V_RUN_BKT_PWR page21 TI TPA6040A4 BKT_SPK
1.5V/1.05V Smart Card
page42 BIO_USB +5V_RUN_BKT_PWR page27
On BIO/B +SC_VCC page32 RJ45 CONN.
1.8V/0.75V SMSC KBC BIOMETRIC
page45 INT. Speaker
MEC5035 page35 2-4W, 4OHM*1
page27
GPIO EXPANSION
CHARGER BC BUS +RTC_CELL
page46 SMSC ECE1088 SMBUS Touch Pad On BLT/B
+3.3V_ALW page36 +3.3V_ALW page34 On MIC/B
+5V_RUN_BKT_PWR page36
DC IN & BATT IN BlackTop CONN.
4
page40 BKT SW and LED 4
BC BUS BC BUS page 22
VCORE (IMVP-6) DELL CONFIDENTIAL/PROPRIETARY
page43 KBD Scan extension SUPER I/O DOCK LPC BUS Compal Electronics, Inc.
INT. KBD SMSC ECE1077 SMSC ECE5028 Title
GFX VCC CORE page36 Block Diagram
+3.3V_ALW page36 +3.3V_ALW page33
page44 Size Document Number Rev
WWW.AliSaler.Com
0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 2 of 49
A B C D E
5 4 3 2 1
POWER STATES
Signal SLP SLP SLP S4 SLP ALWAYS M SUS RUN CLOCKS USB PORT# DESTINATION
State S3# S4# S5# STATE# M# PLANE PLANE PLANE PLANE
0 JUSB (Ext Right Side)
D
S0 (Full ON) / M0 HIGH HIGH HIGH HIGH HIGH ON ON ON ON ON 1 NONE D
2 NONE
S3 (Suspend to RAM) / M1 HIGH HIGH HIGH HIGH ON ON ON ON
LOW OFF
3 JESATA (Ext Left Side)
S4 (Suspend to DISK) / M1 HIGH HIGH HIGH ON ON ON ON 4 WLAN
LOW LOW OFF
S5 (SOFT OFF) / M1 HIGH HIGH ON ON ON ON 5 WWAN
LOW LOW LOW OFF
6 BT
S3 (Suspend to RAM) / M-OFF HIGH HIGH HIGH ON ON
LOW LOW OFF OFF OFF
7 Express card
S4 (Suspend to DISK) / M-OFF HIGH ON 8 DOCKING
LOW LOW LOW LOW OFF OFF OFF OFF
S5 (SOFT OFF) / M-OFF ON 9 DOCKING
LOW LOW LOW LOW LOW OFF OFF OFF OFF
10 USH->BIO
11 NONE
C C
PM TABLE
+15V_ALW +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M +3.3V_RUN_BKT_PWR +3.3V_BKT_PWR PCI EXPRESS DESTINATION
+5V_ALW +1.5V_MEM +3.3V_RUN +1.05V_M +1.05V_M +5V_RUN_BKT_PWR
power +3.3V_ALW +1.8V_RUN (M-OFF) +3.3V_RUN_WWAN_PWR
Lane 1
plane
MINI CARD-2 WWAN
+3.3V_ALW_ICH +1.5V_RUN +INV_PWR_SRC
+3.3V_RTC_LDO +0.75V_DDR_VTT +LCDVDD Lane 2 MINI CARD-1 WLAN
+1.5V_ALW_HDA +VCC_GFXCORE
State
+VCC_CORE Lane 3 None
+1.05V_VCCP
Lane 4 EXPRESS CARD
S0 ON ON ON ON ON ON OFF
S3 ON ON OFF ON OFF OFF OFF Lane 5 None
B
S5 S4/AC ON OFF OFF ON OFF OFF OFF
Lane 6 Giga LAN B
S5 S4/AC don't exist OFF OFF OFF OFF OFF OFF OFF
BLT mode ON OFF OFF OFF OFF ON ON
SATA DESTINATION
SATA0 SSD
PCI TABLE SATA1 None
SATA4 ESATA
PCI DEVICE IDSEL REQ#/GNT# PIRQ
SATA5 DOCKING
R5C833 AD17 REQ#1 / GNT#1 PIRQ[C..D]
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 3 of 49
5 4 3 2 1
5 4 3 2 1
RUN_ON FDS4435
+INV_PWR_SRC
Q33
(12.8V to 20V)
ADAPTER
GFX_VR_ON ADP3209
D +VGFX_COREP D
(PU7)
(1.05V)
ALWON SN0608098 +5V_ALW BAT54SW (PD10/PD11)
+15V_ALW
+PWR_SRC (PU2)
BATTERY
STS11NF30L SI3456BDV VT351FCX VT351FCX
TPS51100 (PU8)
(Q52) (Q95) (PU4) (PU3)
CHARGER +5V_RUN +5V_RUN_BKT_PWR +0.75V_DDR_VTT
+1.5V_MEM +1.05V_M
RUN_ON RUN_ON EN_1.5VALW 0.75V_VTT_ON EN_1.05VALW
C C
BKT_GPIO4 DDR_ON
TPA6040A (U28) SI4336DY (Q118) SI4336DY (Q56)
+VDDA +1.5V_RUN +1.05V_VCCP
RUN_ON/AUD_AMP_MUTE#
1.5V_RUN_ON 1.05V_RUN_ON
ALWON SN0608098 +3.3V_ALW
(PU2)
B B
SI345BVD STS11NF30L SI4336DY STS11NF30L
SI4336DY (Q48)
(Q55) (Q53) (Q54) (Q40)
+3.3V_M +3.3V_WLAN
+3.3V_SUS +3.3V_RUN +3.3V_LAN
AUX_EN_WOWL
M_ON SUS_ON 3.3V_RUN_ON AUX_ON
SI34536BDV SI3456BDV SI4336DY (Q89) SI3456BDV
MAX8794 (PU9) MAX8794 (Q31)
(Q92) (Q51) (PU12)
+3.3V_RUN_WWAN_PWR +1.8V_RUN +LCDVDD
+3.3V_RUN_BKT_PWR +3.3V_ALW_ICH +1.5V_ALW_HDA
3.3V_RUN_ON ICH_ALW 3.3V_RUN_ON 1.8V_RUN_ON EN_VDD ICH_ALW
BKT_GPIO3 BKT_GPIO15 BKT_GPIO2
ADP3207 (PU6)
A A
+VCC_CORE
ADP3419 (PU5)
DELL CONFIDENTIAL/PROPRIETARY
RUNPWROK Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Power Rails
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 4 of 49
5 4 3 2 1
5 4 3 2 1
2.2K 2.2K
2.2K +3.3V_ALW_ICH 2.2K +3.3V_ALW_M
C18 ICH_SMBCLK MEM_SDATA 202
2N7002
C15 ICH_SMBDATA MEM_SCLK 200 JDIMM SMBUS Address [A0]
2N7002
2.2K
ICH9-M 6
D
2.2K +3.3V_ALW_ICH D
5 On board SPD ROM SMBUS Address [TBD]
E18 AMT_SMBCLK
A24 AMT_SMBDAT
2.2K
93 94
2.2K +3.3V_ALW
6 DOCK_SMB_CLK 127
5 DOCK_SMB_DAT 129 DOCKING SMBUS Address [TBD]
2.2K
2.2K +3.3V_ALW
112 PBAT_SMBCLK 100 ohm 7
C C
111 PBAT_SMBDAT 6 BATT CONN SMBUS Address [16]
100 ohm 2.2K
2.2K +3.3V_ALW 2.2K +3.3V_RUN_BKT_PWR
10 ALS_SMBCLK CAPSW_ALS_SMBCLK 5
2N7002
9 ALS_SMBDAT CAPSW_ALS_SMBDAT 2 Ambient light sensor SMBUS Address [TBD]
2N7002
2.2K 11
12 CAP Switch Controller SMBUS Address [TBD]
2.2K +3.3V_ALW
100 BKT_SMBCLK 27
99 BKT_SMBDAT 29 BlackTop CONN SMBUS Address [TBD]
KBC 2.2K 2.2K
2.2K +3.3V_ALW 2.2K +3.3V_SUS
B
8 LCD_SMBCLK 24 B
EXP_SMBCLK 6
7 LCD_SMBDATA 23 JLVDS SMBUS Address [TBD]
MEC 5035 2N7002
EXP_SMBDATA 7 Express Card SMBUS Address [10H]
2N7002
2.2K
2.2K +3.3V_WLAN
2.2K +3.3V_ALW
98 CARD_SMBCLK
97 CARD_SMBDAT WLAN_SMBCLK 30
2N7002
WLAN_SMBDATA 32 WLAN SMBUS Address [TBD]
2N7002
2.2K +3.3V_RUN_WWAN_PWR
2.2K WWAN_SMBCLK 30
2N7002
WWAN_SMBDATA 32 WWAN SMBUS Address [TBD]
2.2K +3.3V_ALW 2.2K +3.3V_M 2N7002
13 CKG_SMBCLK CLK_SCLK 16
A
2N7002 A
12 CKG_SMBDAT CLK_SDATA 17 CLOCK GEN SMBUS Address [D2]
2N7002
DAI_SMBCLK 28
DELL CONFIDENTIAL/PROPRIETARY
9 10 2N7002
DAI_SMBDATA 27 DAI SMBUS Address [TBD]
CHARGER 2N7002 Compal Electronics, Inc.
Title
SMBUS Address [12] SMBus Topology
2.2K +3.3V_RUN_BKT_PWR Size Document Number Rev
WWW.AliSaler.Com
0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 5 of 49
5 4 3 2 1
5 4 3 2 1
+3.3V_M +CK_VDD_MAIN
L1
+3.3V_M
1 2 FSC FSB FSA CPU SRC PCI
2.2K_0402_5%~D
2.2K_0402_5%~D
BLM21AG601SN1D_0805~D
1
MHz MHz MHz
0.1U_0402_16V4Z~D
1 CLKSEL2 CLKSEL1 CLKSEL0
R1
R2
C1
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_6.3V6-M~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 1 1 1 1 1 1 0 0 0 266 100 33.3
1 1
C2
C3
C4
C5
C6
C7
C9
C10
6 1 CLK_SDATA 0 1 0 200 100 33.3
D
<26,34,46> CKG_SMBDAT
Q1A 2 2
2 2 2 2 2 2 * D
2N7002DW-7-F_SOT363-6~D 0 1 1 166 100 33.3
2
+3.3V_M
5
Q1B
2N7002DW-7-F_SOT363-6~D R12
3 4 CLK_SCLK 1 2 +CK_VDD_A
<26,34,46> CKG_SMBCLK
4.7U_0603_6.3V4Z~D
0.047U_0402_16V4Z~D
2.2_0603_5%~D
+3.3V_RUN
1 1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
C14
C15
U1
1 1 MINI2CLK_REQ# R6 1 2 10K_0402_5%~D
2 2
C12
C13
Place close to U1 pin 18 and 40 1 7 MINI1CLK_REQ# R5 1 2 10K_0402_5%~D
VDD_SRC VDD_A
49 VDD_SRC
2 2 EXPCLK_REQ# R10 10K_0402_5%~D
54 8 1 2
65
VDD_SRC
VDD_SRC
SLG8LP554BVTR VSS_A
CLK_3GPLLREQ# R7 1 2 10K_0402_5%~D
25 H_STP_PCI#
PCI_STP# H_STP_PCI# <24>
30 SATA_CLKREQ# R8 1 2 10K_0402_5%~D
VDD_PCI H_STP_CPU#
36 VDD_PCI CPU_STP# 24 H_STP_CPU# <24>
12 VDD_CPU
C16 11 CLK_MCH_BCLK
CPU_1 CLK_MCH_BCLK <10>
2 1 18 VDD_REF
10 CLK_MCH_BCLK#
CPU_1# CLK_MCH_BCLK# <10>
33P_0402_50V8J~D 40 VDD_48
1
Place crystal within CLK_CPU_BCLK
CPU_0 14 CLK_CPU_BCLK <7>
500 mils of CK505 Y6 CLK_XTAL_IN 20
C17 14.31818MHZ_20PF_1Y714318CE1B~D XTAL_IN CLK_CPU_BCLK#
13 CLK_CPU_BCLK# <7>
2
33P_0402_50V8J~D CPU_0#
C R19 CLK_XTAL_OUT C
2 1 1 2 0_0402_5%~D 19 XTAL_OUT
6 CLK_CPU_ITP
CPU_ITP/SRC_10 CLK_CPU_ITP <7>
CLK_ICH_48M R21 2 1 33_0402_5%~D FSA 41 5 CLK_CPU_ITP#
<24> CLK_ICH_48M USB_48MHz/FSLA CPU_ITP#/SRC_10# CLK_CPU_ITP# <7>
<8,10> CPU_MCH_BSEL0 CPU_MCH_BSEL0 R23 1 2 2.2K_0402_5%~D
<8,10> CPU_MCH_BSEL1 CPU_MCH_BSEL1 45 FSL_B/TEST_MODE CLK_PCIE_MINI2
SRC_9 3 CLK_PCIE_MINI2 <30>
<8,10> CPU_MCH_BSEL2 CPU_MCH_BSEL2 R25 1 2 10K_0402_5%~D FSC 23 REF_0/FSL_C/TEST_SEL CLK_PCIE_MINI2#
SRC_9# 2 CLK_PCIE_MINI2# <30>
CLK_PCI_5028 R27 2 1 33_0402_5%~D PCI_SIO 34 72 MINI2CLK_REQ#
<33> CLK_PCI_5028 PCICLK4/FCT_SEL CLKREQ_9# MINI2CLK_REQ# <30>
CLK_PCI_TPM R28 1 2 33_0402_5%~D PCI_TPM 33 70 CLK_PCIE_MINI1
<32> CLK_PCI_TPM PCICLK3 SRC_8 CLK_PCIE_MINI1 <30>
CLK_PCI_R5C833 R31 2 1 22_0402_5%~D PCI_PCM 32 69 CLK_PCIE_MINI1#
<29> CLK_PCI_R5C833 PCICLK2/TME SRC_8# CLK_PCIE_MINI1# <30>
CLK_PCI_DOCK R33 1 2 22_0402_5%~D
<31> CLK_PCI_DOCK
CLK_PCI_5035 R34 2 1 33_0402_5%~D PCI_EC 27 71 MINI1CLK_REQ#
<34> CLK_PCI_5035 PCICLK1 CLKREQ_8# MINI1CLK_REQ# <30>
66 CLK_PCIE_ICH
SRC_7 CLK_PCIE_ICH <24>
CLK_ICH_14M R35 1 2 22_0402_5%~D CLKREF 22
<24> CLK_ICH_14M REF_1
CLK_SIO_14M R37 1 2 22_0402_5%~D 67 CLK_PCIE_ICH#
<33> CLK_SIO_14M SRC_7# CLK_PCIE_ICH# <24>
MCH_DREFCLK R40 1 2 33_0402_5%~D DOT96 43 38
<10> MCH_DREFCLK DOT_96/27M CLKREQ_7#
MCH_DREFCLK# R41 1 2 33_0402_5%~D DOT96# 44 63
<10> MCH_DREFCLK# DOT_96#/27M_SS SRC_6
SRC_6# 64
CLK_PCI_ICH R44 2 1 33_0402_5%~D PCI_ICH 37
<22> CLK_PCI_ICH PCICLK_F0/ITP_EN
CLKREQ_6# 62
<24> CLK_PWRGD CLK_PWRGD 39 60
CKPWRGD/PD# SRC_5
B +3.3V_RUN 61 B
SRC_5#
9 NC
10K_0402_5%~D
CLKREQ_5# 29
2
TME PIN 32 58 CLK_PCIE_EXP
SRC_4 CLK_PCIE_EXP <35>
R45
CLK_SCLK 16 SMBCLK CLK_PCIE_EXP#
0 Overclocking enable SRC_4# 59 CLK_PCIE_EXP# <35>
1
1 Overclocking disable 57 EXPCLK_REQ#
PCI_PCM * CLK_SDATA 17 SMBDAT
CLKREQ_4#
CLK_MCH_3GPLL
EXPCLK_REQ# <35>
SRC_3 55 CLK_MCH_3GPLL <10>
4 56 CLK_MCH_3GPLL#
VSS_SRC SRC_3# CLK_MCH_3GPLL# <10>
+3.3V_RUN 15 28 CLK_3GPLLREQ#_R 1 2
VSS_CPU CLKREQ_3# CLK_3GPLLREQ# <10>
10K_0402_5%~D
21 52 R51
VSS_REF SRC_2
2
475_0402_1%~D
ITP_EN PIN 37 31 VSS_PCI SRC_2# 53
R50
0 Pin 5/6 as SRC_10 35 VSS_PCI CLKREQ_2# 26
1
1 Pin 5/6 as CPU_ITP 42 50 CLK_PCIE_SATA
PCI_ICH * VSS_48 SRC_1/SATA
CLK_PCIE_SATA#
CLK_PCIE_SATA <23>
68 VSS_SRC SRC_1#/SATA# 51 CLK_PCIE_SATA# <23>
46 SATA_CLKREQ#_R 1 R55 2 SATA_CLKREQ# <24>
CLKREQ_1# 475_0402_1%~D
73 THRM_PAD
47 DREF_SSCLK
LCD_CLK/SRC_0 DREF_SSCLK <10>
48 DREF_SSCLK#
LCD_CLK#/SRC_0# DREF_SSCLK# <10>
PCI_SIO
10K_0402_5%~D
A A
1
FCTSEL1 PIN43 PIN44 PIN47 PIN48 SLG8LP554BVTR_QFN72_10X10~D
R58
0=UMA DOT96T DOT96C 96/100M_T 96/100M_C DELL CONFIDENTIAL/PROPRIETARY
*
2
1=DIS 27M_out 27M SSout SRCT0 SRCC0 Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Clock GEN. with internal terminations
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 6 of 49
5 4 3 2 1
5 4 3 2 1
+1.05V_VCCP
<10> H_A#[3..35]
U62A 1 U62D
H_A#3 P2 M4 H_ADS# C18 B42 AM36
H_A#4 A[3]# ADS# H_BNR# H_ADS# <10> 0.1U_0402_16V4Z~D VSS[001] VSS[082]
V4 A[4]# BNR# J5 H_BNR# <10> F44 VSS[002] VSS[083] AR35
H_A#5 W1 L5 H_BPRI# D44 AU35
A[5]# BPRI# H_BPRI# <10> 2 VSS[003] VSS[084]
ADDR GROUP 0
H_A#6 T4 D42 AV34
H_A#7 A[6]# H_DEFER# VSS[004] VSS[085]
AA1 A[7]# DEFER# N5 H_DEFER# <10> F42 VSS[005] VSS[086] AW35
H_A#8 AB4 F38 H_DRD Y# H42 AW33
A[8]# DRDY# H_DRDY# <10> VSS[006] VSS[087]
H_A#9 T2 J1 H_DBSY# K42 AY34
D A[9]# DBSY# H_DBSY# <10> VSS[007] VSS[088] D
H_A#10 AC5 Place close to JITP within 100 mil M42 AT36
H_A#11 A[10]# H_BR0# VSS[008] VSS[089]
CONTROL
AD2 A[11]# BR0# M2 H_BR0# <10> P42 VSS[009] VSS[090] AV36
H_A#12 AD4 T42 BA33
H_A#13 A[12]# H_IERR# R59 VSS[010] VSS[091]
AA5 A[13]# IERR# B40 2 1 56_0402_5%~D +1.05V_VCCP V42 VSS[011] VSS[092] BC33
H_A#14 AE5 D8 H_INIT# Y42 BB36
A[14]# INIT# H_INIT# <23> VSS[012] VSS[093]
H_A#15
29
AB2 A[15]# AB42 VSS[013] VSS[094] BD36
H_A#16 AC1 N1 H_LOCK# +1.05V_VCCP JITP AD42 C27
A[16]# LOCK# H_LOCK# <10> VSS[014] VSS[095]
H_ADSTB#0 Y4 AF42 C29
GND6
<10> H_ADSTB#0 ADSTB[0]# VSS[015] VSS[096]
G5 H_RESET# 28 AH42 C31
RESET# H_RESET# <10> VTT1 VSS[016] VSS[097]
H_REQ#0 R1 K2 H_RS#0 27 AK42 E29
<10> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <10> VTT0 VSS[017] VSS[098]
H_REQ#1 R5 H4 H_RS#1 26 AM42 E27
<10> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <10> VTAP VSS[018] VSS[099]
H_REQ#2 U1 K4 H_RS#2 ITP_DBRESET# 25 AP42 G29
<10> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <10> DBR# VSS[019] VSS[100]
H_REQ#3 P4 L1 H_TRDY# 24 AY44 G27
<10> H_REQ#3 REQ[3]# TRDY# H_TRDY# <10> DBA# VSS[020] VSS[101]
H_REQ#4 W5 ITP_BPM#0 23 AV44 E31
<10> H_REQ#4 REQ[4]# BPM0# VSS[021] VSS[102]
H2 H_HIT# 22 AT42 G31
HIT# H_HIT# <10> GND5 VSS[022] VSS[103]
H_A#17 AN1 F2 H_HITM# ITP_BPM#1 21 AV42 J29
A[17]# HITM# H_HITM# <10> BPM1# VSS[023] VSS[104]
H_A#18 AK4 20 AY42 J27
A[18]# GND4 VSS[024] VSS[105]
ADDR GROUP 1
H_A#19 AG1 AY8 ITP_BPM#0 ITP_BPM#2 19 BA43 L29
H_A#20 A[19]# BPM[0]# ITP_BPM#1 R1077 BPM2# VSS[025] VSS[106]
AT4 A[20]# BPM[1]# BA7 18 GND3 BB42 VSS[026] VSS[107] L27
H_A#21 ITP_BPM#2 0_0402_5%~D ITP_BPM_R#3
XDP/ITP SIGNALS
AK2 A[21]# BPM[2]# BA5 17 BPM3# C39 VSS[027] VSS[108] N29
H_A#22 AT2 AY2 ITP_BPM#3 1 2 ITP_BPM_R#3 16 E39 N27
H_A#23 A[22]# BPM[3]# ITP_BPM#4 ITP_BPM#4 GND2 VSS[028] VSS[109]
AH2 A[23]# PRDY# AV10 15 BPM4# G37 VSS[029] VSS[110] J31
H_A#24 AF4 AV2 ITP_BPM#5 1 2 ITP_BPM_R#5 +1.05V_VCCP 14 H38 L31
H_A#25 A[24]# PREQ# ITP_TCK R60 ITP_BPM_R#5 GND1 VSS[030] VSS[111]
AJ5 A[25]# TCK AV4 13 BPM5# J39 VSS[031] VSS[112] N31
H_A#26 AH4 AW7 ITP_TDI R1078 H_RESET# 1 2 12 L39 R29
A[26]# TDI RESET# VSS[032] VSS[113]
1
H_A#27 AM4 AU1 ITP_TDO 0_0402_5%~D ITP_TCK 11 M38 R27
H_A#28 A[27]# TDO ITP_TMS 1K_0402_5%~D FBO VSS[033] VSS[114]
AP4 A[28]# TMS AW5 10 GND0 N39 VSS[034] VSS[115] U29
H_A#29 AR5 AV8 ITP_TRST# R61 CLK_CPU_ITP 9 R39 U27
A[29]# TRST# <6> CLK_CPU_ITP BCLKP VSS[035] VSS[116]
H_A#30 AJ1 J7 ITP_DBRESET# ITP_DBRESET# <24> 56_0402_5%~D CLK_CPU_ITP# 8 T38 R31
A[30]# DBR# <6> CLK_CPU_ITP# BCLKN VSS[036] VSS[117]
H_A#31 AL1 ITP_TDO 7 U39 U31
2
H_A#32 A[31]# EC_CPU_PROCHOT# TDO VSS[037] VSS[118]
AM2 A[32]# 6 NC2 W39 VSS[038] VSS[119] W29
H_A#33 AU5 THERMAL ITP_TCK 5 Y38 W27
C H_A#34 A[33]# TCK VSS[039] VSS[120] C
AP2 A[34]# 4 NC1 AA39 VSS[040] VSS[121] W31
H_A#35 AR1 D38 H_THERMDA ITP_TRST# 3 AC39 AA29
A[35]# PROCHOT# H_THERMDA <19> TRST# VSS[041] VSS[122]
H_ADSTB#1 AN5 BB34 2 ITP_TMS 2 AD38 AA27
<10> H_ADSTB#1 ADSTB[1]# THERMDA TMS VSS[042] VSS[123]
GND7
BD34 C19 ITP_TDI 1 AE39 AC29
H_A20M# THERMDC @ 100P_0402_50V8K~D TDI VSS[043] VSS[124]
<23> H_A20M# C7 A20M# AG39 VSS[044] VSS[125] AC27
H_FERR# D4 B10 AH38 AA31
<23> H_FERR# FERR# THERMTRIP# 1 VSS[045] VSS[126]
ICH
H_IGNNE# F10 H_THERMDC @ MOLEX_52435-2891_28P~D AJ39 AC31
<23> H_IGNNE#
30
IGNNE# H_THERMDC <19> VSS[046] VSS[127]
AL39 VSS[047] VSS[128] AE29
H_STPCLK# F8 H_THERMTRIP# AM38 AE27
<23> H_STPCLK# STPCLK# H_THERMTRIP# <19> VSS[048] VSS[129]
H_INTR C9 H CLK AN39 AG29
<23> H_INTR LINT0 VSS[049] VSS[130]
H_NMI C5 A35 CLK_CPU_BCLK AR39 AG27
<23> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <6> VSS[050] VSS[131]
H_SMI# E5 C35 CLK_CPU_BCLK# AR37 AJ29
<23> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <6> VSS[051] VSS[132]
AT38 VSS[052] VSS[133] AJ27
V2 RSVD01 AU39 VSS[053] VSS[134] AE31
Y2 RSVD02 AU37 VSS[054] VSS[135] AG31
AG5 RSVD03 AW39 VSS[055] VSS[136] AJ31
RESERVED
AL5 H_THERMDA, H_THERMDC routing together, +3.3V_ALW_ICH AW37 AL29
RSVD04 VSS[056] VSS[137]
J9 RSVD05 BA39 VSS[057] VSS[138] AL27
F4 +1.05V_VCCP Trace width / Spacing = 10 / 10 mil R62 BC41 AN29
RSVD06 R63 150_0402_5%~D VSS[058] VSS[139]
H8 RSVD07 BD40 VSS[059] VSS[140] AN27
56_0402_5%~D 1 2 ITP_DBRESET# BD38 AL31
H_THERMTRIP# VSS[060] VSS[141]
1 2 B36 VSS[061] VSS[142] AN31
H34 VSS[062] VSS[143] AR29
D36 VSS[063] VSS[144] AR27
Place close to JITP within 1ns = 5000 mil K34 VSS[064] VSS[145] AR31
M34 VSS[065] VSS[146] AU29
PENRYN SFF_UFCBGA956~D +1.05V_VCCP M36 AU27
VSS[066] VSS[147]
P34 VSS[067] VSS[148] AW29
R64 T34 AW27
51_0402_5%~D VSS[068] VSS[149]
V34 VSS[069] VSS[150] AU31
1 2 ITP_BPM#5 T36 AW31
VSS[070] VSS[151]
Y34 VSS[071] VSS[152] BA29
B B
AB34 VSS[072] VSS[153] BA27
+1.05V_VCCP
Place close to CPU within 200 mil AD34 VSS[073] VSS[154] BC29
Y36 VSS[074] VSS[155] BC27
R65 AD36 BA31
@ 51_0402_5%~D VSS[075] VSS[156]
AF34 VSS[076] VSS[157] BC31
1 2 H_RESET# AH34 C21
+1.05V_VCCP VSS[077] VSS[158]
AH36 VSS[078] VSS[159] C23
R66 AK34 C25
R67 51_0402_5%~D VSS[079] VSS[160]
AM34 VSS[080] VSS[161] E25
51_0402_5%~D 1 2 ITP_TDO AP34 E23
ITP_TDI VSS[081] VSS[162]
1 2 VSS[163] E21
R68
R69 51_0402_5%~D
51_0402_5%~D 1 2 ITP_TMS PENRYN SFF_UFCBGA956~D
Layout Note: for ITP700Flex debug port with a XDP based Run Control Tools 1 2 ITP_TRST#
R70
51_0402_5%~D
ITP_BPM#[0..5], TCK, and TMS routings 1 2 ITP_TCK
must be a maximum of 1.5ns = 7500 mil Place close to CPU within 200ps = 1000 mil
Place close to JITP within 200ps = 1000 mil
ITP_BPM#[0..5], and TCK to FBO routings
must be length matched to within 50ps = 250 mil
A
Place R70 close to JITP pin 5 A
TCK to FBO routing should refer to debug port design guide
H_RESET# should be routed from GMCH with split to ITP conn. Refer to DG page #56
DELL CONFIDENTIAL/PROPRIETARY
Depop JITP, C18, R68, R70, R64, R67, R69
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
when JIP connector is depopulated BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Penryn SFF ULV Processor(1/3)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 7 of 49
5 4 3 2 1
5 4 3 2 1
<10> H_D#[0..63]
+VCC_CORE +VCC_CORE
U62B U62C
H_D#0 F40 AP44 H_D#32 F32 AB28
H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
G43 D[1]# D[33]# AR43 G33 VCC[002] VCC[069] AD30
H_D#2 E43 AH40 H_D#34 H32 AD28
H_D#3 D[2]# D[34]# H_D#35 VCC[003] VCC[070]
J43 D[3]# D[35]# AF40 J33 VCC[004] VCC[071] Y26
DATA GROUP 0
D H_D#4 H_D#36 D
H40 D[4]# D[36]# AJ43 K32 VCC[005] VCC[072] AB26
H_D#5 H44 AG41 H_D#37 L33 AD26
H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
G39 AF44 M32 AF30
DATA GROUP 2
H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
E41 D[7]# D[39]# AH44 N33 VCC[008] VCC[075] AF28
H_D#8 L41 AM44 H_D#40 P32 AH30
H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
K44 D[9]# D[41]# AN43 R33 VCC[010] VCC[077] AH28
H_D#10 N41 AM40 H_D#42 T32 AF26
H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
T40 D[11]# D[43]# AK40 U33 VCC[012] VCC[079] AH26
H_D#12 M40 AG43 H_D#44 V32 AK30
H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
G41 D[13]# D[45]# AP40 W33 VCC[014] VCC[081] AK28
H_D#14 M44 AN41 H_D#46 Y32 AM30
H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
L43 D[15]# D[47]# AL41 AA33 VCC[016] VCC[083] AM28
<10> H_DSTBN#0 H_DSTBN#0 K40 AK44 H_DSTBN#2 H_DSTBN#2 <10> AB32 AP30
H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[017] VCC[084]
<10> H_DSTBP#0 J41 DSTBP[0]# DSTBP[2]# AL43 H_DSTBP#2 <10> AC33 VCC[018] VCC[085] AP28
H_DINV#0 P40 AJ41 H_DINV#2 AD32 AK26
<10> H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 <10> VCC[019] VCC[086]
AE33 VCC[020] VCC[087] AM26
AF32 VCC[021] VCC[088] AP26
H_D#16 P44 AV38 H_D#48 AG33 AT30
H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
V40 D[17]# D[49]# AT44 AH32 VCC[023] VCC[090] AT28
H_D#18 V44 AV40 H_D#50 AJ33 AV30
H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
AB44 D[19]# D[51]# AU41 AK32 VCC[025] VCC[092] AV28
H_D#20 R41 AW41 H_D#52 AL33 AY30
D[20]# D[52]# VCC[026] VCC[093]
DATA GROUP 1
H_D#21 W41 AR41 H_D#53 AM32 AY28
H_D#22 D[21]# D[53]# H_D#54 VCC[027] VCC[094]
N43 BA37 AN33 AT26
DATA GROUP 3
H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
U41 D[23]# D[55]# BB38 AP32 VCC[029] VCC[096] AV26
H_D#24 AA41 AY36 H_D#56 AR33 AY26
H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
AB40 D[25]# D[57]# AT40 AT34 VCC[031] VCC[098] BB30
H_D#26 AD40 BC35 H_D#58 AT32 BB28
H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099]
AC41 D[27]# D[59]# BC39 AU33 VCC[033] VCC[100] BD30
H_D#28 AA43 BA41 H_D#60 AV32
H_D#29 D[28]# D[60]# H_D#61 VCC[034]
Y40 D[29]# D[61]# BB40 AY32 VCC[035] VCCP_001 J11 +1.05V_VCCP
H_D#30 Y44 BA35 H_D#62 BB32 E11
D[30]# D[62]# VCC[036] VCCP_002
220U_D2_4VY_R15M~D
C H_D#31 H_D#63 C
T44 D[31]# D[63]# AU43 BD32 VCC[037] VCCP_003 G11
<10> H_DSTBN#1 H_DSTBN#1 U43 AY40 H_DSTBN#3 H_DSTBN#3 <10> B28 J37 1
H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 VCC[038] VCCP_004
<10> H_DSTBP#1 W43 DSTBP[1]# DSTBP[3]# AY38 H_DSTBP#3 <10> B30 VCC[039] VCCP_005 K38
C20
H_DINV#1 R43 BC37 H_DINV#3 B26 L37 +
<10> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <10>
D28
VCC[040]
VCC[041]
VCCP_006
VCCP_007 N37 CRB is 270uF
+V_CPU_GTLREF AW43 AE43 COMP0 D30 P38
TEST1 GTLREF COMP[0] COMP1 VCC[042] VCCP_008 2
E37 TEST1 MISC COMP[1] AD44 F30 VCC[043] VCCP_009 R37
TEST2 D40 AE1 COMP2 F28 U37
TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP_010
C43 TEST3 COMP[3] AF2 H30 VCC[045] VCCP_011 V38
TEST4 AE41 H28 W37
TEST4 VCC[046] VCCP_012
54.9_0402_1%~D
27.4_0402_1%~D
54.9_0402_1%~D
27.4_0402_1%~D
TEST5 AY10 G7 H_DPRSTP# D26 AA37
TEST5 DPRSTP# H_DPRSTP# <10,23,43> VCC[047] VCCP_013
1
T1 TEST6 AC43 B8 H_DPSLP# F26 AB38
TEST6 DPSLP# H_DPSLP# <23> VCC[048] VCCP_014
C41 H_DPWR# H26 AC37
DPWR# H_DPWR# <10> VCC[049] VCCP_015
R71
R72
R73
R74
CPU_MCH_BSEL0 A37 E7 H_PW RGOOD K30 AE37
<6,10> CPU_MCH_BSEL0 CPU_MCH_BSEL1 C37 BSEL[0] PWRGOOD H_CPUSLP# H_PWRGOOD <23> VCC[050] VCCP_016
<6,10> CPU_MCH_BSEL1 BSEL[1] SLP# D10 H_CPUSLP# <10> K28 VCC[051]
CPU_MCH_BSEL2 B38 BD10 H_PSI# M30 B34 +1.5V_RUN
H_PSI# <43>
2
<6,10> CPU_MCH_BSEL2 BSEL[2] PSI# VCC[052] VCCA[01]
M28 VCC[053] VCCA[02] D34
0.01U_0402_16V7K~D
10U_0805_10V4Z~D
PENRYN SFF_UFCBGA956~D K26 VCC[054] VID0
M26 VCC[055] VID[0] BD8 VID0 <43>
P30 BC7 VID1 1 1
VCC[056] VID[1] VID1 <43>
C21
C22
Resistor placed within 0.5" of CPU P28 BB10 VID2
VCC[057] VID[2] VID2 <43>
T30 BB8 VID3
pin.Trace should be at least 25 VCC[058] VID[3] VID3 <43>
T28 BC5 VID4
VCC[059] VID[4] VID4 <43> 2 2
V30 BB4 VID5
mils away from any other toggling VCC[060] VID[5] VID6
VID5 <43>
V28 VCC[061] VID[6] AY4 VID6 <43>
FSB BCLK BSEL2 BSEL1 BSEL0 signal. COMP0, COMP2 trace P26 VCC[062]
TEST3 T26
T2
TEST5
should be 27.4 ohm. COMP1, V26
VCC[063]
BD12 VCCSENSE
T3 VCC[064] VCCSENSE VCCSENSE <43>
667 166 0 1 1 COMP3 should be 55ohm. Y30 VCC[065]
Y28 VCC[066]
Route TEST3 and TEST5 signals AB30 BC13 VSSSENSE
VCC[067] VSSSENSE VSSSENSE <43>
800 200 0 1 0
B * through a ground referenced Z0 = 55ohm PENRYN SFF_UFCBGA956~D B
trace that ends in a via that is near a GND via.
1067 266 0 0 0
Length match within 25 mils, Z0=27.4 ohm
+1.05V_VCCP TEST1
TEST2
TEST4 Place R78 and R81 close to CPU within 1000 mil
1
@ 0.1U_0402_10V7K~D
R75
+V_CPU_GTLREF +VCC_CORE
@ 1K_0402_5%~D
@ 1K_0402_5%~D
1K_0402_1%~D
2
2
2
R78 R79
R76
R77
C23
1 2 VCCSENSE 1 2
1
1 100_0402_1%~D @ 27.4_0402_1%~D
1
R80
2K_0402_1%~D R81 Reserve for testing only
1 2 VSSSENSE
2
Place C23 close to the 100_0402_1%~D
Layout close CPU PIN AW43 CPU_TEST4 pin. Make sure
CPU_TEST4 routing is Route VCCSENSE and VSSSENSE trace at 27.4 ohms with 7 mil spacing
Zo = 55 ohm, 0.5 inch (max) reference to GND and away
from other noisy signal.
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Penryn SFF ULV Processor(2/3)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 8 of 49
5 4 3 2 1
5 4 3 2 1
U62F U62E
+VCC_CORE BD28 VCC_101 VCCP_021 AL37 +1.05V_VCCP G25 VSS_164 VSS_280 AA15
BB26 VCC_102 VCCP_022 AN37 G23 VSS_165 VSS_281 AC15
BD26 VCC_103 VCCP_023 AP38 G21 VSS_166 VSS_282 Y10
B22 VCC_104 VCCP_024 B32 J25 VSS_167 VSS_283 AD10
B24 VCC_105 VCCP_025 C33 J23 VSS_168 VSS_284 AH12
D22 VCC_106 VCCP_026 D32 J21 VSS_169 VSS_285 AE15
D24 VCC_107 VCCP_027 E35 L25 VSS_170 VSS_286 AG15
F24 VCC_108 VCCP_028 E33 L23 VSS_171 VSS_287 AJ15
F22 VCC_109 VCCP_029 F34 L21 VSS_172 VSS_288 AH10
H24 VCC_110 VCCP_030 G35 N25 VSS_173 VSS_289 AM12
H22 VCC_111 VCCP_031 F36 N23 VSS_174 VSS_290 AL15
K24 VCC_112 VCCP_032 H36 N21 VSS_175 VSS_291 AN15
K22 VCC_113 VCCP_033 J35 R25 VSS_176 VSS_292 AR15
M24 VCC_114 VCCP_034 L35 R23 VSS_177 VSS_293 AM10
D M22 VCC_115 VCCP_035 N35 R21 VSS_178 VSS_294 AT12 D
P24 VCC_116 VCCP_036 K36 U25 VSS_179 VSS_295 AV12
+VCC_CORE
P22 VCC_117 VCCP_037 R35 U23 VSS_180 VSS_296 AW13
T24 VCC_118 VCCP_038 U35 U21 VSS_181 VSS_297 AW11
T22 VCC_119 VCCP_039 P36 W25 VSS_182 VSS_298 AY12
V24 VCC_120 VCCP_040 V36 W23 VSS_183 VSS_299 AU15 1 1 1 1 1 1 1 1
V22 W35 W21 AW15 C1312 C1313 C1314 C1315 C1316 C1317 C1318 C1319
VCC_121 VCCP_041 VSS_184 VSS_300
Y24 VCC_122 VCCP_042 AA35 AA25 VSS_185 VSS_301 AT10
Y22 AC35 AA23 BA13 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
VCC_123 VCCP_043 VSS_186 VSS_302 2 2 2 2 2 2 2 2
AB24 VCC_124 VCCP_044 AB36 AA21 VSS_187 VSS_303 BA11
AB22 VCC_125 VCCP_045 AE35 AC25 VSS_188 VSS_304 BB12
AD24 VCC_126 VCCP_046 AG35 AC23 VSS_189 VSS_305 BC11
+VCC_CORE
AD22 VCC_127 VCCP_047 AJ35 AC21 VSS_190 VSS_306 BA15
AF24 VCC_128 VCCP_048 AF36 AE25 VSS_191 VSS_307 BC15
AF22 VCC_129 VCCP_049 AL35 AE23 VSS_192 VSS_308 B6
AH24 VCC_130 VCCP_050 AN35 AE21 VSS_193 VSS_309 D6 1 1 1 1 1 1 1 1
AH22 AK36 AG25 E9 C1320 C1321 C1322 C1323 C1324 C1325 C1326 C1327
VCC_131 VCCP_051 VSS_194 VSS_310
AK24 VCC_132 VCCP_052 AP36 AG23 VSS_195 VSS_311 F6
AK22 B12 AG21 G9 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
VCC_133 VCCP_053 VSS_196 VSS_312 2 2 2 2 2 2 2 2
AM24 VCC_134 VCCP_054 B14 AJ25 VSS_197 VSS_313 H6
AM22 VCC_135 VCCP_055 C13 AJ23 VSS_198 VSS_314 K8
AP24 VCC_136 VCCP_056 D12 AJ21 VSS_199 VSS_315 K6
+VCC_CORE
AP22 VCC_137 VCCP_057 D14 AL25 VSS_200 VSS_316 M8
AT24 VCC_138 VCCP_058 E13 AL23 VSS_201 VSS_317 M6
AT22 VCC_139 VCCP_059 F14 AL21 VSS_202 VSS_318 P8
AV24 VCC_140 VCCP_060 F12 AN25 VSS_203 VSS_319 P6 1 1 1 1 1 1 1 1
AV22 G13 AN23 T8 C1328 C1329 C1335 C1336 C1342 C1343 C1344 C1345
VCC_141 VCCP_061 VSS_204 VSS_320
AY24 VCC_142 VCCP_062 H14 AN21 VSS_205 VSS_321 T6
AY22 H12 AR25 V8 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D 10U_0805_4VAM~D
VCC_143 VCCP_063 VSS_206 VSS_322 2 2 2 2 2 2 2 2
BB24 VCC_144 VCCP_064 J13 AR23 VSS_207 VSS_323 V6
BB22 VCC_145 VCCP_065 K14 AR21 VSS_208 VSS_324 U5
BD24 VCC_146 VCCP_066 K12 AU25 VSS_209 VSS_325 Y8
BD22 VCC_147 VCCP_067 L13 AU23 VSS_210 VSS_326 Y6
C B16 L11 AU21 AB8 C
VCC_148 VCCP_068 VSS_211 VSS_327
B18 VCC_149 VCCP_069 M14 AW25 VSS_212 VSS_328 AB6
B20 VCC_150 VCCP_070 N13 AW23 VSS_213 VSS_329 AD8
D16 VCC_151 VCCP_071 N11 AW21 VSS_214 VSS_330 AD6
D18 VCC_152 VCCP_072 K10 BA25 VSS_215 VSS_331 AF8
F18 VCC_153 VCCP_073 P14 BA23 VSS_216 VSS_332 AF6
F16 VCC_154 VCCP_074 P12 BA21 VSS_217 VSS_333 AH8
H18 VCC_155 VCCP_075 R13 BC25 VSS_218 VSS_334 AH6
H16 VCC_156 VCCP_076 R11 BC23 VSS_219 VSS_335 AK8
D20 VCC_157 VCCP_077 T14 BC21 VSS_220 VSS_336 AK6
F20 VCC_158 VCCP_078 U13 C17 VSS_221 VSS_337 AM8
+VCC_CORE
H20 VCC_159 VCCP_079 U11 C19 VSS_222 VSS_338 AM6
K18 VCC_160 VCCP_080 V14 E19 VSS_223 VSS_339 AP8
K16 VCC_161 VCCP_081 V12 E17 VSS_224 VSS_340 AP6
M18 VCC_162 VCCP_082 W13 G19 VSS_225 VSS_341 AT8
470U_X_2VM_R6M~D
470U_X_2VM_R6M~D
470U_X_2VM_R6M~D
M16 VCC_163 VCCP_083 W11 G17 VSS_226 VSS_342 AT6
K20 VCC_164 VCCP_084 P10 J19 VSS_227 VSS_343 AU9 1 1 1
M20 VCC_165 VCCP_085 V10 J17 VSS_228 VSS_344 AV6
C1330
C1331
C1332
P18 Y14 L19 AU7 + + +
VCC_166 VCCP_086 VSS_229 VSS_345
P16 VCC_167 VCCP_087 AA13 L17 VSS_230 VSS_346 AW9
T18 VCC_168 VCCP_088 AA11 N19 VSS_231 VSS_347 AY6
2 2 2
T16 VCC_169 VCCP_089 AB14 N17 VSS_232 VSS_348 BA9
V18 VCC_170 VCCP_090 AB12 R19 VSS_233 VSS_349 BB6
V16 VCC_171 VCCP_091 AC13 R17 VSS_234 VSS_350 BC9
P20 VCC_172 VCCP_092 AC11 U19 VSS_235 VSS_351 BD6
T20 VCC_173 VCCP_093 AD14 U17 VSS_236 VSS_352 B4
V20 VCC_174 VCCP_094 AB10 W19 VSS_237 VSS_353 C3
Y18 VCC_175 VCCP_095 AE13 W17 VSS_238 VSS_354 E3
Y16 VCC_176 VCCP_096 AE11 AA19 VSS_239 VSS_355 G3
AB18 VCC_177 VCCP_097 AF14 AA17 VSS_240 VSS_356 J3
AB16 VCC_178 VCCP_098 AF12 AC19 VSS_241 VSS_357 L3
AD18 VCC_179 VCCP_099 AG13 AC17 VSS_242 VSS_358 N3
AD16 VCC_180 VCCP_100 AG11 AE19 VSS_243 VSS_359 R3
B B
Y20 VCC_181 VCCP_101 AH14 AE17 VSS_244 VSS_360 U3
AB20 VCC_182 VCCP_102 AJ13 AG19 VSS_245 VSS_361 W3
AD20 VCC_183 VCCP_103 AJ11 AG17 VSS_246 VSS_362 AA3
AF18 VCC_184 VCCP_104 AF10 AJ19 VSS_247 VSS_363 AC3
AF16 VCC_185 VCCP_105 AK14 AJ17 VSS_248 VSS_364 AE3 Place these inside cavity on L8(North side Secondary)
AH18 VCC_186 VCCP_106 AK12 AL19 VSS_249 VSS_365 AG3
AH16 VCC_187 VCCP_107 AL13 AL17 VSS_250 VSS_366 AJ3
AF20 VCC_188 VCCP_108 AL11 AN19 VSS_251 VSS_367 AL3
AH20 AN13 AN17 AN3 +1.05V_VCCP
VCC_189 VCCP_109 VSS_252 VSS_368
AK18 VCC_190 VCCP_110 AN11 AR19 VSS_253 VSS_369 AR3
AK16 VCC_191 VCCP_111 AP12 AR17 VSS_254 VSS_370 AU3
AM18 VCC_192 VCCP_112 AR13 AU19 VSS_255 VSS_371 AW3
AM16 VCC_193 VCCP_113 AR11 AU17 VSS_256 VSS_372 BA3 1 1 1 1 1 1
AP18 AK10 AW19 BC3 C25 C26 C27 C28 C29 C30
VCC_194 VCCP_114 VSS_257 VSS_373 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D 0.1U_0402_10V7K~D
AP16 VCC_195 VCCP_115 AP10 AW17 VSS_258 VSS_374 D2
AK20 VCC_196 VCCP_116 AU13 BA19 VSS_259 VSS_375 E1
2 2 2 2 2 2
AM20 VCC_197 VCCP_117 AU11 BA17 VSS_260 VSS_376 G1
AP20 VCC_198 VCCP_118 L9 BC19 VSS_261 VSS_377 AW1
AT18 VCC_199 VCCP_119 L7 BC17 VSS_262 VSS_378 BA1
AT16 VCC_200 VCCP_120 N9 C11 VSS_263 VSS_379 BB2
AV18 VCC_201 VCCP_121 N7 C15 VSS_264 VSS_380 A41
AV16 VCC_202 VCCP_122 R9 E15 VSS_265 VSS_381 A39
AY18 VCC_203 VCCP_123 R7 G15 VSS_266 VSS_382 A29
AY16 VCC_204 VCCP_124 U9 H10 VSS_267 VSS_383 A27
AT20 VCC_205 VCCP_125 U7 M12 VSS_268 VSS_384 A31
AV20 VCC_206 VCCP_126 W9 J15 VSS_269 VSS_385 A25
AY20 VCC_207 VCCP_127 W7 L15 VSS_270 VSS_386 A23
BB18 VCC_208 VCCP_128 AA9 N15 VSS_271 VSS_387 A21
BB16 VCC_209 VCCP_129 AA7 M10 VSS_272 VSS_388 A19
BD18 VCC_210 VCCP_130 AC9 T12 VSS_273 VSS_389 A17
BD16 VCC_211 VCCP_131 AC7 R15 VSS_274 VSS_390 A11
BB20 VCC_212 VCCP_132 AE9 U15 VSS_275 VSS_391 A15
A BD20 VCC_213 VCCP_133 AE7 W15 VSS_276 VSS_392 A7 A
AM14 VCC_214 VCCP_134 AG9 T10 VSS_277 VSS_393 A5
AP14 VCC_215 VCCP_135 AG7 Y12 VSS_278 VSS_394 A9
AT14 VCC_216 VCCP_136 AJ9 AD12 VSS_279 VSS_395 BD4
AV14 VCC_217 VCCP_137 AJ7
AY14 AL9
BB14
VCC_218
VCC_219
VCCP_138
VCCP_139 AL7 PENRYN SFF_UFCBGA956~D DELL CONFIDENTIAL/PROPRIETARY
BD14 VCC_220 VCCP_140 AN9
AF38
VCCP_141 AN7
AR9
Compal Electronics, Inc.
+1.05V_VCCP VCCP_017 VCCP_142 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
AG37 VCCP_018 VCCP_143 AR7
AJ37 A33 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
AK38
VCCP_019
VCCP_020
VCCP_144
VCCP_145 A13 BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Penryn SFF ULV Processor(3/3)
WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
PENRYN SFF_UFCBGA956~D LA-4291P
Date: Friday, December 07, 2007 Sheet 9 of 49
5 4 3 2 1
5 4 3 2 1
U78B
H_A#[3..35] <7>
U78A J43 TP_MCH_RSVD1 T4
<8> H_D#[0..63] RSVD1
H_A#3 M_CLK_DDR0 TP_MCH_RSVD2
DDR CLK/ CONTROL/COMPENSATION
H_A#_3 L15 <16,17> M_CLK_DDR0 BB32 SA_CK_0 RSVD2 L43 T5
H_D#0 J7 B14 H_A#4 M_CLK_DDR1 BA25 J41 TP_MCH_RSVD3 T7
H_D#_0 H_A#_4 T6 SA_CK_1 RSVD3
H_D#1 H6 C15 H_A#5 M_CLK_DDR2 BA33 L41 TP_MCH_RSVD4 T8
H_D#_1 H_A#_5 <18> M_CLK_DDR2 SB_CK_0 RSVD4
H_D#2 L11 D12 H_A#6 M_CLK_DDR3 BA23 AN11 TP_MCH_RSVD5 T9
H_D#_2 H_A#_6 <18> M_CLK_DDR3 SB_CK_1 RSVD5
H_D#3 J3 F14 H_A#7 AM10 TP_MCH_RSVD6 T10
H_D#4 H_D#_3 H_A#_7 H_A#8 M_CLK_DDR#0 RSVD6 TP_MCH_RSVD7
H4 H_D#_4 H_A#_8 G17 <16,17> M_CLK_DDR#0 BA31 SA_CK#_0 RSVD7 AK10 T11
H_D#5 G3 B12 H_A#9 M_CLK_DDR#1 BC25 AL11 TP_MCH_RSVD8 T13
H_D#_5 H_A#_9 T12 SA_CK#_1 RSVD8
H_D#6 K10 J15 H_A#10 M_CLK_DDR#2 BC33 F12 TP_MCH_RSVD9 T14
H_D#_6 H_A#_10 <18> M_CLK_DDR#2 SB_CK#_0 RSVD9
RSVD
H_D#7 K12 D16 H_A#11 M_CLK_DDR#3 BB24
H_D#_7 H_A#_11 <18> M_CLK_DDR#3 SB_CK#_1
H_D#8 L1 C17 H_A#12
H_D#9 H_D#_8 H_A#_12 H_A#13 DDR_CKE0
M10 H_D#_9 H_A#_13 D14 <16,17> DDR_CKE0 BC35 SA_CKE_0
H_D#10 M6 K16 H_A#14 DDR_CKE1 BE33
H_D#_10 H_A#_14 T15 SA_CKE_1
D H_D#11 N11 F16 H_A#15 DDR_CKE2_DIMM BE37 C27 TP_MCH_RSVD14 T16 D
H_D#_11 H_A#_15 <18> DDR_CKE2_DIMM SB_CKE_0 RSVD14
H_D#12 L7 B16 H_A#16 DDR_CKE3_DIMM BC37 D30 TP_MCH_RSVD15 T17
H_D#_12 H_A#_16 <18> DDR_CKE3_DIMM SB_CKE_1 RSVD15
H_D#13 K6 C21 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18 DDR_CS#0 TP_MCH_RSVD17
M4 H_D#_14 H_A#_18 D18 <16,17> DDR_CS#0 BK18 SA_CS#_0 RSVD17 J9 T18
H_D#15 K4 J19 H_A#19 DDR_CS#1 BK16
H_D#_15 H_A#_19 T19 SA_CS#_1
H_D#16 P6 J21 H_A#20 DDR_CS2_DIMM# BE23
H_D#_16 H_A#_20 <18> DDR_CS2_DIMM# SB_CS#_0
H_D#17 W9 B18 H_A#21 DDR_CS3_DIMM# BC19 AW42 TP_MCH_RSVD20 T20
H_D#_17 H_A#_21 <18> DDR_CS3_DIMM# SB_CS#_1 RSVD20
H_D#18 V6 D22 H_A#22
H_D#19 H_D#_18 H_A#_22 H_A#23 M_ODT0
V2 H_D#_19 H_A#_23 G19 <16,17> M_ODT0 BJ17 SA_ODT_0
H_D#20 P10 J17 H_A#24 M_ODT1 BJ19
H_D#_20 H_A#_24 T21 SA_ODT_1
H_D#21 W7 L21 H_A#25 M_ODT2_DIMM BC17 BB20 TP_MCH_RSVD22 T22
H_D#_21 H_A#_25 +1.5V_MEM <18> M_ODT2_DIMM SB_ODT_0 RSVD22
H_D#22 N9 L19 H_A#26 R82 M_ODT3_DIMM BE17 BE19 TP_MCH_RSVD23 T23
H_D#_22 H_A#_26 <18> M_ODT3_DIMM SB_ODT_1 RSVD23
H_D#23 P4 G21 H_A#27 80.6_0402_1%~D BF20 TP_MCH_RSVD24 T24
H_D#24 H_D#_23 H_A#_27 H_A#28 SMRCOMP RSVD24 TP_MCH_RSVD25
U9 H_D#_24 H_A#_28 D20 2 1 BL25 SM_RCOMP RSVD25 BF18 T25
H_D#25 V4 K22 H_A#29 2 1 SMRCOMP# BK26
H_D#26 H_D#_25 H_A#_29 H_A#30 SM_RCOMP#
U1 H_D#_26 H_A#_30 F18
H_D#27 W3 K20 H_A#31 R83 SMRCOMP_VOH BK32
H_D#28 H_D#_27 H_A#_31 H_A#32 80.6_0402_1%~D SMRCOMP_VOL SM_RCOMP_VOH
V10 H_D#_28 H_A#_32 F20 BL31 SM_RCOMP_VOL
H_D#29 U7 F22 H_A#33 AN45 ME_JTAG_TCK R84 1 2 @ 100_0402_5%~D
H_D#30 H_D#_29 H_A#_33 H_A#34 ME_JTAG_TCK ME_JTAG_TDI R85 @ 100_0402_5%~D
W11 H_D#_30 H_A#_34 B20 +V_DDR_MCH_REF BC51 SM_VREF ME_JTAG_TDI AP44 1 2
H_D#31 U11 A19 H_A#35 SM_PWROK AY37 AT44 ME_JTAG_TDO R86 1 2 @ 100_0402_5%~D
H_D#_31 H_A#_35 SM_PWROK ME_JTAG_TDO
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
H_D#32 AC11 1 R87 2 499_0402_1%~D BH20 AN47 ME_JTAG_TMS R88 1 2 @ 100_0402_5%~D
H_D#33 H_D#_32 H_ADS# DDR3_DRAMRST# BA37 SM_REXT ME_JTAG_TMS
AC9 H_D#_33 H_ADS# F10 H_ADS# <7> 1 1 <16,17,18> DDR3_DRAMRST# SM_DRAMRST#
H_D#34 Y4 A15 H_ADSTB#0 H_ADSTB#0 <7>
H_D#_34 H_ADSTB#_0
C31
C32
H_D#35 Y10 C19 H_ADSTB#1 H_ADSTB#1 <7> MCH_DREFCLK B42
H_D#_35 H_ADSTB#_1 <6> MCH_DREFCLK DPLL_REF_CLK
H_D#36 H_BNR# MCH_DREFCLK#
HOST
AB6 H_D#_36 H_BNR# C9 H_BNR# <7> <6> MCH_DREFCLK# D42 DPLL_REF_CLK#
H_D#37 H_BPRI# 2 2 DREF_SSCLK
AA9 H_D#_37 H_BPRI# B8 H_BPRI# <7> <6> DREF_SSCLK B50 DPLL_REF_SSCLK
H_D#38 AB10 C11 H_BR0# H_BR0# <7> DREF_SSCLK# D50
H_D#_38 H_BREQ# <6> DREF_SSCLK# DPLL_REF_SSCLK#
H_D#39 AA1 E5 H_DEFER#
H_D#_39 H_DEFER# H_DEFER# <7>
H_D#40 AC3 D6 H_D BSY# H_DBSY# <7> <6> CLK_MCH_3GPLL CLK_MCH_3GPLL R49
CLK
H_D#41 H_D#_40 H_DBSY# CLK_MCH_BCLK CLK_MCH_3GPLL# PEG_CLK
AC7 H_D#_41 HPLL_CLK AH10 CLK_MCH_BCLK <6> <6> CLK_MCH_3GPLL# P50 PEG_CLK#
H_D#42 AD12 AJ11 CLK_MCH_BCLK# CLK_MCH_BCLK# <6>
H_D#43 H_D#_42 HPLL_CLK# H_DPW R#
AB4 H_D#_43 H_DPWR# G11 H_DPWR# <8>
C H_D#44 Y6 H2 H_D RDY# H_DRDY# <7> C
H_D#45 H_D#_44 H_DRDY# H_HIT# DMI_MRX_ITX_N0
AD10 H_D#_45 H_HIT# C7 H_HIT# <7> <24> DMI_MRX_ITX_N0 AG55 DMI_RXN_0
H_D#46 AA11 F8 H_HITM# H_HITM# <7> DMI_MRX_ITX_N1 AL49
H_D#_46 H_HITM# <24> DMI_MRX_ITX_N1 DMI_RXN_1
H_D#47 AB2 A11 H_LOCK# DMI_MRX_ITX_N2 AH54
H_D#_47 H_LOCK# H_LOCK# <7> <24> DMI_MRX_ITX_N2 DMI_RXN_2
H_D#48 AD4 D8 H_TRDY# DMI_MRX_ITX_N3 AL47
H_D#_48 H_TRDY# H_TRDY# <7> <24> DMI_MRX_ITX_N3 DMI_RXN_3
H_D#49 AE7
H_D#50 H_D#_49 DMI_MRX_ITX_P0
AD2 H_D#_50 <24> DMI_MRX_ITX_P0 AG53 DMI_RXP_0
H_D#51 AD6 DMI_MRX_ITX_P1 AK50 K26
H_D#_51 <24> DMI_MRX_ITX_P1 DMI_RXP_1 CFG_0 CPU_MCH_BSEL0 <6,8>
H_D#52 AE3 DMI_MRX_ITX_P2 AH52 G23
H_D#_52 <24> DMI_MRX_ITX_P2 DMI_RXP_2 CFG_1 CPU_MCH_BSEL1 <6,8>
H_D#53 AG9 L9 H_DINV#0 H_DINV#0 <8> DMI_MRX_ITX_P3 AL45 G25
H_D#_53 H_DINV#_0 <24> DMI_MRX_ITX_P3 DMI_RXP_3 CFG_2 CPU_MCH_BSEL2 <6,8>
H_D#54 AG7 N7 H_DINV#1 H_DINV#1 <8> J25 T30
H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 DMI_MTX_IRX_N0 CFG_3
AE11 H_D#_55 H_DINV#_2 AA7 H_DINV#2 <8> <24> DMI_MTX_IRX_N0 AG49 DMI_TXN_0 CFG_4 L25 T31
H_D#56 AK6 AG3 H_DINV#3 H_DINV#3 <8> DMI_MTX_IRX_N1 AJ49 L27 T90 +3.3V_RUN
H_D#_56 H_DINV#_3 <24> DMI_MTX_IRX_N1 DMI_TXN_1 CFG_5
H_D#57 AF6 DMI_MTX_IRX_N2 AJ47 F24 T91 R91
H_D#_57 <24> DMI_MTX_IRX_N2 DMI_TXN_2 CFG_6
H_D#58 AJ9 K2 H_DSTBN#0 H_DSTBN#0 <8> DMI_MTX_IRX_N3 AG47 D24 T92 PM_EXTTS# 2 1
H_D#_58 H_DSTBN#_0 <24> DMI_MTX_IRX_N3 DMI_TXN_3 CFG_7
H_D#59 AH6 N3 H_DSTBN#1 H_DSTBN#1 <8> D26 T32
H_D#_59 H_DSTBN#_1 CFG_8
CFG
H_D#60 AF12 AA3 H_DSTBN#2 H_DSTBN#2 <8> +3.3V_RUN DMI_MTX_IRX_P0 AF50 J23 T93 10K_0402_5%~D
H_D#_60 H_DSTBN#_2 <24> DMI_MTX_IRX_P0 DMI_TXP_0 CFG_9
DMI
H_D#61 AH4 AF4 H_DSTBN#3 H_DSTBN#3 <8> DMI_MTX_IRX_P1 AH50 B26 T33
H_D#_61 H_DSTBN#_3 <24> DMI_MTX_IRX_P1 DMI_TXP_1 CFG_10
H_D#62 AJ7 DMI_MTX_IRX_P2 AJ45 A23 T34
H_D#_62 <24> DMI_MTX_IRX_P2 DMI_TXP_2 CFG_11
1
H_D#63 AE9 L3 H_DSTBP#0 H_DSTBP#0 <8> DMI_MTX_IRX_P3 AG45 C23 T35 R114
H_D#_63 H_DSTBP#_0 <24> DMI_MTX_IRX_P3 DMI_TXP_3 CFG_12
M2 H_DSTBP#1 H_DSTBP#1 <8> R101 B24 T36 PLTRST1#_R 2 1
H_DSTBP#_1 CFG_13 PLTRST1# <22,35>
Y2 H_DSTBP#2 H_DSTBP#2 <8> 30K_0402_5%~D B22 T37
R89 H_SWNG H_DSTBP#_2 H_DSTBP#3 CFG_14 100_0402_5%~D
B6 H_SWING H_DSTBP#_3 AF2 H_DSTBP#3 <8> CFG_15 K24 T38
1 2 +H_RCOMP D4 C25 T94
2
H_RCOMP H_REQ#0 GFX_VR_ON CFG_16 +1.05V_VCCP
H_REQ#_0 J13 H_REQ#0 <7> CFG_17 L23 T39
GRAPHICS VID
24.9_0402_1%~D L13 H_REQ#1 L33 T40 R116
H_REQ#_1 H_REQ#1 <7> CFG_18
1
C13 H_REQ#2 K32 T95 THERMTRIP_MCH# 1 2
H_REQ#_2 H_REQ#2 <7> CFG_19
G13 H_REQ#3 GFX_VID0 G33 K34 T96
H_REQ#_3 H_REQ#3 <7> <44> GFX_VID0 GFX_VID_0 CFG_20
<7> H_RESET# H_RESET# J11 G15 H_REQ#4 R105 GFX_VID1 G37 56_0402_5%~D
H_CPURST# H_REQ#_4 H_REQ#4 <7> <44> GFX_VID1 GFX_VID_1
H_CPUSLP# G9 100K_0402_5%~D GFX_VID2 F38
<8> H_CPUSLP# H_CPUSLP# <44> GFX_VID2 GFX_VID_2
F4 H_RS#0 GFX_VID3 F36
H_RS#0 <7> <44> GFX_VID3
2
H_RS#_0 H_RS#1 GFX_VID4 GFX_VID_3 PM_SYNC#
H_RS#_1 F2 H_RS#1 <7> <44> GFX_VID4 G35 GFX_VID_4 PM_SYNC# J35 PM_SYNC# <24>
G7 H_RS#2 F6 H_DPRSTP# H_DPRSTP# <8,23,43>
H_RS#_2 H_RS#2 <7> PM_DPRSTP#
B L17 H_AVREF PM_EXT_TS#_0 J39 B
PM
+H_VREF K18 L39 PM_EXTTS#
H_DVREF PM_EXT_TS#_1 PM_EXTTS# <18,19>
GFX_VR_ON G39 AY39 RESET_OUT
+1.05V_M <44> GFX_VR_ON GFX_VR_EN PWROK RESET_OUT <24,34>
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D BB18 PLTRST1#_R
+1.05V_VCCP +1.05V_VCCP RSTIN# THERMTRIP_MCH#
THERMTRIP# K28 THERMTRIP_MCH# <19>
1K_0402_1%~D
K36 DPRSLPVR
DPRSLPVR DPRSLPVR <24,43>
1
1
CL_CLK0 AK52
+3.3V_M <24> CL_CLK0 CL_CLK +1.5V_MEM
R90
CL_DATA0 AK54
<24> CL_DATA0 CL_DATA
R97 R96 C1346 ICH_CL_PWROK AW40 A7
<24,34> ICH_CL_PWROK CL_PWROK NC_1
221_0402_1%~D 1K_0402_1%~D 1 2 CL_RST0# AL53 A49
<24> CL_RST0#
2
CL_RST# NC_2
1
+CL_VREF AL55 A52
ME
2
0.1U_0402_16V4Z~D CL_VREF NC_3 R98
NC_4 A54
5
499_0402_1%~D
0.1U_0402_16V4Z~D
H_SWNG +H_VREF B54
NC_5
2
@ 0.1U_0402_10V7K~D
1 R1058 1 D55 1K_0402_1%~D
P
<34,42> 1.5V_SUS_PWRGD A NC_6
0.1U_0402_10V7K~D
100_0402_1%~D
4 1 2 SM_PWROK DDPC_CTRLCLK F34 G55
<31> DDPC_CTRLCLK
2
Y DDPC_CTRLCLK NC_7
1
1
2K_0402_1%~D
R93
C33
NC
1 1 <34,37,45> DDR_ON 2 DDPC_CTRLDATA F32 BE55 SMRCOMP_VOH
B <31> DDPC_CTRLDATA DDPC_CTRLDATA NC_8
G
1
R103
2.2U_0603_6.3V6K~D
0.01U_0402_16V7K~D
12K_0402_5%~D SDVO_CTRLCLK B38 BH55
2 <31> SDVO_CTRLCLK SDVO_CTRLCLK NC_9
C35
C34
R102
R1060 U92 SDVO_CTRLDATA A37 BK55
<31> SDVO_CTRLDATA
3
SDVO_CTRLDATA NC_10
3.01K_0402_1%~D
1 2 74AHCT1G08GW SOT353~D R1059 CLK_3GPLLREQ# C31 BK54
MISC
<24,34> SIO_SLP_S4# <6> CLK_3GPLLREQ# CLKREQ# NC_11 1 1
1
2 2 10K_0402_5%~D MCH_ICH_SYNC#
<24> MCH_ICH_SYNC# K42 BL54
2
ICH_SYNC# NC_12
C37
C36
@ 0_0402_5%~D BL52
2
NC_13
R104
NC_14 BL49
MCH_TSATN# 2 2
D10 TSATN# NC_15 BL7
BL4
2
+3.3V_RUN NC_16
NC_17 BL2
Place close to pin F34,F32,B38,A37 of U78 NC_18 BK2
SMRCOMP_VOL
NC_19 BK1
2.2U_0603_6.3V6K~D
0.01U_0402_16V7K~D
NC_20 BH1
1K_0402_5%~D
1K_0402_1%~D
+3.3V_RUN BE1
NC_21
1
1
<23> ICH_AZ_MCH_BITCLK C29 HDA_BCLK NC_22 G1 1 1
R94 2 1 100K_0402_5%~D DDPC_CTRLCLK B30
<23> ICH_AZ_MCH_RST# HDA_RST#
1
R112
1K_0402_5%~D
C39
C38
R113
<23> ICH_AZ_MCH_SDIN2 1 R1032 2 MCH_SDIN2 D28 HDA_SDI
R95 2 1 100K_0402_5%~D DDPC_CTRLDATA 33_0402_5%~D A27
HDA
A <23> ICH_AZ_MCH_SDOUT HDA_SDO A
+1.05V_VCCP 2 2
R111
<23> ICH_AZ_MCH_SYNC B28
2
2
R99 HDA_SYNC
2 1 100K_0402_5%~D SDVO_CTRLCLK
<33> MCH_TSATN_EC
2
R100 2 1 100K_0402_5%~D SDVO_CTRLDATA
R115
DELL CONFIDENTIAL/PROPRIETARY
1
C 54.9_0402_1%~D CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
Q22 2
B
MMST3904-7-F_SOT323-3~D
Compal Electronics, Inc.
2
1
E C R118
3
2 2 1 MCH_TSATN# PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
B TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
E 330_0402_5%~D BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga GS(1/6)
3
Q23 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number R ev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
WWW.AliSaler.Com
MMST3904-7-F_SOT323-3~D 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 10 of 49
5 4 3 2 1
5 4 3 2 1
D D
DDR_A_D[0..63] <16,17> DDR_B_D[0..63] <18>
U78D U78E
DDR_A_BS0 BC21 AP46 DDR_A_D0 DDR_B_BS0 BJ13 AP54 DDR_B_D0
<16,17> DDR_A_BS0 SA_BS_0 SA_DQ_0 <18> DDR_B_BS0 SB_BS_0 SB_DQ_0
DDR_A_BS1 BJ21 AU47 DDR_A_D1 DDR_B_BS1 BK12 AM52 DDR_B_D1
<16,17> DDR_A_BS1 SA_BS_1 SA_DQ_1 <18> DDR_B_BS1 SB_BS_1 SB_DQ_1
DDR_A_BS2 BJ41 AT46 DDR_A_D2 DDR_B_BS2 BK38 AR55 DDR_B_D2
<16,17> DDR_A_BS2 SA_BS_2 SA_DQ_2 <18> DDR_B_BS2 SB_BS_2 SB_DQ_2
AU49 DDR_A_D3 AV54 DDR_B_D3
DDR_A_RAS# SA_DQ_3 DDR_A_D4 SB_DQ_3 DDR_B_D4
<16,17> DDR_A_RAS# BH22 SA_RAS# SA_DQ_4 AR45 SB_DQ_4 AM54
DDR_A_CAS# BK20 AN49 DDR_A_D5 DDR_B_RAS# BE21 AN53 DDR_B_D5
<16,17> DDR_A_CAS# SA_CAS# SA_DQ_5 <18> DDR_B_RAS# SB_RAS# SB_DQ_5
DDR_A_WE# BL15 AV50 DDR_A_D6 DDR_B_CAS# BH14 AT52 DDR_B_D6
<16,17> DDR_A_WE# SA_WE# SA_DQ_6 <18> DDR_B_CAS# SB_CAS# SB_DQ_6
AP50 DDR_A_D7 DDR_B_WE# BK14 AU53 DDR_B_D7
SA_DQ_7 <18> DDR_B_WE# SB_WE# SB_DQ_7
AW47 DDR_A_D8 AW53 DDR_B_D8
SA_DQ_8 DDR_A_D9 SB_DQ_8 DDR_B_D9
<16,17> DDR_A_DM[0..7] SA_DQ_9 BD50 SB_DQ_9 AY52
AW49 DDR_A_D10 BB52 DDR_B_D10
SA_DQ_10 <18> DDR_B_DM[0..7] SB_DQ_10
DDR_A_DM0 AT50 BA49 DDR_A_D11 BC53 DDR_B_D11
DDR_A_DM1 SA_DM_0 SA_DQ_11 DDR_A_D12 DDR_B_DM0 SB_DQ_11 DDR_B_D12
BB50 SA_DM_1 SA_DQ_12 BC49 AP52 SB_DM_0 SB_DQ_12 AV52
DDR_A_DM2 BB46 AV46 DDR_A_D13 DDR_B_DM1 AY54 AW55 DDR_B_D13
DDR_A_DM3 SA_DM_2 SA_DQ_13 DDR_A_D14 DDR_B_DM2 SB_DM_1 SB_DQ_13 DDR_B_D14
BE39 SA_DM_3 SA_DQ_14 BA47 BJ49 SB_DM_2 SB_DQ_14 BD52
DDR_A_DM4 BB12 AY50 DDR_A_D15 DDR_B_DM3 BJ43 BC55 DDR_B_D15
DDR_A_DM5 SA_DM_4 SA_DQ_15 DDR_A_D16 DDR_B_DM4 SB_DM_3 SB_DQ_15 DDR_B_D16
BE7 BF46 BH12 BF54
A
DDR_A_DM6 SA_DM_5 SA_DQ_16 DDR_A_D17 DDR_B_DM5 SB_DM_4 SB_DQ_16 DDR_B_D17
AV10 SA_DM_6 SA_DQ_17 BC47 BD2 SB_DM_5 SB_DQ_17 BE51
DDR_A_DM7 AR9 BF50 DDR_A_D18 DDR_B_DM6 AY2 BH48 DDR_B_D18
SA_DM_7 SA_DQ_18 DDR_A_D19 DDR_B_DM7 SB_DM_6 SB_DQ_18 DDR_B_D19
BF48 AJ3 BK48
B
<16,17> DDR_A_DQS[0..7] SA_DQ_19 SB_DM_7 SB_DQ_19
DDR_A_DQS0 AR47 BC43 DDR_A_D20 BE53 DDR_B_D20
SA_DQS_0 SA_DQ_20 <18> DDR_B_DQS[0..7] SB_DQ_20
DDR_A_DQS1 BA45 BE49 DDR_A_D21 DDR_B_DQS0 AR53 BH52 DDR_B_D21
C
DDR_A_DQS2
DDR_A_DQS3
BE45
BC41
SA_DQS_1
SA_DQS_2
SA_DQS_3
MEMORY SA_DQ_21
SA_DQ_22
SA_DQ_23
BA43
BE47
DDR_A_D22
DDR_A_D23
DDR_B_DQS1
DDR_B_DQS2
BA53
BH50
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQ_21
SB_DQ_22
SB_DQ_23
BK46
BJ47
DDR_B_D22
DDR_B_D23 C
DDR_A_DQS4 BC13 BF42 DDR_A_D24 DDR_B_DQS3 BK42 BL45 DDR_B_D24
MEMORY
DDR_A_DQS5 SA_DQS_4 SA_DQ_24 DDR_A_D25 DDR_B_DQS4 SB_DQS_3 SB_DQ_24 DDR_B_D25
BB10 SA_DQS_5 SA_DQ_25 BC39 BH8 SB_DQS_4 SB_DQ_25 BJ45
DDR_A_DQS6 BA7 BF44 DDR_A_D26 DDR_B_DQS5 BB2 BL41 DDR_B_D26
DDR_A_DQS7 SA_DQS_6 SA_DQ_26 DDR_A_D27 DDR_B_DQS6 SB_DQS_5 SB_DQ_26 DDR_B_D27
<16,17> DDR_A_DQS#[0..7] AN7 SA_DQS_7 SA_DQ_27 BF40 AV2 SB_DQS_6 SB_DQ_27 BH44
DDR_A_DQS#0 AR49 BB40 DDR_A_D28 DDR_B_DQS7 AM2 BH46 DDR_B_D28
SA_DQS#_0 SA_DQ_28 <18> DDR_B_DQS#[0..7] SB_DQS_7 SB_DQ_28
DDR_A_DQS#1 AW45 BE43 DDR_A_D29 DDR_B_DQS#0 AT54 BK44 DDR_B_D29
DDR_A_DQS#2 BC45 SA_DQS#_1 SA_DQ_29 DDR_A_D30 DDR_B_DQS#1 SB_DQS#_0 SB_DQ_29 DDR_B_D30
SA_DQS#_2 SA_DQ_30 BF38 BB54 SB_DQS#_1 SB_DQ_30 BK40
DDR_A_DQS#3 BA41 BE41 DDR_A_D31 DDR_B_DQS#2 BJ51 BJ39 DDR_B_D31
DDR_A_DQS#4 BA13 SA_DQS#_3 SA_DQ_31 DDR_A_D32 DDR_B_DQS#3 SB_DQS#_2 SB_DQ_31 DDR_B_D32
SA_DQS#_4 SA_DQ_32 BA15 BH42 SB_DQS#_3 SB_DQ_32 BK10
DDR_A_DQS#5 BA11 BE11 DDR_A_D33 DDR_B_DQS#4 BK8 BH10 DDR_B_D33
DDR_A_DQS#6 SA_DQS#_5 SA_DQ_33 DDR_A_D34 DDR_B_DQS#5 SB_DQS#_4 SB_DQ_33 DDR_B_D34
SYSTEM
BA9 SA_DQS#_6 SA_DQ_34 BE15 BC3 SB_DQS#_5 SB_DQ_34 BK6
DDR_A_DQS#7 AN9 BF14 DDR_A_D35 DDR_B_DQS#6 AW3 BH6 DDR_B_D35
<16,17> DDR_A_MA[0..13] SA_DQS#_7 SA_DQ_35 SB_DQS#_6 SB_DQ_35
BB14 DDR_A_D36 DDR_B_DQS#7 AN3 BJ9 DDR_B_D36
SA_DQ_36 <18> DDR_B_MA[0..14] SB_DQS#_7 SB_DQ_36
DDR_A_MA0 DDR_A_D37 DDR_B_D37
SYSTEM
BC23 SA_MA_0 SA_DQ_37 BC15 SB_DQ_37 BL11
DDR_A_MA1 BF22 BE13 DDR_A_D38 DDR_B_MA0 BJ15 BG5 DDR_B_D38
DDR_A_MA2 SA_MA_1 SA_DQ_38 DDR_A_D39 DDR_B_MA1 SB_MA_0 SB_DQ_38 DDR_B_D39
BE31 SA_MA_2 SA_DQ_39 BF16 BJ33 SB_MA_1 SB_DQ_39 BJ5
DDR_A_MA3 BC31 BF10 DDR_A_D40 DDR_B_MA2 BH24 BG3 DDR_B_D40
DDR_A_MA4 SA_MA_3 SA_DQ_40 DDR_A_D41 DDR_B_MA3 SB_MA_2 SB_DQ_40 DDR_B_D41
BH26 SA_MA_4 SA_DQ_41 BC11 BA17 SB_MA_3 SB_DQ_41 BF4
DDR_A_MA5 BJ35 BF8 DDR_A_D42 DDR_B_MA4 BF36 BD4 DDR_B_D42
DDR_A_MA6 SA_MA_5 SA_DQ_42 DDR_A_D43 DDR_B_MA5 SB_MA_4 SB_DQ_42 DDR_B_D43
BB34 SA_MA_6 SA_DQ_43 BG7 BH36 SB_MA_5 SB_DQ_43 BA3
DDR_A_MA7 BH32 BC7 DDR_A_D44 DDR_B_MA6 BF34 BE5 DDR_B_D44
DDR_A_MA8 SA_MA_7 SA_DQ_44 DDR_A_D45 DDR_B_MA7 SB_MA_6 SB_DQ_44 DDR_B_D45
BB26 SA_MA_8 SA_DQ_45 BC9 BK34 SB_MA_7 SB_DQ_45 BF2
DDR_A_MA9 BF32 BD6 DDR_A_D46 DDR_B_MA8 BJ37 BB4 DDR_B_D46
SA_MA_9 SA_DQ_46 SB_MA_8 SB_DQ_46
DDR
DDR_A_MA10 BA21 BF12 DDR_A_D47 DDR_B_MA9 BH40 AY4 DDR_B_D47
DDR_A_MA11 SA_MA_10 SA_DQ_47 DDR_A_D48 DDR_B_MA10 SB_MA_9 SB_DQ_47 DDR_B_D48
BG25 SA_MA_11 SA_DQ_48 AV6 BH16 SB_MA_10 SB_DQ_48 BA1
DDR_A_MA12 BH34 BB6 DDR_A_D49 DDR_B_MA11 BK36 AP2 DDR_B_D49
SA_MA_12 SA_DQ_49 SB_MA_11 SB_DQ_49
DDR
DDR_A_MA13 BH18 AW7 DDR_A_D50 DDR_B_MA12 BH38 AU1 DDR_B_D50
DDR_A_MA14_R SA_MA_13 SA_DQ_50 DDR_A_D51 DDR_B_MA13 SB_MA_12 SB_DQ_50 DDR_B_D51
BE25 SA_MA_14 SA_DQ_51 AY6 BJ11 SB_MA_13 SB_DQ_51 AT2
AT10 DDR_A_D52 DDR_B_MA14 BL37 AT4 DDR_B_D52
SA_DQ_52 DDR_A_D53 SB_MA_14 SB_DQ_52 DDR_B_D53
SA_DQ_53 AW11 SB_DQ_53 AV4
AU11 DDR_A_D54 AU3 DDR_B_D54
B SA_DQ_54 DDR_A_D55 SB_DQ_54 DDR_B_D55 B
SA_DQ_55 AW9 SB_DQ_55 AR3
AR11 DDR_A_D56 AN1 DDR_B_D56
SA_DQ_56 DDR_A_D57 SB_DQ_56 DDR_B_D57
SA_DQ_57 AT6 SB_DQ_57 AP4
AP6 DDR_A_D58 AL3 DDR_B_D58
SA_DQ_58 DDR_A_D59 SB_DQ_58 DDR_B_D59
SA_DQ_59 AL7 SB_DQ_59 AJ1
AR7 DDR_A_D60 AK4 DDR_B_D60
SA_DQ_60 DDR_A_D61 SB_DQ_60 DDR_B_D61
SA_DQ_61 AT12 SB_DQ_61 AM4
AM6 DDR_A_D62 AH2 DDR_B_D62
SA_DQ_62 DDR_A_D63 SB_DQ_62 DDR_B_D63
SA_DQ_63 AU7 SB_DQ_63 AK2
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
Place close to U78, reserve for 2Gb on board RAMs
R793
DDR_A_MA14_R 1 2 DDR_A_MA14 DDR_A_MA14 <16,17>
@ 0_0402_5%~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga GS(2/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 11 of 49
5 4 3 2 1
5 4 3 2 1
+VCC_PEG
2
U78C
R119
D 49.9_0402_1%~D D
1
BIA_PWM D38
<20> BIA_PWM L_BKLT_CTRL
PANEL_BKEN_MCH C37 U45 PEGCOMP
<33> PANEL_BKEN_MCH L_BKLT_EN PEG_COMPI
K38 T44
L_CTRL_CLK PEG_COMPO Strap Pin Table
L37 L_CTRL_DATA
LDDC_CLK_MCH J37 D52 Low = DMI x 2
<20> LDDC_CLK_MCH L_DDC_CLK PEG_RX#_0
LDDC_DATA_MCH L35 G49 CFG5 DMI X2 Select
<20> LDDC_DATA_MCH L_DDC_DATA PEG_RX#_1
K54 DPB_DOCK_AUX# High = DMI x 4 (Default)
PEG_RX#_2 DPB_DOCK_AUX# <31>
PEG_RX#_3 H50
R120 ENVDD B36 M52 iTPM Host Low = iTPM enable
<20> ENVDD L_VDD_EN PEG_RX#_4
1 2 L_IBG F50 N49 CFG6
LVDS_IBG PEG_RX#_5 DPC_DOCK_AUX# Interface
H46 LVDS_VBG PEG_RX#_6 P54 DPC_DOCK_AUX# <31> High = iTPM disable(Defult)
2.37K_0402_1%~D P44 V46
LVDS_VREFH PEG_RX#_7
K46 LVDS_VREFL PEG_RX#_8 Y50 Management Low = TLS cipher suite with no confidentiality
LCD_ACLK-_MCH D46 V52 CFG7
<20> LCD_ACLK-_MCH
LCD_ACLK+_MCH LVDSA_CLK# PEG_RX#_9 Engine Crypto
<20> LCD_ACLK+_MCH B46 LVDSA_CLK PEG_RX#_10 W49 High = TLS cipher suite with
LVDS
D44 AB54 Strap
B44
LVDSB_CLK# PEG_RX#_11
AD46
confidentiality(Default)
LVDSB_CLK PEG_RX#_12
PEG_RX#_13 AC55 PCI Express Low = Reverse Lane
LCD_A0-_MCH G45 AE49 CFG9
<20> LCD_A0-_MCH
LCD_A1-_MCH F46
LVDSA_DATA#_0 PEG_RX#_14
AF54
Graphic Lane High = Normal Operation(Default)
<20> LCD_A1-_MCH LVDSA_DATA#_1 PEG_RX#_15
LCD_A2-_MCH G41
<20> LCD_A2-_MCH LVDSA_DATA#_2
C45 E51 PCI Express
GRAPHICS
LVDSA_DATA#_3 PEG_RX_0
PEG_RX_1 F48
Lookpback Low = Enable
LCD_A0+_MCH F44 J55 DPB_DOCK_AUX CFG10
<20> LCD_A0+_MCH LVDSA_DATA_0 PEG_RX_2 DPB_DOCK_AUX <31>
<20> LCD_A1+_MCH
LCD_A1+_MCH G47 LVDSA_DATA_1 PEG_RX_3 J49 DPB_DOCK_HPD#
DPB_DOCK_HPD# <31>
enable High = Disable(default)
LCD_A2+_MCH F40 M54
<20> LCD_A2+_MCH LVDSA_DATA_2 PEG_RX_4
A45 LVDSA_DATA_3 PEG_RX_5 M50 Low = ALLZ mode enable
P52 DPC_DOCK_AUX CFG12 ALLZ
PEG_RX_6 DPC_DOCK_HPD# DPC_DOCK_AUX <31>
C
B40 LVDSB_DATA#_0 PEG_RX_7 U47 DPC_DOCK_HPD# <31> High = Disable(default) C
Place close to U78 A41 LVDSB_DATA#_1 PEG_RX_8 AA49
F42 LVDSB_DATA#_2 PEG_RX_9 V54 Low = XOR mode enable
D48 LVDSB_DATA#_3 PEG_RX_10 V50 CFG13 XOR
PEG_RX_11 AB52 High = Disable(default)
R140 1 2 100K_0402_5%~D ENVDD D40 AC47
LVDSB_DATA_0 PEG_RX_12
C41 LVDSB_DATA_1 PEG_RX_13 AC53 Low=Dynamic ODT Disable
R135 1 2 150_0402_1%~D CRT_BLU G43 AD50 CFG16 FSB Dynamic
PCI-EXPRESS
LVDSB_DATA_2 PEG_RX_14
B48 LVDSB_DATA_3 PEG_RX_15 AF52
ODT High=Dynamic ODT Enable(default)
R136 1 2 150_0402_1%~D CRT_GRN
L47 DPB_LANE_N0 C40 2 1 0.1U_0402_10V7K~D DMI Lane Low=Normal (default)
R139 1 CRT_RED PEG_TX#_0 DPB_LANE_N1 DPB_LANE_N0_C <31>
2 150_0402_1%~D F52 C41 2 1 0.1U_0402_10V7K~D CFG19
J27
PEG_TX#_1
P46 DPB_LANE_N2 C42 2 1 0.1U_0402_10V7K~D DPB_LANE_N1_C <31> Reversal High=Lane Reversed
TVA_DAC PEG_TX#_2 DPB_LANE_N2_C <31>
TV
E27 H54 DPB_LANE_N3 C43 2 1 0.1U_0402_10V7K~D
TVB_DAC PEG_TX#_3 DPC_LANE_N0 C44 0.1U_0402_10V7K~D DPB_LANE_N3_C <31>
G27 TVC_DAC PEG_TX#_4 L55 2 1 DPC_LANE_N0_C <31> Low=Only SDVO or PCIEx1 is
T46 DPC_LANE_N1 C45 2 1 0.1U_0402_10V7K~D SDVO/PCIE
F26
PEG_TX#_5
R53 DPC_LANE_N2 C46 2 1 0.1U_0402_10V7K~D DPC_LANE_N1_C <31>
CFG20 operational (default)
TVA_RTN PEG_TX#_6
U49 DPC_LANE_N3 C47 2 1 0.1U_0402_10V7K~D DPC_LANE_N2_C <31> Concurrent High=SDVO and PCIEx1 are operating
PEG_TX#_7 DPC_LANE_N3_C <31>
PEG_TX#_8 T54 Operation simultaneously via PEG port
PEG_TX#_9 Y46
B34 TV_DCONSEL_0 PEG_TX#_10 AB46 Low=No SDVO Device Present
D34 TV_DCONSEL_1 PEG_TX#_11 W53 SDVO_CRTL_DATA (default)
PEG_TX#_12 Y54
PEG_TX#_13 AC49 High=SDVO Device Present
PEG_TX#_14 AF46
PEG_TX#_15 AD54 Low=DisplayPort disabled (default)
DDPC_CTRLDATA
CRT_BLU J29 J47 DPB_LANE_P0 C48 2 1 0.1U_0402_10V7K~D High=DisplayPort device present
<20> CRT_BLU CRT_BLUE PEG_TX_0 DPB_LANE_P0_C <31>
F54 DPB_LANE_P1 C49 2 1 0.1U_0402_10V7K~D
CRT_GRN PEG_TX_1 DPB_LANE_P2 C50 0.1U_0402_10V7K~D DPB_LANE_P1_C <31>
<20> CRT_GRN G29 CRT_GREEN PEG_TX_2 N47 2 1 DPB_LANE_P2_C <31>
H52 DPB_LANE_P3 C51 2 1 0.1U_0402_10V7K~D CFG[5:16] have internal pullup CFG[19:20] have internal pulldown
CRT_RED PEG_TX_3 DPC_LANE_P0 C52 0.1U_0402_10V7K~D DPB_LANE_P3_C <31>
<20> CRT_RED F30 CRT_RED PEG_TX_4 L53 2 1 DPC_LANE_P0_C <31>
VGA
R47 DPC_LANE_P1 C53 2 1 0.1U_0402_10V7K~D
B PEG_TX_5 DPC_LANE_P2 C54 0.1U_0402_10V7K~D DPC_LANE_P1_C <31> B
E29 CRT_IRTN PEG_TX_6 R55 2 1 DPC_LANE_P2_C <31>
T50 DPC_LANE_P3 C55 2 1 0.1U_0402_10V7K~D
G_CLK_DDC2 PEG_TX_7 DPC_LANE_P3_C <31>
D36 CRT_DDC_CLK PEG_TX_8 T52
R126 G_DAT_DDC2 C35 W47
CRT_HSYNC_R CRT_DDC_DATA PEG_TX_9
<20> CRT_HSYNC 1 2 J33 CRT_HSYNC PEG_TX_10 AA47
D32 CRT_TVO_IREF PEG_TX_11 W55
30_0402_1%~D G31 Y52
CRT_VSYNC PEG_TX_12
PEG_TX_13 AB50
R128 AE47
CRT_IREF PEG_TX_14 +3.3V_RUN
2 1 PEG_TX_15 AD52
1.02K_0402_1%~D
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
1 2 CRT_VSYNC_R
<20> CRT_VSYNC
1
R130 R1061 R1062
30_0402_1%~D 2.2K_0402_5%~D 2.2K_0402_5%~D
2
G_CLK_DDC2 1 6 CLK_DDC2
CLK_DDC2 <20>
Q110A
2N7002DW-7-F_SOT363-6~D
2
+3.3V_RUN
Q110B
5
2N7002DW-7-F_SOT363-6~D
G_DAT_DDC2 4 3 DAT_DDC2
DAT_DDC2 <20>
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga GS(3/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 12 of 49
5 4 3 2 1
5 4 3 2 1
64.8mA Max.
+1.05V_VCCP
+1.05V_M_DPLLA +1.05V_M
U78H L8
2 1
+3.3V_CRT_DAC +3.3V_RUN
220U_D2_4VY_R15M~D
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
2.2U_0603_6.3V6K~D
0.47U_0402_10V4Z~D
R13 10UH_LB2012T100MR_20%_0805~D
VTT_1
0.1U_0402_16V4Z~D
220U_D2_4VY_R15M~D
1 T12 L3 1
VTT_2
1 1 1 1 R11 VTT_3 VCCA_CRT_DAC J31 2 1 1
C105
C103
+ T10 4.7UH_LQM18FN4R7M00D_20%_0603~D +
VTT_4 +3.3V_CRT_DAC
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
C64
C65
C66
C67
C68
CRB 270uF R9 VTT_5
T8 VTT_6 1 1
D 2 2 2 2 2 2 2 D
R7 VTT_7 VCCA_DAC_BG L31
CRT
C69
C70
T6 VTT_8 VSSA_DAC_BG M33
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
R5 VTT_9 2 2
T4 VTT_10 1 1
R3 VTT_11
C74
C75
+3.3V_RUN T2 VTT_12 VCCA_DPLLA J45 +1.05V_M_DPLLA
R1 VTT_13 2 2
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
VTT
VCCA_DPLLB L49 +1.05V_M_DPLLB
1 1 64.8mA Max.
PLL
VCCA_HPLL AF10 +1.05V_M_HPLL
C76
C77
K30 AE1 +1.05V_M_DPLLB +1.05V_M
+1.5V_RUN +1.5V_RUN_QDAC 2 2 VCCA_TV_DAC VCCA_MPLL +1.05V_M_MPLL
L9
+VCC_TX_LVDS
TV
L4 2 1
1 2 10UH_LB2012T100MR_20%_0805~D
0.1U_0402_16V4Z~D
220U_D2_4VY_R15M~D
A PEG A LVDS
BLM18PG181SN1_0603~D U43 +VCC_TX_LVDS 1
VCCA_LVDS1
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1000P_0402_50V7K~D
+1.5V_RUN A31 VCC_HDA VCCA_LVDS2 U41 1
C106
C104
D TV/CRT HDA
+
1 1 1
+1.5V_RUN_QDAC
0.1U_0402_16V4Z~D
VSSA_LVDS V44
C85
C84
C79
1 2 2
+1.5V_RUN N34 R143
2 2 VCCD_QDAC 2
C78
AJ43 VCCA_PEG_BG 1 2 +1.5V_RUN
VCCA_PEG_BG
N32 VCCD_TVDAC
2 0_0402_5%~D
1
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
1 1 AG43 +1.05V_M_PEGPLL C80
VCCA_PEG_PLL 0.1U_0402_16V4Z~D
2
C81
C82
2 2 VCCA_SM_1 AW24 24mA Max.
AU24
POWER VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
AW22
AU22 +1.05V_M_HPLL +1.05V_M
C L6 C
VCCA_SM_5 AU21
VCCA_SM_6 AW20 2 1
AU19 +1.05V_M BLM18AG121SN1D_0603~D
VCCA_SM_7
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6M~D
AW18 R146
VCCA_SM_8
100U_D_6.3VM_R15M~D
A SM
+1.5V_MEM +1.5V_SM_CK AU18 +1.05V_M_A_SM 1 2 1 1
VCCA_SM_9
@ 22U_0805_6.3V6M~D
L12 AW16
VCCA_SM_10
1U_0603_10V4Z~D
4.7U_0603_6.3V6M~D
22U_0805_6.3V6M~D
C94
C95
2 1 +1.05V_M AU16 0_0805_5%~D 1
VCCA_SM_11
0.1U_0402_16V4Z~D
1UH_LQM21FN1R0N00D_30%_0805~D R147 AT16 1 1 1 1
VCCA_SM_12 2 2
1_0603_5%~D
2 1 +VCC_AXF AR16 +
VCCA_SM_13
1
@ 10U_0805_6.3VAM~D
C88
C89
C90
C91
C87
1 VCCA_SM_14 AU15
R150
C116
1U_0603_10V4Z~D
0_1210_5%~D 1 1 AT15
VCCA_SM_15 2 2 2 2 2
VCCA_SM_16 AR15
C92
C93
M25 VCC_AXF_1 VCCA_SM_17 AW14
2
N24
2
2 2 VCC_AXF_2
AXF
M23 VCC_AXF_3 VCCA_SM_NCTF_1 AT24
1
C117 VCCA_SM_NCTF_2 AR24 139.2mA Max.
VCCA_SM_NCTF_3 AT22
10U_0805_4VAM~D AR22
VCCA_SM_NCTF_4 +1.05V_M_MPLL +1.05V_M
VCCA_SM_NCTF_5 AT21
2 L7
+1.5V_SM_CK BK24 VCC_SM_CK_1 VCCA_SM_NCTF_6 AR21
BL23 VCC_SM_CK_2 VCCA_SM_NCTF_7 AT19 2 1
BJ23 SM CK AR19 0.15UH_LQH32CNR15M33L_20%_1210~D
VCC_SM_CK_3 VCCA_SM_NCTF_8
0.1U_0402_16V4Z~D
BK22 VCC_SM_CK_4 VCCA_SM_NCTF_9 AT18
2
VCCA_SM_NCTF_10 AR18 1
R148
+1.05V_M_SM_CK
C96
+1.05V_M 0_0603_5%~D
+3.3V_RUN T41 R149
+VCC_TX_LVDS VCC_TX_LVDS 2
AU27 1 2
1
VCCA_SM_CK_4
@ 2.2U_0603_6.3V6K~D
C33 VCC_HV_1 VCCA_SM_CK_3 AU28
0.1U_0402_16V4Z~D
22U_0805_6.3V6M~D
A33 AU29 0_1210_5%~D 1
VCC_HV_2 VCCA_SM_CK_2 C100
1 VCCA_SM_CK_1 AU31 1 1 1
HV
C101 AT31 22U_0805_6.3VAM~D
VCCA_SM_CK_NCTF_1
C97
C99
C98
B 0.1U_0402_16V4Z~D B
VCCA_SM_CK_NCTF_2 AR31
2
+VCC_PEG AB44 VCC_PEG_1 VCCA_SM_CK_NCTF_3 AT29
2 2 2 2
Y44 VCC_PEG_2 VCCA_SM_CK_NCTF_4 AR29
AC43 VCC_PEG_3 VCCA_SM_CK_NCTF_5 AT28
PEG
AA43 VCC_PEG_4 VCCA_SM_CK_NCTF_6 AR28
+VCC_DMI AT27
PJP1 VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8 AR27
+VCC_PEG 1 2
AM44 VCC_DMI_1
PAD-OPEN1x1m 1 AN43 +1.05V_M
VCC_DMI_2
AL43 VCC_DMI_3
DMI
C102 AH12
VCCD_HPLL +1.05V_M_PEGPLL
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D +1.05V_M
2 L5
VCCD_PEG_PLL AE43 +1.05V_M_PEGPLL 1
C107
2 1
+1.05V_M +VCC_PEG
0.1U_0402_16V4Z~D
GMCH_VTTLF1 K14 BLM21PG221SN1D_0805~D
VTTLF1
VTTLF
0.1U_0402_16V4Z~D
R141 GMCH_VTTLF2 Y12 M46 +1.8V_LVDS 1
VTTLF2 VCCD_LVDS_1
1
2
C108
2 1 GMCH_VTTLF3 P2 L45 1
LVDS
VTTLF3 VCCD_LVDS_2
220U_D2_4VY_R15M~D
1U_0603_10V4Z~D
R145
22U_0805_6.3V6M~D
4.7U_0603_6.3V6M~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
C86
0_1210_5%~D 1 1 1_0402_5%~D
2
C112
1 1 1 1 1 2
C109
C110
C111
+ CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
2
C71
C73
C72
2
2 2 2 2 2 2 1
C83
10U_0805_4VAM~D
2
118.8mA Max.
A A
+VCC_TX_LVDS +1.8V_LVDS +1.8V_RUN
L10 PJP38
1 2 1 2
1000P_0402_50V7K~D
22U_0805_6.3V6M~D
100NH_HK1608R10J-T_5%_0603~D
PAD-OPEN 4x4m
PJP39
+1.8V_RUN_LVDS DELL CONFIDENTIAL/PROPRIETARY
1 1
C113
C114
1 2 Compal Electronics, Inc.
PAD-OPEN 4x4m PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2 2 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga GS(4/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 13 of 49
5 4 3 2 1
5 4 3 2 1
U78G
+VCC_SM_BB36
+VCC_SM_BE35 +VCC_GFXCORE
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
VCC_AXG_NCTF_1 T32
2 2 BB36 VCC_SM_1 VCC_AXG_NCTF_2 U31
C755
C756
BE35 VCC_SM_2 VCC_AXG_NCTF_3 T31
AW34 VCC_SM_3 VCC_AXG_NCTF_4 R31
U78F AW32 U29
1 1 VCC_SM_4 VCC_AXG_NCTF_5
BK30 VCC_SM_5 VCC_AXG_NCTF_6 T29
BH30 VCC_SM_6 VCC_AXG_NCTF_7 R29
BF30 VCC_SM_7 VCC_AXG_NCTF_8 U28
D +1.5V_MEM BD30 U27 D
+1.05V_M VCC_SM_8 VCC_AXG_NCTF_9
BB30 VCC_SM_9 VCC_AXG_NCTF_10 T27
AW30 VCC_SM_10 VCC_AXG_NCTF_11 R27
AT41 VCC_1 BL29 VCC_SM_11 VCC_AXG_NCTF_12 U25
330U_D2_2.5VY_R15M
0.1U_0402_10V7K~D
22U_0805_6.3V6M~D
22U_0805_6.3V6M~D
AR41 VCC_2 BJ29 VCC_SM_12 VCC_AXG_NCTF_13 T25
Layout Note: Layout Note: AN41 VCC_3 1 BG29 VCC_SM_13 VCC_AXG_NCTF_14 R25
AJ41 VCC_4 2 1 1 BE29 VCC_SM_14 VCC_AXG_NCTF_15 U24
Place close to U78 Inside GMCH cavity
C118
C121
C122
C123
AH41 + +VCC_SM_BC29 BC29 U22
VCC_5 VCC_SM_15 VCC_AXG_NCTF_16
AD41 VCC_6 BA29 VCC_SM_16 VCC_AXG_NCTF_17 T22
0.1U_0402_10V7K~D
POWER
AC41 VCC_7 AY29 VCC_SM_17 VCC_AXG_NCTF_18 R22
2 1 2 2
Y41 VCC_8 2 BK28 VCC_SM_18 VCC_AXG_NCTF_19 U21
220U_D2_4VY_R15M~D
C757
22U_0805_6.3V6M~D W41 VCC_9 BH28 VCC_SM_19 VCC_AXG_NCTF_20 T21 Cavity Capacitors
0.22U_0402_10V4Z~D
AT40 VCC_10 BF28 VCC_SM_20 VCC_AXG_NCTF_21 R21
1 AM40 VCC_11 BD28 VCC_SM_21 VCC_AXG_NCTF_22 AM19
1
1 1 AL40 VCC_12 Place close to GMCH Place on the edge BB28 VCC_SM_22 VCC_AXG_NCTF_23 AL19
C124
C125
C126
+ BL27 AH19
VCC_SM_23 VCC_AXG_NCTF_24
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.47U_0402_10V4Z~D
1U_0603_10V4Z~D
10U_0805_6.3VAM~D
22U_0805_6.3V6M~D
AJ40 VCC_13 BJ27 VCC_SM_24 VCC_AXG_NCTF_25 AG19
AH40 VCC_14 BG27 VCC_SM_25 VCC_AXG_NCTF_26 AE19
2 2 2
VCC CORE
AG40 BE27 AD19 1 1 1 1 1 1
VCC SM
VCC_15 VCC_SM_26 VCC_AXG_NCTF_27
C129
C130
C127
C128
C131
C132
AE40 VCC_16 BC27 VCC_SM_27 VCC_AXG_NCTF_28 AC19
VCC GFX NCTF
AD40 VCC_17 BA27 VCC_SM_28 VCC_AXG_NCTF_29 W19
AC40 VCC_18 AY27 VCC_SM_29 VCC_AXG_NCTF_30 U19
2 2 2 2 2 2
AA40 VCC_19 AW26 VCC_SM_30 VCC_AXG_NCTF_31 AM18
Y40 +VCC_SM_BF24 BF24 AL18
VCC_20 +VCC_SM_BL19 VCC_SM_31 VCC_AXG_NCTF_32
AN35 VCC_21 BL19 VCC_SM_32 VCC_AXG_NCTF_33 AJ18
CRB 270uF AM35 +VCC_SM_BB16 BB16 AH18
VCC_22 VCC_SM_33 VCC_AXG_NCTF_34
0.22U_0402_10V4Z~D
0.1U_0402_10V7K~D
AJ35 VCC_23 VCC_AXG_NCTF_35 AG18
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
AH35 VCC_24 VCC_AXG_NCTF_36 AE18
AD35 +VCC_GFXCORE AD18
1 1 VCC_25 2 2 2 VCC_AXG_NCTF_37
C133
C134
C758
C759
C760
AC35 VCC_26 VCC_AXG_NCTF_38 AC18
W35 VCC_27 W32 VCC_AXG_1 VCC_AXG_NCTF_39 AA18
AM34 VCC_28 AG31 VCC_AXG_2 VCC_AXG_NCTF_40 Y18
C 2 2 1 1 1 C
AL34 VCC_29 AE31 VCC_AXG_3 VCC_AXG_NCTF_41 W18
AJ34 VCC_30 AD31 VCC_AXG_4 VCC_AXG_NCTF_42 U18
AH34 VCC_31 AC31 VCC_AXG_5 VCC_AXG_NCTF_43 T18
AG34 VCC_32 AA31 VCC_AXG_6 VCC_AXG_NCTF_44 R18
AE34 +1.05V_M Y31
VCC_33 VCC_AXG_7
AD34 VCC_34 W31 VCC_AXG_8
VCC_NCTF_1 AT38 AH29 VCC_AXG_9
POWER
AC34 VCC_35 VCC_NCTF_2 AR38 AG29 VCC_AXG_10
AA34 VCC_36 VCC_NCTF_3 AN38 AE29 VCC_AXG_11
VCC_NCTF_4 AM38 AD29 VCC_AXG_12 VCC_AXG_62 AJ16
Y34 VCC_37 VCC_NCTF_5 AL38 AC29 VCC_AXG_13 VCC_AXG_63 AH16
W34 VCC_38 VCC_NCTF_6 AG38 AA29 VCC_AXG_14 VCC_AXG_64 AD16
AM32 VCC_39 VCC_NCTF_7 AE38 Y29 VCC_AXG_15 VCC_AXG_65 AC16
AL32 VCC_40 VCC_NCTF_8 AA38 W29 VCC_AXG_16 VCC_AXG_66 AA16
AJ32 VCC_41 VCC_NCTF_9 Y38 AH28 VCC_AXG_17 VCC_AXG_67 U16
AH32 VCC_42 VCC_NCTF_10 W38 AG28 VCC_AXG_18 VCC_AXG_68 T16
AE32 U38 AE28 R16
VCC GFX
VCC_43 VCC_NCTF_11 VCC_AXG_19 VCC_AXG_69
AD32 VCC_44 VCC_NCTF_12 T38 AA28 VCC_AXG_20 VCC_AXG_70 AM15
AA32 VCC_45 VCC_NCTF_13 R38 AH27 VCC_AXG_21 VCC_AXG_71 AL15
AM31 VCC_46 VCC_NCTF_14 AT37 AG27 VCC_AXG_22 VCC_AXG_72 AJ15
AL31 VCC_47 VCC_NCTF_15 AR37 AE27 VCC_AXG_23 VCC_AXG_73 AH15
AJ31 VCC_48 VCC_NCTF_16 AN37 AD27 VCC_AXG_24 VCC_AXG_74 AG15
AH31 VCC_49 VCC_NCTF_17 AM37 AC27 VCC_AXG_25 VCC_AXG_75 AE15
AM29 VCC_50 VCC_NCTF_18 AL37 AA27 VCC_AXG_26 VCC_AXG_76 AA15
AL29 VCC_51 VCC_NCTF_19 AJ37 Y27 VCC_AXG_27 VCC_AXG_77 Y15
AM28 VCC_52 VCC_NCTF_20 AH37 W27 VCC_AXG_28 VCC_AXG_78 W15
AL28 VCC_53 VCC_NCTF_21 AG37 AH25 VCC_AXG_29 VCC_AXG_79 U15
AJ28 VCC_54 VCC_NCTF_22 AE37 AD25 VCC_AXG_30 VCC_AXG_80 T15
AM27 VCC_55 VCC_NCTF_23 AD37 AC25 VCC_AXG_31
AL27 VCC_56 VCC_NCTF_24 AC37 W25 VCC_AXG_32
AM25 VCC_57 VCC_NCTF_25 AA37 AJ24 VCC_AXG_33
VCC NCTF
AL25 VCC_58 VCC_NCTF_26 Y37 AH24 VCC_AXG_34
B B
AJ25 VCC_59 VCC_NCTF_27 W37 AG24 VCC_AXG_35
AM24 VCC_60 VCC_NCTF_28 U37 AE24 VCC_AXG_36
N36 VCC_61 VCC_NCTF_29 T37 AD24 VCC_AXG_37
R763 R37 AC24
VCC_NCTF_30 VCC_AXG_38
1 2 VCC_NCTF_31 AT35 AA24 VCC_AXG_39
VCC_NCTF_32 AR35 Y24 VCC_AXG_40
0_0402_5%~D U35 W24
VCC_NCTF_33 VCC_AXG_41
VCC_NCTF_34 AT34 AM22 VCC_AXG_42
VCC_NCTF_35 AR34 AL22 VCC_AXG_43
VCC_NCTF_36 U34 AJ22 VCC_AXG_44
T34 AH22
VCC GFX
VCC_NCTF_37 VCC_AXG_45
VCC_NCTF_38 R34 AG22 VCC_AXG_46
AE22 VCC_AXG_47
AD22 VCC_AXG_48
AC22 VCC_AXG_49
AA22 AU45 VCCSM_LF1
VCC_AXG_50 VCC_SM_LF1 VCCSM_LF2
AM21 BF52
VCC SM LF
VCC_AXG_51 VCC_SM_LF2 VCCSM_LF3
AL21 VCC_AXG_52 VCC_SM_LF3 BB38
AJ21 BA19 VCCSM_LF4
VCC_AXG_53 VCC_SM_LF4 VCCSM_LF5
AH21 VCC_AXG_54 VCC_SM_LF5 BE9
AD21 AU9 VCCSM_LF6
VCC_AXG_55 VCC_SM_LF6 VCCSM_LF7
AC21 VCC_AXG_56 VCC_SM_LF7 AL9
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
0.22U_0402_10V4Z~D
0.22U_0402_10V4Z~D
0.47U_0402_10V4Z~D
1U_0402_6.3V4Z~D
1U_0402_6.3V4Z~D
AA21 VCC_AXG_57
Y21 VCC_AXG_58
W21 VCC_AXG_59 1 1 1 1 1 1 1
C135
C136
C137
C138
C139
C140
C141
AM16 VCC_AXG_60
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D AL16 VCC_AXG_61
2 2 2 2 2 2 2
VCC_AXG_SENSE AG13
<44> VCC_AXG_SENSE VCC_AXG_SENSE
VSS_AXG_SENSE AE13
<44> VSS_AXG_SENSE VSS_AXG_SENSE
A A
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga GS(5/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 14 of 49
5 4 3 2 1
5 4 3 2 1
U78I U78J
BA55 VSS_1 VSS_100 C43 AN25 VSS_199 VSS_300 AM8
AU55 VSS_2 VSS_101 A43 AG25 VSS_200 VSS_301 AK8
AN55 VSS_3 VSS_102 BD42 AE25 VSS_201 VSS_302 AH8
AJ55 VSS_4 VSS_103 H42 AA25 VSS_202 VSS_303 AF8
AE55 VSS_5 VSS_104 BG41 Y25 VSS_203 VSS_304 AD8
AA55 VSS_6 VSS_105 AY41 E25 VSS_204 VSS_305 AB8
U55 VSS_7 VSS_106 AU41 A25 VSS_205 VSS_306 Y8
N55 VSS_8 VSS_107 AM41 BD24 VSS_206 VSS_307 V8
BD54 VSS_9 VSS_108 AL41 AN24 VSS_207 VSS_308 P8
BG53 VSS_10 VSS_109 AG41 AL24 VSS_208 VSS_309 M8
D D
AJ53 VSS_11 VSS_110 AE41 H24 VSS_209 VSS_310 K8
AE53 VSS_12 VSS_111 AA41 BG23 VSS_210 VSS_311 H8
AA53 VSS_13 VSS_112 R41 AY23 VSS_211 VSS_312 BJ7
U53 VSS_14 VSS_113 M41 E23 VSS_212 VSS_313 E7
N53 VSS_15 VSS_114 E41 BD22 VSS_213 VSS_314 BF6
J53 VSS_16 VSS_115 BD40 BB22 VSS_214 VSS_315 BC5
G53 VSS_17 VSS_116 AU40 AN22 VSS_215 VSS_316 BA5
E53 VSS_18 VSS_117 AR40 Y22 VSS_216 VSS_317 AW5
K52 VSS_19 VSS_118 AN40 W22 VSS_217 VSS_318 AU5
BG51 VSS_20 VSS_119 W40 H22 VSS_218 VSS_319 AR5
BA51 VSS_21 VSS_120 U40 BL21 VSS_219 VSS_320 AN5
AW51 VSS_22 VSS_121 T40 BG21 VSS_220 VSS_321 AL5
AU51 VSS_23 VSS_122 R40 AY21 VSS_221 VSS_322 AJ5
AR51 VSS_24 VSS_123 K40 AN21 VSS_222 VSS_323 AG5
AN51 VSS_25 VSS_124 H40 AG21 VSS_223 VSS_324 AE5
AL51 VSS_26 VSS_125 BL39 AE21 VSS_224 VSS_325 AC5
AJ51 VSS_27 VSS_126 BG39 M21 VSS_225 VSS_326 AA5
AG51 VSS_28 VSS_127 BA39 E21 VSS_226 VSS_327 W5
AE51 VSS_29 VSS_128 E39 A21 VSS_227 VSS_328 U5
AC51 VSS_30 VSS_129 C39 BD20 VSS_228 VSS_329 N5
AA51 A39 H20 L5
W51
U51
VSS_31
VSS_32
VSS_130
VSS_131 BD38
AU38
BG19
AY19
VSS_229
VSS_230 VSS VSS_330
VSS_331 J5
G5
R51
N51
VSS_33
VSS_34
VSS_35
VSS VSS_132
VSS_133
VSS_134
H38
BG37
M19
E19
VSS_231
VSS_232
VSS_233
VSS_332
VSS_333
VSS_334
C5
BH4
L51 VSS_36 VSS_135 AU37 BD18 VSS_234 VSS_335 BE3
J51 VSS_37 VSS_136 M37 N18 VSS_235 VSS_336 U3
G51 VSS_38 VSS_137 E37 H18 VSS_236 VSS_337 E3
C51 VSS_39 VSS_138 BD36 BL17 VSS_237 VSS_338 BC1
BK50 VSS_40 VSS_139 AW36 BG17 VSS_238 VSS_339 AW1
AM50 VSS_41 VSS_140 H36 AY17 VSS_239 VSS_340 AR1
K50 VSS_42 VSS_141 BL35 M17 VSS_240 VSS_341 AL1
C C
BG49 VSS_43 VSS_142 BG35 E17 VSS_241 VSS_342 AG1
E49 VSS_44 VSS_143 AY35 A17 VSS_242 VSS_343 AC1
C49 VSS_45 VSS_144 AU35 BD16 VSS_243 VSS_344 W1
BD48 VSS_46 VSS_145 AL35 AN16 VSS_244 VSS_345 N1
BB48 VSS_47 VSS_146 AG35 AG16 VSS_245 VSS_346 J1
AY48 VSS_48 VSS_147 AE35 AE16 VSS_246 VSS_347 AU43
AV48 VSS_49 VSS_148 AA35 Y16 VSS_247 VSS_348 BB42
AT48 VSS_50 VSS_149 Y35 W16 VSS_248 VSS_349 AW38
AP48 VSS_51 VSS_150 M35 N16 VSS_249 VSS_350 BA35
AM48 VSS_52 VSS_151 E35 H16 VSS_250 VSS_351 L29
AK48 VSS_53 VSS_152 A35 BG15 VSS_251 VSS_352 N28
AH48 VSS_54 VSS_153 BD34 AY15 VSS_252 VSS_353 N22
AF48 VSS_55 VSS_154 AU34 AN15 VSS_253 VSS_354 N20
AD48 VSS_56 VSS_155 AN34 AD15 VSS_254 VSS_355 N14
AB48 VSS_57 VSS_156 H34 AC15 VSS_255 VSS_356 AL13
Y48 VSS_58 VSS_157 BL33 R15 VSS_256 VSS_357 B10
V48 VSS_59 VSS_158 BG33 M15 VSS_257 VSS_358 AN13
T48 VSS_60 VSS_159 AY33 E15 VSS_258
P48 VSS_61 VSS_160 E33 BD14 VSS_259 VSS_359 N42
M48 VSS_62 VSS_161 BD32 H14 VSS_260 VSS_360 N40
K48 VSS_63 VSS_162 AU32 BL13 VSS_261 VSS_361 N38
H48 VSS_64 VSS_163 AN32 BG13 VSS_262 VSS_362 M39
BL47 VSS_65 VSS_164 AG32 AY13 VSS_263
BG47 VSS_66 VSS_165 AC32 AU13 VSS_264
E47 VSS_67 VSS_166 Y32 AR13 VSS_265 VSS_NCTF_1 AJ38
C47 VSS_68 VSS_167 H32 AJ13 VSS_266 VSS_NCTF_2 AH38
A47 VSS_69 VSS_168 B32 AC13 VSS_267 VSS_NCTF_3 AD38
BD46 VSS_70 VSS_169 BJ31 AA13 VSS_268 VSS_NCTF_4 AC38
AY46 VSS_71 VSS_170 BG31 W13 VSS_269 VSS_NCTF_5 T35
AM46 VSS_72 VSS_171 AY31 U13 VSS_270 VSS_NCTF_6 R35
VSS NCTF
AK46 VSS_73 VSS_172 AN31 M13 VSS_271 VSS_NCTF_7 AT32
AH46 VSS_74 VSS_173 M31 E13 VSS_272 VSS_NCTF_8 AR32
B B
BG45 VSS_75 VSS_174 E31 A13 VSS_273 VSS_NCTF_9 U32
AE45 VSS_76 VSS_175 N30 BD12 VSS_274 VSS_NCTF_10 R32
AC45 VSS_77 VSS_176 H30 AV12 VSS_275 VSS_NCTF_11 T28
AA45 VSS_78 VSS_177 AN29 AP12 VSS_276 VSS_NCTF_12 R28
W45 VSS_79 VSS_178 AJ29 AM12 VSS_277 VSS_NCTF_13 AT25
R45 VSS_80 VSS_179 M29 AK12 VSS_278 VSS_NCTF_14 AR25
N45 VSS_81 VSS_180 A29 AB12 VSS_279 VSS_NCTF_15 T24
E45 VSS_82 VSS_181 AW28 V12 VSS_280 VSS_NCTF_16 R24
BD44 VSS_83 VSS_182 AN28 P12 VSS_281 VSS_NCTF_17 AN19
BB44 VSS_84 VSS_183 AD28 H12 VSS_282 VSS_NCTF_18 AJ19
AV44 VSS_85 VSS_184 AC28 BG11 VSS_283 VSS_NCTF_19 AA19
AK44 VSS_86 VSS_185 Y28 AG11 VSS_284 VSS_NCTF_20 Y19
AH44 VSS_87 VSS_186 W28 E11 VSS_285 VSS_NCTF_21 T19
AF44 VSS_88 VSS_187 H28 BD10 VSS_286 VSS_NCTF_22 R19
AD44 VSS_89 VSS_188 F28 AY10 VSS_287 VSS_NCTF_23 AN18
K44 VSS_90 VSS_189 AN27 AP10 VSS_288
H44 VSS_91 VSS_190 AJ27 H10 VSS_289
BL43 VSS_92 VSS_191 M27 BL9 VSS_290
BG43 VSS_93 VSS_192 BF26 BG9 VSS_291
AY43 VSS_94 VSS_193 BD26 E9 VSS_292
AR43 VSS_95 VSS_194 N26 A9 VSS_293 VSS_SCB_1 BL55
W43 VSS_96 VSS_195 H26 BD8 VSS_294 VSS_SCB_2 BL1
VSS SCB
R43 VSS_97 VSS_196 BJ25 BB8 VSS_295 VSS_SCB_3 A55
M43 VSS_98 VSS_197 AY25 AY8 VSS_296 VSS_SCB_4 D1
E43 VSS_99 VSS_198 AU25 AV8 VSS_297 VSS_SCB_5 B55
AT8 VSS_298 VSS_SCB_6 B2
AP8 VSS_299 VSS_SCB_7 A4
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
CANTIGA GMCH SFF_QR46 B0_FCBGA1363~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Cantiga GS(6/6)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 15 of 49
5 4 3 2 1
5 4 3 2 1
+1.5V_MEM +1.5V_MEM +1.5V_MEM +1.5V_MEM
U4 U5 U6 U7
<11> DDR_A_DQS0 F4 DQS VDDQ E10 <11> DDR_A_DQS2 F4 DQS VDDQ E10 <11> DDR_A_DQS4 F4 DQS VDDQ E10 <11> DDR_A_DQS6 F4 DQS VDDQ E10
<11> DDR_A_DQS#0 G4 DQS# VDDQ F2 <11> DDR_A_DQS#2 G4 DQS# VDDQ F2 <11> DDR_A_DQS#4 G4 DQS# VDDQ F2 <11> DDR_A_DQS#6 G4 DQS# VDDQ F2
<11> DDR_A_D[0..7] VDDQ H3 <11> DDR_A_D[16..23] VDDQ H3 <11> DDR_A_D[32..39] VDDQ H3 <11> DDR_A_D[48..55] VDDQ H3
DDR_A_D1 E4 H10 DDR_A_D21 E4 H10 DDR_A_D39 E4 H10 DDR_A_D54 E4 H10
D DDR_A_D7 DQ0 VDDQ DDR_A_D18 DQ0 VDDQ DDR_A_D34 DQ0 VDDQ DDR_A_D51 DQ0 VDDQ D
F8 DQ1 F8 DQ1 F8 DQ1 F8 DQ1
DDR_A_D0 F3 D3 DDR_A_D17 F3 D3 DDR_A_D32 F3 D3 DDR_A_D49 F3 D3
DDR_A_D6 DQ2 VDD DDR_A_D19 DQ2 VDD DDR_A_D35 DQ2 VDD DDR_A_D50 DQ2 VDD
F9 DQ3 VDD D10 F9 DQ3 VDD D10 F9 DQ3 VDD D10 F9 DQ3 VDD D10
DDR_A_D4 H4 G8 DDR_A_D22 H4 G8 DDR_A_D36 H4 G8 DDR_A_D52 H4 G8
DDR_A_D3 DQ4 VDD DDR_A_D16 DQ4 VDD DDR_A_D33 DQ4 VDD DDR_A_D48 DQ4 VDD
H9 DQ5 VDD K3 H9 DQ5 VDD K3 H9 DQ5 VDD K3 H9 DQ5 VDD K3
DDR_A_D5 G3 K9 DDR_A_D20 G3 K9 DDR_A_D37 G3 K9 DDR_A_D53 G3 K9
DDR_A_D2 DQ6 VDD DDR_A_D23 DQ6 VDD DDR_A_D38 DQ6 VDD DDR_A_D55 DQ6 VDD
H8 DQ7 VDD N2 H8 DQ7 VDD N2 H8 DQ7 VDD N2 H8 DQ7 VDD N2
VDD N10 VDD N10 VDD N10 VDD N10
D8 NU/TDQS# VDD R2 D8 NU/TDQS# VDD R2 D8 NU/TDQS# VDD R2 D8 NU/TDQS# VDD R2
<11> DDR_A_DM0 E8 DM/TDQS VDD R10 <11> DDR_A_DM2 E8 DM/TDQS VDD R10 <11> DDR_A_DM4 E8 DM/TDQS VDD R10 <11> DDR_A_DM6 E8 DM/TDQS VDD R10
1 2 L9 ZQ 1 2 L9 ZQ 1 2 L9 ZQ 1 2 L9 ZQ
R154 240_0402_5%~D K2 M_ODT0 R155 240_0402_5%~D K2 M_ODT0 R156 240_0402_5%~D K2 M_ODT0 R157 240_0402_5%~D K2 M_ODT0
ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0
+V_DDR_MCH_REF H2 VREFDQ CK J8 +V_DDR_MCH_REF H2 VREFDQ CK J8 +V_DDR_MCH_REF H2 VREFDQ CK J8 +V_DDR_MCH_REF H2 VREFDQ CK J8
M9 K8 M_CLK_DDR#0 M9 K8 M_CLK_DDR#0 M9 K8 M_CLK_DDR#0 M9 K8 M_CLK_DDR#0
VREFCA CK# DDR_CKE0 VREFCA CK# DDR_CKE0 VREFCA CK# DDR_CKE0 VREFCA CK# DDR_CKE0
CKE K10 CKE K10 CKE K10 CKE K10
DDR_A_MA0 N4 DDR_A_MA0 N4 DDR_A_MA0 N4 DDR_A_MA0 N4
DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0
P8 A1 BA0 M3 P8 A1 BA0 M3 P8 A1 BA0 M3 P8 A1 BA0 M3
DDR_A_MA2 P4 N9 DDR_A_BS1 DDR_A_MA2 P4 N9 DDR_A_BS1 DDR_A_MA2 P4 N9 DDR_A_BS1 DDR_A_MA2 P4 N9 DDR_A_BS1
DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2
N3 A3 BA2 M4 N3 A3 BA2 M4 N3 A3 BA2 M4 N3 A3 BA2 M4
DDR_A_MA4 P9 DDR_A_MA4 P9 DDR_A_MA4 P9 DDR_A_MA4 P9
DDR_A_MA5 A4 DDR_CS#0 DDR_A_MA5 A4 DDR_CS#0 DDR_A_MA5 A4 DDR_CS#0 DDR_A_MA5 A4 DDR_CS#0
P3 A5 CS# L3 P3 A5 CS# L3 P3 A5 CS# L3 P3 A5 CS# L3
DDR_A_MA6 R9 J4 DDR_A_RAS# DDR_A_MA6 R9 J4 DDR_A_RAS# DDR_A_MA6 R9 J4 DDR_A_RAS# DDR_A_MA6 R9 J4 DDR_A_RAS#
DDR_A_MA7 A6 RAS# DDR_A_CAS# DDR_A_MA7 A6 RAS# DDR_A_CAS# DDR_A_MA7 A6 RAS# DDR_A_CAS# DDR_A_MA7 A6 RAS# DDR_A_CAS#
R3 A7 CAS# K4 R3 A7 CAS# K4 R3 A7 CAS# K4 R3 A7 CAS# K4
DDR_A_MA8 T9 L4 DDR_A_WE# DDR_A_MA8 T9 L4 DDR_A_WE# DDR_A_MA8 T9 L4 DDR_A_WE# DDR_A_MA8 T9 L4 DDR_A_WE#
DDR_A_MA9 A8 WE# DDR3_DRAMRST# DDR_A_MA9 A8 WE# DDR3_DRAMRST# DDR_A_MA9 A8 WE# DDR3_DRAMRST# DDR_A_MA9 A8 WE# DDR3_DRAMRST#
R4 A9 RESET# T3 R4 A9 RESET# T3 R4 A9 RESET# T3 R4 A9 RESET# T3
DDR_A_MA10 L8 DDR_A_MA10 L8 DDR_A_MA10 L8 DDR_A_MA10 L8
DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP
R8 A11 VSSQ E3 R8 A11 VSSQ E3 R8 A11 VSSQ E3 R8 A11 VSSQ E3
DDR_A_MA12 N8 E9 DDR_A_MA12 N8 E9 DDR_A_MA12 N8 E9 DDR_A_MA12 N8 E9
DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ
T4 A13 VSSQ F10 T4 A13 VSSQ F10 T4 A13 VSSQ F10 T4 A13 VSSQ F10
VSSQ G2 VSSQ G2 VSSQ G2 VSSQ G2
A1 NC VSSQ G10 A1 NC VSSQ G10 A1 NC VSSQ G10 A1 NC VSSQ G10
A2 NC VSS D2 A2 NC VSS D2 A2 NC VSS D2 A2 NC VSS D2
C C
A4 NC VSS D9 A4 NC VSS D9 A4 NC VSS D9 A4 NC VSS D9
A8 NC VSS E2 A8 NC VSS E2 A8 NC VSS E2 A8 NC VSS E2
A10 NC VSS G9 A10 NC VSS G9 A10 NC VSS G9 A10 NC VSS G9
A11 NC VSS J3 A11 NC VSS J3 A11 NC VSS J3 A11 NC VSS J3
D1 NC VSS J9 D1 NC VSS J9 D1 NC VSS J9 D1 NC VSS J9
D4 NC VSS M2 D4 NC VSS M2 D4 NC VSS M2 D4 NC VSS M2
D11 NC VSS M10 D11 NC VSS M10 D11 NC VSS M10 D11 NC VSS M10
J2 NC VSS P2 J2 NC VSS P2 J2 NC VSS P2 J2 NC VSS P2
J10 NC VSS P10 J10 NC VSS P10 J10 NC VSS P10 J10 NC VSS P10
L2 NC VSS T2 L2 NC VSS T2 L2 NC VSS T2 L2 NC VSS T2
L10 NC VSS T10 L10 NC VSS T10 L10 NC VSS T10 L10 NC VSS T10
M8 NC M8 NC M8 NC M8 NC
T1 NC T1 NC T1 NC T1 NC
DDR_A_MA14 T8 DDR_A_MA14 T8 DDR_A_MA14 T8 DDR_A_MA14 T8
NC NC NC NC
T11 NC T11 NC T11 NC T11 NC
W1 NC W1 NC W1 NC W1 NC
W2 NC W2 NC W2 NC W2 NC
W4 NC W4 NC W4 NC W4 NC
W8 NC W8 NC W8 NC W8 NC
W10 NC W10 NC W10 NC W10 NC
W11 NC W11 NC W11 NC W11 NC
K4B1G0846C-ZCF7_FBGA94~D K4B1G0846C-ZCF7_FBGA94~D K4B1G0846C-ZCF7_FBGA94~D K4B1G0846C-ZCF7_FBGA94~D
+1.5V_MEM +1.5V_MEM
B B
Place close to GMCH Place the end of the DDR3
<11,17> DDR_A_MA[0..14]
330U_D2_2.5VY_R15M
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
<10,17> M_ODT0 M_ODT0 1 M_CLK_DDR0
1 1 1 1 1 1
1
C159
C143
C144
C145
C146
C147
C148
M_CLK_DDR0 +
<10,17> M_CLK_DDR0 2 2 2 2 2 2 2 2
C164
C165
C166
C167
C168
C169
C170
C171
R152
M_CLK_DDR#0 30_0402_1%~D
<10,17> M_CLK_DDR#0 2 2 2 2 2 2 2
3.3P_0402_50V8C~D
DDR_CKE0 1 1 1 1 1 1 1 1
<10,17> DDR_CKE0 1
2
C142
DDR_A_BS0 M_CLK_DDR0_TERM
<11,17> DDR_A_BS0
0.1U_0402_10V7K~D
DDR_A_BS1 2
<11,17> DDR_A_BS1 1
1
+V_DDR_MCH_REF
C149
DDR_A_BS2
<11,17> DDR_A_BS2
R153
DDR_CS#0 30_0402_1%~D 2
<10,17> DDR_CS#0
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
DDR_A_RAS# M_CLK_DDR#0
<11,17> DDR_A_RAS#
1 1 1 1 1 1 1 1 1 1
C152
C160
C150
C151
C153
C154
C155
C156
C157
C158
DDR_A_CAS#
<11,17> DDR_A_CAS#
DDR_A_WE#
<11,17> DDR_A_WE# 2 2 2 2 2 2 2 2 2 2
DDR3_DRAMRST#
<10,17,18> DDR3_DRAMRST#
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-Memory Down (Top)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 16 of 49
5 4 3 2 1
5 4 3 2 1
+1.5V_MEM +1.5V_MEM +1.5V_MEM +1.5V_MEM
U8 U9 U10 U11
<11> DDR_A_DQS1 F4 DQS VDDQ E10 <11> DDR_A_DQS3 F4 DQS VDDQ E10 <11> DDR_A_DQS5 F4 DQS VDDQ E10 <11> DDR_A_DQS7 F4 DQS VDDQ E10
<11> DDR_A_DQS#1 G4 DQS# VDDQ F2 <11> DDR_A_DQS#3 G4 DQS# VDDQ F2 <11> DDR_A_DQS#5 G4 DQS# VDDQ F2 <11> DDR_A_DQS#7 G4 DQS# VDDQ F2
<11> DDR_A_D[8..15] VDDQ H3 <11> DDR_A_D[24..31] VDDQ H3 <11> DDR_A_D[40..47] VDDQ H3 <11> DDR_A_D[56..63] VDDQ H3
DDR_A_D10 E4 H10 DDR_A_D27 E4 H10 DDR_A_D42 E4 H10 DDR_A_D58 E4 H10
D DDR_A_D13 DQ0 VDDQ DDR_A_D30 DQ0 VDDQ DDR_A_D41 DQ0 VDDQ DDR_A_D61 DQ0 VDDQ D
F8 DQ1 F8 DQ1 F8 DQ1 F8 DQ1
DDR_A_D11 F3 D3 DDR_A_D26 F3 D3 DDR_A_D43 F3 D3 DDR_A_D59 F3 D3
DDR_A_D8 DQ2 VDD DDR_A_D25 DQ2 VDD DDR_A_D47 DQ2 VDD DDR_A_D60 DQ2 VDD
F9 DQ3 VDD D10 F9 DQ3 VDD D10 F9 DQ3 VDD D10 F9 DQ3 VDD D10
DDR_A_D9 H4 G8 DDR_A_D31 H4 G8 DDR_A_D46 H4 G8 DDR_A_D63 H4 G8
DDR_A_D14 DQ4 VDD DDR_A_D28 DQ4 VDD DDR_A_D40 DQ4 VDD DDR_A_D57 DQ4 VDD
H9 DQ5 VDD K3 H9 DQ5 VDD K3 H9 DQ5 VDD K3 H9 DQ5 VDD K3
DDR_A_D12 G3 K9 DDR_A_D24 G3 K9 DDR_A_D44 G3 K9 DDR_A_D62 G3 K9
DDR_A_D15 DQ6 VDD DDR_A_D29 DQ6 VDD DDR_A_D45 DQ6 VDD DDR_A_D56 DQ6 VDD
H8 DQ7 VDD N2 H8 DQ7 VDD N2 H8 DQ7 VDD N2 H8 DQ7 VDD N2
VDD N10 VDD N10 VDD N10 VDD N10
D8 NU/TDQS# VDD R2 D8 NU/TDQS# VDD R2 D8 NU/TDQS# VDD R2 D8 NU/TDQS# VDD R2
<11> DDR_A_DM1 E8 DM/TDQS VDD R10 <11> DDR_A_DM3 E8 DM/TDQS VDD R10 <11> DDR_A_DM5 E8 DM/TDQS VDD R10 <11> DDR_A_DM7 E8 DM/TDQS VDD R10
1 2 L9 ZQ 1 2 L9 ZQ 1 2 L9 ZQ 1 2 L9 ZQ
R158 240_0402_5%~D K2 M_ODT0 R159 240_0402_5%~D K2 M_ODT0 R160 240_0402_5%~D K2 M_ODT0 R161 240_0402_5%~D K2 M_ODT0
ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0 ODT M_CLK_DDR0
+V_DDR_MCH_REF H2 VREFDQ CK J8 +V_DDR_MCH_REF H2 VREFDQ CK J8 +V_DDR_MCH_REF H2 VREFDQ CK J8 +V_DDR_MCH_REF H2 VREFDQ CK J8
M9 K8 M_CLK_DDR#0 M9 K8 M_CLK_DDR#0 M9 K8 M_CLK_DDR#0 M9 K8 M_CLK_DDR#0
VREFCA CK# DDR_CKE0 VREFCA CK# DDR_CKE0 VREFCA CK# DDR_CKE0 VREFCA CK# DDR_CKE0
CKE K10 CKE K10 CKE K10 CKE K10
DDR_A_MA0 N4 DDR_A_MA0 N4 DDR_A_MA0 N4 DDR_A_MA0 N4
DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0 DDR_A_MA1 A0 DDR_A_BS0
P8 A1 BA0 M3 P8 A1 BA0 M3 P8 A1 BA0 M3 P8 A1 BA0 M3
DDR_A_MA2 P4 N9 DDR_A_BS1 DDR_A_MA2 P4 N9 DDR_A_BS1 DDR_A_MA2 P4 N9 DDR_A_BS1 DDR_A_MA2 P4 N9 DDR_A_BS1
DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2 DDR_A_MA3 A2 BA1 DDR_A_BS2
N3 A3 BA2 M4 N3 A3 BA2 M4 N3 A3 BA2 M4 N3 A3 BA2 M4
DDR_A_MA4 P9 DDR_A_MA4 P9 DDR_A_MA4 P9 DDR_A_MA4 P9
DDR_A_MA5 A4 DDR_CS#0 DDR_A_MA5 A4 DDR_CS#0 DDR_A_MA5 A4 DDR_CS#0 DDR_A_MA5 A4 DDR_CS#0
P3 A5 CS# L3 P3 A5 CS# L3 P3 A5 CS# L3 P3 A5 CS# L3
DDR_A_MA6 R9 J4 DDR_A_RAS# DDR_A_MA6 R9 J4 DDR_A_RAS# DDR_A_MA6 R9 J4 DDR_A_RAS# DDR_A_MA6 R9 J4 DDR_A_RAS#
DDR_A_MA7 A6 RAS# DDR_A_CAS# DDR_A_MA7 A6 RAS# DDR_A_CAS# DDR_A_MA7 A6 RAS# DDR_A_CAS# DDR_A_MA7 A6 RAS# DDR_A_CAS#
R3 A7 CAS# K4 R3 A7 CAS# K4 R3 A7 CAS# K4 R3 A7 CAS# K4
DDR_A_MA8 T9 L4 DDR_A_WE# DDR_A_MA8 T9 L4 DDR_A_WE# DDR_A_MA8 T9 L4 DDR_A_WE# DDR_A_MA8 T9 L4 DDR_A_WE#
DDR_A_MA9 A8 WE# DDR3_DRAMRST# DDR_A_MA9 A8 WE# DDR3_DRAMRST# DDR_A_MA9 A8 WE# DDR3_DRAMRST# DDR_A_MA9 A8 WE# DDR3_DRAMRST#
R4 A9 RESET# T3 R4 A9 RESET# T3 R4 A9 RESET# T3 R4 A9 RESET# T3
DDR_A_MA10 L8 DDR_A_MA10 L8 DDR_A_MA10 L8 DDR_A_MA10 L8
DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP DDR_A_MA11 A10/AP
R8 A11 VSSQ E3 R8 A11 VSSQ E3 R8 A11 VSSQ E3 R8 A11 VSSQ E3
DDR_A_MA12 N8 E9 DDR_A_MA12 N8 E9 DDR_A_MA12 N8 E9 DDR_A_MA12 N8 E9
DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ DDR_A_MA13 A12/BC# VSSQ
T4 A13 VSSQ F10 T4 A13 VSSQ F10 T4 A13 VSSQ F10 T4 A13 VSSQ F10
VSSQ G2 VSSQ G2 VSSQ G2 VSSQ G2
A1 NC VSSQ G10 A1 NC VSSQ G10 A1 NC VSSQ G10 A1 NC VSSQ G10
A2 NC VSS D2 A2 NC VSS D2 A2 NC VSS D2 A2 NC VSS D2
C C
A4 NC VSS D9 A4 NC VSS D9 A4 NC VSS D9 A4 NC VSS D9
A8 NC VSS E2 A8 NC VSS E2 A8 NC VSS E2 A8 NC VSS E2
A10 NC VSS G9 A10 NC VSS G9 A10 NC VSS G9 A10 NC VSS G9
A11 NC VSS J3 A11 NC VSS J3 A11 NC VSS J3 A11 NC VSS J3
D1 NC VSS J9 D1 NC VSS J9 D1 NC VSS J9 D1 NC VSS J9
D4 NC VSS M2 D4 NC VSS M2 D4 NC VSS M2 D4 NC VSS M2
D11 NC VSS M10 D11 NC VSS M10 D11 NC VSS M10 D11 NC VSS M10
J2 NC VSS P2 J2 NC VSS P2 J2 NC VSS P2 J2 NC VSS P2
J10 NC VSS P10 J10 NC VSS P10 J10 NC VSS P10 J10 NC VSS P10
L2 NC VSS T2 L2 NC VSS T2 L2 NC VSS T2 L2 NC VSS T2
L10 NC VSS T10 L10 NC VSS T10 L10 NC VSS T10 L10 NC VSS T10
M8 NC M8 NC M8 NC M8 NC
T1 NC T1 NC T1 NC T1 NC
DDR_A_MA14 T8 DDR_A_MA14 T8 DDR_A_MA14 T8 DDR_A_MA14 T8
NC NC NC NC
T11 NC T11 NC T11 NC T11 NC
W1 NC W1 NC W1 NC W1 NC
W2 NC W2 NC W2 NC W2 NC
W4 NC W4 NC W4 NC W4 NC
W8 NC W8 NC W8 NC W8 NC
W10 NC W10 NC W10 NC W10 NC
W11 NC W11 NC W11 NC W11 NC
K4B1G0846C-ZCF7_FBGA94~D K4B1G0846C-ZCF7_FBGA94~D K4B1G0846C-ZCF7_FBGA94~D K4B1G0846C-ZCF7_FBGA94~D
+V_DDR_MCH_REF
DDR3 Terminations
2.2U_0603_6.3V6K~D
2.2U_0603_6.3V6K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
B +0.75V_DDR_VTT B
<11,16> DDR_A_MA[0..14] 1 1 1 1 1 1 1 1 1 1
C161
C196
C190
C191
C192
C193
C194
C195
C197
C198
RP1 RP2
<10,16> M_ODT0 M_ODT0 DDR_A_CAS# 1 4 1 4 DDR_A_RAS#
DDR_CKE0 2 3 2 3 M_ODT0
M_CLK_DDR0 2 2 2 2 2 2 2 2 2 2
<10,16> M_CLK_DDR0
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
M_CLK_DDR#0 RP3 RP4
<10,16> M_CLK_DDR#0
DDR_CS#0 1 4 1 4 DDR_A_MA2 +0.75V_DDR_VTT
DDR_CKE0 DDR_A_WE# 2 3 2 3 DDR_A_MA3
<10,16> DDR_CKE0
DDR_A_BS0 36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
<11,16> DDR_A_BS0
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
RP5 RP6
DDR_A_BS1 DDR_A_MA12 1 4 1 4 DDR_A_MA6
<11,16> DDR_A_BS1
DDR_A_BS1 2 3 2 3 DDR_A_MA8 2 2 2 2 2 2
C183
DDR_A_BS2
<11,16> DDR_A_BS2 +3.3V_M
C184
C185
C186
C187
C188
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
DDR_CS#0 C199 RP7 RP8
<10,16> DDR_CS#0 1 1 1 1 1 1
1 2 DDR_A_MA10 1 4 1 4 DDR_A_MA5
DDR_A_RAS# U2 DDR_A_BS2 2 3 2 3 DDR_A_MA9
<11,16> DDR_A_RAS#
1 8 @ 0.1U_0402_16V4Z~D
DDR_A_CAS# A0 VCC 36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
<11,16> DDR_A_CAS# 2 A1 WP 7
@ 1K_0402_5%~D
@ 1K_0402_5%~D
3 6 MEM_SCLK RP9 RP10
A2 SCL MEM_SCLK <18,24>
1
DDR_A_WE# 4 5 MEM_SDATA DDR_A_BS0 1 4 1 4 DDR_A_MA11
<11,16> DDR_A_WE# GND SDA MEM_SDATA <18,24>
R163
DDR_A_MA0 2 3 2 3 DDR_A_MA14 Place decaps close end termination resistors, one decap for 4 resistors
R162
DDR3_DRAMRST# @ AT24C02N-10SU-2.7_SO8
<10,16,18> DDR3_DRAMRST#
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
RP11 RP12
2
DDR_A_MA4 1 4 1 4 DDR_A_MA7
DDR_A_MA1 2 3 2 3 DDR_A_MA13
36_0404_4P2R_5%~D 36_0404_4P2R_5%~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII-Memory Down (Bottom)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 17 of 49
5 4 3 2 1
5 4 3 2 1
+1.5V_MEM +1.5V_MEM +V_DDR_MCH_REF
+V_DDR_MCH_REF
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
JDIMM
1 VREF_DQ VSS 2
3 4 DDR_B_D4 1 1
VSS DQ4
C201
C200
DDR_B_D0 5 6 DDR_B_D5
<11> DDR_B_D[0..63] DQ0 DQ5
DDR_B_D1 7 8
DQ1 VSS DDR_B_DQS#0
9 VSS DQS0# 10
DDR_B_DM0 DDR_B_DQS0 2 2
<11> DDR_B_DQS[0..7] 11 DM0 DQS0 12
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6
D DDR_B_D3 DQ2 DQ6 DDR_B_D7 D
<11> DDR_B_DQS#[0..7] 17 DQ3 DQ7 18
19 VSS VSS 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
<11> DDR_B_DM[0..7] 23 DQ9 DQ13 24
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1 DDR3_DRAMRST#
<11> DDR_B_MA[0..14] 29 DQS1 RESET# 30 DDR3_DRAMRST# <10,16,17>
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20 Place close to SO-DIMM
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2 +1.5V_MEM
47 DQS2 VSS 48
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23
51 DQ18 DQ23 52
330U_D2_2.5VY_R15M
DDR_B_D19 53 54
DQ19 VSS
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
55 56 DDR_B_D28
DDR_B_D24 VSS DQ28 DDR_B_D29
57 DQ24 DQ29 58 1
DDR_B_D25 59 60 1 1 1 1 1 1
DQ25 VSS
C162
C202
C203
C204
C205
C206
C207
61 62 DDR_B_DQS#3 +
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66
DDR_B_D26 DDR_B_D30 2 2 2 2 2 2 2
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
71 VSS VSS 72
DDR_CKE2_DIMM 73 74 DDR_CKE3_DIMM
<10> DDR_CKE2_DIMM CKE0 CKE1 DDR_CKE3_DIMM <10>
75 VDD VDD 76
C C
77 NC A15 78 T41
DDR_B_BS2 79 80 DDR_B_MA14
<11> DDR_B_BS2 BA2 A14
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11 1 1 1 1
A12/BC# A11
C163
C208
C209
C210
DDR_B_MA9 85 86 DDR_B_MA7
A9 A7
87 VDD VDD 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4 2 2 2 2
91 A5 A4 92
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
M_CLK_DDR2 101 102 M_CLK_DDR3
<10> M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 <10>
M_CLK_DDR#2 103 104 M_CLK_DDR#3
<10> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <10>
105 VDD VDD 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 <11>
DDR_B_BS0 109 110 DDR_B_RAS#
<11> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <11>
111 VDD VDD 112
DDR_B_WE# 113 114 DDR_CS2_DIMM#
<11> DDR_B_WE# WE# S0# DDR_CS2_DIMM# <10>
DDR_B_CAS# 115 116 M_ODT2_DIMM
<11> DDR_B_CAS# CAS# ODT0 M_ODT2_DIMM <10>
117 VDD VDD 118
DDR_B_MA13 119 120 M_ODT3_DIMM
A13 ODT1 M_ODT3_DIMM <10>
DDR_CS3_DIMM# 121 122 +0.75V_DDR_VTT
<10> DDR_CS3_DIMM# S1# NC
123 VDD VDD 124
125 126 +V_DDR_MCH_REF +V_DDR_MCH_REF
T42 TEST VREF_CA
127 VSS VSS 128
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
DDR_B_D32 129 130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 DQ33 DQ37 132
133 VSS VSS 134 1 1 2 2 2 2
C212
C211
C213
C214
C215
C216
DDR_B_DQS#4 135 136 DDR_B_DM4
DDR_B_DQS4 DQS4# DM4
137 DQS4 VSS 138
139 140 DDR_B_D38
B DDR_B_D34 VSS DQ38 DDR_B_D39 2 2 1 1 1 1 B
141 DQ34 DQ39 142
DDR_B_D35 143 144
DQ35 VSS DDR_B_D44
145 VSS DQ44 146
DDR_B_D40 147 148 DDR_B_D45
DDR_B_D41 DQ40 DQ45
149 DQ41 VSS 150
151 152 DDR_B_DQS#5
DDR_B_DM5 VSS DQS5# DDR_B_DQS5
153 DM5 DQS5 154 Place close to JDIMM pin 203 and 204
155 VSS VSS 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS VSS 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS6# DM6
171 DQS6 VSS 172
173 174 DDR_B_D54
DDR_B_D50 VSS DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS DDR_B_D60
179 VSS DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS 184
185 186 DDR_B_DQS#7
DDR_B_DM7 VSS DQS7# DDR_B_DQS7
187 DM7 DQS7 188
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63 R759
193 DQ59 DQ63 194
+3.3V_M 195 196 0_0402_5%~D
VSS VSS PM_EXTTS#_R
197 SA0 EVENT# 198 1 2 PM_EXTTS# <10,19>
R164 199 200 MEM_SDATA MEM_SDATA <17,24>
VDDSPD SDA MEM_SCLK
+3.3V_M 1 2 201 SA1 SCL 202 MEM_SCLK <17,24>
+0.75V_DDR_VTT 203 VTT VTT 204 +0.75V_DDR_VTT
0.1U_0402_16V4Z~D
2.2U_0603_6.3V6K~D
A 10K_0402_5%~D A
1
10K_0402_5%~D
1 1 205 GND1 BOSS1 206
C217
C218
R165
207 GND2 BOSS2 208
2 2 TYCO_1903892-1 DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
DDR3 SO-DIMM/Standard Type PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Title
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DDRIII SO-DIMM SLOT
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 18 of 49
5 4 3 2 1
5 4 3 2 1
PWR_MON_GFX <44>
PWR_MON <43>
<34> BC_DAT_EMC4002
<34> BC_CLK_EMC4002 1 2 MAX8731_IINP <46>
Place Q29 under CPU R1098
4.7K_0402_5%~D
2 2 Diode circuit at DP4/DN4 is used for skin temp sensor
1
C224 C C225
2 Q29 (placed Q28 optimally between CPU, MCH and MEM)
D @ 100P_0402_50V8K~D B MMST3904-7-F_SOT323-3~D 2200P_0402_50V7K~D R1063 D
1 E 1 0_0402_5%~D
1
1 C 1
2
C225 close to Guardian and C224 close to Q29 C222 2 C228
B @ 100P_0402_50V8K~D
2200P_0402_50V7K~D E Q30
3
2 2
@ 270K_0402_1%
Place C226 close to Guardian pin as possible MMST3904-7-F_SOT323-3~D
1
C222 close to Guardian and C228 close to Q30
R1064
<7> H_THERMDA
1
C226 THERMISTOR OPTION:
2
U3
470P_0402_50V7K~D Single-ended routing to thermistor is permissible
2 BC_DAT_EMC4002
<7> H_THERMDC
BC_CLK_EMC4002
10 SMDATA/BC-LINK_DATA (ground return). Place R173 and C227 near EMC4002
11 SMBCLK/BC-LINK_CLK VIN1 39
VCP1 48
VCP2 45 1 2 1 2
Place Q28 close to SO-DIMM REM_DIODE1_P REM_DIODE4_P R173 R174
36 DP1/VREF_T DP4/DN8 44
REM_DIODE1_N 35 43 REM_DIODE4_N 1.2K_0402_1%~D 10K_0603_1%_TSM1A103F34D3RZ~D
DN1/THERM DN4/DP8
1 1
1
C223 C C229 38 47 1 2
DP2 DP5/DN9
2 Q28 37 DN2 DN5/DP9 46
@ 100P_0402_50V8K~D B MMST3904-7-F_SOT323-3~D 2200P_0402_50V7K~D C227 +RTC_CELL
2 E 2 REM_DIODE3_P 0.1U_0402_16V4Z~D C1358
41 1
3
REM_DIODE3_N DP3/DN7 DP6/VREF_T2
40 DN3/DP7 DN6/VIN2 2 1 2
C229 close to Guardian and C223 close to Q28 0.1U_0402_16V4Z~D
R175 2 1 10K_0402_5%~D +3.3V_M U95 R1105
5
+3.3V_M 1 2 +3V_M_THRM 4 74AHCT1G08GW_SOT353-5~D 0_0402_5%~D
VCC BC_INT#_EMC4002
12 2 2 1
P
ATF_INT#/BC-LINK_IRQ# BC_INT#_EMC4002 <34> A DOCK_PWR_SW# <34>
0.1U_0402_16V4Z~D
C R176 +RTC_CELL_R POWER_SW# C
+RTC_CELL 1 2 21 RTC_PWR3V POWER_SW# 26 4 Y
0_0603_5%~D 1 27 ACAV_IN ACAV_IN <34,46> 1 2 1 POWER_SW_IN# <34>
ACAVAIL_CLR B
G
+3.3V_M
C230
1U_0603_10V4Z~D
R178 1 20 2 1 +3.3V_M
THERMTRIP_SIO/PWM1/GPIO5
C231
0_0603_5%~D 25 THERM_STP# THERM_STP# <41> R1106
3
R181 1 SYS_SHDN#
2 10K_0402_5%~D 18 VCC_PWRGD
R180 0_0402_5%~D
2 R183 1
<34> ICH_PWRGD# 2 1K_0402_5%~D 17 3V_PWROK# 1 2 +RTC_CELL 10K_0402_5%~D
2 R182 @ 47K_0402_1%~D R1107
THERMATRIP1# 22 @ 0_0402_5%~D
THERMATRIP2# THERMTRIP1# R184
THERMATRIP3#
23 THERMTRIP2# 1 2 Voltage margining
24 THERMTRIP3# LDO_SHDN# 19 2 1 +3.3V_SUS 1 2
circuit for LDO output
VSET 42 34 10K_0402_5%~D R179
VSET LDO_POK @ 0_0402_5%~D
+1.8V_RUN_LVDS
0.1U_0402_16V4Z~D
+3V_M_THRM R185 2 1 4.7K_0402_5%~D 3 33 LDO_SET
ADDR_MODE/XEN LDO_SET
1
+5V_RUN +3.3V_RUN
953_0402_1%~D
1
R187
C232
R186
1.27K_0402_1%~D
6 32 +3V_LDOIN 2 1
VDD_5V VDDH/VDD_5V2
1
5 VDD_5V VDDH/VDD_5V2 31
2
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
R188
0_1210_5%~D
Ra
2
9 28 +1.8V_RUN_LVDS
1 1 +3.3V_RUN VDD_3V VDDL/VDD_3V2 1 1
C236
C235
C234
C233
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
+FAN1_VOUT 7 29
2
FAN_OUT LDO_OUT/FAN_OUT2
2 2 1 1 8 FAN_OUT LDO_OUT/FAN_OUT2 30
2 2 At maximum load current of 600mA,the the
C238
C237
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
Rset=953,Tp=88degree LDO_SET
FAN1_TACH_FB 15 16 1 1 voltage drop across the should be keep in
TACH1/GPIO3 TACH2/GPIO4
C240
C239
2K_0402_1%~D
14 CLK_IN/GPIO2 PWM2/GPIO1 13 the range of 0.5V to 1V
1
2 2
R190
Rb
VSS
2 2
49 EMC4002-HZHK C_QFN48_7X7~D
2
<34> EC_32KHZ_OUT EC_32KHZ_OUT
B +3.3V_M R189 B
2 1 PM_EXTTS# <10,18>
1
0_0402_5%~D Adjustable from 1.2V to 2.5V
R167
8.2K_0402_5%~D FAN control and Tachometer Ra = ((LDO_OUT/1.1)-1) x Rb
Pull-up Resistor on SMBus
For Remote1 mode
2
THERMATRIP1# ADDR_MODE/XEN Address +3.3V_M
+1.05V_VCCP
1
R168 C 1 * <= 4.7K +/- 5% 2N3904 2F(r/w)
1
1 2 2 C219
B
2.2K_0402_5%~D E 0.1U_0402_16V4Z~D
10K 2N3904 2F(r/w) R169
3
Q26 2 10K_0402_5%~D
MMST3904-7-F_SOT323-3~D
18K Thermistor 2F(r/w) JFAN
2
>= 33K Thermistor 2F(r/w) <22> FAN1_DET# FAN1_DET# 1
+FAN1_VOUT 1
<7> H_THERMTRIP# 2 2
RB751S40T1_SOD523-2~D
FAN1_TACH_FB 3 3
22U_0805_6.3VAM~D
4 4
1
1 5 GND
C220
6 GND
+3.3V_M +3.3V_M
D2
MOLEX_53780-0470
2
2
1
R171 R191
8.2K_0402_5%~D 8.2K_0402_5%~D
2
THERMATRIP2# THERMATRIP3#
+1.05V_VCCP
1
A R172 C A
1
C221
1
C241
Must confirm we can get C version to solve leakage issue
1 2 2
B Backdrive from RTC PWR to 3VSUS
2.2K_0402_5%~D E 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
B Version need external solution , check Roush I schematic
3
Q27 2 2
MMST3904-7-F_SOT323-3~D DELL CONFIDENTIAL/PROPRIETARY
<10> THERMTRIP_MCH# Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Thermal Sensor and FAN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 19 of 49
5 4 3 2 1
5 4 3 2 1
JLVDS
<38> BATT_BLUE BATT_BLUE 1
BATT_YELLOW 1
<38> BATT_YELLOW 2 2
EDID signals drive low when BlackTop mode <38> BREATH_BLUE_LED BREATH_BLUE_LED 3
+3.3V_RUN_BKT_PWR PNL_BKLT_CBL_DET# 3
<22> PNL_BKLT_CBL_DET# 4 4
5 5
U84 +3.3V_RUN_BKT_PWR +LCDVDD 6 6
7 7
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
5 V+ +LCDVDD 8 8
1 1 1 8 1 9
C761 V+
MAX4889 9
C762
C763
2.2K_0402_5%~D
2.2K_0402_5%~D
C249
13 2 SW_LVDS_A0+ 10
V+ COM1+ 10
1
18 3 SW_LVDS_A0- <33> LCD_TST LCD_TST 11
V+ COM1- 11
20 V+ 12 12
2 2 2 2
R196
R194
30 <12> BIA_PWM BIA_PWM 13
D V+ SW_LVDS_A1+ 13 D
40 V+ COM2+ 6 14 14
42 7 SW_LVDS_A1- Q111A 15
2
V+ COM2- 2N7002DW-7-F_SOT363-6~D C244 15
16 16
<12> LDDC_DATA_MCH 1 6 LDDC_DATA_MCH_LVDS 2 1 17
LCD_A0+_MCH SW_LVDS_A2+ 17
<12> LCD_A0+_MCH 38 NC1+ COM3+ 11 18 18
<12> LCD_A0-_MCH LCD_A0-_MCH 37 12 SW_LVDS_A2- Place close to JLVDS.8,9,10 0.1U_0603_50V4Z~D 19
NC1- COM3- 19
+INV_PWR_SRC 20
2
BKT_LVDS_RIN0+ 20
<21> BKT_LVDS_RIN0+ 34 NO1+ +3.3V_RUN 21 21
<21> BKT_LVDS_RIN0- BKT_LVDS_RIN0- 33 15 SW_LVDS_ACLK+ 22
NO1- COM4+ 22
5
16 SW_LVDS_ACLK- +3.3V_RUN_BKT_PWR 23
COM4- <34> LCD_SMBDAT 23
<34> LCD_SMBCLK 24 24
0.1U_0402_16V4Z~D
<12> LCD_A1+_MCH LCD_A1+_MCH 36 <12> LDDC_CLK_MCH 4 3 LDDC_CLK_MCH_LVDS +3.3V_RUN_BKT_PWR 25
LCD_A1-_MCH NC2+ 25
<12> LCD_A1-_MCH 35 NC2- SEL 9 BKT_GPIO1 <36> 26 26
Q111B 1 LVDS_CBL_DET# 27
<22> LVDS_CBL_DET# 27
C248
<21> BKT_LVDS_RIN1+ BKT_LVDS_RIN1+ 32 2N7002DW-7-F_SOT363-6~D LDDC_CLK_MCH_LVDS 28
BKT_LVDS_RIN1- NO2+ LDDC_DATA_MCH_LVDS 28
<21> BKT_LVDS_RIN1- 31 NO2- 29 29
30 30
2 SW_LVDS_A0- 31 31
<12> LCD_A2+_MCH LCD_A2+_MCH 29 SW_LVDS_A0+ 32
LCD_A2-_MCH NC3+ 32
<12> LCD_A2-_MCH 28 NC3- GND 1 33 33
4 SW_LVDS_A1- 34
BKT_LVDS_RIN2+ GND SW_LVDS_A1+ 34
<21> BKT_LVDS_RIN2+ 25 NO3+ GND 10 35 35
<21> BKT_LVDS_RIN2- BKT_LVDS_RIN2- 24 14 Place close to JLVDS.25 36
NO3- GND SW_LVDS_A2- 36
GND 17 37 37
19 SW_LVDS_A2+ 38
LCD_ACLK+_MCH GND 38
<12> LCD_ACLK+_MCH 27 NC4+ GND 21 39 39
<12> LCD_ACLK-_MCH LCD_ACLK-_MCH 26 39 SW_LVDS_ACLK- 40
NC4- GND SW_LVDS_ACLK+ 40
GND 41 41 41
<21> BKT_LVDS_CLK+ BKT_LVDS_CLK+ 23 43 42
BKT_LVDS_CLK- NO4+ GND 42
<21> BKT_LVDS_CLK- 22 NO4- Dual layout for Q33 and Q34
43 GND
44 GND
C MAX4889ETO+_TQFN42_3P5x9~D Q33 C
SEL Logic 1 Work from BKT @ FDS4435_NL_SO8~D
45 GND
46 GND
SEL NC to COM NO toCOM +PWR_SRC
47 GND
40mil 8 +INV_PWR_SRC 40mil 48 GND
0 ON OFF 1 7 49 GND
2 6 50 GND
1000P_0402_50V7K~D
1 OFF ON 3 5 51 GND
100K_0402_5%~D
1
1
1 C246
C247
R201
0.1U_0603_50V4Z~D
4
JAE_FI-G42SB-VF25
2
2
2
PWR_SRC_ON Q35
2N7002W-7-F_SOT323-3~D
R202 Q34
SI3457DV-T1_TSOP6~D
S
1 2 1 3
+PWR_SRC
D
+3.3V_RUN 100K_0402_5%~D 6 +INV_PWR_SRC
S
U14 4 5
G
2
4 VCC <36> BKT_GPIO14 3 2
10 R1119 1
VCC DAT_DDC2_CRT EN_INVPWR
18 48 1 1 2
G
VCC 0B1 CLK_DDC2_CRT DAT_DDC2_CRT <35>
27 47
3
VCC 1B1 VSYNC_BUF CLK_DDC2_CRT <35> @ 100K_0402_5%~D
38 VCC 2B1 43 VSYNC_BUF <35> <21,27,33,37,45> RUN_ON 2
50 42 HSYNC_BUF To MB CRT CONN PWR_SRC_ON
VCC 3B1 RED_CRT HSYNC_BUF <35> D51
56 VCC 4B1 37 RED_CRT <35>
36 GREEN_CRT BAT54CW_SOT323~D
DAT_DDC2 5B1 BLUE_CRT GREEN_CRT <35>
<12> DAT_DDC2 2 A0 6B1 32 BLUE_CRT <35>
CLK_DDC2 3 31
B <12> CLK_DDC2 A1 7B1 B
CRT_VSYNC 7 22
<12> CRT_VSYNC
<12> CRT_HSYNC
CRT_HSYNC 8
A2
A3
8B1
9B1 23 LCD POWER
CRT_RED 11
<12> CRT_RED A4
CRT_GRN 12 Q31
<12> CRT_GRN A5
CRT_BLU 14 SI3456BDV-T1-E3_TSOP6~D
<12> CRT_BLU A6 +LCDVDD +15V_ALW +LCDVDD
15
D
A7 DAT_DDC2_DOCK
S
19 A8 0B2 46 DAT_DDC2_DOCK <31> 6 +3.3V_ALW
20 45 CLK_DDC2_DOCK 4 5
A9 1B2 CLK_DDC2_DOCK <31>
1
470_0402_5%~D
0.1U_0402_16V4Z~D
41 VSYNC_DOCK 2
2B2 VSYNC_DOCK <31>
1
CRT_SWITCH H SYNC_DOCK +15V_ALW
<33> CRT_SWITCH 17 SEL 3B2 40 HSYNC_DOCK <31> To Docking CRT CONN 1 1
R193
C242
RED_DOCK R192
G
4B2 35 RED_DOCK <31>
1 34 GREEN_DOCK 100K_0402_5%~D
3
GND 5B2 GREEN_DOCK <31>
100K_0402_5%~D
6 30 BLUE_DOCK
2
GND 6B2 BLUE_DOCK <31>
1
2
2N7002DW-7-F_SOT363-6~D
9 29
2
GND 7B2
R195
@ 100K_0402_5%~D
0.1U_0402_25V4Z~D
13 GND 8B2 25
2N7002DW-7-F_SOT363-6~D
16 GND 9B2 26
1
21 +3.3V_RUN 1
GND
R197
C243
SEL CRT 24
2
GND
Q2A
Q2B
28 GND
0 MB 33 52 D50 2 5
GND NC 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
39 5 <33> LCD_VCC_TEST_EN 2 1
2
GND NC
1 DOCK 44 54
4
GND NC
1
49 51 1 1 1 1 1 1 1 1 RB751V_SOD323-2~D
GND NC
C251
C252
C253
C254
C255
C256
C257
C250
53
O
GND
55 GND <21,36> BKT_GPIO2 3
TS3DV520ERHUR_QFN56_11X5~D 2 2 2 2 2 2 2 2 EN_LCDPWR
1 2 I
2 D3
<12> ENVDD
G
BAT54CW_SOT323~D Q32
DDTC124EUA-7-F_SOT323-3~D
3
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, CRT SWITCH,LVDS MUX,LVDS CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 20 of 49
5 4 3 2 1
2 1
+3.3V_BKT_PWR +3.3V_BKT_PWR
+3.3V_RUN_BKT_PWR Source JBKTOP
1 PAID_IN VSS 2
Q92 BKT_LVDS_RIN0- 3 4 BKT_LVDS_RIN1-
<20> BKT_LVDS_RIN0- Odd Rin0- Odd Rin1- BKT_LVDS_RIN1- <20>
+15V_ALW +3.3V_ALW SI3456BDV-T1-E3_TSOP6~D BKT_LVDS_RIN0+ 5 6 BKT_LVDS_RIN1+
<20> BKT_LVDS_RIN0+ Odd Rin0+ Odd Rin1+ BKT_LVDS_RIN1+ <20>
+3.3V_RUN_BKT_PWR 7 8
VSS VSS
D
6 BKT_LVDS_RIN2- 9 10 BKT_LVDS_CLK-
S
<20> BKT_LVDS_RIN2- Odd Rin2- Odd Clk- BKT_LVDS_CLK- <20>
1
5 4 BKT_LVDS_RIN2+ 11 12 BKT_LVDS_CLK+
<20> BKT_LVDS_RIN2+ Odd Rin2+ Odd Clk+ BKT_LVDS_CLK+ <20>
10U_0805_10V4Z~D
20K_0402_5%~D
2 13 VSS VSS 14
1
+3.3V_ALW2 R787 1 1 15 16
Even Rin0- Even Rin1-
C775
R788
100K_0402_5%~D 17 18
G
Even Rin0+ Even Rin1+
19 20
3
VSS VSS
1
21 Even Rin2- Even Clk- 22
R789 2
1 23 24
2
Even Rin2+ Even Clk+
3
100K_0402_5%~D C776 25 26
Q93B BKT_SMBCLK VSS VSS BKT_I2S_LRC
<34> BKT_SMBCLK 27 SMBCLK I2S_LRC 28 BKT_I2S_LRC <26>
470P_0402_50V7K~D BKT_SMBDAT 29 30
<34> BKT_SMBDAT
2
2N7002DW-7-F_SOT363-6~D 2 BKT_GPIO16 SMBDATA I2S_DIN BKT_I2S_DO
5 <36> BKT_GPIO16 31 SMBALERT I2S_DOUT 32 BKT_I2S_DO <26>
D53 BKT_GPIO7 33 34 BKT_I2S_SCLK
<36> BKT_GPIO7 RST- I2S_SCLK BKT_I2S_SCLK <26>
6
BAT54CW_SOT323~D BKT_GPIO8 35 36
<36> BKT_GPIO8
4
Q93A USB_SEL_BLK VSS BKT_MCLK
<20,27,33,37,45> RUN_ON 3 37 VSS M_Clk 38 BKT_MCLK <26>
39 VSS VSS 40
1 3.3V_RUN_BKT_PWR_EN 2 2N7002DW-7-F_SOT363-6~D 41 42
VDD 3.3v 5% VDD 3.3v 5%
43 VDD 3.3v 5% VDD 3.3v 5% 44
2 R1113 45 46
<36> BKT_GPIO19
1
VDD 3.3v 5% VDD 3.3v 5%
1 2 47 VSS VSS 48
49 VSS VSS 50
@ 100K_0402_5%~D BKT_USBH- 51 52 BKT_USBBIO-
BKT_USBH+ USB Host Port Data- BioMetric BKT_USBBIO+
53 USB Host Port Data+ BioMetric 54
55 VSS VSS 56
57 58
B +5V_RUN_BKT_PWR Source, for Touch Pad and Audio Amplifier 59
Reserved Reserved
60 B
Reserved Reserved
61 VSS VSS 62
Q95 63 64 BKT_LED BKT_LED <35>
+15V_ALW +5V_ALW SI3456BDV-T1-E3_TSOP6~D GPIO Reserved
65 SM CLK Reserved 66
+5V_RUN_BKT_PWR 67 68
SK DAT Reserved
D
6 69 70
S
SM Alert Reserved
1
5 4 71 VSS VSS 72
10U_0805_10V4Z~D
20K_0402_5%~D
2 BKT_GPIO9 73 74 BKT_GPIO5
<36> BKT_GPIO9 Radio_OFF LID Closed BKT_GPIO5 <36>
1
R790 1 1 75 76
Reserved Reserved
C777
R792
+3.3V_ALW2 100K_0402_5%~D 77 78
G
Reserved Reserved
79 80
3
Reserved Reserved
1 81 Reserved Reserved 82
2
1 83 84
2
R791 C778 Reserved Reserved
85 Reserved Reserved 86
3
100K_0402_5%~D 87 88
Q96B 2200P_0402_50V7K~D Reserved Reserved
89 Reserved Reserved 90
2
91 92
2
2N7002DW-7-F_SOT363-6~D Reserved Reserved
5 93 Reserved Reserved 94
D54 95 96
Reserved Reserved
6
BAT54CW_SOT323~D 97 98
4
Q96A Reserved Reserved BKT_GPIO6
<36> BKT_GPIO4 3 99 VSS PAID_Out 100 BKT_GPIO6 <36>
1 5V_RUN_BKT_PWR_EN 2 2N7002DW-7-F_SOT363-6~D 101 102
GND GND
103 GND GND 104
RUN_ON 2 R1114
1
1 2
MOLEX_55299-1078
@ 100K_0402_5%~D
Enable BlackTop POWER
+3.3V_RUN_WWAN_PWR Source, for WWAN Q36
+15V_ALW +3.3V_ALW SI3456BDV-T1-E3_TSOP6~D
+15V_ALW +3.3V_ALW Q89 +3.3V_RUN_WWAN_PWR +3.3V_BKT_PWR
D
SI4336DY-T1-E3_SO8~D 6
S
1
8 1 +3.3V_ALW2 5 4
1
10U_0805_10V4Z~D
20K_0402_5%~D
7 2 2
100K_0402_5%~D
10U_0805_10V4Z~D
20K_0402_5%~D
6 3 1 R1065 1
1
C773
R785
+3.3V_ALW2 R784 5 1
G
100K_0402_5%~D
3
R1066
470P_0402_50V7K~D
C258
R206
100K_0402_5%~D
2
4
1
2
1
3
2
C1347
R786 1
2
3
100K_0402_5%~D C774 Q112B
Q90B
470P_0402_50V7K~D 2N7002DW-7-F_SOT363-6~D 2
5
2
2N7002DW-7-F_SOT363-6~D 2
5
D52
4
6
6
BAT54CW_SOT323~D
4
RUN_ON 3 Q90A Q112A
1 3.3V_RUN_WWAN_PWR_EN 2 2N7002DW-7-F_SOT363-6~D 2 2N7002DW-7-F_SOT363-6~D
<20,36> BKT_GPIO2
2 R1115
<36> BKT_GPIO15
1
1
1 2
@ 100K_0402_5%~D
Add BlackTop to ICH9M interface by USB signals when diagnostic mode
For Biometric USB signals isolation For WWAN USB signals isolation
+3.3V_RUN_BKT_PWR
+3.3V_RUN_BKT_PWR +3.3V_RUN_BKT_PWR C1351
A A
2 1
C784 C783
U86 1 2 U85 1 2 0.1U_0402_16V4Z~D
+3.3V_RUN_BKT_PWR
FP_USBD+ 1 10 0.1U_0402_16V4Z~D USBP5+ 1 10 0.1U_0402_16V4Z~D C785 U82
<32> FP_USBD+ 1D+ VCC <24> USBP5+ 1D+ VCC
1 2 8 VCC NC 1
FP_USBD- 2 9 BKT_GPIO4 USBP5- 2 9 BKT_GPIO4
<32> FP_USBD- 1D- S <24> USBP5- 1D- S 0.1U_0402_16V4Z~D BKT_USBH- 2 3 USBP5-
BKT_USBBIO+ FP_SW_USBD+ BKT_USBH+ WWAN_SW_USBD+ HSD- D-
3 2D+ D+ 8 FP_SW_USBD+ <35> 3 2D+ D+ 8 WWAN_SW_USBD+ <30>
5
1
BKT_USBH+ 6 5 USBP5+
BKT_USBBIO- FP_SW_USBD- BKT_USBH- W WAN_SW_USBD- HSD+ D+
4 7 4 7
P
NC
2D- D- FP_SW_USBD- <35> 2D- D- WWAN_SW_USBD- <30> BKT_GPIO3 EN_DIAG
2 A Y 4 7 OE# GND 4
5 6 BKT_GPIO3 5 6 BKT_GPIO3
GND OE# GND OE# BKT_GPIO3 <36>
G
U64 FSUSB31K8X_US8~D
S OE# Function S OE# Function 74LVC1G14GV_SOT753-5
3
X H Disconnect TS3USB221RSER_QFN10_2x1P5~D X H Disconnect TS3USB221RSER_QFN10_2x1P5~D BKT_GPIO3 Logic 1 on diagnostic mode
L L D=1D L L D=1D
H L D=2D Select logic 1 Work from BlackTop H L D=2D Select logic 1 Work from BlackTop
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, BlackTop POWER and CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 21 of 49
2 1
5 4 3 2 1
D D
+3.3V_ALW_ICH
+3.3V_RUN C259
R219 1 2 8.2K_0402_5%~D PCI_REQ0# <29> PCI_AD[0..31]
U79B 0.1U_0402_16V4Z~D
R220 1 2 8.2K_0402_5%~D PCI_REQ1# PCI_AD0 PCI_REQ0#
14
A11 AD0 REQ0# G4
PCI_AD1 B12 E1 PCI_GNT0# U16A
R764 1 2 8.2K_0402_5%~D ICH_GPIO54 PCI_AD2 A10
AD1 PCI GNT0#
A9 PCI_REQ1# PCI_PCIRST# 1
P
AD2 REQ1#/GPIO50 PCI_REQ1# <29> IN1
PCI_AD3 C12 E12 PCI_GNT1# PCI_GNT1# <29> 3 PCI_RST#
AD3 GNT1#/GPIO51 OUT PCI_RST# <29,31>
R212 1 2 8.2K_0402_5%~D PCI _IRDY# PCI_AD4 A8 B11 PCIE_MCARD2_DET# PCIE_MCARD2_DET# <30> 2
AD4 REQ2#/GPIO52 IN2
G
PCI_AD5 A12 C10 ICH_GPIO53 T99
R207 1 PCI_DEVSEL# PCI_AD6 AD5 GNT2#/GPIO53 ICH_GPIO54
2 8.2K_0402_5%~D E10 D6 74VHC08MTCX_NL_TSSOP14~D
7
PCI_AD7 AD6 REQ3#/GPIO54 ICH_GPIO55
C11 AD7 GNT3#/GPIO55 C6 T100
R214 1 2 8.2K_0402_5%~D PCI_PERR# PCI_AD8 B9
PCI_AD9 AD8 PCI_C_BE0#
D8 AD9 C/BE0# D10 PCI_C_BE0# <29>
R211 1 2 8.2K_0402_5%~D PCI_PLOCK# PCI_AD10 A4 A5 PCI_C_BE1#
AD10 C/BE1# PCI_C_BE1# <29> +3.3V_ALW_ICH
PCI_AD11 E8 E6 PCI_C_BE2#
AD11 C/BE2# PCI_C_BE2# <29>
R213 1 2 8.2K_0402_5%~D PCI_SERR# PCI_AD12 A3 C9 PCI_C_BE3#
AD12 C/BE3# PCI_C_BE3# <29>
PCI_AD13
14
D9 AD13
R208 1 2 8.2K_0402_5%~D PCI_STOP# PCI_AD14 C8 C3 PCI _IRDY# PCI_IRDY# <29> U16B
PCI_AD15 AD14 IRDY# PCI_PAR PCI_PLTRST#
C2 B1 4
P
AD15 PAR PCI_PAR <29> IN1
R209 1 2 8.2K_0402_5%~D PCI_TRDY# PCI_AD16 D7 T3 PCI_PCIRST# 6 PLTRST1#
AD16 PCIRST# OUT PLTRST1# <10,35>
PCI_AD17 B3 A7 PCI_DEVSEL# 5
AD17 DEVSEL# PCI_DEVSEL# <29> IN2
G
R210 1 2 8.2K_0402_5%~D PCI_FRAME# PCI_AD18 D11 D4 PCI_PERR#
AD18 PERR# PCI_PERR# <29>
PCI_AD19 B6 C5 PCI_PLOCK# 74VHC08MTCX_NL_TSSOP14~D
7
PCI_AD20 AD19 PLOCK# PCI_SERR#
D5 AD20 SERR# H5 PCI_SERR# <29>
PCI_AD21 D3 A6 PCI_STOP#
AD21 STOP# PCI_STOP# <29>
PCI_AD22 F4 A2 PCI_TRDY#
AD22 TRDY# PCI_TRDY# <29>
PCI_AD23 E3 B8 PCI_FRAME#
+3.3V_RUN AD23 FRAME# PCI_FRAME# <29> +3.3V_ALW_ICH
PCI_AD24 E4
PCI_AD25 AD24 PCI_PLTRST#
B2 AD25 PLTRST# A21
C R215 1 PCI_PIRQA# PCI_AD26 CLK_PCI_ICH C
2 8.2K_0402_5%~D
14
C4 AD26 PCICLK B5 CLK_PCI_ICH <6>
PCI_AD27 C1 T1 ICH_PME# U16C
AD27 PME# ICH_PME# <33>
R216 1 2 8.2K_0402_5%~D PCI_PIRQB# PCI_AD28 D1 10
P
PCI_AD29 AD28 IN1 PLTRST2#
E2 AD29 OUT 8 PLTRST2# <33,34>
R217 1 2 8.2K_0402_5%~D PCI_PIRQC# PCI_AD30 J4 9
AD30 IN2
G
PCI_AD31 H2
R218 1 AD31
2 8.2K_0402_5%~D PCI_PIRQD# 74VHC08MTCX_NL_TSSOP14~D
7
R221 1 2 100K_0402_5%~D FAN1_DET# PCI_PIRQA# F1
Interrupt I/F G3 LVDS_CBL_DET#
PIRQA# PIRQE#/GPIO2 LVDS_CBL_DET# <20>
PCI_PIRQB# F5 G1 PNL_BKLT_CBL_DET#
PIRQB# PIRQF#/GPIO3 PNL_BKLT_CBL_DET# <20>
R222 1 2 100K_0402_5%~D LVDS_CBL_DET# PCI_PIRQC# F2 F3 BT_DET#
<29> PCI_PIRQC# PIRQC# PIRQG#/GPIO4 BT_DET# <30> +3.3V_ALW_ICH
PCI_PIRQD# C7 H4 FAN1_DET#
<29> PCI_PIRQD# PIRQD# PIRQH#/GPIO5 FAN1_DET# <19>
R224 1 2 100K_0402_5%~D PNL_BKLT_CBL_DET#
ICH9-M SFF ES_FCBGA569~D
14
R223 1 2 100K_0402_5%~D BT_DET# U16D
13
P
IN1 PLTRST3#
OUT 11 PLTRST3# <30,32>
12 IN2
G
74VHC08MTCX_NL_TSSOP14~D
7
There is a weak integrated pull-up resistor on SPI_CS#1 pin Place closely pin U79.B5
B B
Boot BIOS Strap CLK_PCI_ICH
PCI_GNT0#
2
PCI_GNT0# SPI_CS1# Boot BIOS Destination
1
R227
R225
@ 10_0402_5%~D
1K_0402_5%~D
* 0 1 SPI
1CLK_ICH_TERM
2
1 0 PCI
1 1 LPC
1
C260
@ 8.2P_0402_50V8J~D
2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9M SFF(1/4)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 22 of 49
5 4 3 2 1
5 4 3 2 1
CMOS_CLR CMOS setting
Short Clear CMOS
Open Keep CMOS
+3.3V_RUN
ME_CLR TPM setting R233
SIO_A20GATE 2 1
D C261 D
Short Clear ME RTC Registers 15P_0402_50V8J~D 10K_0402_5%~D
Open Keep ME RTC Registers 2 1 ICH_RTCX1
R236
SIO_RCIN# 2 1
1
1
Y1 R231 10K_0402_5%~D
32.768KHZ_12.5PF_1TJE125DP1~D
10M_0402_5%~D
C262 R232 U79A
2
15P_0402_50V8J~D 0_0402_5%~D F25 H3 LPC_LAD0
RTCX1 FWH0/LAD0 LPC_LAD0 <32,33,34>
2 1 1 2 ICH_RTCX2 G25 J3 LPC_LAD1
RTCX2 FWH1/LAD1 LPC_LAD1 <32,33,34>
K5 LPC_LAD2 +1.05V_VCCP
FWH2/LAD2 LPC_LAD2 <32,33,34>
+RTC_CELL R234 1 2 20K_0402_5%~D ICH_RTCRST# G24 L3 LPC_LAD3
RTCRST# FWH3/LAD3 LPC_LAD3 <32,33,34>
R235 1 2 20K_0402_5%~D SRTCRST# C24
RTC
LPC
+RTC_CELL +RTC_CELL R237 1 INTRUDER# SRTCRST# LPC_LFRAME#
2 1M_0402_5%~D C23 INTRUDER# FWH4/LFRAME# J2 LPC_LFRAME# <32,33,34>
@ 56_0402_1%~D
@ 56_0402_1%~D
1
1
ME_CLR CMOS_CLR ICH_INTVRMEN E25 H1 LPC_LDRQ0#
INTVRMEN LDRQ0# LPC_LDRQ0# <33>
1
R239
R240
LAN100_SLP D25 J1 LPC_LDRQ1#
R228 R767 LAN100_SLP LDRQ1#/GPIO23 LPC_LDRQ1# <33>
332K_0402_1%~D 332K_0402_1%~D 1 2 1 2 LAN_CLK G22 N3 SIO_A20GATE
1 2 1 2 <28> LAN_CLK GLAN_CLK A20GATE SIO_A20GATE <34>
AB23 H_A20M#
H_A20M# <7>
2
LAN_RSTSYNC A20M#
<28> LAN_RSTSYNC D14
2
ICH_INTVRMEN LAN100_SLP LAN_RSTSYNC H_DPRSTP#
DPRSTP# AE23 H_DPRSTP# <8,10,43>
LAN_RX0 A14 AE24 H_DPSLP#
LAN / GLAN
<28> LAN_RX0 LAN_RXD0 DPSLP# H_DPSLP# <8>
LAN_RX1 D12
<28> LAN_RX1 LAN_RXD1
C263 1 2 C264 1 2 LAN_RX2 B14 AD25 R242 2 1 56_0402_5%~D
<28> LAN_RX2 LAN_RXD2 FERR# H_FERR# <7>
1U_0603_10V4Z~D 1U_0603_10V4Z~D LAN_TX0 D13 AE22 H_PW RGOOD
<28> LAN_TX0 LAN_TXD0 CPUPWRGD H_PWRGOOD <8>
LAN_TX1 C13
<28> LAN_TX1 LAN_TXD1
LAN_TX2 A13 AD23 H_IGNNE#
<28> LAN_TX2 LAN_TXD2 IGNNE# H_IGNNE# <7>
+1.05V_VCCP
CPU
C R230 10K_0402_5%~D H_INIT# C
+3.3V_ALW_ICH 2 1 D15 GPIO56 INIT# AE21 H_INIT# <7>
ICH9M Internal VR Enable Strap AD24 H_INTR R241
INTR H_INTR <7>
+1.5V_RUN_PCIE_ICH R243 1 2 24.9_0402_1%~D H22 L1 SIO_RCIN# H_FERR# 2 1
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) GLAN_COMPI RCIN# SIO_RCIN# <34>
H21 GLAN_COMPO
AD21 H_NMI 56_0402_5%~D
NMI H_NMI <7>
Low = Internal VR Disabled ICH_AZ_BITCLK AE7 AC21 H_SMI#
HDA_BIT_CLK SMI# H_SMI# <7>
ICH_INTVRMEN I CH_AZ_SYNC AB7
High = Internal VR Enabled(Default) HDA_SYNC H_STPCLK#
STPCLK# AC25 H_STPCLK# <7>
ICH_AZ_RST# AA7 HDA_RST# THRMTRIP_ICH# R246 2
THRMTRIP# AC23 1 56_0402_5%~D +1.05V_VCCP
ICH_AZ_CODEC_SDIN0 AB6
<26> ICH_AZ_CODEC_SDIN0 HDA_SDIN0
AE6 AC22 ICH_TP11 T43
ICH_AZ_MCH_SDIN2 HDA_SDIN1 TP11
ICH9M LAN100 SLP Strap AC6
IHDA
<10> ICH_AZ_MCH_SDIN2 HDA_SDIN2
AA5 HDA_SDIN3
(Internal VR for VccLAN1.05 and VccCL1.05) AD12
ICH_AZ_SDOUT SATA4RXN ESATA_IRX_DTX_N4_C <35>
AC7 HDA_SDOUT SATA4RXP AE12 ESATA_IRX_DTX_P4_C <35>
Low = Internal VR Disabled AB12 ESATA_ITX_DRX_N4_C C267 2 1 0.01U_0402_16V7K~D
SATA4TXN ESATA_ITX_DRX_N4 <35>
ICH_LAN100_SLP <33> ME_FWP ME_FWP AD8 AA12 ESATA_ITX_DRX_P4_C C268 2 1 0.01U_0402_16V7K~D
High = Internal VR Enabled(Default) HDA_DOCK_EN#/GPIO33 SATA4TXP ESATA_ITX_DRX_P4 <35>
RTC_BAT_DET# AB8 HDA_DOCK_RST#/GPIO34
SATA5RXN AC11 SATA_SBRX_DTX_N3_C <31>
SATA_ACT#_R AC9 AD11
<38> SATA_ACT#_R SATALED# SATA5RXP SATA_SBRX_DTX_P3_C <31>
AB10 SATA_ITX_DRX_N3_C C269 2 1 0.01U_0402_16V7K~D
SATA5TXN SATA_SBTX_C_DRX_N3 <31>
PSATA_IRX_DTX_N0_C AE14 AA10 SATA_ITX_DRX_P3_C C270 2 1 0.01U_0402_16V7K~D
<35> PSATA_IRX_DTX_N0_C SATA0RXN SATA5TXP SATA_SBTX_C_DRX_P3 <31>
PSATA_IRX_DTX_P0_C AD14
<35> PSATA_IRX_DTX_P0_C SATA0RXP
SATA
C271 2 1 0.01U_0402_16V7K~D PSATA_ITX_DRX_N0_C AC15 AC16 CLK_PCIE_SATA#
<35> PSATA_ITX_DRX_N0 SATA0TXN SATA_CLKN CLK_PCIE_SATA# <6>
C272 2 1 0.01U_0402_16V7K~D PSATA_ITX_DRX_P0_C AD15 AB16 CLK_PCIE_SATA
<35> PSATA_ITX_DRX_P0 SATA0TXP SATA_CLKP CLK_PCIE_SATA <6>
AD13 SATA1RXN SATARBIAS# AD10
AC13 SATA1RXP SATARBIAS AE10 2 1
AA14 SATA1TXN
AB14 R253
SATA1TXP 24.9_0402_1%~D
B ICH9-M SFF ES_FCBGA569~D B
Within 500 mils
Place close to U79 RTC BATT connector detect circuit
R244 1 2 33_0402_5%~D ICH_AZ_SDOUT +3.3V_RUN +3.3V_RUN
<26> ICH_AZ_CODEC_SDOUT
100K_0402_5%~D
R245 1 2 33_0402_5%~D I CH_AZ_SYNC XOR Chain Entrance Strap
<26> ICH_AZ_CODEC_SYNC
1
+COINCELL
R247 1 2 33_0402_5%~D ICH_AZ_RST# R256 R1100
<26> ICH_AZ_CODEC_RST#
R1099
ICH_RSVD_TP3 HDA SDOUT DESCRIPTION @ 1K_0402_5%~D 1 2
R248 1 2 33_0402_5%~D ICH_AZ_BITCLK
<26> ICH_AZ_CODEC_BITCLK
2
1M_0402_5%~D
G
1
2
C266
0 0 RSVD ICH_AZ_SDOUT RTC_BAT_DET# 1 3
@ 27P_0402_50V8J~D
1
2 ICH_RSVD_TP3
0 1 Enter XOR Chain ICH_RSVD_TP3 <24>
R1102 Q121 R1101
1 2 2N7002W-7-F_SOT323-3~D 1K_0402_5%~D
<40> RTC_BAT_DET_R#
1
R1033 2 33_0402_5%~D ICH_AZ_SDOUT
<10> ICH_AZ_MCH_SDOUT 1
* 1 0 Normal Operation (Default) R259 @ 0_0402_5%~D
2
R1034 1 2 33_0402_5%~D I CH_AZ_SYNC @ 1K_0402_5%~D
<10> ICH_AZ_MCH_SYNC
R1035 ICH_AZ_RST#
1 1 Set PCIE port config bit 1
<10> ICH_AZ_MCH_RST# 1 2 33_0402_5%~D
2
There is a weak integrated pull-up resistor on ICH_RSVD_TP3 pin
R1036 1 2 33_0402_5%~D ICH_AZ_BITCLK
<10> ICH_AZ_MCH_BITCLK
A
1 There is a weak integrated pull-down resistor on HDA_SDOUT pin A
C1290
@ 27P_0402_50V8J~D
2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9M SFF(2/4)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 23 of 49
5 4 3 2 1
5 4 3 2 1
+3.3V_M +3.3V_ALW_ICH
R262
1 2 +3.3V_RUN
+3.3V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
2.2K_0402_5%~D
U79C 8.2K_0402_5%~D SPEAKER_DET# R276 1 2 100K_0402_5%~D
1
ICH_SMBCLK C18 AE19
SMBCLK SATA0GP/GPIO21
R318
R319
R264
R261
ICH_SMBDATA C15 AA18 SPEAKER_DET# AUDIO_BD_DET# R273 1 2 100K_0402_5%~D
SMBDATA SATA1GP/GPIO19 SPEAKER_DET# <27>
ICH_GPIO60 B21 AE20 AUDIO_BD_DET#
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 AUDIO_BD_DET# <35>
GPIO
SATA
SMB
AMT_SMBCLK E18 AA20 1394_DET# 1394_DET# R269 1 2 100K_0402_5%~D
<34> AMT_SMBCLK SMLINK0 SATA5GP/GPIO37 1394_DET# <35>
Q3A AMT_SMBDAT A24
<34> AMT_SMBDAT
2
2N7002DW-7-F_SOT363-6~D SMLINK1 CLK_ICH_14M
CLK14 K1 CLK_ICH_14M <6>
1 6 ICH_SMBDATA I CH_RI# C20 AB5 CLK_ICH_48M +3.3V_ALW_ICH
<17,18> MEM_SDATA RI# CLK48 CLK_ICH_48M <6>
Clocks
T97 SUS_STAT#/LPCPD# T5 R3 ICH_SUSCLK T44 ME_SUS_PWR_ACK R279 1 2 10K_0402_5%~D
ITP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
<7> ITP_DBRESET# C25
2
D SYS_RESET# SIO_SLP_S3# D
+3.3V_M SLP_S3# D18 SIO_SLP_S3# <33>
PM_SYNC# L2 B20 SIO_SLP_S4# RESET_OUT R285 1 2 10K_0402_5%~D
<10> PM_SYNC# PMSYNC#/GPIO0 SLP_S4# SIO_SLP_S4# <10,34>
5
D16 SIO_SLP_S5#
SMB_ALERT# SLP_S5# SIO_SLP_S5# <34> ICH_RSMRST# R288
A23 SMBALERT#/GPIO11 1 2 10K_0402_5%~D
4 3 ICH_SMBCLK E14 ICH_GPIO26 T45
<17,18> MEM_SCLK S4_STATE#/GPIO26
H_STP_PCI# B15 ICH_CL_PWROK R280 1 2 100K_0402_5%~D
<6> H_STP_PCI# STP_PCI#/GPIO15
SYS GPIO
Q3B H_STP_CPU# A20 D23 RESET_OUT
<6> H_STP_CPU# STP_CPU#/GPIO25 PWROK RESET_OUT <10,34>
2N7002DW-7-F_SOT363-6~D ME_WOL_EN R291 1 2 100K_0402_5%~D
+3.3V_ALW_ICH CLKRUN# M5 M1 DPRSLPVR
<29,33,34> CLKRUN# CLKRUN#/GPIO32 DPRSLPVR/GPIO16 DPRSLPVR <10,43>
R304
Power MGT
1 2 ICH_GPIO60 1 2 ITP_DBRESET# ICH_PCIE_WAKE# C21 C16 ICH_BATLOW# R290 2 1 8.2K_0402_5%~D +3.3V_ALW_ICH
<33> ICH_PCIE_WAKE# WAKE# BATLOW#
R289 10K_0402_5%~D IRQ_SERIRQ L4
<29,32,33,34> IRQ_SERIRQ SERIRQ
1 2 AMT_SMBCLK @ 100K_0402_5%~D RSV_THRM# AD20 U4 SIO_PWRBTN#
THRM# PWRBTN# SIO_PWRBTN# <34>
R268 10K_0402_5%~D
1 2 AMT_SMBDAT R306 IMVP_PWRGD B24 D22 ICH_LAN_RST# Place closely pin U79.K1
<33,43,44> IMVP_PWRGD VRMPWRGD LAN_RST# ICH_LAN_RST# <34>
R271 10K_0402_5%~D 1 2 DMI_TERM_SEL ICH_LAN_RST#
1 2 I CH_RI# T46 ICH_TP12 A19 D19 ICH_RSMRST#
TP12 RSMRST# ICH_RSMRST# <34>
10K_0402_5%~D
R274 10K_0402_5%~D @ 1K_0402_5%~D
1
1 2 SMB_ALERT# SIO_EXT_SCI# AE16 U1 CLK_PWRGD CLK_ICH_14M
<34> SIO_EXT_SCI# GPIO1 CK_PWRGD CLK_PWRGD <6>
R297
R293 10K_0402_5%~D TPM_ID AE18 GPIO6
1
1 2 ICH_PCIE_WAKE# SIO_EXT_WAKE# AD18 T4 ICH_CL_PWROK
<33> SIO_EXT_WAKE# GPIO7 CLPWROK ICH_CL_PWROK <10,34>
R277 10K_0402_5%~D SIO_EXT_SMI# B25 R298
<34> SIO_EXT_SMI# GPIO8
1 2 SIO_EXT_SMI# LAN_DISABLE# C14 B23 SIO_SLP_M# @ 10_0402_5%~D
2
R287 10K_0402_5%~D <28> LAN_DISABLE# KYBRD_BKT_DET# GPIO12 SLP_M# SIO_SLP_M# <34>
<36> KYBRD_BKT_DET# D20 GPIO13
1 2 KYBRD_BKT_DET# R299 SNIFFER_DET# AE17 C22 CL_CLK0
<35> SNIFFER_DET# CL_CLK0 <10>
2
R1116 100K_0402_5%~D GPIO17 CL_CLK0 ICH_CL_CLK1
<30> USB_MCARD1_DET# 1 2 K3 GPIO18 CL_CLK1 A18 ICH_CL_CLK1 <30>
1 2 IO_BD_DET# 4.7K_0402_5%~D T49 ICH_GPIO20 AC8 1
R1117 100K_0402_5%~D GPIO20 CL_DATA0 +3.3V_M C276
<30> USB_MCARD2_DET# AC19 SCLOCK/GPIO22 CL_DATA0 E22 CL_DATA0 <10>
@ 47P_0402_50V8J~D
Controller Link
@ 47P_0402_50V8J~D
@ 47P_0402_50V8J~D
1 2 LED_BD_DET# IO_BD_DET# D17 B18 ICH_CL_DATA1 @ 4.7P_0402_50V8C~D
GPIO
<35> IO_BD_DET# GPIO27 CL_DATA1 ICH_CL_DATA1 <30>
3.24K_0402_1%~D
R278 100K_0402_5%~D 1 1 1 LED_BD_DET# E20
<38> LED_BD_DET# GPIO28
1
2
C277
C278
C279
1 2 BIO_DET# SATA_CLKREQ# M4 F21 +CL_VREF0_ICH
<6> SATA_CLKREQ# SATACLKREQ#/GPIO35 CL_VREF0
R309
R295 100K_0402_5%~D KB_DET# AB18 A17 +CL_VREF1_ICH
C <36> KB_DET# SLOAD/GPIO38 CL_VREF1 C
T50 WPAN_RADIO_DIS_MINI# AC18
2 2 2 HDD_DET# SDATAOUT0/GPIO39 CL_RST0#
<35> HDD_DET# AB19 SDATAOUT1/GPIO48 CL_RST0# C17 CL_RST0# <10>
DMI_TERM_SEL AC20 B17 ICH_CL_RST1#
2
+3.3V_RUN BIO_DET# GPIO49 CL_RST1# ICH_CL_RST1# <30>
<35> BIO_DET# A16 GPIO57/CLGPIO5 PCIE_MCARD1_DET# +CL_VREF0_ICH
Place closely pin U79.AB5
MEM_LED/GPIO24 A22 PCIE_MCARD1_DET# <30>
1 2 IRQ_SERIRQ +3.3V_RUN SPKR K4 E16 ME_SUS_PWR_ACK
<26> SPKR SPKR GPIO10/SUS_PWR_ACK ME_SUS_PWR_ACK <34>
0.1U_0402_16V4Z~D
453_0402_1%~D
R267 10K_0402_5%~D MCH_ICH_SYNC# AB20 A15 AC_PRESENT
<10> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT AC_PRESENT <34>
1
1 2 RSV_THRM# 1 2 SNIFFER_DET# ICH_RSVD_TP3 C19 D21 ME_WOL_EN 1 CLK_ICH_48M
<23> ICH_RSVD_TP3 TP3 WOL_EN/GPIO9 ME_WOL_EN <34>
MISC
C290
R311
R265 8.2K_0402_5%~D R292 100K_0402_5%~D T51 ICH_TP8 AB17 TP8
1
1 2 SIO_EXT_SCI# 1 2 KB_DET# T52 ICH_TP9 AC17 R305
R282 10K_0402_5%~D R272 100K_0402_5%~D ICH_TP10 TP9 R307
T53 AD17 TP10 1 2 +3.3V_ALW_ICH
TPM_ID HDD_DET# 2 @ 10_0402_5%~D
1 2 1 2
2
R794 100K_0402_5%~D R275 100K_0402_5%~D ICH9-M SFF ES_FCBGA569~D @ 100K_0402_5%~D CRB pop
2
U79D 1
+3.3V_RUN PCIE_IRX_WANTX_N1 T25 V25 DMI_MTX_IRX_N0 +3.3V_WLAN C281
<30> PCIE_IRX_WANTX_N1 PERN1 DMI0RXN DMI_MTX_IRX_N0 <10>
Direct Media Interface
PCIE_IRX_WANTX_P1 T24 V24 DMI_MTX_IRX_P0 @ 4.7P_0402_50V8C~D
<30> PCIE_IRX_WANTX_P1 PERP1 DMI0RXP DMI_MTX_IRX_P0 <10>
3.24K_0402_1%~D
MINIWWAN (Mini Card 2) C280 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_N1 R24 U24 DMI_MRX_ITX_N0
<30> PCIE_ITX_WANRX_N1_C PETN1 DMI0TXN DMI_MRX_ITX_N0 <10>
1
1
C282 2
<30> PCIE_ITX_WANRX_P1_C 1 2 0.1U_0402_10V7K~D PCIE_ITX_WANRX_P1 R23 PETP1 DMI0TXP U23 DMI_MRX_ITX_P0
DMI_MRX_ITX_P0 <10>
R308
R301 PCIE_IRX_WLANTX_N2 P25 W23 DMI_MTX_IRX_N1
<30> PCIE_IRX_WLANTX_N2 PERN2 DMI1RXN DMI_MTX_IRX_N1 <10>
8.2K_0402_5%~D PCIE_IRX_WLANTX_P2 P24 W24 DMI_MTX_IRX_P1
<30> PCIE_IRX_WLANTX_P2 PERP2 DMI1RXP DMI_MTX_IRX_P1 <10>
MINIWLAN (Mini Card 1) C283 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_N2 P21 V21 DMI_MRX_ITX_N1
DMI_MRX_ITX_N1 <10>
2
2
CLKRUN# <30> PCIE_ITX_WLANRX_N2_C C284 PETN2 DMI1TXN
<30> PCIE_ITX_WLANRX_P2_C 1 2 0.1U_0402_10V7K~D PCIE_ITX_WLANRX_P2 P22 PETP2 DMI1TXP V22 DMI_MRX_ITX_P1
DMI_MRX_ITX_P1 <10>
+CL_VREF1_ICH
1
N23 Y24 DMI_MTX_IRX_N2
PERN3 DMI2RXN DMI_MTX_IRX_N2 <10>
0.1U_0402_16V4Z~D
453_0402_1%~D
DMI_MTX_IRX_P2
PCI-Express
N24 PERP3 DMI2RXP Y25 DMI_MTX_IRX_P2 <10>
1
R303 M21 Y21 DMI_MRX_ITX_N2 1
PETN3 DMI2TXN DMI_MRX_ITX_N2 <10>
C289
R310
@ 10_0402_5%~D M22 Y22 DMI_MRX_ITX_P2
PETP3 DMI2TXP DMI_MRX_ITX_P2 <10>
2
PCIE_IRX_EXPTX_N4 M25 AB24 DMI_MTX_IRX_N3
B <35> PCIE_IRX_EXPTX_N4 PERN4 DMI3RXN DMI_MTX_IRX_N3 <10> 2 B
PCIE_IRX_EXPTX_P4 M24 AB25 DMI_MTX_IRX_P3
<35> PCIE_IRX_EXPTX_P4 DMI_MTX_IRX_P3 <10>
2
C287 PCIE_ITX_EXPRX_N4 PERP4 DMI3RXP DMI_MRX_ITX_N3
Express card <35> PCIE_ITX_EXPRX_N4_C 1 2 0.1U_0402_10V7K~D L24 PETN4 DMI3TXN AA23 DMI_MRX_ITX_N3 <10>
C288 1 2 0.1U_0402_10V7K~D PCIE_ITX_EXPRX_P4 L23 AA24 DMI_MRX_ITX_P3
<35> PCIE_ITX_EXPRX_P4_C PETP4 DMI3TXP DMI_MRX_ITX_P3 <10>
Option to "disable" CLKRUN. CLK_PCIE_ICH#
K24 PERN5 DMI_CLKN T21 CLK_PCIE_ICH# <6>
Pulling it down will keep the CLK running. K25 T22 CLK_PCIE_ICH
CLK_PCIE_ICH <6>
PERP5 DMI_CLKP
K21 PETN5
K22 AB21 R313
PETP5 DMI_ZCOMP DMI_IRCOMP
The same as MDC connector and for TAA module only PCIE_IRX_GLANTX_N6 DMI_IRCOMP AB22 1 2
24.9_0402_1%~D
+1.5V_RUN_PCIE_ICH
<28> PCIE_IRX_GLANTX_N6 H24 PERN6/GLAN_RXN
PCIE_IRX_GLANTX_P6 USBP0-
+3.3V_LAN <28> PCIE_IRX_GLANTX_P6
C291 1 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_N6
H25 PERP6/GLAN_RXP USBP0N AE2
USBP0+ ----->Right Side Top
JTAA
GIGA LAN <28> PCIE_ITX_GLANRX_N6_C C292 1
J24 PETN6/GLAN_TXN USBP0P AD1
<28> PCIE_ITX_GLANRX_P6_C 2 0.1U_0402_10V7K~D PCIE_ITX_GLANRX_P6 J23 PETP6/GLAN_TXP USBP1N AD3 Place close to ICH9M
SPI_CS0# 12 11 AD4
12 11 SPI_HOLD# SPI_CLK R323 USBP1P
10 10 9 9 1 2 15_0402_5%~D ICH_SPI_CLK E24 SPI_CLK USBP2N AC2
SPI_DIN 8 7 SPI_CS0# R316 1 2 15_0402_5%~D ICH_SPI_CS0# E23 AC3 +3.3V_SUS
8 7 SPI_CLK SPI_CS0# USBP2P USBP3- C1348
SPI_WP#
6
4
6 5 5
3
F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AC5
AB4 USBP3+
USBP3- <35> ----->Left Side Top 1 2
4 3 USBP3P USBP3+ <35>
SPI_DO SPI_DO R324 2 15_0402_5%~D ICH_SPI_DO USBP4-
2 2 1 1 1 F22 SPI_MOSI USBP4N AB2 USBP4- <30> ----->WLAN
SPI
ICH_SPI_DIN G23 AB1 USBP4+ 0.1U_0402_16V4Z~D
SPI_MISO USBP4P USBP4+ <30>
1@ TYCO_1-1734054-2~D USBP5-
USB_OC0# P4
USBP5N AA3
AA2 USBP5+
USBP5- <21> ----->WWAN U93
<35> USB_OC0# OC0#/GPIO59 USBP5P USBP5+ <21>
USBP6-
ESATA_USB_OC#
N4
N1
OC1#/GPIO40 USBP6N Y1
Y2 USBP6+
USBP6- <30> ----->BT 8 VCC NC 1
<35> ESATA_USB_OC# OC2#/GPIO41 USBP6P USB USBP7-
USBP6+ <30>
USBP0-
SPI Flash ROM: 208 mil SO8 USB_OC4#
P5 OC3#/GPIO42 USBP7N W2
USBP7+
USBP7- <35> ----->Express Card 2 HSD- D- 3 SW_USBP0- <35>
P1 OC4#/GPIO43 USBP7P W3 USBP7+ <35>
USB_OC5# USBP8- USBP0+
+3.3V_LAN +3.3V_ALW_ICH USB_OC6#
P2
M3
OC5#/GPIO29 USBP8N V1
V2 USBP8+
USBP8- <31> ----->DOCK 6 HSD+ D+ 5 SW_USBP0+ <35>
OC6#/GPIO30 USBP8P USBP8+ <31>
+3.3V_LAN RP13 USB_OC7# USBP9-
C293 5 4 USB_OC0# USB_OC8#
M2
P3
OC7#/GPIO31 USBP9N Y5
Y4 USBP9+
USBP9- <31> ----->DOCK 7 OE# GND 4
OC8#/GPIO44 USBP9P USBP9+ <31>
2
ESATA_USB_OC# USB_OC9# USBP10- FSUSB31K8X_US8~D
R320
1 2 6
7
3
2 USB_OC4# USB_OC10#
R1
R4
OC9#/GPIO45 USBP10N U3
U2 USBP10+
USBP10- <32> ----->BIO
OC10#/GPIO46 USBP10P USBP10+ <32>
2
A 3.3K_0402_5%~D 0.1U_0402_16V4Z~D USB_OC5# A
8 1 R2 OC11#/GPIO47 USBP11N V4
USBP11P V5
U12 R321 10K_1206_8P4R_5%~D USBRBIAS AE5
1
SPI_CS0# 3.3K_0402_5%~D RP14 USBRBIAS
1 /CS VCC 8 AD5 USBRBIAS#
22.6_0402_1%~D
R322 5 4 USB_OC6#
DELL CONFIDENTIAL/PROPRIETARY
1
ICH_SPI_DIN 1 2 SPI_DIN 2 7 SPI_HOLD# 6 3 USB_OC7# ICH9-M SFF ES_FCBGA569~D
DO /HOLD
R325
7 2 USB_OC8#
15_0402_5%~D SPI_WP# SPI_CLK USB_OC9#
3 /WP CLK 6 8 1 Compal Electronics, Inc.
4 5 SPI_DO 10K_1206_8P4R_5%~D PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
2
GND DIO USB_OC10# TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
1 2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9M SFF(3/4)
2@ W25X32VSSIG_SO8~D R314 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
10K_0402_5%~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
Within 500 mils
LA-4291P
Date: Friday, December 07, 2007 Sheet 24 of 49
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +1.05V_VCCP
U79F U79E
G17 VCCRTC VCC1_05[01] L11 B4 VSS[001] VSS[107] U5
VCC1_05[02] L12 B7 VSS[002] VSS[108] U10
+5V_RUN +3.3V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.022U_0402_16V7K~D
0.022U_0402_16V7K~D
ICH_V5REF_RUN G7 L13 B10 W11
V5REF VCC1_05[03] VSS[003] VSS[109]
1 1 VCC1_05[04] L14 1 1 B13 VSS[004] VSS[110] U14
C296
C297
C298
C299
ICH_V5REF_SUS U7 L15 B16 W16
V5REF_SUS VCC1_05[05] VSS[005] VSS[111]
2
VCC1_05[06] M11 B19 VSS[006] VSS[112] U21
R333 D8 J19 M15 B22 U22
100_0402_5%~D 2 2 VCC1_5_B[01] VCC1_05[07] 2 2 VSS[007] VSS[113]
RB751S40T1_SOD523-2~D K18 VCC1_5_B[02] VCC1_05[08] N11 D2 VSS[008] VSS[114] U25
K19 VCC1_5_B[03] VCC1_05[09] N15 D24 VSS[009] VSS[115] V3
L18 P11 E5 V8
2
1
ICH_V5REF_RUN VCC1_5_B[04] VCC1_05[10] VSS[010] VSS[116]
L19 VCC1_5_B[05] VCC1_05[11] P15 E7 VSS[011] VSS[117] V19
D D
M18 VCC1_5_B[06] VCC1_05[12] R11 E9 VSS[012] VSS[118] V23
1 M19 R12 L14 E11 W1
C300 +1.5V_RUN +1.5V_RUN_PCIE_ICH VCC1_5_B[07] VCC1_05[13] VSS[013] VSS[119]
N18 VCC1_5_B[08] VCC1_05[14] R13 1 2 +1.5V_RUN E13 VSS[014] VSS[120] W4
0.01U_0402_16V7K~D
10U_0805_4VAM~D
1U_0603_10V6K~D L13 N19 R14 BLM18PG181SN1_0603~D E15 W5
VCC1_5_B[09] VCC1_05[15] VSS[015] VSS[121]
1 2 P18 VCC1_5_B[10] VCC1_05[16] R15 1 1 E17 VSS[016] VSS[122] W7
2
220U_D2_4VY_R15M~D
C305
C306
BLM21PG600SN1D_0805~D R18 E19 W9
VCC1_5_B[11] VSS[017] VSS[123]
10U_0603_6.3V6M~D
10U_0603_6.3V6M~D
1 T18 VCC1_5_B[12] E21 VSS[018] VSS[124] W15
1 1 T19 VCC1_5_B[13] F24 VSS[019] VSS[125] W19
2 2
C301
C302
C303
+ U18 G2 W21
CORE
VCC1_5_B[14] VSS[020] VSS[126]
U19 VCC1_5_B[15] G5 VSS[021] VSS[127] W22
+5V_ALW +3.3V_ALW_ICH
G10 VSS[022] VSS[128] W25
2 2 2 L15 G13 VSS[023] VSS[129] Y3
1 2 +1.05V_VCCP G16 VSS[024] VSS[130] Y23
1
BLM18PG181SN1_0603~D G19 AA1
R335 D9 VSS[025] VSS[131]
1 G21 VSS[026] VSS[132] AA4
100_0402_5%~D RB751S40T1_SOD523-2~D H10 AA6
+VCCDMIPLL C308 VSS[027] VSS[133]
VCCDMIPLL P19 H12 VSS[028] VSS[134] AA8
4.7U_0603_6.3V6M~D +1.05V_VCCP H18 AA11
2
ICH_V5REF_SUS +VCC_DMI_ICH 2 VSS[029] VSS[135]
VCC_DMI[1] T17 H23 VSS[030] VSS[136] AA13
VCC_DMI[2] U17 J5 VSS[031] VSS[137] AA15
1 J9 VSS[032] VSS[138] AA16
4.7U_0603_6.3V6M~D
0.1U_0402_16V4Z~D
C307 V16 J10 AA17
1U_0603_10V6K~D V_CPU_IO[1] +3.3V_RUN VSS[033] VSS[139]
V_CPU_IO[2] U16 1 1 J11 VSS[034] VSS[140] AA19
C309
C310
J12 VSS[035] VSS[141] AA21
2
VCC3_3[01] V18 J13 VSS[036] VSS[142] AA22
0.1U_0402_16V4Z~D
J15 VSS[037] VSS[143] AA25
2 2
VCCA3GP
VCC3_3[02] AE9 +3.3V_RUN 1 J21 VSS[038] VSS[144] AB3
C312
J22 VSS[039] VSS[145] AB9
+3.3V_RUN J25 AB11
1 VSS[040] VSS[146]
C313 K2 AB13
+1.05V_VCCP C314 2 VSS[041] VSS[147]
VCC3_3[03] AA9 K9 VSS[042] VSS[148] AB15
V14 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D K10 AC24
C +1.5V_RUN +1.5V_RUN_SATAPLL VCC3_3[04] 2 VSS[043] VSS[149] C
VCC3_3[05] W14 1 2 K11 VSS[044] VSS[150] AC1
2 +1.5V_RUN L16 K12 AC4
VSS[045] VSS[151]
VCCP_CORE
R332 1 2 K13 AC10
10UH_LB2012T100MR_20%_0805~D VSS[046] VSS[152]
1 1 2 VCC3_3[06] G8 +3.3V_RUN K15 VSS[047] VSS[153] AC12
10U_0805_4VAM~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
@ 0.1U_0402_16V4Z~D
@ 0.1U_0402_16V4Z~D
VCC3_3[07] H7 +1.5V_RUN K17 VSS[048] VSS[154] AC14
0.1U_0402_16V4Z~D
3 10_0805_5%~D 1 1 H8 K23 AD2
C315 VCC3_3[08] VSS[049] VSS[155]
C316
D7 1 1 1 1 L5 AD6
VSS[050] VSS[156]
C317
C318
C319
C320
MMBD4148-7-F_SOT23-3~D L9 AD9
VSS[051] VSS[157]
L10 VSS[052] VSS[158] AD16
2 2
L16 VSS[053] VSS[159] AD19
2 2 2 2
PCI
L17 VSS[054] VSS[160] AD22
AD7 +1.5V_ALW_HDA L21 AE3
VCCHDA VSS[055] VSS[161]
L22 VSS[056] VSS[162] AE4
+1.5V_RUN W17 V10 L25 AE11
VCCSATAPLL VCCSUSHDA VSS[057] VSS[163]
0.1U_0402_16V4Z~D
M9 VSS[058] VSS[164] AE13
U13 T7 TP_VCCSUS1.05_INT_ICH1 T54 2 M10 AE15
VCC1_5_A[01] VCCSUS1_05[1] VSS[059] VSS[165]
C321
V13 H15 TP_VCCSUS1.05_INT_ICH2 T55 M12 V17
VCC1_5_A[02] VCCSUS1_05[2] VSS[060] VSS[166]
1 W13 VCC1_5_A[03] M13 VSS[061] VSS[167] AE8
ARX
H16 VCCSUS1_5_ICH_1 M14 V9
C322 VCCSUS1_5[1] T56 1 VSS[062] VSS[168]
M16 VSS[063] VSS[169] J16
0.1U_0402_16V4Z~D V7 VCCSUS1_5_ICH_2 M17
2 VCCSUS1_5[2] VSS[064]
M23 VSS[065]
1 N2 VSS[066]
G14 +3.3V_ALW_ICH C324 N5
VCCSUS3_3[01] VSS[067]
U12 VCC1_5_A[04] VCCSUS3_3[02] G15 N9 VSS[068]
V12 H14 0.1U_0402_16V4Z~D N10
VCC1_5_A[05] VCCSUS3_3[03] VSS[069]
VCCPSUS
2
0.1U_0402_16V4Z~D
1 W12 VCC1_5_A[06] N12 VSS[070]
C323
ATX
N13 VSS[071]
N14 VSS[072]
VCCSUS3_3[04] W8 N16 VSS[073]
2
N17 VSS[074]
VCCSUS3_3[05] J7 N21 VSS[075]
B
J8 +3.3V_ALW_ICH N22 B
VCCSUS3_3[06] VSS[076]
W10 VCC1_5_A[07] VCCSUS3_3[07] K7 N25 VSS[077]
VCCSUS3_3[08] K8 P9 VSS[078]
U15 VCC1_5_A[08] VCCSUS3_3[09] L7 P10 VSS[079]
0.022U_0402_16V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
V15 VCC1_5_A[09] VCCSUS3_3[10] L8 P12 VSS[080]
+1.5V_RUN
0.1U_0402_16V4Z~D
1 VCCSUS3_3[11] M7 1 1 1 P13 VSS[081]
C786
C325
C326
C327
W18 VCC1_5_A[10] VCCSUS3_3[12] M8 P14 VSS[082]
VCCSUS3_3[13] N7 P16 VSS[083]
VCCPUSB
G9 VCC1_5_A[11] VCCSUS3_3[14] N8 P17 VSS[084]
2 2 2 2
0.1U_0402_16V4Z~D
H9 VCC1_5_A[12] VCCSUS3_3[15] P7 P23 VSS[085]
1 VCCSUS3_3[16] P8 R5 VSS[086]
0.1U_0402_16V4Z~D
C328
1 V11 VCC1_5_A[13] R7 VSS[087]
C329
U11 VCC1_5_A[14] R8 VSS[088]
R9 VSS[089]
2 C330 R10 VSS[090]
+3.3V_LAN 2 VCCCL1_05_ICH
U8 VCCUSBPLL VCCCL1_05 G18 1 2 R16 VSS[091]
R17 VSS[092]
T9 H17 VCCCL1_5 0.1U_0402_16V4Z~D R19
VCC1_5_A[15] VCCCL1_5 VSS[093]
USB CORE
1U_0603_10V4Z~D
U9 VCC1_5_A[16] R21 VSS[094] VSS_NCTF[01] A1
0.1U_0402_16V4Z~D
1 VCCCL3_3[1] J14 +3.3V_LAN 1 R22 VSS[095] VSS_NCTF[02] A25
C331
C332
VCCCL3_3[2] K14 R25 VSS[096] VSS_NCTF[03] AE1
T2 VSS[097] VSS_NCTF[04] AE25
C334 T8
2 VCCLAN1.05_INT_ICH 2 VSS[098]
1 2 G11 VCCLAN1_05[1] T10 VSS[099]
H11 VCCLAN1_05[2] T11 VSS[100]
0.1U_0402_16V4Z~D T12 VSS[101]
G12 VCCLAN3_3[1] T13 VSS[102]
+1.5V_RUN H13 T14
L17 VCCLAN3_3[2] VSS[103]
T15 VSS[104]
1 2 +VCCGLANPLL J17 T16
1UH_GLF2012T1R0M_20%_0805~D VCCGLANPLL VSS[105]
T23 VSS[106]
+1.5V_RUN_PCIE_ICH
10U_0805_4VAM~D
2.2U_0603_6.3V6K~D
GLAN POWER
H19 VCCGLAN1_5[1]
A ICH9-M SFF ES_FCBGA569~D A
1 1 J18 VCCGLAN1_5[2]
C335
C336
10U_0805_4VAM~D
2 2 1
C337
K16
+3.3V_RUN VCCGLAN3_3
ICH9-M SFF ES_FCBGA569~D
DELL CONFIDENTIAL/PROPRIETARY
2
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, ICH9M SFF(4/4)
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 25 of 49
5 4 3 2 1
2 1
Place close to U22 pin 13 and 34
R376 +VDDA
+3.3V_RUN 5.11K_0402_1%~D
AUD_SENSE_A 2 1
+VDDA
1000P_0402_50V7K~D
1
1
+3.3V_RUN +3.3V_RUN
39.2K_0402_1%~D
20K_0402_1%~D
1
@ 10U_0805_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1000P_0402_50V7K~D
C388
@ 10U_0805_10V6K~D
100K_0402_5%~D
R378
R379
100K_0402_5%~D
+1.5V_RUN
1
0.1U_0402_10V7K~D
1U_0603_10V6K~D
1 1 1 1 2
C373
C374
C375
C372
R380
R385
1 1 1
6 2
3 2
C369
C371
C370
0.1U_0402_10V7K~D
U22
2 2 2 2
1
2
2 2 2
C377
1 DVDD_CORE AVDD 25
9 DVDD_CORE AVDD 38 <27,33,35> AUD_HP_NB_SENSE 2 5 AUD_MIC_SWITCH <35>
40 NC/OTP
2 Q6A Q6B
3
4
DVDD_IO AUD_SENSE_A 2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D
SENSE_A 13
34 AUD_SENSE_B R377 +VDDA BKT_GPIO11 EN_I2S_NB_CODEC
SENSE_B 5.11K_0402_1%~D
AUD_SENSE_B 2 1
1000P_0402_50V7K~D
ICH_AZ_CODEC_BITCLK 6 39 AUD_HP_OUT_L Without BKT H L
<23> ICH_AZ_CODEC_BITCLK HDA_BITCLK PORT_A_L AUD_HP_OUT_L <27>
1
+3.3V_RUN +3.3V_RUN
20K_0402_1%~D
39.2K_0402_1%~D
41 AUD_HP_OUT_R 1
PORT_A_R AUD_HP_OUT_R <27>
C389
2 ICH_AC_SDIN0_R 1 8 37
<23> ICH_AZ_CODEC_SDIN0 HDA_SDI_CODEC NC
100K_0402_5%~D
R381
R382
100K_0402_5%~D
33_0402_5%~D R366 BKT L H
1
ICH_AZ_CODEC_SDOUT 5
<23> ICH_AZ_CODEC_SDOUT HDA_SDO 2
R383
R384
21 AUD_EXT_MIC_L
AUD_EXT_MIC_L <35>
6 2
3 2
ICH_AZ_CODEC_SYNC PORT_B_L AUD_EXT_MIC_R
<23> ICH_AZ_CODEC_SYNC 10 HDA_SYNC PORT_B_R 22 AUD_EXT_MIC_R <35>
B B
VREFOUT_B 28 +VREFOUT
ICH_AZ_CODEC_RST# 11 Input Output
<23> ICH_AZ_CODEC_RST#
2
HDA_RST#
PORT_C_L 23 <33> DOCK_HP_DET 2 5 DOCK_MIC_DET <33> OE# A Y
PORT_C_R 24
29 Q7A Q7B 0 H L
4
VREFOUT_C 2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D
92HD71B 35 AUD_LINE_OUT_L
0 L H
PORT_D_L AUD_LINE_OUT_L <27>
36 AUD_LINE_OUT_R
PORT_D_R AUD_LINE_OUT_R <27>
R370 1 2 0_0402_5%~D DMIC_CLK_R 46
<35> DMIC_CLK DMIC_CLK
DMIC0 2 14 AUD_DOCK_MIC_IN_L C378 2 1 1U_0805_10V7K~D AUD_DOCK_MIC_IN_L_C
<35> DMIC0 DMIC0/VOL_UP/GPIO1 PORT_E_L +3.3V_RUN_BKT_PWR
15 AUD_DOCK_MIC_IN_R C379 2 1 1U_0805_10V7K~D AUD_DOCK_MIC_IN_R_C
PORT_E_R C779
4 DMIC1/VOL_DN/GPIO2 GPIO4/VREFOUT_E 31
R371 1 2
0_0603_5%~D U81
16 AUD_DOCK_HP_OUT_L C380 2 1 1U_0805_10V7K~D AUD_DOCK_HP_L_C 1 2 AUD_DOCK_HP_L_R BKT_GPIO11 1 16 0.1U_0402_16V4Z~D
PORT_F_L <36> BKT_GPIO11 1OE# VCC
17 AUD_DOCK_HP_OUT_R C381 2 1 1U_0805_10V7K~D AUD_DOCK_HP_R_C 1 2 AUD_DOCK_HP_R_R
PORT_F_R I2S_12MHZ BKT_GPIO11
GPIO3 30 2 1A1 2OE# 15
R372
AUD_EAPD 47 0_0603_5%~D BKT_MCLK 3 14
<27> AUD_EAPD SPDIF_OUT_0_1/EAPD/GPIO0 <21> BKT_MCLK 1Y1 2A2
NC 18
48 19 Place close to U22 BKT_I2S_SCLK 4 13
SPDIF_OUT_0 NC <21> BKT_I2S_SCLK 1A2 2Y2
Close to U22 pin6 Close to U22 pin5 NC 20
I2S_BCLK 5 1Y2 2A1 12
R360 C358
12 AUD_PC_BEEP 2 1 2 1 BKT_I2S_LRC 6 11
PC_BEEP SPKR <24> <21> BKT_I2S_LRC 1A3 2Y1
ICH_AZ_CODEC_BITCLK ICH_AZ_CODEC_SDOUT
Trace>15 mil 20K_0402_5%~D 0.1U_0402_16V4Z~D I2S_LRCLK 7 10 BKT_I2S_DO
1Y3 1A4 BKT_I2S_DO <21>
1
43 GPIO5 MONO_OUT 32
44 R361 C362 8 9 I2S_DI#
R373 R374 GPIO6 GND 1Y4
45 SPDIF_OUT_1/GPIO7 2 1 2 1 BEEP <34>
@ 10_0402_5%~D @ 47_0402_5%~D 33 CAP2 SN74HC368PWR_TSSOP16~D
CAP2
10K_0402_5%~D
27 VREFFILT 20K_0402_5%~D 0.1U_0402_16V4Z~D
2
VREFFILT
1
10U_0805_10V6K~D
1U_0603_10V6K~D
1 1
R362
7 1 1 +3.3V_RUN
DVSS
C384
C385
C382 C386 26
@ 10P_0402_50V8J~D @ 0.1U_0402_10V7K~D AVSS
49 Thermal PAD GND AVSS 42
2 2 +3.3V_RUN
2
2 2
@ DA204U_SOT323-3~D
@ DA204U_SOT323-3~D
@ DA204U_SOT323-3~D
@ DA204U_SOT323-3~D
92HD71B7X5NLGXB3X8_QFN48_7x7~D
0.1U_0402_16V7K~D
2
2
C383
+3.3V_RUN_BKT_PWR
D10
D11
D12
D13
L19
2 1 +3.3V_RUN_I2S_VDD
1
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
0.1U_0402_16V7K~D
BK1608LM182-T_0603~D
+3.3V_RUN_BKT_PWR U23
1
+3.3V_RUN_BKT_PWR +3.3V_RUN_BKT_PWR 1 2 2 16 VCC
C359
C360
C361
I2S_BCLK 2 3
1A 1Y DAI_BCLK# <31>
2.2K_0402_5%~D
2.2K_0402_5%~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
1U_0402_6.3V6K~D
0.1U_0402_16V7K~D
1
+3.3V_RUN_BKT_PWR 2 1 1 I2S_LRCLK
1 2 1 2 4 2A 2Y 5 DAI_LRCK# <31>
R369
R368
C367
C368
C365
C366
U21 I2S_DO 6 7
3A 3Y DAI_DO# <31>
SSM2602
2
2 1 2 1 I2S_12MHZ 10 9
2
4A 4Y DAI_12MHZ# <31>
3 DCVDD DVSS 4
6 1 DAI_SMBCLK 18 19 12 11
<6,34,46> CKG_SMBCLK AVDD AVSS 5A 5Y
12 HPVDD HPVSS 15 <33> EN_I2S_NB_CODEC
Q5A 5 14 13 I2S_DI#
DBVDD 6A 6Y
5
2N7002DW-7-F_SOT363-6~D
AUD_DOCK_HP_L_R 24 16 AUD_DOCK_MIC_IN_L_C R375 1
A DAI_SMBDATA LLINEIN LOUT AUD_DOCK_MIC_IN_R_C OE1# A
<6,34,46> CKG_SMBDAT 3 4 ROUT 17 2 1 15 OE2# GND 8
AUD_DOCK_HP_R_R 23
Q5B RLINEIN 1K_0402_5%~D
2N7002DW-7-F_SOT363-6~D DAI_SMBCLK 28 13 BKT_LSPK BKT_LSPK <27> CD74HC366M96_SO16~D
DAI_SMBDATA SCLK LHPOUT BKT_RSPK +3.3V_RUN
27 SDIN RHPOUT 14 BKT_RSPK <27>
I2S will disconnect SMBUS and PU for next version. XTALI_12MHZ I2S_12MHZ +3.3V_RUN +3.3V_RUN
1 MCLK/XTI CLKOUT 6
2
Need to check the PU value. XTALO_12MHZ 2 C390 C391
XTO/ POR I2S_BCLK
BCLK 7 2 1 2 1
T59 NC_MICIN 22 D14
R365 NC_MICBIAS MICIN I2S_DI# 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D @ DA204U_SOT323-3~D
T60 21 MICBIAS DACDAT 8
1
5
1
5
10K_0402_5%~D 10 I2S_DO
ADCDAT
2 1 25
P
NC
NC
1
R359 MODE
1 2 0_0402_5%~D XTALO_12MHZ R364
DACLRC 9 I2S_LRCLK 4 Y A 2 4 Y A 2 DAI_DI <31>
+3.3V_RUN_BKT_PWR 1 2 26 11 NC_ADCLRC T61
CSB ADCLRC
G
10K_0402_5%~D
Y2 @ 10K_0402_5%~D 20 29 U20 U25
3
VMID Thermal Pad
1
1 2 XTALI_12MHZ 74LVC1G14GV_SOT753-5~D 74LVC1G14GV_SOT753-5~D
1 SSM2602_LFCSP28_5X5~D
27P_0402_50V8J~D
27P_0402_50V8J~D
R367
12MHZ_12PF_1Y712000CE1I~D
C376
2 2
DELL CONFIDENTIAL/PROPRIETARY
C363
C364
1U_0402_6.3V6K~D
2
1 1 Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Codec 92HD71B and I2C D/A A/D converters
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
LA-4291P
Date: Friday, December 07, 2007 Sheet 26 of 49
2 1
5 4 3 2 1
+5V_SPK_AMP
C392
1 2
5
0.1U_0402_10V7K~D
AUD_NB_MUTE 2 R386
P
A
Y 4 1 2
<26,33,35> AUD_HP_NB_SENSE 1 B
G
D @ 0_0402_5%~D D
U26
3
74AHCT1G08GW_SOT353-5~D
Place close to Audio Chip W=40mils Gain Setting for TPA6040A4
+5V_SPK_AMP
C393 L20 +5V_SPK_AMP
1 2 1 2 +5V_SPK_AMP
+5V_RUN_BKT_PWR
BLM21PG600SN1D_0805~D
@ 100K_0402_5%~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
0.1U_0402_10V7K~D
1U_0603_10V6K~D
1U_0603_10V6K~D
10U_0805_10V6K~D
10U_0805_10V6K~D
100K_0402_5%~D
AUD_EAPD 2
P
<26> AUD_EAPD A
1
4 AUD_HP_EN 2 2 1 2 2 1 1
Y
1
C398
C399
C400
C401
C403
C402
C404
1 B
R388
R389
3 U27
74AHCT1G08GW_SOT353-5~D 1 1 2 1 1 2 2
2
AUD_GAIN1
AUD_GAIN2
30
18
8
@ 100K_0402_5%~D
U28
100K_0402_5%~D
VDD
SPVDD
SPVDD
1
R391
R392
C405 0 .033U_0805_50V7K~D
2 1 SPKR_INL_C 3 6 INT_SPK_R1
<26> AUD_LINE_OUT_L SPKR_LIN+ LOUT+
C406 0 .033U_0805_50V7K~D
2
2 1 SPKR_INR_C 2 7
<26> AUD_LINE_OUT_R SPKR_RIN+ LOUT-
C407 2.2U_1206_25V7M~D
C R387 1 HP_INL_C C
<26> AUD_HP_OUT_L 1 2 2 0_0402_5%~D 27 HP_INL ROUT+ 20
C408 2.2U_1206_25V7M~D
1 2 R390 1 2 0_0402_5%~D HP_INR_C 26 19 INT_SPK_R2
<26> AUD_HP_OUT_R HP_INR ROUT-
@ 47P_0402_50V8J~D
@ 47P_0402_50V8J~D
@ 47P_0402_50V8J~D
@ 47P_0402_50V8J~D
1 1 1 1
C410
C411
C412
C413
1 2 24 16 HP_SPK_L1_R R1124 1 2 0_0402_5%~D
C409 1U_0603_10V6K~D BYPASS HP_OUTL HP_SPK_L1 <35>
2 2 2 2 AUD_SPK_ENABLE# HP_SPK_R1_R R1125 0_0402_5%~D
INPUT
23 /SPKR_EN HP_OUTR 15 1 2 HP_SPK_R1 <35> GAIN1 GAIN2 AV(inv)
AUD_HP_EN
IMPEDANCE
22 HP_EN
AUD_AMP_MUTE# 25 31 AUD_GAIN1 0 0 6dB 82K ohm
REG_EN GAIN0
32 AUD_GAIN2
GAIN1
+5V_SPK_AMP 17 HPVDD 0 1 10dB 66K ohm
10U_0805_10V6K~D
1U_0603_10V6K~D
C1352 1 2 0.033U_0402_16V7K~D
BKT_LSPK <26>
1 2
C415
C416
For MAX9789A, depop R399 and pop R397 9 4 R393 1 2 @ 0_0402_5%~D 1 0 15.6dB 45K ohm
CPVDD SPKR_LIN-
C414
RUN_ON <20,21,33,37,45>
*
1 2 @ 0.033U_0402_16V7K~D
+5V_SPK_AMP 2 1 C1P 10 C1P 1 1 21.6dB 26K ohm
1U_0603_10V6K~D
REG_OUT 29 +VDDA
1
1M_0402_1%~D
1U_0603_10V6K~D
1U_0603_10V6K~D
C1N 12 C1N
1
2 2 2 Minimam 150 mA
R394
C417
R397 11 CPGND
C418
C419
@ 100K_0402_5%~D SET
SPGND
SPGND
1
HPVSS
CPVSS
SPKR_RIN-
SGND
2
R399 1 1 1
TP
2
RUN_ON 1 2 AUD_AMP_MUTE#
TPA6040A4RHBR_QFN32_5X5~D
14
13
28
5
21
33
B 0_0402_5%~D C420 B
2 1 +CPVSS C421
2 1 BKT_RSPK <26>
1U_0603_10V6K~D
0.033U_0402_16V7K~D
JSPK
SPEAKER_DET# 1
<24> SPEAKER_DET# INT_SPK_R1 1
2 2
+5V_SPK_AMP INT_SPK_R2 3 3
4 4
5 GND
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
6 GND
2
100K_0402_5%~D
R395
1 1 @ MOLEX_53780-0470
C396
C397
1
100K_0402_5%~D
1
AUD_SPK_ENABLE# 2 2
R396
6
<26> AUD_EAPD 2 15 mils trace
Q8A
1
2N7002DW-7-F_SOT363-6~D
3
A A
<33> AUD_NB_MUTE 5
Q8B
4
2N7002DW-7-F_SOT363-6~D
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Audio amplifier and speaker CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 27 of 49
5 4 3 2 1
5 4 3 2 1
+3.3V_LAN SOURCE
U29 +3.3V_ALW
C422 2 1 0.1U_0402_10V7K~D PCIE_IRX_GLANTX_P6_C 52 26 LAN_TX0-
<24> PCIE_IRX_GLANTX_P6 GLAN_TXP MDI_N_0
C423 2 1 0.1U_0402_10V7K~D PCIE_IRX_GLANTX_N6_C 53 27 LAN_TX0+
<24> PCIE_IRX_GLANTX_N6 GLAN_TXN MDI_P_0 +3.3V_LAN
Q40
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
PCIE_ITX_GLANRX_P6_C 55 22 LAN_TX1- STS11NF30L_SO8~D
<24> PCIE_ITX_GLANRX_P6_C GLAN_RXP MDI_N_1
PCIE_ITX_GLANRX_N6_C 56 23 LAN_TX1+ +15V_ALW 2 2 8 1
<24> PCIE_ITX_GLANRX_N6_C GLAN_RXN MDI_P_1
C424
C425
7 2
100K_0402_5%~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
20 LAN_TX2- 6 3
MDI_N_2
1
R400 1 2 33_0402_5%~D LAN_CLK_R 45 21 LAN_TX2+ 5 2 2
<23> LAN_CLK JKCLK MDI_P_2 1 1
C428
C429
LAN_RSTSYNC 50
<23> LAN_RSTSYNC JRSTSYNC
R710
D LAN_TX3- D
16
4
LAN_TX0 MDI_N_3 LAN_TX3+ +3.3V_ALW2
<23> LAN_TX0 42 JTXD_0 MDI_P_3 17
LAN_TX1 1 1
<23> LAN_TX1 43
2
LAN_TX2 JTXD_1
<23> LAN_TX2 44 JTXD_2 VDDO_33_3 3 +3.3V_LAN
1
46 ENAB_3VLAN
VDDO_33_46
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
4700P_0402_25V7K~D
@ 470K_0402_5%~D
LAN_RX0 47 28 R711
<23> LAN_RX0 JRXD_0 AVDD_33_28
1
2N7002DW-7-F_SOT363-6~D
LAN_RX1 48 2 2 100K_0402_5%~D 1
<23> LAN_RX1 JRXD_1
C431
C432
C702
R712
LAN_RX2 49 5 +1V_LAN_M
<23> LAN_RX2 JRXD_2 DVDD_10_5
Q18B
8
2
DVDD_10_8 AUX_ON_R
DVDD_10_33 33 5
1 1 2
38 Place close to U29
2
DVDD_10_38
6
2N7002DW-7-F_SOT363-6~D
@ 200K_0402_5%~D
LOM_ACTLED_YEL# 4
4
LED_0
1
LOM_SPD100LED_ORG# 2 11 +1.8V_LAN_M
LED_1 AVDD_18_11 +1V_LAN_M
Q18A
LOM_SPD10LED_GRN# 1 14
LED_2 AVDD_18_14
R720
AVDD_18_19 19 <34> AUX_ON 2
AVDD_18_18 18
R403 2 1 4.99K_0402_1%~D 15 24
2
RSET AVDD_18_24
0.1U_0402_16V4Z~D
4.7U_0603_6.3V6K~D
4.7U_0603_6.3V6K~D
AVDD_18_25 25
AVDD_18_41 41
R404 1 2 @ 0_0402_5%~D LAN_TEST_P 12 54 2 1 1
IEEE_TEST_P AVDD_18_54
C448
C445
C446
LAN_TEST_N 13 32
IEEE_TEST_N AVDD_18_32
AVDD_18_30 30
R407 2 1 1K_0402_5%~D 34 DIS_REG10 REGCTL_PNP18 1 2 2
CTRL18 29
1 2 LAN_DISABLE#_R 37 31
<24> LAN_DISABLE# LAN_DISABLE_N CTRL10
R1093 36 51 +1.8V_LAN_M regulator control
0_0402_5%~D TEST_EN RESERVED_NC
JTAG_TRST
JTAG_TMS
JTAG_TDO
JTAG_TCK
10K_0402_5%~D
XTALO
JTAG_TDI
<33> LAN_DISABLE#_R 9 XTAL2
2
XTALI 10 57
XTAL1 GND_PAD +3.3V_LAN
R409
C C
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
WG82567LM Q036 B0~D
1
35
40
39
7
6
1
2_1210_5%~D
2_1210_5%~D
R410 XTALO JTAG_TDO_LAN
Place close to U29
1 2 0_0402_5%~D R1103 1 2 @ 0_0402_5%~D 1 1
R401
R402
C433
C434
Y5 JTAG_TDI_LAN R783 1 2 @ 200_0402_5%~D +1.8V_LAN_M
+3.3V_LAN
1 2 XTALI
2
JTAG_TMS_LAN R411 2 2
1 2 @ 200_0402_5%~D
27P_0402_50V8J~D
27P_0402_50V8J~D
2 25MHZ_18PF_1Y725000CE1A~D 2
470P_0402_50V7K~D
470P_0402_50V7K~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
10U_0805_10V4Z~D
JTAG_TCK_LAN R412 1 2 @ 200_0402_5%~D
C443
C444
R405
JTAG_TRST_LAN R414 1 2 @ 1K_0402_5%~D 1 1 2 2 2 2 1 2 1
1 1
C440
C441
C436
C437
C438
C439
C435
Q41
3
5.1K_0402_5%~D BCP69_SOT223~D
2 2 1 1 1 1 2 REGCTL_PNP18 1
+1.8V_LAN_M
Make sure crystal at least 300uW max drive level
2
4
10U_0805_10V4Z~D
1
C442
+3.3V_LAN 2
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2 2
C462
C463
C464
1 1 1
56
50
38
27
18
10
4
B U31 B
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
VDD0
48 SW_LAN_TX0- +3.3V_LAN +LOM_VCT
0B1 SW_LAN_TX0- <35>
47 SW_LAN_TX0+ U94
1B1 SW_LAN_TX0+ <35>
LAN_TX0- L21 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX0-R 2 1 5
A0 IN OUT
4.7U_0603_6.3V4Z~D
4.7U_0603_6.3V4Z~D
0.1U_0402_16V4Z~D
43 SW_LAN_TX1- 2
2B1 SW_LAN_TX1- <35> GND
LAN_TX0+ L22 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX0+R 3 42 SW_LAN_TX1+ 1 3 4 1 1
A1 3B1 SW_LAN_TX1+ <35> EN NR/FB
C1356
C1357
C1355
37 SW_LAN_TX2- TPS73601DBVR_SOT23-5~D
LAN_TX1- L23 22NH_0603CS-360EJTS_5%_0603~D LAN_TX1-R 4B1 SW_LAN_TX2+ SW_LAN_TX2- <35>
1 2 7 A2 5B1 36 SW_LAN_TX2+ <35> 2 2 2
LAN_TX1+ L24 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX1+R 8 32 SW_LAN_TX3-
A3 6B1 SW_LAN_TX3- <35>
4.64K_0402_1%
31 SW_LAN_TX3+
7B1 SW_LAN_TX3+ <35>
1
3
R1094
E
LAN_TX2- L25 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX2-R 11 22 LAN_LEDACT# R432 1 2 150_0402_5%~D LAN_ACTLED_YEL_R# <35> R1095
A4 0LED1 LINK_LED100# R433 110_0402_5%~D DOCK_DET#
B
1LED1 23 1 2 LED_100_ORG_R# <35> <31,33> DOCK_DET# 1 2 2
LAN_TX2+ L26 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX2+R 12 52 LINK_LED10# R434 1 2 200_0402_5%~D LED_10_GRN_R# <35>
A5 2LED1 10K_0402_5%~D
C
2
46 DOCK_LOM_TRD0- Q120
0B2 DOCK_LOM_TRD0- <31>
LAN_TX3- L27 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX3-R 14 45 DOCK_LOM_TRD0+ MMBT3906WT1G_SC70-3~D
A6 1B2 DOCK_LOM_TRD0+ <31>
1
LAN_TX3+ L28 1 2 22NH_0603CS-360EJTS_5%_0603~D LAN_TX3+R 15 41 DOCK_LOM_TRD1- R1096
A7 2B2 DOCK_LOM_TRD1- <31>
40 DOCK_LOM_TRD1+ 39.2K_0402_1%~D
3B2 DOCK_LOM_TRD1+ <31>
DOCKED 17 35 DOCK_LOM_TRD2-
2
<33> DOCKED SEL 4B2 DOCK_LOM_TRD2+ DOCK_LOM_TRD2- <31>
1: TO DOCK 5B2 34 DOCK_LOM_TRD2+ <31>
DOCKED
1
0: TO RJ45 LOM_ACTLED_YEL# 19 30 DOCK_LOM_TRD3-
LED0 6B2 DOCK_LOM_TRD3- <31>
LOM_SPD100LED_ORG# 20 29 DOCK_LOM_TRD3+ R1097
+3.3V_LAN LED1 7B2 DOCK_LOM_TRD3+ <31>
LOM_SPD10LED_GRN# 54 VOUT = 1.204 (1+R1/R2), 36.5K_0402_1%~D
LED2 DOCK_LOM_ACTLED_YEL#
0LED2 25 DOCK_LOM_ACTLED_YEL# <31>
5 26 DOCK_LOM_SPD100LED_ORG#
DOCK_LOM_SPD100LED_ORG# <31>
where R1 = R1094 + R1096, R2 = R1097
2
A NC 1LED2 DOCK_LOM_SPD10LED_GRN# A
2LED2 51 DOCK_LOM_SPD10LED_GRN# <31>
@ 10K_0402_5%~D
@ 10K_0402_5%~D
@ 10K_0402_5%~D
57 PAD_GND
GND10
GND11
GND12
GND13
1
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
R429
R430
R431
PI3L500-AZFEX_TQFN56~D
DELL CONFIDENTIAL/PROPRIETARY
1
6
9
13
16
21
24
28
33
39
44
49
53
55
Compal Electronics, Inc.
2
LOM_ACTLED_YEL# PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
LOM_SPD10LED_GRN# TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
LOM_SPD100LED_ORG# BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Boazman 82567LM and LAN SWITCH
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 28 of 49
5 4 3 2 1
5 4 3 2 1
Function set pin define
UDIO3 UDIO4 MSEN XDEN Function
Enable
Pull-up Pull-up Pull-down Pull-down SD,MMC Card
+3.3V_RUN
U56
<22> PCI_AD[0..31]
PCI_AD31 125 10 SD,MMC muti-function pin define
PCI_AD30 AD31 VCC_PCI3V
126 AD30 VCC_PCI3V 20
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
10U_0805_6.3V6M~D
D PCI_AD29 D
127 AD29 VCC_PCI3V 27
PCI_AD28 1 32 Media I/F SD Card MMC Card
PCI_AD27 2
AD28
AD27 R5C833 VCC_PCI3V
VCC_PCI3V 41
+3.3V_RUN
1 1 1 1 1 1
0.01U_0402_16V7K~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
10U_0805_6.3V6M~D
C465
C466
C467
C468
C469
C470
PCI_AD26 3 128 MDIO00 SDCD# MMCCD#
PCI_AD25 AD26 VCC_PCI3V
5 AD25
PCI_AD24 6 61 1 1 1 1 MDIO01
AD24 VCC_RIN 2 2 2 2 2 2
C471
C472
C473
C474
PCI_AD23 9
+3.3V_RUN PCI_AD22 AD23
11 AD22 VCC_ROUT 16 +VCC_ROUT MDIO02
PCI_AD21 12 34
AD21 VCC_ROUT +3.3V_RUN 2 2 2 2
100K_0402_5%~D
PCI_AD20 14 64 MDIO03 SDWP#
PCI_AD19 AD20 VCC_ROUT
15 AD19 VCC_ROUT 114
1
PCI_AD18 17 120 MDIO04 SDPWR0 MMCPWR
AD18 VCC_ROUT
R436
PCI_AD17 18 AD17
C475
0.01U_0402_16V7K~D
C476
10U_0805_6.3V6M~D
PCI_AD16 19 67 1 1 MDIO05 SDPWR1
PCI_AD15 AD16 VCC_3V
36 AD15 +VCC_ROUT
PCI_AD14 37 86 MDIO06 SDLED# MMCLED#
2
AD14 VCC_MD3V +3.3V_RUN_PHY
0.01U_0402_16V7K~D
0.01U_0402_16V7K~D
0.47U_0402_10V4Z~D
0.47U_0402_10V4Z~D
PCI_AD13 38
BUS_GRST# PCI_AD12 AD13 2 2
39 AD12 AVCC_PHY3V 98 MDIO07 SDEXTCK
PCI_AD11 40 106 1 1 1 1
AD11 AVCC_PHY3V
1U_0603_10V6K~D
C477
C478
C479
C480
PCI_AD10 42 110 MDIO08 SDCCMD MMCCMD
PCI_AD9 AD10 AVCC_PHY3V
1 43 AD9 AVCC_PHY3V 112
C481
PCI_AD8 44 MDIO09 SDCCLK MMCCLK
PCI_AD7 AD8 TPBIAS0 2 2 2 2
46 AD7 TPBIAS0 113
CLK_PCI_R5C833 PCI_AD6 47 MDIO10 SDCDAT0 MMCDAT0
2 PCI_AD5 AD6 TPA0+
48 AD5 TPAP0 109
@ PCI_AD4 TPA0-
49 AD4 TPAN0 108 MDIO11 SDCDAT1 MMCDAT1
1
10_0402_5%~D
PCI_AD3 50 AD3
R439
PCI_AD2 51 105 TPB0+ MDIO12 SDCDAT2 MMCDAT2
PCI_AD1 AD2 TPBP0 TPB0-
52 AD1 TPBN0 104
PCI_AD0 53 MDIO13 SDCDAT3 MMCDAT3
AD0 SDCD#_MMCCD#
80 SDCD#_MMCCD# <35>
2
MDIO00
C MDIO01 79 MDIO14 MMCDAT4 C
<22> PCI_C_BE3# PCI_C_BE3# 7 78 +3.3V_RUN_PHY
PCI_C_BE2# C/BE3# MDIO02 SDWP# L29
<22> PCI_C_BE2# 21 C/BE2# MDIO03 77 SDWP# <35> MDIO15 MMCDAT5
@ <22> PCI_C_BE1# PCI_C_BE1# 35 76 CARD_EN CARD_EN <35> 2 1 +3.3V_RUN
C/BE1# MDIO04
10P_0402_50V8J~D
<22> PCI_C_BE0# PCI_C_BE0# 45 75 MDIO16 MMCDAT6
C/BE0# MDIO05
1000P_0402_50V7K~D
0.1U_0402_16V4Z~D
0.01U_0402_16V7K~D
10U_0805_6.3V6M~D
1 74 TP_SD/MMC_LED# T67 BLM21AG601SN1D_0805~D
MDIO06
MDIO07 73 MDIO17 MMCDAT7
C485
PCI_PAR 33 88 SDCCMD_MMCCMD 1 1 1 1
<22> PCI_PAR PAR MDIO08 SDCCMD_MMCCMD <35>
C489
C488
C487
C486
PCI_FRAME# 23 84 SDCCLK_MMCCLK MDIO18
2 <22> PCI_FRAME# FRAME# MDIO09 SDCCLK_MMCCLK <35>
PCI_TRDY# 25 82 SDCDAT0_MMCDAT0
<22> PCI_TRDY# TRDY# MDIO10 SDCDAT0_MMCDAT0 <35>
PCI _IRDY# 24 81 SDCDAT1_MMCDAT1 MDIO19
<22> PCI_IRDY# IRDY# MDIO11 SDCDAT1_MMCDAT1 <35> 2 2 2 2
PCI_STOP# 29 93 SDCDAT2_MMCDAT2
<22> PCI_STOP# STOP# MDIO12 SDCDAT2_MMCDAT2 <35>
PCI_DEVSEL# 26 90 SDCDAT3_MMCDAT3
<22> PCI_DEVSEL# DEVSEL# MDIO13 SDCDAT3_MMCDAT3 <35>
PCI_AD17 1 2 PCI_IDSEL 8 91 MMCDAT4
IDSEL MDIO14 MMCDAT4 <35>
100_0402_5%~D R440 PCI_PERR# 30 89 MMCDAT5
<22> PCI_PERR# PERR# MDIO15 MMCDAT5 <35>
PCI_SERR# 31 92 MMCDAT6
<22> PCI_SERR# SERR# MDIO16 MMCDAT6 <35>
87 MMCDAT7
MDIO17 MMCDAT7 <35>
MDIO18 85
PCI_REQ1# 124 83
<22> PCI_REQ1# PCI_GNT1# REQ# MDIO19
<22> PCI_GNT1# 123 GNT#
MSEN 58
XDEN 55 Layout Note:
<6> CLK_PCI_R5C833
PCI_RST#
121 PCICLK R5C833XI Place C490,C492,R445 close to R5C833 Place close to R5C833 Chip
<22,31> PCI_RST# 119 PCIRST# XI 94
BUS_GRST# 71 95 R5C833XO
GBRST# XO TPBIAS0
117 CLKRUN#
R442 1 2 0_0402_5%~D 70 96 0.01U_0402_16V7K~D 1 2 C490
<24,33,34> CLKRUN# PME# FIL0
0.01U_0402_16V7K~D
0.33U_0603_10V7K~D
R443 101
REXT
56.2_0603_1%~D
56.2_0603_1%~D
<33> SYS_PME# 1 2 VREF 100
1
0.01U_0402_16V7K~D
115 INTA# 1 1
10K_0402_1%~D
R457
R458
C494
C495
@ 0_0402_5%~D 116 72
INTB# UDIO0/SRIRQ# IRQ_SERIRQ <24,32,33,34>
2
<22> PCI_PIRQD# 60 2
UDIO1 +3.3V_RUN
C492
R445
<22> PCI_PIRQC# 56 R447
B R446 1 UDIO2 2 2 B
<33> CB_HWSPND# 2 @ 0_0402_5%~D 69 65 10K_0402_5%~D
2
HWSPND# UDIO3 UDIO4
66 TEST UDIO4 59 1 2
R450 UDIO5 1
57 1 2
1
UDIO5
100K_0402_5%~D
+3.3V_RUN 1 2 R448 TPA0+
TPA0+ <35>
2
99 4 100K_0402_5%~D
AGND GND
R452
10K_0402_5%~D 102 13
AGND GND TPA0-
103 AGND GND 22 TPA0- <35>
107 AGND GND 28
111 54 TPB0+
TPB0+ <35>
1
AGND GND
GND 62
GND 63
97 68 TPB0-
RSV GND TPB0- <35>
GND 118
56.2_0603_1%~D 270P_0402_50V7K~D
56.2_0603_1%~D
GND 122
1
R460
R461
R5C833-TQFP128P_TQFP128_14X14~D
Layout Note: Place close to
R5C833 and Shield GND
2
5.1K_0603_1%~D
2
2
C498
R462
C491
22P_0402_50V8J~D
R5C833XI 2 1
1
1
2
X2
24.576MHz_16P_1BG24576CKIA~D
A A
1
R451
R5C833XO 2 1 2 1
220_0402_5%~D C493
22P_0402_50V8J~D DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, R5C833-SD/MMC and 1394 Controller
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 29 of 49
5 4 3 2 1
5 4 3 2 1
Mini Card 1---WLAN
WLAN_RADIO_DIS#_R 2 1 WLAN_RADIO_DIS# <33>
+3.3V_WLAN +3.3V_WLAN D18
RB751S40T1_SOD523-2~D +3.3V_WLAN
JMINI1 +1.5V_RUN
2.2K_0402_5%~D
2.2K_0402_5%~D
D PCIE_WAKE# D
1 1 2 2
1
COEX2_WLAN_ACTIVE R486 1 2 0_0402_5%~D 3 4
3 4
R477
R478
COEX1_BT_ACTIVE R487 1 2 0_0402_5%~D 5 6
<6> MINI1CLK_REQ# 7
9
5
7
9
6
8
10
8
10
C1353
1 2
BlueTooth
2
COEX2_WLAN_ACTIVE 11 12
2
<6> CLK_PCIE_MINI1# 11 12 4700P_0402_25V7K~D
<6> CLK_PCIE_MINI1 13 13 14 14
1 15 16 WLAN_SMBCLK 1 6 +3.3V_RUN
15 16 HOST_DEBUG_TX <34> CARD_SMBCLK <34,35>
C521 17 18 C545
@ 33P_0402_50V8J~D <34> HOST_DEBUG_RX 17 18 WLAN_RADIO_DIS#_R Q12A
<34> MSCLK 19 19 20 20 1 2
5
21 22 2 1 PLTRST3# 2N7002DW-7-F_SOT363-6~D
2 21 22 R490 0.1U_0402_16V4Z~D
<24> PCIE_IRX_WLANTX_N2 23 23 24 24
25 26 0_0402_5%~D WLAN_SMBDATA 4 3
<24> PCIE_IRX_WLANTX_P2 25 26 CARD_SMBDAT <34,35>
27 28 JBT
27 28 WLAN_SMBCLK Q12B
29 29 30 30 1 1
+1.5V_RUN 31 32 WLAN_SMBDATA 2N7002DW-7-F_SOT363-6~D COEX1_BT_ACTIVE 2
<24> PCIE_ITX_WLANRX_N2_C 31 32 2
33 34 COEX2_WLAN_ACTIVE 3
<24> PCIE_ITX_WLANRX_P2_C 33 34 3
35 36 USBP4_D- R498 2 1 0_0402_5%~D 4
35 36 USBP4- <24> 4
37 38 USBP4_D+ R499 2 1 0_0402_5%~D +15V_ALW 5
<24> PCIE_MCARD1_DET# 37 38 USBP4+ <24> <22> BT_DET# 5
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
39 40 USB_MCARD1_DET# 6
39 40 USB_MCARD1_DET# <24> <33> BT_RADIO_DIS# 6
41 42 MSDATA_WIMAX_LED 7
41 42 <24> USBP6+ 7
100K_0402_5%~D
1 1 43 44 LED_WLAN_OUT# +3.3V_ALW +3.3V_WLAN 8
43 44 LED_WLAN_OUT# <38> <24> USBP6- 8
C524
C525
<24> ICH_CL_CLK1 45 45 46 46 1 2 BT_ACTIVE <38> BT_ACTIVE 9 9
D
47 48 R492 6 10
S
<24> ICH_CL_DATA1 47 48 10
100K_0402_5%~D
R476
@ 100P_0402_50V8J~D
1 2 49 50 @ 0_0402_5%~D 5 4 11
<24> ICH_CL_RST1# 49 50 11
1
2 2
33P_0402_50V8J~D
10K_0402_5%~D
R493 51 52 2 1 12
51 52 12
C1334
0_0402_5%~D 1 2 1 Q48 1
MSDATA <34>
R479
C546
R500
53 54 R1085 0_0402_5%~D SI3456BDV-T1-E3_TSOP6~D 13
G
2
GND1 GND2 MSDATA_WIMAX_LED WIMAX LED GND1
1 2 14
3
R1086 @ 0_0402_5%~D 2 GND2
2
TYCO_1775861-1~D 2 MOLEX_52893-1219
2
3
2N7002DW-7-F_SOT363-6~D
+3.3V_WLAN WWAN noise
+3.3V_RUN
Q11B
@ 470K_0402_5%~D
C C
4700P_0402_25V7K~D
R484
1
@ 0.1U_0402_16V4Z~D
@ 330U_D2E_6.3VM_R25~D
USB_MCARD1_DET# 1 2 USB_MCARD1_DET# 5 1
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
4.7U_0603_6.3V4Z~D
@ 200K_0402_5%~D
R480
C520
1 100K_0402_5%~D 1
4
6
1
1 1 1 1 1 1 C522 Q11A
2
C527
C528
C529
C530
C526
C531
C523
R481
+ R485 4700P_0402_25V7K~D 2N7002DW-7-F_SOT363-6~D
2
PCIE_MCARD1_DET# 1 2
2
<34> AUX_EN_WOWL 2
2 2 2 2 2 2 2 @ 100K_0402_5%~D
2
1
100K_0402_5%~D
1
+3.3V_ALW_ICH
R483
R1128
PCIE_MCARD1_DET# 1 2 R488
USB_MCARD1_DET# 1 2 PCIE_MCARD1_DET#
2
100K_0402_5%~D
@ 0_0402_5%~D
Mini Card 2---WWAN SIM Card
+3.3V_RUN_WWAN_PWR +3.3V_RUN_WWAN_PWR U39
JMINI2 +1.5V_RUN
+3.3V_RUN_WWAN_PWR
1 2 UIM_RESET 1 6 UIM_VPP
<33,35> PCIE_WAKE# 1 2
2.2K_0402_5%~D
2.2K_0402_5%~D
3 3 4 4
1
5 5 6 6
R474
R475
<6> MINI2CLK_REQ# 7 7 8 8 +SIM_PWR 2 5 +SIM_PWR
B UIM_DATA B
9 9 10 10
11 12 UIM_CLK
<6> CLK_PCIE_MINI2# 11 12
2
13 14 UIM_RESET UIM_CLK 3 4 UIM_DATA
2
<6> CLK_PCIE_MINI2 13 14 UIM_VPP
15 15 16 16
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
33P_0402_50V8J~D
17 18 WWAN_SMBCLK 1 6 CARD_SMBCLK
17 18 WWAN_RADIO_DIS#
19 19 20 20 WWAN_RADIO_DIS# <33> 1 1 1 1
C541
C542
C543
C544
21 22 1 2 Q10A SRV05-4.TCT_SOT23-6~D
21 22 PLTRST3# <22,32>
5
23 24 R489 2N7002DW-7-F_SOT363-6~D
<24> PCIE_IRX_WANTX_N1 23 24 0_0402_5%~D
<24> PCIE_IRX_WANTX_P1 25 25 26 26
WWAN_SMBDATA CARD_SMBDAT 2 2 2 2
27 27 28 28 4 3
29 30 WWAN_SMBCLK
29 30 WWAN_SMBDATA Q10B
<24> PCIE_ITX_WANRX_N1_C 31 31 32 32
33 34 2N7002DW-7-F_SOT363-6~D
<24> PCIE_ITX_WANRX_P1_C 33 34
35 36 WWAN_USBD- R496 2 1 0_0402_5%~D
35 36 WWAN_SW_USBD- <21> +SIM_PWR
37 38 WW AN_USBD+ R497 2 1 0_0402_5%~D
<22> PCIE_MCARD2_DET# 37 38 WWAN_SW_USBD+ <21>
39 40 USB_MCARD2_DET# JSIM
39 40 USB_MCARD2_DET# <24> +3.3V_RUN_WWAN_PWR
41 42 LED_WWAN_OUT# 1
41 42 LED_WWAN_OUT# <38> 1
43 44 R494 UIM_RESET 2
43 44 USB_MCARD2_DET# UIM_CLK 2
45 45 46 46 2 1 3 3
+1.5V_RUN
1U_0603_10V4Z~D
+3.3V_RUN_WWAN_PWR 47 48 R491 4
47 48 WIMAX LED 100K_0402_5%~D 4
49 49 50 50 1 2 1 5 5
C540
51 52 UIM_VPP 6
51 52 @ 0_0402_5%~D R495 UIM_DATA 6
7 7
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
33P_0402_50V8J~D
33P_0402_50V8J~D
0.047U_0402_16V4Z~D
0.047U_0402_16V4Z~D
22U_0805_6.3VAM~D
330U_D2E_6.3VM_R25~D
53 54 PCIE_MCARD2_DET# 1 2 8
GND1 GND2 2 8
1 For WIMAX LED debug 100K_0402_5%~D
9 GND
1 1 1 1 1 1 1 10 GND
C538
C539
C535
C537
C533
C534
C536
C532
+ TYCO_1775861-1~D
MOLEX_475531001_NR
R482
2 2 2 2 2 2 2 2 USB_MCARD2_DET# PCIE_MCARD2_DET#
1 2
@ 0_0402_5%~D
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Mini WLAN/WWAN, SIM card and BT
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 30 of 49
5 4 3 2 1
2 1
JDOCK
Place close to JDOCK connector HPD# inverting level shifting circuit for DisplayPort C
1 2 DOCK_AC_OFF
@ D19 1 2 DOCK_AC_OFF <33> +3.3V_RUN
<28> DOCK_LOM_SPD10LED_GRN# 3 3 4 4 DOCK_LOM_SPD100LED_ORG# <28>
DPB_LANE_P0_C 1 10 DPB_LANE_P0_C DPB_CA_DET 5 6 DPC_CA_DET
5 6
7 7 8 8
2
DPB_LANE_N0_C 2 9 DPB_LANE_N0_C DPB_LANE_P0_C 9 10 DPC_LANE_P0_C
<12> DPB_LANE_P0_C DPB_LANE_N0_C 9 10 DPC_LANE_N0_C DPC_LANE_P0_C <12> R501
<12> DPB_LANE_N0_C 11 11 12 12 DPC_LANE_N0_C <12>
DPB_LANE_P1_C 4 7 DPB_LANE_P1_C 13 14
DPB_LANE_P1_C 13 14 DPC_LANE_P1_C 20K_0402_5%~D
<12> DPB_LANE_P1_C 15 15 16 16 DPC_LANE_P1_C <12>
DPB_LANE_N1_C 5 6 DPB_LANE_N1_C DPB_LANE_N1_C 17 18 DPC_LANE_N1_C
1
<12> DPB_LANE_N1_C 17 18 DPC_LANE_N1_C <12>
19 19 20 20 DPC_DOCK_HPD# <12>
3 DPB_LANE_P2_C 21 22 DPC_LANE_P2_C
<12> DPB_LANE_P2_C 21 22 DPC_LANE_P2_C <12>
2
DPB_LANE_N2_C DPC_LANE_N2_C D Q49
<12> DPB_LANE_N2_C 23 23 24 24 DPC_LANE_N2_C <12>
8 25 26 DPC_DOCK_HPD 2 R502
DPB_LANE_P3_C 25 26 DPC_LANE_P3_C G BSS138_SOT23~D
<12> DPB_LANE_P3_C 27 27 28 28 DPC_LANE_P3_C <12>
100K_0402_5%~D
RCLAMP0524P.TCT~D DPB_LANE_N3_C 29 30 DPC_LANE_N3_C S 7.5K_0402_5%~D
3
<12> DPB_LANE_N3_C 29 30 DPC_LANE_N3_C <12>
2
31 32
1
@ D20 SDVO_CTRLCLK 31 32 DDPC_CTRLCLK
<10> SDVO_CTRLCLK 33 33 34 34 DDPC_CTRLCLK <10>
R503
DPB_LANE_P2_C 1 10 DPB_LANE_P2_C SDVO_CTRLDATA 35 36 DDPC_CTRLDATA
<10> SDVO_CTRLDATA 35 36 DDPC_CTRLDATA <10>
37 37 38 38
DPB_LANE_N2_C 2 9 DPB_LANE_N2_C DPB_DOCK_HPD 39 40 DPC_DOCK_HPD
1
39 40 ACAV_DOCK_SRC#
+NBDOCK_DC_IN_SS 41 41 42 42 ACAV_DOCK_SRC# <34,47>
DPB_LANE_P3_C 4 7 DPB_LANE_P3_C 43 44
BLUE_DOCK 43 44 DAT_DDC2_DOCK
<20> BLUE_DOCK 45 45 46 46 DAT_DDC2_DOCK <20>
DPB_LANE_N3_C 5 6 DPB_LANE_N3_C 47 48 CLK_DDC2_DOCK
47 48 CLK_DDC2_DOCK <20>
49 49 50 50
3 51 51 52 52
B RED_DOCK SATA_SBRX_DTX_P3 C548 B
<20> RED_DOCK 53 53 54 54 2 1 0.01U_0402_16V7K~D SATA_SBRX_DTX_P3_C <23>
8 55 56 SATA_SBRX_DTX_N3 C549 2 1 0.01U_0402_16V7K~D
55 56 SATA_SBRX_DTX_N3_C <23>
57 57 58 58
RCLAMP0524P.TCT~D GREEN_DOCK 59 60
<20> GREEN_DOCK 59 60 SATA_SBTX_C_DRX_P3 <23>
61 61 62 62 SATA_SBTX_C_DRX_N3 <23>
@ D21 63 64
SDVO_CTRLCLK SDVO_CTRLCLK H SYNC_DOCK 63 64 USBP8+
1 10 <20> HSYNC_DOCK 65 65 66 66 USBP8+ <24>
VSYNC_DOCK USBP8-
SDVO_CTRLDATA 2 9 SDVO_CTRLDATA
<20> VSYNC_DOCK 67
69
67 68 68
70
USBP8- <24> Switch that support both DisplayPort C and DVI/HDMI
CLK_MSE 69 70 USBP9+
<34> CLK_MSE 71 71 72 72 USBP9+ <24>
DPB_DOCK_HPD 4 7 DPB_DOCK_HPD DAT_MSE 73 74 USBP9-
<34> DAT_MSE 73 74 USBP9- <24>
75 75 76 76
DPB_CA_DET 5 6 DPB_CA_DET DAI_BCLK# 77 78 CLK_KBD
<26> DAI_BCLK# 77 78 CLK_KBD <34>
2
DAI_LRCK# 79 80 DAT_KBD
<26> DAI_LRCK# 79 80 DAT_KBD <34>
3 81 82 C550 R504
DAI_DI 81 82 DDPC_CTRLCLK DPC_F DPC_B
<26> DAI_DI 83 83 84 84 1 2 6 1 2 1 DPC_DOCK_AUX <12>
8 DAI_DO# 85 86
<26> DAI_DO# 85 86
87 88 0.1U_0402_10V7K~D Q13A 0_0402_5%~D
RCLAMP0524P.TCT~D DAI_12MHZ# 87 88 2N7002DW-7-F_SOT363-6~D
<26> DAI_12MHZ# 89 89 90 90
91 91 92 92
@ D22 93 94 Q13B
DPC_LANE_P0_C DPC_LANE_P0_C 93 94 C551 2N7002DW-7-F_SOT363-6~D R505
1 10 95 95 96 96
D_LAD0 97 98 BREATH_LED# DDPC_CTRLDATA 1 2 DPC#_F 3 4 DPC#_B 2 1
<33> D_LAD0 97 98 BREATH_LED# <34,38> DPC_DOCK_AUX# <12>
DPC_LANE_N0_C 2 9 DPC_LANE_N0_C D_LAD1 99 100
<33> D_LAD1 99 100 DOCK_LOM_ACTLED_YEL# <28>
101 102 0.1U_0402_10V7K~D 0_0402_5%~D
DPC_LANE_P1_C DPC_LANE_P1_C D_LAD2 101 102 DOCK_LOM_TRD0+
4 7 <33> D_LAD2 103 104
5
D_LAD3 103 104 DOCK_LOM_TRD0- DOCK_LOM_TRD0+ <28>
<33> D_LAD3 105 105 106 106 DOCK_LOM_TRD0- <28>
DPC_LANE_N1_C 5 6 DPC_LANE_N1_C 107 108 +3.3V_RUN
D_LFRAME# 107 108 DOCK_LOM_TRD1+ C552
<33> D_LFRAME# 109 109 110 110 DOCK_LOM_TRD1+ <28>
3 D_CLKRUN# 111 112 DOCK_LOM_TRD1- 1 2
<33> D_CLKRUN# 111 112 DOCK_LOM_TRD1- <28>
113 113 114 114
8 D_SERIRQ 115 116 0.1U_0402_16V4Z~D
<33> D_SERIRQ 115 116 +LOM_VCT
D_DLDRQ1# 117 118
<33> D_DLDRQ1# 117 118
1
RCLAMP0524P.TCT~D 119 120
CLK_PCI_DOCK 119 120 DOCK_LOM_TRD2+
121 122
NC
<6> CLK_PCI_DOCK 121 122 DOCK_LOM_TRD2+ <28>
@ D23 123 124 DOCK_LOM_TRD2- DPC_CA_DET 2 4
123 124 DOCK_LOM_TRD2- <28> A Y
DPC_LANE_P2_C 1 10 DPC_LANE_P2_C 125 126
125 126
G
DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ U40
<34> DOCK_SMB_CLK 127 128 DOCK_LOM_TRD3+ <28>
DPC_LANE_N2_C 2 9 DPC_LANE_N2_C DOCK_SMB_DAT 129 130 DOCK_LOM_TRD3- NC7SZ04P5X_NL_SC70-5~D
<34> DOCK_SMB_DAT DOCK_LOM_TRD3- <28>
3
129 130
131 131 132 132
DPC_LANE_P3_C 4 7 DPC_LANE_P3_C DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+
<34,40> DOCK_SMB_ALERT# 133 134 DOCK_DCIN_IS+ <46>
DOCK_PSID 135 136 DOCK_DCIN_IS-
<40> DOCK_PSID 135 136 DOCK_DCIN_IS- <46>
DPC_LANE_N3_C 5 6 DPC_LANE_N3_C 137 138
DOCK_PWR_BTN# 137 138 PCI_RST#
<34> DOCK_PWR_BTN# 139 139 140 140 PCI_RST# <22,29>
3 141 141 142 142
SLICE_BAT_PRES# 143 144 DOCK_DET#
8 <33,40,47> SLICE_BAT_PRES# 143 144 DOCK_DET# <28,33>
145 149 +DOCK_PWR_BAR
Switch that support both DisplayPort B and DVI/HDMI
RCLAMP0524P.TCT~D GND1 PWR2
+DOCK_PWR_BAR 146 PWR1 PWR2 150
147 PWR1 PWR2 151
SM24.TCT_SOT23-3
0.1U_0603_50V4Z~D
@ D24 148 152
PWR1 GND2
3
2
0.1U_0603_50V4Z~D
DDPC_CTRLCLK 1 10 DDPC_CTRLCLK 1
2
C553
1 153 Shield_G Shield_G 159
C554
D56
DDPC_CTRLDATA 2 9 DDPC_CTRLDATA 154 160 C555 R506
Shield_G Shield_G SDVO_CTRLCLK DPB_F DPB_B
155 Shield_G Shield_G 161 1 2 6 1 2 1 DPB_DOCK_AUX <12>
DPC_DOCK_HPD DPC_DOCK_HPD 2
4 7 156 Shield_G Shield_G 162
2 0.1U_0402_10V7K~D Q14A 0_0402_5%~D
157 163
1
DPC_CA_DET DPC_CA_DET Shield_G Shield_G 2N7002DW-7-F_SOT363-6~D
5 6 158 Shield_G Shield_G 164
3 Q14B
JAE_WD2F144WD4 C556 2N7002DW-7-F_SOT363-6~D R509
8 +RTC_CELL SDVO_CTRLDATA 1 2 DPB#_F 3 4 DPB#_B 2 1 DPB_DOCK_AUX# <12>
R508
RCLAMP0524P.TCT~D CLK_PCI_DOCK DOCK_DET# 2 1 0.1U_0402_10V7K~D 0_0402_5%~D
A A
5
100K_0402_5%~D
1
+3.3V_RUN
R507 C558
HPD# inverting level shifting circuit for DisplayPort B 1 2
@ 10_0402_5%~D
+3.3V_RUN 0.1U_0402_16V4Z~D
2
1
C557
2
NC
R510 @ 4.7P_0402_50V8C~D DPB_CA_DET 2 4
2 A Y
G
20K_0402_5%~D U41
NC7SZ04P5X_NL_SC70-5~D
1
3
DPB_DOCK_HPD# <12>
1
D Q50
DPB_DOCK_HPD 2 R511
G BSS138_SOT23~D
100K_0402_5%~D
S 7.5K_0402_5%~D
3
2
DELL CONFIDENTIAL/PROPRIETARY
1
R512
Compal Electronics, Inc.
1
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, DOCKING CONNECTOR
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 31 of 49
2 1
2 1
U32A +3.3V_RUN U32B
BCM5880 BCM5880
2
CLK_PCI_TPM M7 H1 F12 A7
<6> CLK_PCI_TPM LCLK SMC_ADD_0 +1.2V_RUN_PLL POR_AVSS HF_RFIDTAG_AVDD2P5
R514 1 2 0_0402_5%~D LPC_EN_R R6 J4 R540 POR_EXTR G13 F7
<33> SP_TPM_LPC_EN LPCEN SMC_ADD_1 POR_EXTR HF_RFIDTAG_AVDD2P5
PLTRST3# N5 H2 510K_0402_5%~D G15 C6
<22,30> PLTRST3# GPIO_17/LRESET_N SMC_ADD_2 +3.3V_RUN POR_INT12 HF_RFIDTAG_DVDD1P2
R516 LPC_LFRAME# P5 H3 G14 E10
<23,33,34> LPC_LFRAME# GPIO_18/LFRAME_N SMC_ADD_3 POR_MONITOR HF_RX_ADC_AVDD1P2
1U_0603_10V4Z~D
1 2 IRQ_SERIRQ_R M6 G1 F9
<24,29,33,34> IRQ_SERIRQ
1
LPC_LAD0 GPIO_19/LSERIRQ SMC_ADD_4 POR_EXTR HF_RX_AVDD1P2
<23,33,34> LPC_LAD0 R5 GPIO_20/LAD[0] SMC_ADD_5 H4 1 1 B14 PLL_VDD_1P2I HF_RX_AVDD2P5 G9
C561
0_0402_5%~D <23,33,34> LPC_LAD1 LPC_LAD1 N6 F2 C562 B15 D8
GPIO_21/LAD[1] SMC_ADD_6 PLL_AVDD_1P2O HF_TX_AVDD1P2
2
@ 4.7K_0402_5%~D
<23,33,34> LPC_LAD2 LPC_LAD2 N7 G4 D12 A8
GPIO_22/LAD[2] SMC_ADD_7 PLL_VSS HF_TX_AVDD2P5
UART LPC
4.7K_0402_5%~D
4.7K_0402_5%~D
R517 <23,33,34> LPC_LAD3 LPC_LAD3 P6 G2 1U_0603_10V4Z~D D13 D9
GPIO_23/LAD[3] SMC_ADD_8 PLL_VDD_1P2I HF_TX_AVDD3P3
1
LPD# R548 2 2
<33> SP_TPM_LPC_EN 1 2 P7 GPIO_24/LPCPD_N SMC_ADD_9 G3 E12 PLL_VSS
R534
R535
R543
E2 330K_0402_5%~D A15
+3.3V_RUN @ 0_0402_5%~D UART_RX/GPIO0 SMC_ADD_10 NC
B5 F4 B6
1
UART_TX/GPIO1 GPIO_0/UART_RX SMC_ADD_11 OVSTB HF_RFIDTAG_AVSS
B4 GPIO_1/UART_TX SMC_ADD_12 F1 N9 OVSTB/ZEROB HF_RFIDTAG_VREF A6
1 2 LPC_EN_R R520 GPIO2_TER_VDDMON D6 F3 T71 SCANMOD M8 C7
2
R770 47K_0402_1%~D SC_DET SC_DET#_R GPIO_2/UART_CTS SMC_ADD_13 C568 SBOOT SCANACCMODE HF_RFIDTAG_VRX_N
2 1 A4 GPIO_3/UART_RTS SMC_ADD_14 D2 P9 SECURE_BOOT HF_RFIDTAG_VRX_P B7
1 2 IRQ_SERIRQ_R E3 SMC_ADD15 +3.3V_RUN 1 2 SWV M12 E7
R771 @ 47K_0402_1%~D 10K_0402_5%~D SPI_CLK_USH SMC_ADD_15/REFCLK_FREQ_0 SMC_ADD16 TSTMOD SWV/ERROR,OSC1,OSC2,SPL HF_RFIDTAG_VTX
C5 GPIO_6/SSP_CLK SMC_ADD_16/REFCLK_FREQ_1 D1 T72 R9 TESTMODE/TST_SEC_BOOT HF_RX_TEST0 B10
1 2 LPD# UART_RX/GPIO0 SPI_CS B3 E1 SMC_ADD17 680P_0402_50V7K T73 IDQ_EN R10 C10
GPIO_7/SSP_FSS SMC_ADD_17/BOOT_SRC_0 IDDQ_EN/CM3_MODE HF_RX_TEST1
RDIF
R529 4.7K_0402_5%~D @ R769 SPI_RXD D5 C2 SMC_ADD18 A11
GPIO_8/SSP_RXD SMC_ADD_18/BOOT_SR_1 HF_RX_TEST2
@ 4.7K_0402_5%~D
0_0402_5%~D SPI_TXD R569 REF_XIN
SPI
A3 GPIO_9/SSP_TXD SMC_ADD_19 D3 F15 REFCLK_XTALIN HF_RX_TEST3 A12
4.7K_0402_5%~D
4.7K_0402_5%~D
1 2 C1 4.7K_0402_5%~D REF_XOUT F14 C11
SMC_ADD_20 REFCLK_XTALOUT HF_RX_N
2
SMC_ADD_21 E4 HF_RX_P B11
R550
R551
R542
UART_TX/GPIO1 GPIO14_TER_ON/OFF C4 B1 AUX_XIN D15 C9
1
BCM5880_GPIO15 GPIO_14 SMC_ADD_22 SBOOT R772 AUX_XOUT E14 AUXCLK_XTALIN HF_TX_N
A2 GPIO_15 SMC_ADD_23 C3 AUXCLK_XTALOUT HF_TX_P B9
GPIO16_TER_TRIS D4 @ 22_0402_5%~D
GPIO_16
CLK
R2 BBCLK 1 2 BBCLK_R A1
1
SMC_DATA_0 CLKOUT
SMC_DATA_1 P3 1 2 B2 CLKOUT_EN
R521 1 2 22_0402_5%~D USBP10-_R R549 R773 @ 4.7K_0402_1%~D
BootStrap
<24> USBP10- R13 USBD_DN SMC_DATA_2 R1 HF_RFIDTAG_AVSS C8
B R522 1 B
<24> USBP10+ 2 22_0402_5%~D USBP10+_R R14 USBD_UP SMC_DATA_3 P2 @ 4.7K_0402_5%~D RST_N N8 RST_N HF_RFIDTAG_AVSS D7
R523 1 2 1.5K_0402_5%~D P14 R3 SPI_RST R8 A5
1
GPIO_27/USBD_ATATCH SMC_DATA_4 RSTOUT_N HF_RFIDTAG_DVSS
SMC_DATA_5 M4 FP_RESET# <35> HF_RX_ADC_AVSS1 E9
+3.3V_RUN N2 JTAG_CLK_USH P10 G10
FP_USBD- SMC_DATA_6 JTAG_TDI_USH JTAG_TCK HF_RX_ADC_AVSS2
<21> FP_USBD- N11 USBH_DN0 SMC_DATA_7 N3 R11 JTAG_TDI HF_RX_AVSS F10
JTAG
FP_USBD+ N12 P1 JTAG_CLK_USH JTAG_TDO_USH JTAG_RST#_USH AUX_XIN JTAG_TDO_USH N10 A10
<21> FP_USBD+ USBH_UP0 SMC_DATA_8 JTAG_TDO HF_RX_AVSS
USBH_OC0# M11 M3 R774 R775 R781 R1112 JTAG_TMS_USH R12 A9
USBH_OC_0 SMC_DATA_9 JTAG_TMS HF_TX_AVSS
4.7K_0402_5%~D
4.7K_0402_5%~D
M2 @ 0_0402_5%~D @ 0_0402_5%~D @ 0_0402_5%~D @ 0_0402_5%~D JTAG_RST#_USH P11 B8
SMC_DATA_10 JTAG_TRSTN HF_TX_AVSS
2
L4 1 2 1 2 1 2 1 2 JTCE_USH M9 E8
SPI
SMC_DATA_11 JTCE HF_TX_AVSS
R537
R536
TER_USBH_N1 R525 1 2 22_0402_5%~D USBH_N1 N13 N1
USBH_DN1 SMC_DATA_12
2
TER_USBH_P1 R526 1 2 22_0402_5%~D USBH_P1 P13 L3 JTAG_TDI_USH JTAG_TMS_USH JTCE_USH AUX_XOUT
USBH_OC1# USBH_UP1 SMC_DATA_13 BCM5880KFBG B0_FBGA225~D
R15 USBH_OC_1 SMC_DATA_14 L2
C572 K4 +3.3V_RUN R527 R544
1
SMC_DATA_15 +3.3V_RUN @ 0_0402_5%~D 0_0402_5%~D
1 2
4.7K_0402_5%~D
USBH_OC0# 5880_GPIO25 P8 K2 1 2 REF_XOUT
1
GPIO_25/SC_SEL5V SMC_ADV_N
2
Smard Card
USBH_OC1# @ 680P_0402_50V7K 5880_GPIO26 R7 J1 1 2 OVSTB 1 2 BBCLK
GPIO_26/SC_SEL18V SMC_BLS_N_0
R531
@ 4.7K_0402_5%~D
@ 4.7K_0402_5%~D
R528 N15 K1 R532 4.7K_0402_5%~D R530 10K_0402_5%~D R546
BCM5880_SCCLK BCM5880_SCCLK_R L14 SC_CINRUSH SMC_BLS_N_1 RST_N REF_XIN
1 2 SC_CLK SMC_CRE J3 1 2 1 2 1 2
2
T82 BCM5880_SCVCC L15 M1 R541 4.7K_0402_5%~D 1 2 JTAG_RST#_USH
SC_VCC SMC_CS_N_0
R553
R552
10_0402_5%~D BCM5880_SCRST K15 K3 1 2 FP_RESET# R539 1K_0402_5%~D @ 10M_0402_5%~D R547
1
BCM5880_IO SC_RST SMC_CS_N_1 R1120 4.7K_0402_5%~D 0_0402_5%~D
K14 SC_IO SMC_IO_3V P12
CLK_PCI_TPM AUX1UC J14 J2 Y3
AUX2UC SC_FCB SMC_OE_N XI XO
J15 L1 1 3
1
BCM5880_SCDET SC_FCB_ENB SMC_WE_N IN OUT
M10 SC_DET
1
+SC_PWR M15 SC_PWR 2 GND GND 4
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
R573
N14 SC_PWR Function SMC 00 01 10 11 27.12MHZ_12PF_1N227120CC0B~D 1
Pull down for 5880 Rev A0, and pull up for Rev B0 2 2 1
C579
C580
@ 10_0402_5%~D Boot SRC AD[18:17] SMC SPI USB RVD
+3.3V_RUN BCM5880KFBG B0_FBGA225~D C581 C582
PCI_TPM_TERM 2
C620 REF CLK AD[16:15] RVD 24MHZ 27.12MHz 48MHz 22P_0402_50V8J~D 22P_0402_50V8J~D
1 1 2 2
1 2
+3.3V_RUN
1U_0603_10V4Z~D
U34 C559
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
SPI_TXD 1 8 SPI_RXD U32C 1 2
SPI_CLK_USH D Q +1.2V_VDDC_5880
2 7
SPI_RST 3
C
RESET#
VSS
VCC 6 2 2 2 2 2 2 2 2 2 BCM5880 680P_0402_50V7K
C585
C586
C587
C588
C589
C590
C591
C592
SPI_CS 4 5 BCM5880_GPIO15 C621 C13 R4
S# W# @ 4.7P_0402_50V8C~D VDDC CORE_CINRUSH R513 1
E5 VDDC CORE_PWRDN M5 2 2.2K_0402_5%~D
M45PE16-VMP6TP_SO8~D R576 F5 D10 R515 1 2 4.7K_0402_5%~D
1 1 1 1 1 1 1 1 1 VDDC ALDO_PWRDN
1 2 J11 VDDC AVDD33_LDO25 A14
K11 VDDC AVDD_2P5I G12 +2.5V_RUN_AVDD
@ 4.7K_0402_5%~D K6 B13
VDDC AVDD_2P5O
K7 VDDC AVDD25_ldo12 A13
K9 B12
Universal Smart Card Interface IC VDDC AVDD25_ldo12
4.7U_0603_6.3V6M~D
4.7U_0603_6.3V6M~D
N4 VDDC AVDD_1P2O E11
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
P4 VDDC AVDD_1P2I_AUX E13 +1.2V_RUN_PLL
+3.3V_RUN F13
AVDD_1P2I_REF +3.3V_RUN
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2 2 2 2 1 1 +3.3V_RUN E6 VDDO_VAR AVDD25_PLL D14
C603
C604
C605
C606
C607
C608
C609
F6 P15 +OTP_PWR 2 1 +3.3V_RUN
VDDO_VAR OTP_PWR
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
1 1
C764
C765
4.7U_0603_6.3V6M~D
1 2 G5 F11 R518
1 1 1 1 1 2 2 VDDO_SMC AVSS_LDO12
C584
C583
H5 C12 1 @ 0_0603_5%~D
VDDO_SMC AVSS_ldo25
C560
R782 J5 D11
GPIO2_TER_VDDMON 8009_VDDMON 2 2 VDDO_SMC AVSS_ldo25 R519
1 2 AVSS_AUX C15
2 1
K8 VDDO_LPC AVSS_REF E15 2 1 +SC_PWR
@ 47K_0402_1%~D U33 2
L7 VDDO_LPC AVSS_PLL C14
19 +SC_VCC 0_0603_5%~D
GPIO14_TER_ON/OFF VCC
24 ON/OFF VPC 26 K5 VDDO_33CORE VSS G11
BCM5880_SCCLK R554 2 1 10K_0402_5%~D 7 29 C596 +3.3V_RUN L5 G6
CLKIN VDD VDDO_33CORE VSS
8 RDY VP 15 2 1 L6 VDDO_33CORE VSS G7
T83 +LIN
T84
9 OFF_ACK LIN 27 2 1 VSS G8 Place C560 close to U32.A14
0_0402_5%~D
R555 11 4.7U_0603_6.3V6K~D L37 L13 H10
OFF_REQ VDDO_33SC VSS
2
T85
4.7K_0402_5%~D
47K_0402_1%~D 12 23 TER_USBH_N1 10UH_LQH32CN100K53L_10%~D M14 H11
CS DM VDDO_33SC VSS
1
+2.5V_RUN_AVDD
R524
A GPIO16_TER_TRIS SC_USB# TER_USBH_P1 A
1 2 13 SC_USB# DP 25 K13 VDDO_SC VSS H6
R538
5880_GPIO26 R556 1 2 47K_0402_1%~D 4 14 R557 2 1 100K_0402_5%~D SC_DET H7
CMDVCC5# PRES VSS
@ 4.7U_0603_6.3V6M~D
5880_GPIO25 R558 1 2 47K_0402_1%~D 5 22 R559 1 2 0_0402_5%~D SC_IO BBCLK H14 H8
CMDVCC3# I/O V3P3_BBLCLK VSS
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
BCM5880_SCRST R560 2 1 10K_0402_5%~D 6 21 R561 1 2 0_0402_5%~D SC_C4 H9
1
BCM5880_SCDET RSTIN AUX1 R562 1 VSS
32 20 2 0_0402_5%~D SC_C8 H15 J10
2
OFF# AUX2 R563 1 SC_CLK V3P3_PWRGOOD VSS
10 TEST1 CLK 16 2 0_0402_5%~D VSS J12 2 2 2 1
+3.3V_RUN
C1291
C1292
C1293
C1294
30 18 SC_RST TAMPER_N H13 J6
R545 BCM5880_IO TEST2 RST V3P3_TAMPER_N VSS
1 I/OUC 2 2 VSS J7
2 1 SC_USB# AUX1UC 2 17 C611 C612 +1.2V_VDDC_5880 H12 J8
AUX1UC GND +3.3V_RUN VDD_BB VSS 1 1 1 2
AUX2UC 3 28 J13 J9
10K_0402_5%~D AUX2UC GND 27P_0402_50V8J~D 27P_0402_50V8J~D VDD_BB VSS
GND 31 VSS K10
1 1
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
1U_0402_6.3V6K~D
@ 4.7U_0603_6.3V6M~D
L8 VESD VSS K12
73S8009CN-32IMR/F_QFN32_5X5~D L12
VSS
2 2 2 2 2 2 1 L9 VDDO_33 VSS M13
C564
C565
C566
C567
C569
C570
C571
L10 VDDO_33 VSS F8
JSC L11
R575 SC_DET VDDO_33
Place close to JSC 1 1 1 1 1 1 1 1 2
+3.3V_RUN 1 2 2 2
SC_C8 3 BCM5880KFBG B0_FBGA225~D
+SC_VCC 4.7K_0402_5%~D SC_C4 3
4 4
SC_IO 5 5 DELL CONFIDENTIAL/PROPRIETARY
0.47U_0402_6.3V4Z~D
SC_CLK 6 6
2 7 7
C618
SC_RST 8
9
8 Compal Electronics, Inc.
9 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
+SC_VCC 10 10
1 TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
11 GND
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, USH BCM5880
12 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
GND
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
TYCO_1-1775784-1 LA-4291P
Date: Friday, December 07, 2007 Sheet 32 of 49
2 1
5 4 3 2 1
+3.3V_ALW
+3.3V_ALW +3.3V_ALW
1 2 DCIN_CBL_DET#
R584 100K_0402_5%~D SNIFFER_BLUE# 2 1
1 2 SYS_PME# R588 @ 100K_0402_5%~D
R1031 10K_0402_5%~D 1 1 1 1 1 SNIFFER_YELLOW# 2 1
1 2 PCIE_WAKE# C622 C626 C623 C624 C625 R589 @ 100K_0402_5%~D
R577 10K_0402_5%~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D 0.1U_0402_10V7K~D 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D TP_DET# 2 1
1 2 USB_POWERSHARE_PWR_EN# R590 100K_0402_5%~D
R1088 @ 100K_0402_5%~D 2 2 2 2 2
108
D DET_PCCRD_EXPSCRD# D
34
57
85
1 2
R583 100K_0402_5%~D U35 +3.3V_RUN
1 2 CAP_SW_SMB_INT#
VCC1
VCC1
VCC1
VCC1
R579 10K_0402_5%~D D_CLKRUN# 2 1
1 2 CELL_CHARGER_DET# PBAT_PRES# 97 +3.3V_ALW R592 100K_0402_5%~D
<40> PBAT_PRES# GPIOA[0]
R1089 100K_0402_5%~D SCRL_LED# 98 D_DLDRQ1# 2 1
<38> SCRL_LED# GPIOA[1]
0.1U_0402_16V4Z~D
1 2 ESATA_USB_PWR_EN# NUM_LED# 99 8 R595 100K_0402_5%~D
R581 @ 10K_0402_5%~D <38> NUM_LED# DCIN_CBL_DET# GPIOA[2] VCC1(VDDA33) DOCK_MIC_DET D_SERIRQ
<40> DCIN_CBL_DET# 100 GPIOA[3] GPIOJ[7](VDDA33) 14 DOCK_MIC_DET <26> 1 2 1
C627
1 2 INSTANT_ON_SW_D# <47> PBATT_OFF PBATT_OFF 101 20 MCH_TSATN_EC R593 100K_0402_5%~D
GPIOA[4] GPIOK[4](VDDA33) MCH_TSATN_EC <10>
R1126 100K_0402_5%~D SYS_PME# 102 SP_TPM_LPC_EN 2 1
1
R580
2
100K_0402_5%~D
SLICE_BAT_PRES#
<29> SYS_PME#
<30,35> PCIE_WAKE#
PCIE_WAKE# 103
104
GPIOA[5]
GPIOA[6]
ECE5028-NU GPIOI[1](VCC1) 119 1.8V_RUN_ON T109 2
R582 @ 10K_0402_5%~D
<35> USB_POWERSHARE_PWR_EN# GPIOA[7]
1 2 SW_BD_DET# 9 SNIFFER_BLUE#
R1118 100K_0402_5%~D
<35> WIRELESS_ON#/OFF
WIRELESS_ON#/OFF
BT_RADIO_DIS#
24
25
GPIOH[0]
(ECE5018) GPIOJ[2](USBDP0)
GPIOJ[3](USBDN0) 10
13
SNIFFER_YELLOW#
DOCK_HP_DET
SNIFFER_BLUE# <35>
SNIFFER_YELLOW# <35>
RUN_ON 2 1
<30> BT_RADIO_DIS# GPIOH[1] GPIOJ[6](USBDP1) DOCK_HP_DET <26>
EXPRCRD_PWREN# 26 12 CRT_SWITCH CRT_SWITCH <20> R597 100K_0402_5%~D
<35> EXPRCRD_PWREN# GPIOH[4] GPIOJ[5](USBDN1)
+3.3V_RUN EXPRCRD_STDBY# 27 15 ME_FWP ME_FWP <23> 0.75V_DDR_VTT_ON 2 1
<35> EXPRCRD_STDBY# GPIOH[5] GPIOK[0](USBDP2)
BC_INT#_ECE5028 58 16 NB_AC_OFF R602 100K_0402_5%~D
1 2 WIRELESS_ON#/OFF
<34> BC_INT#_ECE5028
<34> BC_DAT_ECE5028
BC_DAT_ECE5028 59
BC_INT#
BC_DAT
USB GPIOK[1](USBDN2)
GPIOK[3](USBDP3) 19
NB_AC_OFF <40,46,47>
T102
R585 100K_0402_5%~D BC_CLK_ECE5028 60 18 T103
<34> BC_CLK_ECE5028 BC_CLK GPIOK[2](USBDN3)
21 RUN_ON
GPIOK[5](USBDP4) RUN_ON <20,21,27,37,45>
1 GPIOE[0]/RXD GPIOK[6](USBDN4) 22
2 GPIOE[1]/TXD
1 2 PBATT_OFF 3 125 IMVP_VR_ON
GPIOE[2]/RTS# GPIOI[6](VDDA33PLL) IMVP_VR_ON <43>
R604 100K_0402_5%~D 4 124 IMVP_PWRGD
LCD_TST DET_PCCRD_EXPSCRD# GPIOE[3]/DSR# GPIOI[5](VDDA18PLL) 0.75V_DDR_VTT_ON IMVP_PWRGD <24,43,44>
1 2 <35> DET_PCCRD_EXPSCRD# 5 GPIOE[4]/CTS# GPIOI[2](VDD18) 120 0.75V_DDR_VTT_ON <45>
R586 100K_0402_5%~D 84 86 +CAP_LDO
PANEL_BKEN_MCH BIOS_RECOVERY GPIOE[5]/DTR# CAP_LDO
2 1 T87 83 GPIOE[6]/RI# GPIOJ[0](RBIAS) 127
R587 100K_0402_5%~D 6 8mil
SYS_LED_MASK# GPIOE[7]/DCD#
1 2
R1104 10K_0402_5%~D CAP_SW_SMB_INT# 65 +3.3V_ALW
<35> CAP_SW_SMB_INT# GPIOB[0]/INIT#
2 1 VGA_IDENTIFY EN_I2S_NB_CODEC 66 R600 C1359
C <26> EN_I2S_NB_CODEC GPIOB[1]/SLCTIN# C
R605 100K_0402_5%~D CB_HWSPND# 67 35 2 1 1 2
<29> CB_HWSPND# GPIOC[2]/SCLT TEST_PIN
EN_DOCK_PWR_BAR 68
<47> EN_DOCK_PWR_BAR
ADAPT_OC 69
GPIOC[3]/PE TEST 1K_0402_5%~D 0.1U_0402_16V4Z~D
<46> ADAPT_OC GPIOC[4]/BUSY GPIO
5
ADAPT_TRIP_SEL 70
<46> ADAPT_TRIP_SEL GPIOC[5]/ACK#
LCD_TST 71 126 DOCK_AC_OFF_EC 2
P
<20> LCD_TST GPIOC[6]/ERROR# GPIOI[7](ATEST) A
PSID_DISABLE# 73 4
<40> PSID_DISABLE# PANEL_BKEN_MCH GPIOC[7]/ALF# SIO_SLP_S3# Y DOCK_AC_OFF <31>
<12> PANEL_BKEN_MCH 74 GPIOD[0]/STROBE# GPIOI[4](XTAL1/CLKIN) 123 SIO_SLP_S3# <24> 1 B
G
+3.3V_ALW DOCKED 75 122
<28> DOCKED
<28,31> DOCK_DET#
DOCK_DET# 76
GPIOC[1]/PD7 CLK GPIOI[3](XTAL2) U96
3
AUD_NB_MUTE GPIOC[0]/PD6 74AHCT1G08GW_SOT353-5~D
<27> AUD_NB_MUTE 77 GPIOB[7]/PD5 <34,46> ACAV_IN_NB
1
1M_0402_5%~D
<35> CELL_CHARGER_DET# CELL_CHARGER_DET# 78
LCD_VCC_TEST_EN GPIOB[6]/PD4 LPC_LAD0
<20> LCD_VCC_TEST_EN 79 GPIOB[5]/PD3 LAD0 54 LPC_LAD0 <23,32,34>
R612
80 52 LPC_LAD1
GPIOB[4]/PD2 LAD1 LPC_LAD1 <23,32,34>
AUD_HP_NB_SENSE 81 49 LPC_LAD2
<26,27,35> AUD_HP_NB_SENSE GPIOB[3]/PD1 LAD2 LPC_LAD2 <23,32,34>
ESATA_USB_PWR_EN# 82 47 LPC_LAD3
<35> ESATA_USB_PWR_EN# LPC_LAD3 <23,32,34>
2
R613 GPIOB[2]/PD0 LAD3 LPC_LFRAME#
LFRAME# 42 LPC_LFRAME# <23,32,34>
1 2 LID_CL_SIO# 61 41 PLTRST2#
<35,38> LID_CL#
62
GPIOD[1]
GPIOD[2]
LPC LRESET#
PCICLK 56 CLK_PCI_5028
PLTRST2# <22,34>
CLK_PCI_5028 <6>
0.047U_0402_16V4Z~D
10_0402_5%~D 37 CLKRUN#
CLKRUN# CLKRUN# <24,29,34>
1 63 46 LPC_LDRQ0# CLK_PCI_5028 CLK_SIO_14M
GPIOD[3]/VBUS_DET LDRQ0# LPC_LDRQ0# <23>
C631
INSTANT_ON_SW_D# 28 44 LPC_LDRQ1#
GPIOD[4]/OCS1_N LDRQ1# LPC_LDRQ1# <23>
29 39 IRQ_SERIRQ
GPIOD[5]/OCS2_N SER_IRQ IRQ_SERIRQ <24,29,32,34>
1
30 GPIOD[6]/OCS3_N
2 CLK_SIO_14M R608 R607
31 GPIOD[7]/OCS4_N CLKI (14.318 MHz) 64 CLK_SIO_14M <6>
@ 10_0402_5%~D @ 10_0402_5%~D
SLICE_BAT_PRES# 32 96
<31,40,47> SLICE_BAT_PRES# GPIOH[6] VSS
SW_BD_DET# 33
<35> SW_BD_DET#
2
D57 GPIOH[7] D_LAD0
DLAD0 55 D_LAD0 <31>
RB751S40T1_SOD523-2~D LAN_DISABLE#_R 88 53 D_LAD1 1 1
<28> LAN_DISABLE#_R GPIOG[0] DLAD1 D_LAD1 <31>
CAP_LED# 89 50 D_LAD2 C629 C628
<38> CAP_LED# SYS_LED_MASK# GPIOG[1] DLAD2 D_LAD3 D_LAD2 <31> @ 4.7P_0402_50V8C~D @ 4.7P_0402_50V8C~D
<34,35> INSTANT_ON_SW# 1 2 <38> SYS_LED_MASK# 90 GPIOG[2] DLPC DLAD3 48 D_LAD3 <31>
91 43 D_LFRAME#
B GPIOG[3] DLFRAME# D_LFRAME# <31> 2 2 B
<24> SIO_EXT_WAKE# SIO_EXT_WAKE# 92 38 D_CLKRUN#
GPIOG[4] DCLK_RUN# D_CLKRUN# <31>
1 2 ICH_PME# 93 45 D_DLDRQ1#
<22> ICH_PME# GPIOG[5] DLDRQ1# D_DLDRQ1# <31>
ICH_PCIE_WAKE# 94 40 D_SERIRQ
<24> ICH_PCIE_WAKE# GPIOG[6] DSER_IRQ D_SERIRQ <31>
R1127 WLAN_RADIO_DIS# 95
<30> WLAN_RADIO_DIS# GPIOG[7]
@ 0_0402_5%~D
WWAN_RADIO_DIS# 106
<30> WWAN_RADIO_DIS# SYSOPT1/GPIOH[2]
107 SYSOPT0/GPIOH[3]
7 RUNPWROK_R1 R1121 2 1 10K_0402_5%~D +3.3V_RUN
PWRGD +3.3V_RUN
109 GPIOF[7]
110 105 SP_TPM_LPC_EN
GPIOF[6] OUT65 SP_TPM_LPC_EN <32>
VGA_IDENTIFY 111 GPIOF[5]
2
CHIPSET_ID1 112
R611 GPIOF[4] GPIO_PSID_SELECT
GPIOJ[4](VSS) 11 GPIO_PSID_SELECT <40>
10K_0402_5%~D 113 17 R606
IRTX VSS 10K_0402_5%~D
2 1 114 IRRX GPIOK[7](VSS) 23 1
36
1
CHIPSET_ID0 VSS C630 ME_FWP
115 GPIOF[3]/IRMODE/IRRX3B VSS 51
BID2 116 72 4.7U_0603_6.3V4Z~D
GPIOF[2]/IRTX2 VSS
2
BID1 2
117 GPIOF[1]/IRRX2 VSS 87
BID0 118 121
GPIOF[0]/IRMODE/IRRX3A VSS TP_DET# R610
GPIOJ[1](VSS) 128 TP_DET# <36>
@ 10K_0402_5%~D
+3.3V_ALW
1
@ 10K_0402_5%~D
@ 10K_0402_5%~D
@ 10K_0402_5%~D
@ 10K_0402_5%~D
ECE5028-NU_VTQFP128_14X14~D
10K_0402_5%~D
2
2
R614
R615
R616
R617
R618
1
BID0 R619 1 2 10K_0402_5%~D CHIPSET_ID0 CHIPSET_ID1 Note
A BID2 BID1 BID0 REV A
BID1 R620 1 2 10K_0402_5%~D Small Form Factor Platform
0 0 0 X00 0 1
BID2 R621 1 2 10K_0402_5%~D
0 0 1 X01
CHIPSET_ID0 R622 1 2 10K_0402_5%~D
0 1 0 X02 DELL CONFIDENTIAL/PROPRIETARY
CHIPSET_ID1 R623 1 2 @ 10K_0402_5%~D
0 1 1 X03 Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, SIO ECE5028
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 33 of 49
5 4 3 2 1
5 4 3 2 1
+RTC_CELL +3.3V_ALW
+RTC_CELL
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_10V4Z~D
100K_0402_5%~D
1
+3.3V_ALW 1 1 1 1 1 1 1 1 1
C634
C635
C637
C638
C639
C640
C641
C636
R626
1 2 ALS_SMBDAT C633 C632
R1081 2.2K_0402_5%~D 1 2
ALS_SMBCLK 2 2 2 2 2 2 2 2 2
1 2
2
R1082 2.2K_0402_5%~D R630 @ 1U_0402_6.3V6K~D
1 2 PBAT_SMBDAT 1 2
<19> POWER_SW_IN# POWER_SW#_MB <35,39>
121
116
104
R635 2.2K_0402_5%~D
21
44
65
83
52
4
1 2 PBAT_SMBCLK U36 1 1K_0402_5%~D
R636 2.2K_0402_5%~D
VTR[1]
VTR[2]
VTR[3]
VTR[4]
VTR[5]
VTR[6]
VTR[7]
VTR[8]
VBAT
2 1 EC_SPI_CS# C642
D R642 100K_0402_5%~D +3.3V_RUN 1U_0603_10V4Z~D D
BC_DAT_EMC4002 R1123 2
2 1
R629 100K_0402_5%~D PS/2 INTERFACE MISC INTERFACE RUNPWROK 2 1
2 1 BC_DAT_ECE1088 <35> ALS_SMBDAT ALS_SMBDAT 9 19 RC_ ID
R640 100K_0402_5%~D ALS_SMBCLK GPIO007/I2C1D_DATA/PS2_CLK0B GPIO021/RC_ID DDR_ON 10K_0402_5%~D +RTC_CELL
<35> ALS_SMBCLK 10 GPIO010/I2C1D_CLK/PS2_DAT0B GPIO025/UART_CLK 27 DDR_ON <10,37,45>
2 1 BC_DAT_ECE1077 CLK_TP_SIO 75 49 RUNPWROK
<36> CLK_TP_SIO GPIO110/PS2_CLK2/GPTP-IN6 VCC_PRWGD
100K_0402_5%~D
R631 100K_0402_5%~D DAT_TP_SIO 76 50 ICH_LAN_RST# ICH_LAN_RST# <24>
<36> DAT_TP_SIO GPIO111/PS2_DAT2/GPTP-OUT6 GPIO060/KBRST
1
1 2 BC_DAT_ECE5028 CLK_KBD 77 67 EC_FLASH_SPI_CLK
<31> CLK_KBD GPIO112/PS2_CLK1A GPIO101/ECGP_SCLK
R628 100K_0402_5%~D DAT_KBD 78 68 EC_FLASH_SPI_DO
<31> DAT_KBD GPIO113/PS2_DAT1A GPIO102/ECGP_SOUT
R638
2 1 LPC_LDRQ#_MEC5035 CLK_MSE 79 69 EC_FLASH_SPI_DIN C643
<31> CLK_MSE GPIO114/PS2_CLK0A GPIO103/ECGP_SIN
R643 @ 100K_0402_5%~D DAT_MSE 80 70 HOST_DEBUG_TX 1 2
<31> DAT_MSE GPIO115/PS2_DAT0A GPIO104/UART_TX HOST_DEBUG_TX <30>
PBAT_SMBDAT 111 71 HOST_DEBUG_RX
<40> PBAT_SMBDAT
2
PBAT_SMBCLK GPIO154/I2C1C_DATA/PS2_CLK1B GPIO105/UART_RX RESET_OUT HOST_DEBUG_RX <30> R641 @ 1U_0402_6.3V6K~D
<40> PBAT_SMBCLK 112 GPIO155/I2C1C_CLK/PS2_DAT1B GPIO106/nRESET_OUT 72 RESET_OUT <10,24>
81 MSDATA 1 2
GPIO116/MSDATA MSDATA <30> <19> DOCK_PWR_SW# DOCK_PWR_BTN# <31>
+5V_RUN 82 MSCLK
GPIO117/MSCLK MSCLK <30>
92 SIO_A20GATE 1 1K_0402_5%~D
GPIO127/A20M SIO_A20GATE <23>
1 2 CLK_KBD JTAG INTERFACE 110 PS_ID
GPIO153/LED3 PS_ID <40>
R657 4.7K_0402_5%~D JTAG_TDI 102 114 BAT1_LED# C644
GPIO145/I2C1K_DATA/JTAG_TDI GPIO156/LED1 BAT1_LED# <38>
1 2 DAT_KBD JTAG_TDO 103 115 BAT2_LED# 1U_0603_10V4Z~D
GPIO146/I2C1K_CLK/JTAG_TDO GPIO157/LED2 BAT2_LED# <38> 2
R659 4.7K_0402_5%~D JTAG_CLK 105 123 FWP#
CLK_MSE JTAG_TMS GPIO147/I2C1J_DATA/I2C2C_DATA/JTAG_CLK nFWP +3.3V_ALW +3.3V_ALW
1
R660
2
4.7K_0402_5%~D JTAG_RST#
106 GPIO150/I2C1J_CLK/I2C2C_CLK/JTAG_TMS Bat2 = Amber LED
107 JTAG_RST#
1 2 DAT_MSE Bat1 = Blue LED
2
R664 4.7K_0402_5%~D GENERAL PURPOSE I/O
2 SIO_SLP_M# R1110 R652
GPIO001 SIO_SLP_M# <24>
FAN PWM & TACH 3 DOCK_SMB_ALERT# 1K_0402_5%~D 10K_0402_5%~D
ACAV_DOCK_SRC# GPIO002 ME_WOL_EN DOCK_SMB_ALERT# <31,40>
<31,47> ACAV_DOCK_SRC# 41 GPIO050/FAN_TACH1 GPIO014/GPTP-IN7 14 ME_WOL_EN <24>
SUS_ON 42 15 ME_SUS_PWR_ACK
<37> SUS_ON ME_SUS_PWR_ACK <24>
1
SUS_ON GPIO051/FAN_TACH2 GPIO015/GPTP-OUT7 1.5V_SUS_PWRGD
1 2 43 GPIO052/FAN_TACH3 GPIO016/GPTP-IN8 16 1.5V_SUS_PWRGD <10,42>
4700P_0402_25V7K~D
R654 100K_0402_5%~D BREATH_LED# 45 17 ICH_CL_PWROK RC_ ID FWP#
<31,38> BREATH_LED# GPIO053/PWM0 GPIO017/GPTP-OUT8 ICH_CL_PWROK <10,24>
1 2 ICH_ALW ICH_ALW 46 18 T106
<37> ICH_ALW GPIO054/PWM1 GPIO020
R656 100K_0402_5%~D KYBRD_BKLT_PWM 47 28 1.05V_M_PWRGD 1
<36> KYBRD_BKLT_PWM GPIO055/PWM2 GPIO26/GPTP-IN1 1.05V_M_PWRGD <42>
2
C1360
C EC_SPI_CS# ALW_PWRGD_3V_5V C
48 GPIO056/PWM3 GPIO27/GPTP-OUT1 29 ALW_PWRGD_3V_5V <41>
30 T107 R658
GPIO30/GPTP-IN2 SIO_SLP_S5# @ 10K_0402_5%~D
GPIO31/GPTP-OUT2 31 SIO_SLP_S5# <24>
BEEP 2
GPIO032/GPTP-IN3 32 BEEP <26>
BC-LINK 33 AUX_ON
AUX_ON <28>
1
BC_CLK_EMC4002 GPIO040/GPTP-OUT3
<19> BC_CLK_EMC4002 23 GPIO022/BCM_B_CLK/V_CLK GPIO041 34
+3.3V_ALW BC_DAT_EMC4002 24 73 +3.3V_ALW
<19> BC_DAT_EMC4002 GPIO023/BCM_B_DAT/V_DATA GPIO107 T108
<19> BC_INT#_EMC4002 BC_INT#_EMC4002 25 84 AUX_EN_WOWL
BC_INT#_ECE1088 GPIO024/BCM_B_INT#/V_FRAME GPIO120 SIO_SLP_S4# AUX_EN_WOWL <30> HOST_DEBUG_TX
<36> BC_INT#_ECE1088 35 GPIO042/BCM_C_INT# GPIO124/GPTP-OUT5 89 SIO_SLP_S4# <10,24> 1 2
<36> BC_DAT_ECE1088 BC_DAT_ECE1088 36 90 M_ON R639 10K_0402_5%~D
GPIO043/BCM_C_DAT GPIO125/GPTP-IN5 M_ON <37>
10K_0402_5%~D
+3.3V_ALW
49.9_0402_1%~D
10K_0402_5%~D
10K_0402_5%~D
10K_0402_5%~D
BC_CLK_ECE1088 37 91 ICH_RSMRST# DOCK_SMB_ALERT# 1 2
<36> BC_CLK_ECE1088 GPIO044/BCM_C_CLK GPIO126 ICH_RSMRST# <24>
1
<36> BC_INT#_ECE1077 BC_INT#_ECE1077 38 108 AC_PRESENT R632 10K_0402_5%~D
GPIO045/LSBCM_D_INT# GPIO151/GPTP-IN4 AC_PRESENT <24>
R668
R669
R670
R671
BC_DAT_ECE1077 SIO_PWRBTN# DOCK_SMB_DAT
R672
<36> BC_DAT_ECE1077 39 GPIO046/LSBCM_D_DAT GPIO152/GPTP-OUT4 109 SIO_PWRBTN# <24> 2 1
10K_0402_5%~D
100K_0402_5%~D
10K_0402_5%~D
BC_CLK_ECE1077 40 R653 2.2K_0402_5%~D
<36> BC_CLK_ECE1077 GPIO047/LSBCM_D_CLK
1
BC_INT#_ECE5028 85 DOCK_SMB_CLK 2 1
<33> BC_INT#_ECE5028 GPIO121/BCM_A_INT#
BC_DAT_ECE5028 86 R655 2.2K_0402_5%~D
<33> BC_DAT_ECE5028
2
GPIO122/BCM_A_DAT
R663
R661
R662
JP1 BC_CLK_ECE5028 87 SMBUS INTERFACE LCD_SMBDAT 2 1
<33> BC_CLK_ECE5028 GPIO123/BCM_A_CLK
1 5 DOCK_SMB_DAT R634 2.2K_0402_5%~D
1 GPIO003/I2C1A_DATA DOCK_SMB_DAT <31>
2 JTAG_TDI 6 DOCK_SMB_CLK JDEG LCD_SMBCLK 2 1
DOCK_SMB_CLK <31>
2
2 JTAG_TMS GPIO004/I2C1A_CLK LCD_SMBDAT R633 2.2K_0402_5%~D
7 G1 3 3 GPIO005/I2C1B_DATA 7 LCD_SMBDAT <20> 5 5
8 4 JTAG_CLK HOST INTERFACE 8 LCD_SMBCLK MSDATA 4 4 CKG_SMBDAT 2 1
G2 4 GPIO006/I2C1B_CLK LCD_SMBCLK <20>
5 JTAG_TDO SIO_EXT_SMI# 11 12 CKG_SMBDAT MSCLK 3 3 R624 2.2K_0402_5%~D
5 <24> SIO_EXT_SMI# GPIO011/nSMI GPIO012/I2C1H_DATA/I2C2D_DATA CKG_SMBDAT <6,26,46>
6 SIO_RCIN# 54 13 CKG_SMBCLK HOST_DEBUG_RX 2 2 CKG_SMBCLK 2 1
6 <23> SIO_RCIN# GPIO061/LPCPD# GPIO013/I2C1H_CLK/I2C2D_CLK CKG_SMBCLK <6,26,46>
LPC_LDRQ#_MEC5035 55 93 AMT_SMBDAT 1 1 R627 2.2K_0402_5%~D
LDRQ# GPIO130/I2C2A_DATA AMT_SMBDAT <24>
@ ACES_85204-06001~D IRQ_SERIRQ 56 94 AMT_SMBCLK CARD_SMBDAT 2 1
<24,29,32,33> IRQ_SERIRQ SER_IRQ GPIO131/I2C2A_CLK AMT_SMBCLK <24>
PLTRST2# 57 95 ACAV_IN_NB Molex_53261 R644 2.2K_0402_5%~D
<22,33> PLTRST2# LRESET# GPIO132/I2C1G_DATA ACAV_IN_NB <33,46>
CLK_PCI_5035 58 96 CARD_SMBCLK 2 1
<6> CLK_PCI_5035 PCI_CLK GPIO140/I2C1G_CLK
+3.3V_ALW LPC_LFRAME# 59 97 CARD_SMBDAT R645 2.2K_0402_5%~D
<23,32,33> LPC_LFRAME# LFRAME# GPIO141/I2C1F_DATA/I2C2B_DATA CARD_SMBDAT <30,35>
LPC_LAD0 60 98 CARD_SMBCLK BKT_SMBDAT 2 1
<23,32,33> LPC_LAD0 LAD0 GPIO142/I2C1F_CLK/I2C2B_CLK CARD_SMBCLK <30,35>
10K_0402_5%~D
LPC_LAD1 61 99 BKT_SMBDAT +RTC_CELL R1079 2.2K_0402_5%~D
<23,32,33> LPC_LAD1 LAD1 GPIO143/I2C1E_DATA BKT_SMBDAT <21>
1
LPC_LAD2 62 100 BKT_SMBCLK C645 BKT_SMBCLK 2 1
<23,32,33> LPC_LAD2 LAD2 GPIO144/I2C1E_CLK BKT_SMBCLK <21>
LPC_LAD3 63 1 2 R1080 2.2K_0402_5%~D
R667
B <23,32,33> LPC_LAD3 LAD3 B
CLKRUN# 64
<24,29,33> CLKRUN# CLKRUN#
SIO_EXT_SCI# 66 0.1U_0402_16V4Z~D
<24> SIO_EXT_SCI# GPIO100/nEC_SCI
5
DELL PWR SW INF
2
118 1
P
BGPO0 A INSTANT_ON_SW# <33,35>
JTAG_RST# 119 SNIFFER/INSTANT_SW# 4 Y
VCI_IN2#
@ 100_0402_1%~D
MASTER CLOCK 120 ALWON 2
VCI_OUT ALWON <41> B SNIFFER_PWR_SW# <35>
G
0.1U_0402_16V4Z~D
MEC5035_XTAL1 122 126
XTAL1 VCI_IN1# EN_CELL_CHARGER_DET# <35>
1
1 MEC5035_XTAL2 R674 2 1 0_0402_5%~D 124 127 POWER_SW_IN# U47
3
XTAL2 VCI_IN0#
C646
R673
JTAG 117 128 ACAV_IN 74AHCT1G08GW SOT353~D +RTC_CELL
1
<19> EC_32KHZ_OUT GPIO160/32KHZ_OUT VCI_OVRD_IN ACAV_IN <19,46>
DOCK_PWR_SW#
thermal GND
VCI_IN3# 1
VR_CAP[1]
INSTANT_ON_SW#
2 1
2
VSS_RO
Place close to pin 58 R647 100K_0402_5%~D
2
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[7]
VSS[8]
AGND
SNIFFER_PWR_SW# 1 2
R649 100K_0402_5%~D
CLK_PCI_5035 SNIFFER/INSTANT_SW# 1 2
2
MEC5035_XVTQFP128_14X14~D R1111 100K_0402_5%~D
125
26
51
74
88
113
20
53
22
+5035_VSS 101
129
1
EN_CELL_CHARGER_DET# 1 2
2
1=JTAG interface Reset disabled R1090 100K_0402_5%~D
R675 +3.3V_M
+5035_AGND
+VR_CAP
0=Reset JTAG interface @ 10_0402_5%~D
15 mil 8 mil 15 mil
2
1
4.7U_0603_6.3V4Z~D
1 DDR_ON 2 1
C651 1 R733 R651 100K_0402_5%~D
C648
C650 @ 4.7P_0402_50V8C~D L39 L38 100K_0402_5%~D AUX_ON 2 1
2 1 MEC5035_XTAL1 2 1 1 2 R650 2.7K_0402_5%~D
2 BLM18AG121SN1D_0603~D BLM18AG121SN1D_0603~D M_ON 1 2
2
22P_0402_50V8J~D 2 ICH_PWRGD# R648 1M_0402_5%~D
ICH_PWRGD# <19>
2
AC_PRESENT 1 2
1
Y4 D R665 10K_0402_5%~D
32.768KHZ_12.5PF_1TJE125DP1~D RESET_OUT 2 Q71
+3.3V_ALW G 2N7002W-7-F_SOT323-3~D
1
C649 C652 S
3
A MEC5035_XTAL2 A
2 1 1 2
1
22P_0402_50V8J~D 0.1U_0402_16V4Z~D
1
R676
3.3K_0402_5%~D R677
U37
3.3K_0402_5%~D Place R679,R680 close to U36 DELL CONFIDENTIAL/PROPRIETARY
2
R678 EC_SPI_CS# R679
1 8
Compal Electronics, Inc.
2
EC_FLASH_SPI_DIN SPI_DIN_R3 CS# VCC 33_0402_5%~D
1 2 2 SO HOLD# 7
3 6 SPI_CLK_R3 1 2 EC_FLASH_SPI_CLK PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
33_0402_5%~D WP# SCLK SPI_DO_R3 EC_FLASH_SPI_DO TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
4 5 1 2
GND SI BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, KBC/GPIO, MEC5035
@ SST25VF016B-50-4C-S2AF_SO8~D R680 NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
Place R678 close to U37
WWW.AliSaler.Com
33_0402_5%~D PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 34 of 49
5 4 3 2 1
5 4 3 2 1
Express Card IO/B connector, Right side
+1.5V_CARD JIO
+1.5V_RUN C503 52
+1.5V_CARD GND
1 2 GND 51
50 IO_BD_DET# IO_BD_DET# <24>
+3.3V_SUS +3.3V_RUN 0.1U_0402_16V4Z~D 50 POWER_SW#_MB
49 49 POWER_SW#_MB <34,39>
0.1U_0402_16V4Z~D
1 +3.3V_CARD 48 BREATH_BLUE_LED_PWR
48 BREATH_BLUE_LED_PWR <38>
C508
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
R464 JEXP 47 LAN_ACTLED_YEL_R#
47 LAN_ACTLED_YEL_R# <28>
1 1 0_0402_5%~D 1 46 LED_10_GRN_R#
1 46 LED_10_GRN_R# <28>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
C509
C510
1 2 USBP7_D- 2 45 LED_100_ORG_R#
2 <24> USBP7- 2 45 LED_100_ORG_R# <28>
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
10U_0805_6.3V6M~D
1 1 U52 1 2 USBP7_D+ 3 44
<24> USBP7+ 3 44
C511
C512
12 11 1 1 1 CPUSB# 4 43 SW_LAN_TX0+
1.5Vin 1.5Vout 2 2 4 43 SW_LAN_TX0+ <28>
C513
C514
C515
14 13 R463 5 42 SW_LAN_TX0-
D 1.5Vin 1.5Vout 5 42 SW_LAN_TX0- <28> D
0_0402_5%~D EXP_SMBCLK 6 41 SW_LAN_TX1+
2 2 6 41 SW_LAN_TX1+ <28>
EXP_SMBDATA 7 40 SW_LAN_TX1-
2 2 2 +3.3V_CARDAUX 7 40 SW_LAN_TX1- <28>
2 3 8 39 SW_LAN_TX2+
3.3Vin 3.3Vout +3.3V_CARD 8 39 SW_LAN_TX2+ <28>
4 5 9 38 SW_LAN_TX2-
3.3Vin 3.3Vout 9 38 SW_LAN_TX2- <28>
PCIE_WAKE# 10 37 SW_LAN_TX3+
<30,33> PCIE_WAKE# 10 37 SW_LAN_TX3+ <28>
17 15 +3.3V_CARDAUX 11 36 SW_LAN_TX3-
AUX_IN AUX_OUT 11 36 SW_LAN_TX3- <28>
CARD_RESET# 12 35
+3.3V_SUS 12 35
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
<10,22> PLTRST1# PLTRST1# 6 19 13 34 +3.3V_LAN
SYSRST# OC# 13 34
1 14 14 33 33 +LOM_VCT
C506
0.1U_0402_16V4Z~D
R467 1 2 100K_0402_5%~D 20 8 1 EXPCLK_REQ# 15 32
SHDN# PERST# +3.3V_SUS <6> EXPCLK_REQ# 15 32 USB_POWERSHARE_PWR_EN# <33>
C517
1 EXPRCRD_PWREN# 16 31 CELL_CHARGER_DET_R#
16 31
C507
EXPRCRD_STDBY# 1 16 17 30 SW_USBP0-
<33> EXPRCRD_STDBY# STBY# NC 2 <33> DET_PCCRD_EXPSCRD# 17 30 SW_USBP0- <24>
CLK_PCIE_EXP# 18 29 SW_USBP0+
2 <6> CLK_PCIE_EXP# 18 29 SW_USBP0+ <24>
R471 1 2 100K_0402_5%~D EXPRCRD_PWREN# 10 7 CLK_PCIE_EXP 19 28
CPPE# GND 2 <6> CLK_PCIE_EXP 19 28
2.2K_0402_5%~D
2.2K_0402_5%~D
20 20 27 27 +5V_ALW
1
R472 1 2 100K_0402_5%~D CPUSB# 9 21 26
CPUSB# 21 26
22 22 25 25
R465
R466
18 CARD_RESET# <24> PCIE_IRX_EXPTX_N4 PCIE_IRX_EXPTX_N4 23 24
<33> EXPRCRD_PWREN# RCLKEN PCIE_IRX_EXPTX_P4 23 24
<24> PCIE_IRX_EXPTX_P4 24 24 23 23
R5538_QFN20~D 25 22 TPA0+
TPA0+ <29>
2
25 22 TPA0-
26 26 21 21 TPA0- <29>
6 1 EXP_SMBDATA 27 20 TPB0+
<30,34> CARD_SMBDAT 27 20 TPB0+ <29>
PCIE_ITX_EXPRX_N4_C 28 19 TPB0-
<24> PCIE_ITX_EXPRX_N4_C 28 19 TPB0- <29>
Q9A PCIE_ITX_EXPRX_P4_C 29 31 18 1394_DET# 1394_DET# <24>
<24> PCIE_ITX_EXPRX_P4_C 29 GND1 18
2N7002DW-7-F_SOT363-6~D 30 32 17 USB_OC0#
2
30 GND2 17 USB_OC0# <24>
+3.3V_SUS 16 16
MOLEX_52892-3019 15 +3.3V_RUN
15
5
Q9B 14 CARD_EN
14 CARD_EN <29>
2N7002DW-7-F_SOT363-6~D 13 SDWP# SDWP# <29>
EXP_SMBCLK 13 SDCD#_MMCCD#
<30,34> CARD_SMBCLK 3 4 12 12 SDCD#_MMCCD# <29>
11 SDCDAT1_MMCDAT1
11 SDCDAT1_MMCDAT1 <29>
10 SDCDAT0_MMCDAT0
C 10 SDCDAT0_MMCDAT0 <29> C
9 SDCCLK_MMCCLK
9 SDCCLK_MMCCLK <29>
8 MMCDAT7
8 MMCDAT7 <29>
7 DETECT GND
R1091 C1354 7 SDCCMD_MMCCMD
6 6 SDCCMD_MMCCMD <29>
0_0402_5%~D 0.1U_0402_16V4Z~D 5 MMCDAT5
5 MMCDAT5 <29>
2 1 1 2 CELL_CHARGER_DET_R# 4 SDCDAT3_MMCDAT3
AUDIO/B BTB connector, Left side <34> EN_CELL_CHARGER_DET# 4
3 MMCDAT4
SDCDAT3_MMCDAT3 <29>
3 MMCDAT4 <29>
2 1 2 MMCDAT6
<33> CELL_CHARGER_DET# 2 MMCDAT6 <29>
1 SDCDAT2_MMCDAT2
1 SDCDAT2_MMCDAT2 <29>
JAUDIO R1092
AUDIO_BD_DET# 2 1 DMIC_CLK DMIC_CLK <26> 0_0402_5%~D MOLEX_54132-5062
<24> AUDIO_BD_DET# BKT_LED 2 1 DMIC0
<21> BKT_LED 4 4 3 3 DMIC0 <26>
INSTANT_ON_SW#
<33,34> INSTANT_ON_SW# 6
8
6 5 5
7 BLUE_CRT SNIFFER connector and LED
8 7 BLUE_CRT <20>
<20> CLK_DDC2_CRT CLK_DDC2_CRT 10 9 GREEN_CRT
10 9 GREEN_CRT <20> +3.3V_ALW
<20> DAT_DDC2_CRT DAT_DDC2_CRT 12 11 RED_CRT
12 11 RED_CRT <20>
14 14 13 13
+3.3V_RUN_BKT_PWR 16 15 HSYNC_BUF
16 15 HSYNC_BUF <20>
3
+3.3V_RUN 18 17 VSYNC_BUF
18 17 VSYNC_BUF <20> +3.3V_ALW
+5V_RUN 20 20 19 19
22 21 USBP3+ JSNIFF
22 21 USBP3+ <24>
24 23 USBP3- 2 SNIFFER_DET# 1
24 23 USBP3- <24> <33> SNIFFER_YELLOW# <24> SNIFFER_DET# 1
26 25 Q86 2
ESATA_IRX_DTX_P4_C 26 25 DDTA114EUA-7-F_SOT323-3~D SNIFFER_PWR_SW# 2
<23> ESATA_IRX_DTX_P4_C 28 28 27 27 +5V_ALW <34> SNIFFER_PWR_SW# 3 3
ESATA_IRX_DTX_N4_C 30 29 +5V_ALW WIRELESS_ON#/OFF 4
<23> ESATA_IRX_DTX_N4_C 30 29 <33> WIRELESS_ON#/OFF SNIFFER_BLUE 4
32 32 31 31 5 5
<23> ESATA_ITX_DRX_N4 ESATA_ITX_DRX_N4 34 33 R757 SNIFFER_YELLOW 6
1
34 33 6
3
<23> ESATA_ITX_DRX_P4 ESATA_ITX_DRX_P4 36 35 1 2 SNIFFER_YELLOW 7
36 35 <33,38> LID_CL# 7
38 38 37 37 8 8
0.1U_0402_16V4Z~D
+VREFOUT 40 39 ESATA_USB_PWR_EN# 220_0402_5%~D <21> FP_SW_USBD- FP_SW_USBD- 9
40 39 ESATA_USB_PWR_EN# <33> 9
<26> AUD_MIC_SWITCH 42 41 ESATA_USB_OC# ESATA_USB_OC# <24> 2 2 <21> FP_SW_USBD+ FP_SW_USBD+ 10
42 41 <33> SNIFFER_BLUE# 10
C717
<26,27,33> AUD_HP_NB_SENSE AUD_HP_NB_SENSE 44 43 Q88 BIO_DET# 11
B 44 43 AUD_EXT_MIC_L DDTA114EUA-7-F_SOT323-3~D <24> BIO_DET# FP_RESET# 11 B
46 46 45 45 AUD_EXT_MIC_L <26> <32> FP_RESET# 12 12
<27> HP_SPK_L1 HP_SPK_L1 48 47 AUD_EXT_MIC_R +3.3V_RUN_BKT_PWR 13
HP_SPK_R1 48 47 DETECT GND AUD_EXT_MIC_R <26> 1 DETECT GND 13
<27> HP_SPK_R1 50 50 49 49 14 14
R758 15
1
FOX_QT510506-1010-7F SNIFFER_BLUE GND
1 2 16 GND
150_0402_5%~D MOLEX_52893-1419
1.8" Micro SATA HDD connector CAP Switch and ALS connector
PJP2 JHDD +3.3V_RUN_BKT_PWR
+3.3V_RUN 1 2 +3.3V_HDD 1 1
2 2
PAD-OPEN 4x4m 3 JSW
3 +3.3V_RUN_BKT_PWR
2.2K_0402_5%~D
2.2K_0402_5%~D
HDD_DET# 4 12
<24> HDD_DET# 4 G2
1
5 5 11 G1
6 6
R1083
R1084
C769 2 1 0.01U_0402_16V7K~D PSATA_IRX_DTX_P0 7 DETECT GND 10
<23> PSATA_IRX_DTX_P0_C C768 0.01U_0402_16V7K~D PSATA_IRX_DTX_N0 7 10
<23> PSATA_IRX_DTX_N0_C 2 1 8 8 9 9
2
9 +3.3V_RUN_BKT_PWR 8
2
9 8
10 10 7 7
PSATA_ITX_DRX_N0 11 <34> ALS_SMBDAT ALS_SMBDAT 6 1 CAPSW_ALS_SMBDAT 6
<23> PSATA_ITX_DRX_N0 11 6
PSATA_ITX_DRX_P0 12 CAP_SW_SMB_INT# 5
+3.3V_HDD <23> PSATA_ITX_DRX_P0 12 <33> CAP_SW_SMB_INT# 5
Q119A CAPSW_ALS_SMBDAT 4 4
5
13 2N7002DW-7-F_SOT363-6~D CAPSW_ALS_SMBCLK 3
GND1 3
14 GND2 +5V_RUN_BKT_PWR 2 2
ALS_SMBCLK 3 4 CAPSW_ALS_SMBCLK 1
<34> ALS_SMBCLK <33> SW_BD_DET# 1
10U_0805_10V4Z~D
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
MOLEX_52893-1219
1 1 1 Q119B MOLEX_52746-1070
C770
A 2N7002DW-7-F_SOT363-6~D A
C340
C341
2 2 2
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
Place close to JHDD BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Express Card, HDD, Sniffer, IO CONN
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 35 of 49
5 4 3 2 1
5 4 3 2 1
GPIO Expander for BlackTop
+3.3V_ALW
+3.3V_ALW
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
1 1
C653
C654
U38
0.1U_0402_16V4Z~D
0.1U_0402_16V4Z~D
2 2
ECE1088GPIO00 17 BKT_GPIO1
BKT_GPIO1 <20> 1 1
C663
C664
7 18 BKT_GPIO2 U51
D VCC GPIO01 BKT_GPIO3 BKT_GPIO2 <20,21> D
21 VCC GPIO02 19 BKT_GPIO3 <21>
20 BKT_GPIO4 30 9 KSO0
GPIO03 BKT_GPIO5 BKT_GPIO4 <21> 2 2 VCC1 KSO0 KSO1
GPIO07 26 BKT_GPIO5 <21> 10 VCC1 KSO1 11
1 BKT_GPIO6 12 KSO2
BC_DAT_ECE1088 GPIO13 BKT_GPIO7 BKT_GPIO6 <21> KSO2 KSO3
22 2 39 13
<34> BC_DAT_ECE1088
<34> BC_CLK_ECE1088
BC_CLK_ECE1088 23
BC_DAT/SMB_DATA
BC_CLK/SMB_CLK
GPIO14
GPIO15 3 BKT_GPIO8 BKT_GPIO7
BKT_GPIO8
<21>
<21>
NC3 ECE1077 KSO3
KSO4 14 KSO4
BC_INT#_ECE1088 24 4 BKT_GPIO9 15 KSO5
<34> BC_INT#_ECE1088 BC_INT#/SMB_INT# GPIO16 BKT_GPIO9 <21> KSO5 KSO6
GPIO17 5 KSO6 16
6 BKT_GPIO11 17 KSO7
R683 2 GPIO20 BKT_GPIO11 <26> KSO7
+3.3V_ALW 1 @ 10K_0402_5%~D GPIO24 8 37 NC1 KSO8 18 KSO8
R684 2 1 10K_0402_5%~D 25 9 38 19 KSO9
R685 2 SMB_ADDR GPIO25 NC2 KSO9
1 10K_0402_5%~D 28 TEST GPIO26 10 BKT_GPIO14
BKT_GPIO14 <20> KSO10 20 KSO10
27 11 BKT_GPIO15 21 KSO11
RESERVE GPIO27 BKT_GPIO16 BKT_GPIO15 <21> KSO11 KSO12
GPIO30 12 BKT_GPIO16 <21> KSO12 22
13 23 KSO13
GPIO31 KSO13 KSO14
29 THER_PAD GPIO32 14 KSO14 24
15 BKT_GPIO19 25 KSO15
GPIO36 BKT_GPIO19 <21> BC_DAT_ECE1077 KSO15 KSO16
GPIO37 16 <34> BC_DAT_ECE1077 34 BC_DATA KSO16/GPIO_0 26
27 KSO17
ECE1088-FZG_QFN28_5X5~D BC_CLK_ECE1077 KSO17/GPIO_1
<34> BC_CLK_ECE1077 35 BC_CLK KSO18/GPIO_2 28
KSO19/GPIO_3 29
BC_INT#_ECE1077 36 31
<34> BC_INT#_ECE1077 BC_INT# KSO20/GPIO_4
KSO21/GPIO_5 32
KSO22/GPIO_6 33
1 KSI0
Touch Pad connector KSI0
2 KSI1
KSI1 KSI2
KSI2 3
+5V_RUN_BKT_PWR 4 KSI3
R687 KSI3 KSI4
KSI4 5
2 1 40 6 KSI5
TEST_PIN KSI5 KSI6
KSI6 7
4.7K_0402_5%~D
4.7K_0402_5%~D
C 1K_0402_5%~D KSI7 C
41 GND_PAD KSI7 8
1
1
R682
R681
ECE1077-FZG_QFN40~D
JTP
L41 TP_DET# 1
2
BLM18AG601SN1D_0603~D <33> TP_DET# 1
2 2
CLK_TP_SIO 2 1 TP_CLK 3
<34> CLK_TP_SIO 3
DAT_TP_SIO 2 1 TP_DATA 4
<34> DAT_TP_SIO 4
L40 +5V_RUN_BKT_PWR 5 5
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
10P_0402_50V8J~D
@ SD05.TCT_SOD323-2~D
@ SD05.TCT_SOD323-2~D
BLM18AG601SN1D_0603~D 6 6
0.1U_0402_16V4Z~D
1 1 1 1 1 7 GND
1
C659
C658
C657
C656
C660
8 GND
D27
D28
TYCO_1734242-6
2 2 2 2 2
2
JKYBD
KB_DET# 1
KSI7 <24> KB_DET# 1
2 2
B KSI6 B
3 3
KSI4 4
KSI2 4
5 5
KSI5 6
KSI1 7
6 Keyboard Backlight connector
KSI3 7
8 8
KSI0 9
KSO5 9 +5V_RUN_BKT_PWR
10 10
KSO4 11 JKBBKT
KSO7 11
12 12 1 1
KSO6 13 <34> KYBRD_BKLT_PWM KYBRD_BKLT_PWM 2
KSO8 13 2
14 14 3 3
KSO3 15 KYBRD_BKT_DET# 4
KSO1 15 <24> KYBRD_BKT_DET# 4
16 16 5 GND
KSO2 17 6
KSO0 17 GND
18 18
KSO12 19 MOLEX_52745-0459
KSO16 19
20 20
KSO15 21
KSO13 21
22 22
KSO14 23
KSO9 23
24 24
KSO11 25
KSO10 25
26 26
KSO17 27 29
27 GND
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
@ 100P_0402_50V8J~D
DETECT GND 28 30
28 GND
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 IPEX_20413-028E
C1333
C669
C670
C671
C672
C673
C674
C675
C676
C677
C678
C679
C680
C681
C682
C683
C684
C685
C686
C687
C688
C665
C666
C667
C668
C689
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Keyboard,TouchPad and GPIO expander
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 36 of 49
5 4 3 2 1
5 4 3 2 1
+3.3V_ALW_ICH Source +5VRUN/+3.3V_RUN/+1.05V_VCCP/+1.5V_RUN Source
Q51 +15V_ALW +5V_ALW Q52 +5V_RUN
+15V_ALW +3.3V_ALW SI3456BDV-T1-E3_TSOP6~D STS11NF30L_SO8~D
+3.3V_ALW_ICH 8 1
1
D
10U_0805_10V4Z~D
20K_0402_5%~D
6 7 2
S
1
1
5 4 R689 6 3 1
10U_0805_10V4Z~D
20K_0402_5%~D
C691
R693
R688 2 +3.3V_ALW2 100K_0402_5%~D 5
1
+3.3V_ALW2 100K_0402_5%~D 1 1
C690
R690
G
4
1
RUN_ENABLE 2
2
1
ALW_ENABLE R692 1
3
D R691 2 100K_0402_5%~D C693 D
1
2
3
100K_0402_5%~D C692 Q19B
Q15B 2200P_0402_50V7K~D
2
4700P_0402_25V7K~D RUN_ON_ENABLE# 2N7002DW-7-F_SOT363-6~D 2
5
2
ALW_ON_3.3V# 2N7002DW-7-F_SOT363-6~D 2
5
4
6
Q19A
4
Q15A
2 2N7002DW-7-F_SOT363-6~D
<20,21,27,33,45> RUN_ON
2 2N7002DW-7-F_SOT363-6~D
<34> ICH_ALW
+15V_ALW
1
1 +3.3V_ALW Q54 +3.3V_RUN
SI4336DY-T1-E3_SO8~D
1
8 1
10U_0805_10V4Z~D
20K_0402_5%~D
R697 7 2
1
100K_0402_5%~D 6 3 1
C695
R698
+3.3V_SUS Source 5
2
R700
4
+15V_ALW +3.3V_ALW Q53 +3.3V_SUS 2
1 2
2
STS11NF30L_SO8~D 1
8 1 0_0402_5%~D C697
1
D
10U_0805_10V4Z~D
20K_0402_5%~D
7 2
1
R694 6 3 1 2 Q113 470P_0402_50V7K~D
2
C694
R695
+3.3V_ALW2 100K_0402_5%~D 5 G 2N7002W-7-F_SOT323-3~D
S
3
2
4
1
SUS_ENABLE 2
2
R696 1
100K_0402_5%~D 3 C696
Q16B
4700P_0402_25V7K~D +15V_ALW
2
C SUS_ON_3.3V# 2N7002DW-7-F_SOT363-6~D 2 +1.05V_M Q56 +1.05V_VCCP C
5
SI4336DY-T1-E3_SO8~D
6
1
8 1
4
10U_0805_10V4Z~D
20K_0402_5%~D
Q16A R704 7 2
1
100K_0402_5%~D 6 3 1
C699
R705
2 2N7002DW-7-F_SOT363-6~D 5
<34> SUS_ON
2
R709
1
4
2
1 2
2
1
0_0402_5%~D C701
1
D
Q114 470P_0402_50V7K~D
+3.3V_M Source 2
G 2N7002W-7-F_SOT323-3~D 2
S
3
Q55
+15V_ALW +3.3V_ALW SI3456BDV-T1-E3_TSOP6~D
+3.3V_M
D
6
S
1
5 4
10U_0805_10V4Z~D
20K_0402_5%~D
R701 2 +15V_ALW
1
+3.3V_ALW2 100K_0402_5%~D 1 1 +1.5V_MEM Q118 +1.5V_RUN
C698
R703
SI4336DY-T1-E3_SO8~D
G
1
8 1
2
3
1
10U_0805_10V4Z~D
20K_0402_5%~D
M_ENABLE R1069 7 2
1
R702 2 100K_0402_5%~D
1 6 3 1
2
3
C1349
R1070
100K_0402_5%~D C700 5
Q17B
2
4700P_0402_25V7K~D R1071
2
4
M_ON_3.3V# 2N7002DW-7-F_SOT363-6~D 2 2
5 1 2
2
1
6
0_0402_5%~D C1350
4
1
B Q17A D B
2 Q115 470P_0402_50V7K~D
2N7002DW-7-F_SOT363-6~D G 2N7002W-7-F_SOT323-3~D 2
<34> M_ON 2
S
3
1
Level shifter for +1.05V_M and +1.5V_MEM PWM IC
Discharg Circuit
+5V_ALW +5V_ALW
+3.3V_SUS +3.3V_RUN
2
+5V_ALW +5V_ALW
1
R1073 R1075
4.7K_0402_5%~D
4.7K_0402_5%~D
4.7K_0402_5%~D 4.7K_0402_5%~D
2
R718 R716
1
EN_1.05VALW EN_1.05VALW <42> EN_1.5VALW EN_1.5VALW <42> @ 1K_0402_5%~D @ 1K_0402_5%~D
R1074
R1076
1 2
1 2
3
D D
1
SUS_ON_3.3V# 2 Q64 RUN_ON_ENABLE# 2 Q62
5 Q116B 5 Q117B G @ 2N7002W-7-F_SOT323-3~D G @ 2N7002W-7-F_SOT323-3~D
2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D S S
3
6
6
4
M_ON 2 Q116A <10,34,45> DDR_ON DDR_ON 2 Q117A
A 2N7002DW-7-F_SOT363-6~D 2N7002DW-7-F_SOT363-6~D A
1
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, POWER CONTROL
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 37 of 49
5 4 3 2 1
5 4 3 2 1
Keyboard Status, Num Lock/Caps Lock/Scroll Lock LEDs POWER/SUSPEND breathing LED
+5V_ALW +3.3V_ALW
+5V_ALW
1
R1046
3
100K_0402_5%~D
Q98B
2N7002DW-7-F_SOT363-6~D JLED
2
<24> LED_BD_DET#
<33> NUM_LED# 2 4 3 2 1 1
Q102 SATA_LED 2 2
6
Q74 DDTA114EUA-7-F_SOT323-3~D BATT_BLUE_LED 3 3
3
D DDTA114EUA-7-F_SOT323-3~D Q98A BATT_YELLOW_LED D
4
5
+3.3V_ALW 2N7002DW-7-F_SOT363-6~D W LAN_LED 4
5 5
C1338 2 R1047 BT_LED 6
1
R741 +3.3V_ALW 6
<33> CAP_LED# 2 1 2 150_0402_5%~D R_NUM_LED MASK_BASE_LEDS# 1 2 BREATH_BLUE_LED_PWR <35> W WAN_LED 7 7
R_NUM_LED 8
1
Q75 0.1U_0402_16V4Z~D +5V_ALW 150_0402_5%~D R_CAP_LED 8
9 9
3
1
DDTA114EUA-7-F_SOT323-3~D R_SCRL_LED 10 10
1
R1048 DETECT GND 11 11
3
100K_0402_5%~D 12
NC
1
R744 12
<33> SCRL_LED# 2 1 2 150_0402_5%~D R_CAP_LED
<31,34> BREATH_LED# 2 A Y 4 Q99B
2N7002DW-7-F_SOT363-6~D 13
2
GND1
G
Q76 U88 4 3 2 14
DDTA114EUA-7-F_SOT323-3~D NC7SZ04P5X_NL_SC70-5~D Q103 GND2
6
DDTA114EUA-7-F_SOT323-3~D TYCO_1-1775784-2
Q99A
1
5
R745 1 2 150_0402_5%~D R_SCRL_LED 2N7002DW-7-F_SOT363-6~D
2 R1049
1
SYS_LED_MASK# 1 2 BREATH_BLUE_LED <20>
1
150_0402_5%~D
HDD LED
+3.3V_RUN
+5V_RUN BATTERY LED
1
R742 +5V_ALW
10K_0402_5%~D 3
R1050
3
+5V_ALW 1 2
2
3 1 SATA_ACT# 2
<23> SATA_ACT#_R
Q77 @ 100K_0402_5%~D
C Q78 PDTA114EU_SC70-3~D C
1 6 2
2N7002W-7-F_SOT323-3~D Q104
G
2
DDTA114EUA-7-F_SOT323-3~D
MASK_BASE_LEDS# Q100A
1
2
R747 MASK_BASE_LEDS# 2N7002DW-7-F_SOT363-6~D
1 2 SATA_LED
1
+5V_ALW R1051
150_0402_5%~D +3.3V_ALW 1 2 BATT_BLUE_LED
100K_0402_5%~D
C1339
1
150_0402_5%~D +5V_ALW
BATT_YELLOW_LED
WLAN LED
R1052
0.1U_0402_16V4Z~D
Q106
3
5
1
+3.3V_WLAN 2N7002W-7-F_SOT323-3~D
2
P
NC
D
+5V_RUN 2 4 BAT2_LED 5 3 1 2
<34> BAT2_LED# A Y
1
Q100B
G
R749 U89 2N7002DW-7-F_SOT363-6~D
4
3
100K_0402_5%~D NC7SZ04P5X_NL_SC70-5~D
G
3
2
Q105
SYS_LED_MASK# DDTA114EUA-7-F_SOT323-3~D
2
1
S
<30> LED_WLAN_OUT# 3 1 2
Q81 +3.3V_ALW
Q82 PDTA114EU_SC70-3~D
2N7002W-7-F_SOT323-3~D R1053
G
2
3
+3.3V_ALW 1 2
MASK_BASE_LEDS#
1
R751 @ 100K_0402_5%~D
1 2 W LAN_LED 1 6 2
Q107
150_0402_5%~D DDTA114EUA-7-F_SOT323-3~D
Q101A
2
B MASK_BASE_LEDS# 2N7002DW-7-F_SOT363-6~D B
WWAN LED
1
+3.3V_ALW R1054
+3.3V_ALW 1 2
100K_0402_5%~D
+3.3V_RUN_BKT_PWR C1340
1
150_0402_5%~D +3.3V_ALW
+5V_RUN_BKT_PWR
1
R1055
0.1U_0402_16V4Z~D
Q109
3
R753
3
100K_0402_5%~D 2N7002W-7-F_SOT323-3~D
2
P
NC
D
2 4 BAT1_LED 5 3 1 2 R1056
<34> BAT1_LED#
2
A Y
S
3 1 2 Q101B 1 2 BATT_BLUE <20>
<30> LED_WWAN_OUT#
G
Q83 U90 2N7002DW-7-F_SOT363-6~D
4
Q84 PDTA114EU_SC70-3~D NC7SZ04P5X_NL_SC70-5~D 150_0402_5%~D
G
3
2
2N7002W-7-F_SOT323-3~D
G
2
SYS_LED_MASK# Q108 R1057
1
MASK_BASE_LEDS# DDTA114EUA-7-F_SOT323-3~D 1 2 BATT_YELLOW <20>
1
R754
1 2 W WAN_LED 150_0402_5%~D
150_0402_5%~D
+3.3V_ALW
LED Circuit Control Table C1341
BLUETOOTH LED
+3.3V_RUN 0.1U_0402_16V4Z~D
SYS_LED_MASK# LID_CL#
5
C1337
2 1 +5V_RUN SYS_LED_MASK# 2
P
<33> SYS_LED_MASK# A
Mask All LEDs (Sniffer Function) 0 X 4 MASK_BASE_LEDS#
0.1U_0402_16V4Z~D LID_CL# Y
<33,35> LID_CL# 1 B
3
G
A U91 A
5
1
Mask Base MB LEDs (Lid Closed) 1 0 74AHCT1G08GW_SOT353-5~D
3
P
NC
<30> BT_ACTIVE BT_ACTIVE 2 4 BT_ACTIVE_R# 3 1 BT_ACTIVE# 2
A Y Q79 Do not Mask LEDs (Lid Opened) 1 1
DELL CONFIDENTIAL/PROPRIETARY
G
10K_0402_5%~D
U87 Q80 DDTA114EUA-7-F_SOT323-3~D
1
74LVC1G14GV_SOT753-5 2N7002W-7-F_SOT323-3~D
G
3
Compal Electronics, Inc.
R748
MASK_BASE_LEDS#
1
R750 PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
1 2 BT_LED TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
System LEDs Control
2
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
150_0402_5%~D NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 38 of 49
5 4 3 2 1
5 4 3 2 1
Power button switch for debug
D PWR_SW1 D
<34,35> POWER_SW#_MB 1 1 2 2
@ 100P_0402_50V8J~D
1
C655
Fiducial Mark Place on Top
2 PWR_SW2
FD1 FD2 FD3 FD4
1 1 1 1 1 1 2 2
FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D FIDUCIAL MARK~D
Place on Bottom
C C
MB_PCB
BARE PCB
1 NC
Minicooper_LA-4291P REV0_M/B~D
H1 H2 H3 H4 H5 H6 H7 H8 H9 H10
H_4P0 H_4P0 H_1P2 H_1P2 H_3P25 H_2P2 H_2P3 H_2P1 H_2P2 H_2P6x2P1
1
H11 H12 H13 H14 H15
H_2P2 H_2P2 H_2P2 H_2P2 H_3P25
1
1
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Standoff and EE Design Part
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 39 of 49
5 4 3 2 1
5 4 3 2 1
+COINCELL
COIN RTC Battery
1
PR1
1K_0402_5%~D PJRTC
+COINCELL 1 1
+3.3V_RTC_LDO 2
<23> RTC_BAT_DET_R#
2
+3.3V_ALW 2
3 3
Z4012
4 GND
D ESD Diodes 5 GND D
MOLEX_53780-0370~D
3
+RTC_CELL
2
Primary Battery Connector
PL1 PD1
1
FBMA-L18-453215-900LMA90T_1812~D BAT54CW_SOT323~D
PD2 PD3 PD4 PD5 1 2 1
1
@ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D @ DA204U_SOT323~D +3.3V_ALW PC1
27.4 1U_0603_10V4Z~D
PJP6
2
1 2 PBATT+
0.1U_0603_25V7K~D
Move to power schematic
1
10K_0402_1%~D
PAD-OPEN 4x4m
PC2
PJBATT
PR2
11
2
GND
10 <BOM Structure>
GND PR3
9
2
9 100_0402_5%~D PR4
8 8
2200P_0402_50V7K~D
7 Z4304 1 2 100_0402_5%~D PR5
7 PBAT_SMBCLK <34>
6 Z4305 1 2 100_0402_5%~D
6 PBAT_SMBDAT <34>
5 Z4306 1 2
5 PBAT_PRES# <33>
1
PC3
4 4
3 3
2
2
2
1 1
SUYIN_200277MR009G515ZR PQ44
PD22 NTR4502PT1G_SOT23-3~D
RB751V_SOD323~D
3
1 2 1 3 DOCK_SMB_ALERT# <31,34>
2
2
C C
PR334
<31,33,47> SLICE_BAT_PRES# 1 2
0_0402_5%~D
+5V_ALW +3.3V_ALW
DA204U_SOT323~D
2
PD6
2.2K_0402_5%~D
@ PR7 PU1
2
1 2 <31> DOCK_PSID 1 NO IN 6 GPIO_PSID_SELECT <33>
0_0402_5%~D
PR8
2 GND V+ 5 +5V_ALW
PL2 PR9
1
BLM18BD102SN1D_0603~D 33_0402_5%~D
NB_PSID NB_PSID_TS5A63157
S
2 1 1 3 1 2 3 NC COM 4 PS_ID <34>
100K_0402_1%~D
PQ4 TS5A63157DCKR_SC70-6~D
2
2
FDV301N_SOT23~D
G
2
PR10
+3.3V_ALW +5V_ALW
10K_0402_1%~D
1
1
DA204U_SOT323~D
@ C
1
PR11
PD7 2 PQ5
SM24_SOT23 B MMST3904-7-F_SOT323~D
3
B B
PD21
15K_0402_1%~D
3
2
2
PR12
@ PR13
@ PR331 1 2
1K_0402_1%~D PSID_DISABLE# <33>
1
1 2 DCIN_CBL_DET# <33> @ 10K_0402_5%~D
.47U_0402_6.3V6-K~D
2
PC177
@
PQ6
+DC_IN FDS6679AZ_SO8~D DC_IN+ Source +DC_IN_SS
1 8
2 7
PL3 3 6
FBMJ4516HS720NT_1806~D 5
1 2 +D C_IN
0.1U_0805_25V7K
1M_0402_5%~D
1
VZ0603M260APT_0603
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
0.1U_0603_25V7K~D
4.7K_0805_5%~D
10U_1206_25V6M~D
4
1
PR14
PC4
PQ1B
1
PD9
1
1
IMD2AT-108_SC74-6~D
PR15
PC5
PC6
PC7
PC8
0.1U_0603_25V7K~D
2
1
@
2
0.1U_0603_25V7K~D
PJDCIN @ 3 4
2
1
PC9
1
2
1
1M_0402_5%~D
2 2
1
2
PC10
0_0402_5%~D
22K_0402_5%~D
3 -D CIN_JACK
2
3
1
4 4
PR17
PR18
5
2
5
PR16
6 + DCIN_JACK @
6
2
A MOLEX_87438-0643 PL4 A
2
FBMJ4516HS720NT_1806~D
1 2 @
1
0.1U_0603_25V7K~D
RHU002N06_SOT323
@ PQ1A
1
IMD2AT-108_SC74-6~D PR332
1
D 100K_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
PC11
PQ7
5 2 1 2
2
<47> NB_AC_OFF_BJT G NB_AC_OFF <33,46,47>
S
Compal Electronics, Inc.
3
PC12
0.1U_0603_25V7K~D Title
6
+DCIN
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WWW.AliSaler.Com
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-4291P
Date: Friday, December 07, 2007 Sheet 40 of 49
5 4 3 2 1
5 4 3 2 1
+3.3V_ALWP/ +5V_ALWP/ +5V_ALW2 / +15V_ALWP
+DC1_PWR_SRC
D D
PJP7
+PWR_SRC 1 2
PAD-OPEN 4x4m
2
0_0805_5%
0_0805_5%
PJP8 +5V_VCC1
2200P_0402_50V7K~D
0.1U_0805_50V7K
+5V_ALW2 1 2
PR19
PR20
2200P_0402_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
0.1U_0805_50V7K
@ PR21
1
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
PAD-OPEN1x1m 10_0603_5%~D
1
1
PC13
PC14
PC15
PC16
PC17
4.7U_0805_6.3V6K
2 1
PC18
PC19
PC20
PC21
PC22
2
2
1
PC23
+3.3V_ALW2
2
1U_0603_25V7K~D
1U_0603_10V6K~D
1
PC24
0_0402_5%~D
1U_0603_10V6K~D
PR22
1
PC25
@ 0_0402_5%~D
1
PC26
PR354
1 2
2
PR23
2
0_0402_5%~D
EN_3V_5V
1 2
+3.3V_RTC_LDO
5V_3V_REF PC27
0.1U_0603_25V7K~D
1
GNDA_3V5V 1 2 GNDA_3V5V
PR24
3.3 Volt +/-5%
FDMC8878_1N_POWER33-8~D
0_0402_5%~D
5 Volt +/-5% 1 2
0.1U_0402_10V7K~D
Thermal Design Current: 6.73A
5
FDMS8692_POWER56-8~D
0.1U_0402_10V7K~D
@ PR25
Thermal Design Current:7.39A
2
3
PC28
0_0603_5%~D @ PR26 Peak current: 9.62A
8
7
6
5
4
3
2
1
1
Peck current: 10.55A GNDA_3V5V PU2 2 1
1
+5V_ALWP
PC29
OCP min: 11A
V5FILT
LDO
VREF3
EN_LDO
TONSEL
VREF2
LDOREFIN
VIN
PQ9
C OCP min: 11A 0_0402_5%~D @ C
2
PQ8
2
2 @ PR27
G 154K_0402_1%~D
9 VSW REFIN2 32
+5V_ALWP PR28 10 31 1 2 GNDA_3V5V
VOUT1 TRIP2
S
150K_0402_1%~D 11 30
3
2
1
VFB1 VOUT2
GNDA_3V5V 1 2 12 29 2 PR29 0_0402_5%~D
1 +3.3V_ALWP
1
PL5 ALW_PWRGD_3V_5V 13 TRIP1 SKIPSEL POK_3.3V PL6
PGOOD1 PGOOD2 28
2.2UH_MPLC1040L2R2_11A_20%~D EN_3V_5V 14 27 EN_3V_5V 2.2UH_MPLC1040L2R2_11A_20%~D
+5V_ALW_UGATE EN1 EN2 +3.3V_ALW_UGATE
15 DRVH1 DRVH2 26
2 1 +5V_ALW_PHASE 16 25 +3.3V_ALW_PHASE 2 1
LL1 LL2
1000P_0603_50V7K~D
0_0603_5%~D
1000P_0603_50V7K~D
0.1U_0603_25V7K~D
V5DRV
SECFB
DRVL1
DRVL2
VBST1
VBST2
2
8
7
6
5
PGND
0.1U_0603_25V7K~D
0_0603_5%~D
GNDA_3V5V
GND
PAD
2
PR30
330U_D3L_6.3V_R18~D
FDS6676AS_NL_SO8~D
PC179
330U_D2E_6.3VM_R25~D
1
0.1U_0402_10V7K~D
0.1U_0402_10V7K~D
PC178
1
PC30
PC31
PR31
FDMC8854_1N_POWER33-8~D
1 SN0608098_QFN32_5X5~D 1
33
17
18
19
20
21
22
23
24
2
PQ10
@ @
1
2
1
1
PC32
PC34
PC35
PC33
+ @ 4 GNDA_3V5V +
1
4
2
2
2.2_0805_1%~D
PQ11
PR32 PR33
2
2
2 2
PR335
1_0603_5%~D 1_0603_5%~D
0_0603_5%~D
2.2_0805_1%~D
0_0603_5%~D
1 2 +5V_ALW_BOOT +3.3V_ALW_BOOT1 2
1
2
3
2
2
PR336
3
2
1
PR35
+5V_ALW_LGATE +3.3V_ALW_LGATE
1
1
PR34
@
@
@
1
1
GNDA_3V5V
GNDA_3V5V
4.7U_0603_6.3V6K~D
GNDA_3V5V PC36 PJP9
1
+5V_ALWP 2 0.1U_0603_25V7K~D 1 2
+3.3V_ALW +3.3V_ALW
PC37
1 1 2
0.1U_0603_25V7K~D
+5V_ALW2
3 VOUT2=3.3V
2
VOUT1=5V PAD-OPEN1x1m
L=2.2uF
1
B B
100K_0402_1%~D
100K_0402_1%~D
L=2.2uF PD10 GNDA_3V5V Fsw=500KHz
PC38
BAT54SW-7-F_SOT323-3~D
Fsw=400KHz D=0.169
2
2
PR36
PR37
D=0.256 PC39 Output Ripple Current=2.49A
2 0.1U_0603_25V7K~D PD12
Output Ripple Voltage=2.49A*25mOhm=62.25mV
1
Output Ripple Current=4.23A 1 1 2 BAT54CW_SOT323~D
3 @
1
Output Ripple Voltage=4.23A*18mOhm=76.14mV
PR38 PD11 POK_3.3V
2K_0402_5%~D
2 1 BAT54SW-7-F_SOT323-3~D
<34> ALWON
3
0_0402_5%~D
1
200K_0402_5%
2
PR39
PR41
PR40
0_0402_5%~D
<19> THERM_STP# 2 1
2
1
ALW_PWRGD_3V_5V
ALW_PWRGD_3V_5V <34>
PR42
PJP10 200K_0402_1%~D
+15V_ALW 2 1 +15V_ALWP 2 1
0.1U_0603_25V7K~D
39.2K_0402_1%~D
PAD-OPEN1x1m
2
(100mA,20mils ,Via NO.=1)
1
PJP11
PC40
PR43
+5V_ALWP 1 2 +5V_ALW
2
PAD-OPEN 4x4m
1
A A
GNDA_3V5V
PJP13
+3.3V_ALWP 1 2 +3.3V_ALW
PAD-OPEN 4x4m
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
DC/DC +3V/ +5V
WWW.AliSaler.Com
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-4291P
Date: Friday, December 07, 2007 Sheet 41 of 49
5 4 3 2 1
5 4 3 2 1
VT351_PWR2 +1.5V_SUS_P / +1.05V_M
PJP15
1 2 +5V_ALWP
PAD-OPEN 4x4m
0.1U_0603_25V7K~D
0.01U_0402_25V7K~D
2
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
PC42
PC43
1
1
PR44
PC174
PC41
D5
D4
E5
E4
E3
E2
E1
10_0402_1%~D
PU3
2
VT351FCX-ADJ_CSP25~D
VX
VX
VDD
VDD
GND
GND
GND
1
A1 BIAS VX D3
D D
A2 D2
1.05 Volt +/-5%
R_SEL/ILOAD VX
A3 D1
Thermal Design Current: 4.94A
AVDD2 VDES VX
VSENSE2 A4 C5
Peack current: 7.05A
VSENSE+ VDD
EN2 A5 C4
OCP min:10A +1.05V_MP
OE VDD
B1 AGND GND C3
TEMP
AVDD
STAT
IRIPL
GND
GND
PL7
0.2UH_ MPC0730LR20C_17.5A~D
2200P_0402_50V7K~D
PHASE2_L 2 1
B2
AVDD2 B3
B4
B5
C1
C2
39K_0402_1%~D
0_0603_5%~D
2
0.22U_0402_10V7K~D
6800P_0402_25V7K~D
1
3.09K_0402_1%~D
1000P_0603_50V7K~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
PR47
PR321
POK2
1
0.1U_0603_25V7K~D
44.2K_0402_1%~D
PC45
PC180
PC52
1
1
PC44
31.6K_0402_1%~D
PC53
2
PR45
PR46
PR48
PC46
PC47
PC48
PC49
PC50
PC51
2
1
2.2_0805_1%~D
@ VSENSE2
2
2
2
0_0603_5%~D
@
2
PR337
PR322
@
PJP16
1
@
1
2 1
GNDA_1P05V
PAD-OPEN1x1m
C VT351_PWR1 C
GNDA_1P05V
PJP17
1 2 +5V_ALWP
0.01U_0402_25V7K~D
PAD-OPEN 4x4m
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
0.1U_0603_25V7K~D
PC56
PC57
1
1
2
PC54
PC55
PR49
2
10_0402_1%~D
1
AVDD1
D5
D4
E5
E4
E3
E2
E1
PU4
VT351FCX-ADJ_CSP25~D
1.5 Volt +/-5%
VX
VX
VDD
VDD
GND
GND
GND
BIAS1 A1 BIAS VX D3 Thermal Design Current: 7.64A
A2 R_SEL/ILOAD VX D2 Peak current: 10.92A
A3 VDES VX D1 OCP min: 15A
VSENSE1 A4 C5
VSENSE+ VDD
EN1 A5 C4 +1.5V_SUS_P
OE VDD
B1 AGND GND C3
TEMP
0.22U_0402_10V7K~D
2200P_0402_50V7K~D
AVDD
STAT
IRIPL
GND
GND
B PL8 B
56K_0402_1%
3.74K_0402_1%~D
44.2K_0402_1%
0.2UH_ MPC0730LR20C_17.5A~D
1
1
PC58
PR52
PHASE1_L 2 1
B2
AVDD1 B3
B4
B5
C1
C2
1000P_0603_50V7K~D
PR50
PR51
PC59
24K_0402_1%~D
0_0603_5%~D
6800P_0402_25V7K~D
2
10U_0805_6.3V6K~D
10U_1206_6.3V7K~D
10U_1206_6.3V7K~D
10U_0805_6.3V6K~D
POK1
1
10U_0805_6.3V6K~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
22U_1206_6.3V6M~D
PC181
PR323
PC70
0.1U_0603_25V7K~D
1
1
PR53
PC71
PC60
PC61
PC62
PC63
PC64
PC65
PC66
PC67
PC68
PC69
2
2
2
VSENSE1 @ @ @
2
0_0603_5%~D
2
2.2_0805_1%~D
PR338
PR324
GNDA_1P5V
PJP18
1
1
2 1 @
PAD-OPEN1x1m +3.3V_ALW
PJP19 GNDA_1P5V
+1.05V_MP 1 2 +1.05V_M
100K_0402_1%~D
100K_0402_1%~D
PAD-OPEN 4x4m
2
2
PR355
PR356
PR58
0_0402_5%~D PR59
PJP20 1 2 EN2
1
A +1.5V_SUS_P 1 2 +1.5V_MEM <37> EN_1.05VALW 0_0402_5%~D A
POK2 1 2 1.05V_M_PWRGD <34>
PAD-OPEN 4x4m
PJP21 PR60
1 2 0_0402_5%~D
PAD-OPEN 4x4m <37> EN_1.5VALW
1 2 EN1
PR57
0_0402_5%~D
DELL CONFIDENTIAL/PROPRIETARY
POK1 1 2 1.5V_SUS_PWRGD <10,34> Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +1.5V_SUS_P / +1.05V_MP
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
WWW.AliSaler.Com
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 42 of 49
5 4 3 2 1
8 7 6 5 4 3 2 1
H H
7.32K_0603_1%
1
@ PL9
+PWR_SRC
PR61
FBMA-L11-321611-800LMA40T
+5V_RUN PD13
RB751V-40_SOD323~D +CPU_PWR_SRC 2 1
2
2 1 AD3419_BST1
PJP22
1000P_0402_50V7K~D
0.1U_0805_25V7K~D
@
10U_1206_25V6M~D
10U_1206_25V6M~D
68U_25V_M_R0.36
68U_25V_M_R0.36
1 2
+5V_RUN
0.01U_0402_25V7K~D
4.7U_0805_10V6K
0.33U_0603_10V7K
SI7686DP-T1-E3_SO8~D
1 1
D
1
2
0_0402_5%~D
0_0603_5%~D
PAD-OPEN 4x4m
1
PC73
PC76
PC77
PC78
PC79
PC170
PC171
+ +
1
PR64
PR62
PC75
1U_0805_25V4Z~D 10_0603_5%
PQ12
<33> IMVP_VR_ON
2
1
PC80
PR63
2
2
G G 2 @ 2 @ G
1
PU5
S
@
2
Thermistor PH1 should be placed +VCC_CORE
1
100K_0603_5%_TH11-4H104FT
close to the hot spot of the VR 1 IN BST 10
@ PL10
1
2 9 AD3419_DRVH1 0.45UH_ETQP4LR45XFC_25A_20%~D
SD# DRVH
1
PH1
GNDA_CORE
PC81
3 8 AD3419_SW1 4 1
@ DRVLSD# SW
1000P_0603_50V7K~D
4 7 3 2
2
CROWBAR GND
FDMS8670AS_POWER56-8~D
FDMS8670AS_POWER56-8~D
ADP3207_SW1
1
ADP3207_CSREF
5 VCC DRVL 6
PC182
GNDA_CORE
2
PH3
GNDA_CORE PR67 ADP3419JRMZ-REEL_MSOP10~D @
PQ14
PQ13
@ PR66 AD3419_DRVL1 1 2
+3.3V_RUN 0_0402_5%~D 0_0402_5%~D 2 2
F G G F
<8> H_PSI# 2 1 1 2
2
220K_0402_5%_ERTJ0EV224J~D
<8,10,23> H_DPRSTP#
S
PR720_0402_5%~D
PR730_0402_5%~D
PR740_0402_5%~D
PR750_0402_5%~D
PR760_0402_5%~D
2.2_0805_1%~D
<8> VID6
1.91K_0402_1%~D
1.91K_0402_1%~D
<8> VID5
1
1
PR339
<8> VID4
PR70 0_0402_5%~D
<8> VID3
1
1
1
PR68
PR69
<8> VID2 1 2
ADP3207_TTSENSE
<8> VID1 1 2
PR71 0_0402_5%~D PR78 @
2
1 2 0_0402_5%~D
<8> VID0
PR77 0_0402_5%~D @ 1 2
2
2
PR79
<24,33,44> IMVP_PWRGD 0_0402_5%~D
GNDA_CORE
40
39
38
37
36
35
34
33
32
31
<33> IMVP_VR_ON 2 1
PU6
DPRSTP
PSI
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCC
PR80
Solution for Penryn SFF ULV: 1-phase
<19> PWR_MON
E
10K_0402_5%~D Icc MAX:19A E
2 1
CLK_ENABLE# 1 EN TTSENSE 30 Icc dynamic:15.5A
PC82
1000P_0402_50V7K~D PC83 2 PWRGD VRTT 29 ADP3207_VRTT
T110
Icc Inst time:(35us- up to 70us maximum)
1 2 0.1U_0402_10V7K~D
GNDA_CORE 1 2 3 28 ADP3207_#DCM Load line :4mOhm
PMON DCM
GNDA_CORE
4 CLKEN OD 27
PC84 5 26 ADP3207_PWM1
100P_0402_50V8K FBRTN PWM1
2 1 6 ADP3207AJCPZ-RL_LFCSP40~D 25
FB PWM2
2
PR81 PC86 PWM2, PWM3 pull high
1K_0402_1% 820P_0402_25V8K PC85 7 24
27P_0402_50V8K COMP PWM3
2 1 1 2 1 2
1
PR82 8 23
10K_0603_0.1%~D SS SW1
9 STSET SW2 22
0.015U_0402_16V7K
D D
10 DPRSLP SW3 21
1
390P_0402_50V7K
PC87
PC88
RAMPADJ
CSCOMP
2
CSSUM
CSREF
2
LLSET
RRPM
VRPM
ILIMIT
GND
PR84
RT
499_0402_1%
1
11
12
13
14
ADP3207_RAMPADJ 15
16
17
18
19
20
<10,24> DPRSLPVR
1
309K_0402_1%
GNDA_CORE GNDA_CORE
2
160K_0402_1%~D2
ADP3207_CSSUM
ADP3207_CSREF
2
PR86
PR85
PR87
0_0402_5%~D GNDA_CORE
392K_0402_1%
2
2 1 2 1 1 2
1
1
PR88
1
1
1000P_0402_50V7K~D
PR90 PR330 PR95
2200P_0402_50V7K~D
2200P_0402_50V7K~D
C PR89 71.5K_0402_1%~D 165K_0402_1%~D 84.5K_0603_1%~D C
PR91 280K_0402_1%
0_0402_5%~D
1
PC175
PC176
GNDA_CORE
2
2
PC89
@
2
VCCSense <8>
1
GNDA_CORE
0_0402_5%~D
GNDA_CORE
1000P_0402_50V7K~D
VSSSense <8>
1
1
PC90
1000P_0402_50V7K~D
PR93
@ 100_0402_5%~D
1
PC91
PR92
1 2 +VCC_CORE
2
B B
2
PR94
2
@ 100_0402_5%~D
1 2
GNDA_CORE +PWR_SRC
GNDA_CORE
NOTE: ( Connection VCORE output Cap GND)
De-populate PR93 and PR94 when CPU is present
PJP23 DELL CONFIDENTIAL/PROPRIETARY
A 1 2 A
Compal Electronics, Inc.
PAD-OPEN1x1m Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCORE
WWW.AliSaler.Com
GNDA_CORE AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-4291P
Date: Friday, December 07, 2007 Sheet 43 of 49
8 7 6 5 4 3 2 1
5 4 3 2 1
PR96
0_0402_5%~D
<10> GFX_VID4 1 2
PR97
0_0402_5%~D
<10> GFX_VID3 1 2
PR98
0_0402_5%~D
D <10> GFX_VID2 1
PR99
2 D
0_0402_5%~D
<10> GFX_VID1 1 2
PR100
0_0402_5%~D
<10> GFX_VID0 1 2
<10> GFX_VR_ON 1 2
PR101
0_0402_5%~D
+5V_ALW
PJP24
+VGFX_SRC 1 2 +PWR_SRC
PAD-OPEN 4x4m
2
PR102
10U_1206_25V6M~D
10U_1206_25V6M~D
2200P_0402_50V7K~D
0.1U_0805_50V7K
10_0603_5%~D
<24,33,43> IMVP_PWRGD VGFX_CORE
1
Thermal Design Current: 6.09A
PC92
PC93
PC94
PC95
FDMC8878_1N_POWER33-8~D
5
Peak current: 8.7A
2
1
PC96 OCP min: 11A
C
<14> VSS_AXG_SENSE 1U_0603_10V4Z~D C
PQ16
GNDA_VGA
4.7U_0805_10V4Z
32
31
30
29
28
27
26
25
4
PU7
GNDA_VGA
VARFREQ#
PWRGD
VID0
VID1
VID2
VID3
VID4
EN
1
PD14
PC97
1 24 PR104 RB751V-40_SOD323~D
3
2
1
FBRTN VCC 0_0603_5%~D
2
2 1 2 FB BST 23 2 1 1 2
+VGFX_COREP
PR103 3 COMP DRVH 22 DR VH PL11
33.2K_0402_1%~D 0.42UH_MPC0740LR42C_20A_20%~D
PC99 4 SS SW 21 S W 2 1
2
1
VSS_AXG_SENSE
22P_0402_50V8J
0.012U_0402_16V7K~D
PR105 @ PC98 5 20
ST PVCC
680P_0402_50V7K~D
100_0402_5%~D 22P_0402_50V8J @
2
330U_D2_2VY_R7~D
330U_D2_2VY_R7~D
PR108 6 PMON DRVL 19 DR VL PC107
1
FDMC8854_1N_POWER33-8~D
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
PC102
PC103
PR107 20K_0402_1%~D 1 2 1000P_0603_50V7K~D 1 1
1
1
0.1U_0402_16V7K
PC106
2 1 1 2 1 2 7 18
2
PMONFS PGND
PC104
PC105
PC172
PC173
PC100 + +
CSCOMP
2
1K_0402_1%~D PC101 8 17 1U_0603_10V6K~D
CSREF
2
CLIM GND
RAMP
VRPM
LLINE
CSFB
470P_0402_50V7K
RPM
2
2 2
PQ17
@ @
RT
AGND 33 4
2
@ PR109 @
2
2
187K_0402_1%
78.7K_0402_1%~D
100_0402_1%~D ADP3209JCPZ-RL_LFCSP32_5X5~D PR106
9
10
11
12
13
14
15
16
PR110
PR111
2.2_0805_1%~D
+VGFX_COREP 1
3
2
1
GNDA_VGA 1 2
1
1000P_0402_50V7K~D
GNDA_VGA
1
200K_0402_1%~D
1000P_0402_50V7K~D
357K_0603_1%~D
PR112 200K_0402_1%~D PH2 VOUT=Vgfx_core(1.25V)
1
1
2 1 220K_0402_5%_ERTJ0EV224J~D
<19> PWR_MON_GFX Load line:6.9mOhm
1
PC108
PR113
PR114
PC109
GNDA_VGA
L=0.42uF
2
Fsw=436KHz
2
1
2
1
PR115 D=?
PC110 3K_0402_1% PR116
B 2.2U_0603_6.3VAK~D 0_0402_5%~D
Output Ripple Current=?A
B
2
GNDA_VGA @ GNDA_VGAGNDA_VGA Output Ripple Voltage=?A*7.5mOhm=?mV
2
PR117 Input Ripple Current=TDC*(D*(1-D))^0.5=?A
1
PR118 PR119
VGFX_CORE_FB 2 1 2 1 1 2
GNDA_VGA Component select
<14> VCC_AXG_SENSE
76.8K_0402_1%~D 169K_0402_1%~D 49.9K_0603_1%~D
Input CAP 10uF_1206_25V*2
Output Cap 330U 2V Y D2 LESR7M S H1.9*2
2
PR120 @ PC111 PC112 H_MOSFET SI4682DY
0_0402_5%~D L_MOSFET SI4362DY(4.2/[email protected], 15A)
2
2200P_0402_50V7K~D 1200P_0402_50V7K~D
Inductor 0.42U_MPC0740LR42C_20A(NEC_TOKIN)
1
PR121
0_0402_5%~D
1 2 VGFX_CORE_FB
PJP25 PR122 PR123
2 1 340K_0402_1% 1K_0402_1%~D
2 1 2 1 +VGFX_SRC
PAD-OPEN1x1m
GNDA_VGA
PJP26
1
+VGFX_COREP 1 2 +VCC_GFXCORE
PC113 PC114
1000P_0402_50V7K~D 100P_0402_50V8J PAD-OPEN 4x4m
2
GNDA_VGA GNDA_VGA
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL Title
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
ADP3209_NB_core
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. 0.1
LA-4291P
Date: Friday, December 07, 2007 Sheet 44 of 49
5 4 3 2 1
+1.8VRUN/ +0.75V_DDR_VTT
DDR3 Termination
+0.75V_P
+5V_ALW
+V_DDR_MCH_REF
D 0.75Volt +/-5% D
PU8
10 3
Thermal Design Current: 0.7A
VIN VTT
+1.5V_SUS_P 2
PJP27
1 2 5
Peak current: 1A
VLDOIN VTTSNS
10U_0805_6.3V6M~D
10U_0805_6.3V6M~D
PAD-OPEN 2x2m~D 1 6
VDDQSNS VTTREF
0.1U_0603_25V7K~D
7 S3 PGND 4
2
<33> 0.75V_DDR_VTT_ON
PC115
PC116
GND 8
1
10U_0805_6.3V6M~D
0.1U_0603_25V7K~D
9 S5 BP 11
<10,34,37> DDR_ON
PC117
PJP28
1
TPS51100DGQRG4_MSOP10~D 2 1 +0.75V_DDR_VTT
2
2
1
PC118
+0.75V_P
PC119
PAD-OPEN 2x2m~D
2
DC_1+1.8V_RUN_PWR_SRC 1.8 Volt +/-5%
+3.3V_ALWP
PJP30 PC120 Design Current: 134mA
C
2 1 10U_0805_6.3V6M~D Peak current: 191mA C
PAD-OPEN 2x2m~D 2 1
+1.8V_RUNP
+3.3V_ALW
PU9
PR124 10 9
100K_0402_5%~D IN OUT
2 1 2 VCC PGND 8
1.8V_RUN_PWRGD 5 3
PGOOD AGND
10U_0805_6.3V6M~D
1U_0603_10V6K~D
7 6
1
SHDN OUTS
2
<20,21,27,33,37> RUN_ON
1U_0603_10V6K~D
PC121
PC122
4 REFIN REFOUT 1
10U_0805_6.3V6M~D
2
11
1
BP
1
PC124
2
PC123
1U_0603_10V6K~D MAX8794ETB+T_TDFN10~D
PC125
2 1
1
PR125 PR126
10K_0402_1% 91K_0402_1%~D PJP32
5V_3V_REF 1 2 1 2 +1.8V_RUNP 2 1 +1.8V_RUN
PAD-OPEN 2x2m~D
GNDA_1P8V
PGND and GND sholud be tied
together at one point near the GND Pin
PJP33
2 1
PAD-OPEN1x1m
B B
GNDA_1P8V
PU12
+3.3V_ALW PJP36
MAX8511EXK15+T_SC70-5~D
2 1 1 IN
PJP37 1.5 Volt +/-5%
+1.5V_ALW_HDA
OUT 5 2 1
Design Current: ?mA
PAD-OPEN1x1m
3 #SHDN
PAD-OPEN1x1m
Peak current: ?mA
1U_0603_10V6K~D
4
GND
NC
2
1U_0603_10V6K~D
PC186
2
1
PC187
1
A It's for layout first. A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT +1.8VRUNP/ +0.75V_DDR_VT
WWW.AliSaler.Com
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4291P
Date: Friday, December 07, 2007 Sheet 45 of 49
5 4 3 2 1
5 4 3 2 1
PD23
B340A-13-F_SMA2~D
2 1
+SDC_IN PR127 +PWR_SRC
+DC_IN discharge path 0.01_1206_1%~D CHAGER_SRC
8 1 PJP34
+DC_IN_SS
33K_0402_5%~D
0.1U_0603_25V7K~D
7 2 1 4 1 2
6 3
1
5 +DC_IN @ 2 3 PAD-OPEN 4x4m
1
PR128
PQ18
4
PC126
10K_0402_5%~D
SI4835BDY-T1-E3_SO8~D D
2200P_0402_50V7K~D
PR130 PR131
2
PR129
10K_0402_5%~D 100K_0402_5%~D
0.1U_0603_25V7K~D
2 1 2 1 3 PQ19B
1
NB_AC_OFF <33,40,47>
PC127
G NTGD4161PT1G_TSOP6~D
1
PC128
D S
2
D PQ20A D
2
10K_0402_5%~D
2 2N7002DW-7-F_SOT363-6~D
2
1
1 PQ21B @
3
3
2N7002DW-7-F_SOT363-6~D
PR132
G NTGD4161PT1G_TSOP6~D
1
PQ19A S
5
PQ20B
S
PQ22B NTGD4161PT1G_TSOP6~D
D
2 4
5 5 DOCK_DCIN_IS+ <31>
2
<47> ACAV_DOCK_SRC PQ21A
PR333 2N7002DW-7-F_SOT363-6~D NTGD4161PT1G_TSOP6~D
G
4
3
6
200K_0402_1%~D
D
2 1 2 1 5 6
DOCK_DCIN_IS- <31>
100K_0402_1%~D
100K_0402_1%~D
PQ22A
1
2 2N7002DW-7-F_SOT363-6~D PR133
1
0.1U_0603_25V7K~D
33K_0402_5%~D
0_0402_5%~D
10K_0402_5%~D
G
1
PR341
PR342
MAX8731_LDO
1
1
+SDC_IN
PR134
PR343
1
PR135
PC130
MAX8731_REF @ PC131 PC129 100K_0402_1%~D
2
0.1U_0402_10V7K~D @ 1 2 SW_GND <47>
2
0_0402_5%~D
10K_0402_1%~D
1 2 1 2
2
@
2
1
0.22U_0402_6.3V6K
PR137
PR138
PR136 PC132
365K_0402_1%~D 1U_0603_10V6K~D
28
27
1 2 GNDA_CHG
1
@ PC133 GNDA_CHG PU10
2
1U_0805_25V4Z~D
CSSP
GND
CSSN
2
PR140 2 1 22 26
49.9K_0402_1%~D DCIN VCC PR141 PR139
RB751V_SOD323~D
2 1 2 0_0603_5%~D 33_0603_1%~D
PR142 ACIN
BST 25 1 2
15.8K_0402_1%~D
SI7326DN-T1-E3_POWERPAK 1212-8
PC134 1 2 13
1
<19,34> ACAV_IN ACOK
1
0.1U_0603_25V7K~D
0_0402_5%~D
1
PD15
C C
2 1 11 VDD
PR143
PC135
5
0.01U_0402_25V7K~D 10 PC136
2
SCL
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
1U_0603_10V6K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
GNDA_CHG 9 21 MAX8731_LDO 1 2
2
+3.3V_ALW SDA LDO
1 1
1
PQ24
PC137
PC138
GNDA_CHG 14 BATSEL
PC139
PC140
Vin Detector 24 CHG_UGATE 4
DHI
3300PF_0402_50V7K~D
MAX8731_IINP 8 PR144
2
IINP
1
High 17.9 V 23 2 1 CHG_LX 2 2
PC141 LX
Low 17.24 V 6 CCV 1 1_0603_1%~D
0.1U_0402_10V7K~D @ PR145
2
3
2
1
1
1 2 5 PC142
CCI
0.01U_0402_25V7K~D 10K_0402_5%~D
PC144
200K_0402_1%~D @ PC143 @ PR146 220P_0402_50V7K~D
2 CHG_LGATE
1 2 1 2 4 20
2
CCS DLO
1
+VCHGR
0.01U_0402_25V7K~D 51P_0402_10V
GNDA_CHG 7.5K_0402_1%~D PL12 PR148
<6,26,34> CKG_SMBCLK
PR147
2000P_0402_10V @ 0.01_1206_1%~D
1
PC145
5.8UH +-30% SIL104R-5R8 5.5A~D
1.8K_1206_5%~D
SI7230DN-T1-E3_POWERPAK1212-8
MAX8731_REF 3 19 1 2 +VCHGR_L1 4
<6,26,34> CKG_SMBDAT @ PC146 REF PGND
18
2
CSIP
2
1000P_0603_50V7K~D
10U_1206_25V6M~D
10U_1206_25V6M~D
10U_1206_25V6M~D
PR150
130p_0402_10V @ @ PR149 2 3
<19> MAX8731_IINP
47P_0603_50V8J~D
1 2 1 2 7 DAC CSIN 17 1 1 1 1
0.1U_0402_10V7K~D
8.45K_0402_1%~D
0.01U_0402_25V7K~D
PC183
0_0402_5%~D
1
1
PC152
PC149
PC150
PC151
15 1 2 +VCHGR
2
FBSA
1
0.1U_0402_10V7K~D
PR152
PC153
1U_0603_10V6K~D
PC148
0_0402_5%~D
12
1 1
GND
1
1
2 2 2 2
PC155
16 PR151 4 @
2
FBSB
1
D
PC154
PC156
PC157
PQ26
29 100_0402_5%~D
2
GND
2
2.2_0805_1%~D
RHU002N06_SOT323-3~D
<19,34> ACAV_IN 2
2
PR153
G
PR340
MAX8731AETI+_TQFN28~D S
3
2
1
3
@ PC158
PQ27
1
B @ 0.22U_0402_6.3V6K~D B
Maximum charging current:1.8A
0.1U_0402_10V7K~D
PJP35 1 2
1 2
1
PC159
GNDA_CHG
PAD-OPEN1x1m Adapter Trip current PR156 PR161 PR162 PR159
2
?W ?A ? ? ? N/A @
GNDA_CHG
MAX8731_REF GNDA_CHG
+5V_ALW +3.3V_ALW
MAX8731_REF
100K_0402_5%~D
PR154 +3.3V_ALW
1M_0402_1%~D +DC_IN
1
57.6K_0402_1%~D
1 2 PR344
1
232K_0402_1%~D
47K_0402_1%~D
1M_0402_1%~D
1
PR156
PR155
100K_0402_1%~D
PR157 1 2
1
100K_0402_1%~D
PR345
PR346
MAX8731_IINP
1 2
1
0_0402_5%~D
2
PR347
+5V_ALW
2
PR158
2
GNDA_CHG ADAPT_OC <33>
2
4
8
PU11A
2
@ PR159 LM393DR_SO8~D D PR348
2 5
P
G
33.2K_0402_1%~D IN- IN+
O 1 2 O 7 1 2 ACAV_IN_NB <33,34>
0.1U_0402_25V~D
21.5K_0402_1%~D
1 2 3 G 6 0_0402_5%~D
IN+ IN-
1
G
P
10P_0402_50V8J~D
100P_0402_50V8J~D
27.4K_0402_1%~D
13K_0402_1%~D
PQ28 S PU11B
3
1
1
0.01U_0402_25V7K~D
PC160
1K_0402_5%~D
RHU002N06_SOT323-3~D LM393DR_SO8~D
8
4
1
1
100P_0402_50V8J~D
100P_0402_50V8J~D
PR161
0.01U_0402_25V7K~D
@ PR160
PC184
PR349
PC185
1
100P_0402_50V8J~D
0.01U_0402_25V7K~D
PR350
PC161
@
2
2
1
1
PC163
PC164
A A
2
2
1
1
PC162
PC165
2
<33> ADAPT_TRIP_SEL
PC166
GNDA_CHG
2
2
105_0402_1%~D
DELL CONFIDENTIAL/PROPRIETARY
2
2
1
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG
+5V_ALW GNDA_CHG GNDA_CHG GNDA_CHG
PR162
GNDA_CHG GNDA_CHG GNDA_CHG GNDA_CHG
Compal Electronics, Inc.
2
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Charger
GNDA_CHG GNDA_CHG AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
WWW.AliSaler.Com
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, December 07, 2007 Sheet 46 of 49
5 4 3 2 1
5 4 3 2 1
PD16
B540C~D
2 1
FDS6679AZ_SO8~D
PQ29
+DOCK_PWR_BAR 8 1
7 2
6 3 PQ2B
3
0.47U_0805_25V7K~D
240K_0402_5%~D
5 IMD2AT-108_SC74-6~D
+3.3V_ALW +3.3V_ALW
22K_0402_5%~D
1
D D
1
PC167
PR163
2
100K_0402_5%~D
100K_0402_5%~D
100K_0402_5%~D
PR164
4
2
1
1
PR165
PR166
PR167
2
4
2
47K_0402_1%~D
5
PQ31
NB_AC_OFF <33,40,46>
1
+3.3V_ALW2 PQ2A RHU002N06_SOT323
1
D
PR168
PQ30A IMD2AT-108_SC74-6~D 2
6
EN_DOCK_PWR_BAR <33>
100K_0402_5%~D
2 2N7002DW-7-F_SOT363-6~D G
S
3
1
1
PR169
PQ33A 1 2
2N7002DW-7-F_SOT363-6~D PQ32A
2 2N7002DW-7-F_SOT363-6~D PR170
22K_0402_5%~D
2 22K_0402_5%~D
1
PR171
2 +5V_ALW
<31,34> ACAV_DOCK_SRC#
2
1
22K_0402_5%~D
1
+3.3V_ALW2
PR172
100K_0402_5%~D
SW_GND <46>
1
C C
2
3
PR173
NB_AC_OFF_BJT <40>
PQ32B
3
5
2
2N7002DW-7-F_SOT363-6~D
ACAV_DOCK_SRC <46> PQ30B
4
5
2N7002DW-7-F_SOT363-6~D
3
4
PQ33B
5
2N7002DW-7-F_SOT363-6~D
4
PD17
B540C~D
2 1
PBATT+
FDS6679AZ_SO8~D FDS6679AZ_SO8~D
PQ25 PQ35 PQ36
FDS6679AZ_SO8~D
8 1 1 8 PBATT_PSRC 8 1 +PWR_SRC
2200P_0402_50V7K~D
0.1U_0603_25V7K~D
+VCHGR 7 2 2 7 7 2
240K_0402_5%~D
6 3 3 6 6 3
240K_0402_5%~D
5 PQ3B 5 5
1
1
PC168
PC169
IMD2AT-108_SC74-6~D
PR351
PQ38B +NBDOCK_DC_IN_SS PD18
2
PR174
2 PD19 NTGD4161PT1G_TSOP6~D 2
4
4
RB751V_SOD323~D +DC_IN_SS
1
2
+DC_IN_SS
S
B B
D
2 1 2 4 3
1
1
2
240K_0402_5%~D
RB715F_SOT323
47K_0402_1%~D
G
4
3
PR352
PR325
PQ38A
1
+3.3V_ALW NTGD4161PT1G_TSOP6~D
PD20
2
1
2
+3.3V_ALW2
100K_0402_5%~D
D
+DOCK_PWR_BAR 5 6 2 1
PR176
1
2
100K_0402_5%~D
240K_0402_5%~D
5 47K_0402_5%~D
<33> PBATT_OFF RB751V_SOD323~D
47K_0402_5%~D
PR353
G
1
1
PR326
PQ3A
1
6
PR329
PR327
33K_0402_5%~D
IMD2AT-108_SC74-6~D
2
2
PQ23A
6 1
PR175
2 2N7002DW-7-F_SOT363-6~D
2
3
47K_0402_5%~D
PQ40A
1
PQ23B 2 2N7002DW-7-F_SOT363-6~D
PR328
<33> PBATT_OFF 5
3
2N7002DW-7-F_SOT363-6~D 1
4
1
PQ40B
<31,33,40> SLICE_BAT_PRES# 5
2N7002DW-7-F_SOT363-6~D
4
1
D
2 PQ42
A G RHU002N06_SOT323 A
S
3
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT Selector
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, Size Document Number Rev
WWW.AliSaler.Com
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD 0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4291P
Date: Friday, December 07, 2007 Sheet 47 of 49
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List )
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1 30 R5C833 xx/xx/2007 Dell
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
EE-Change History 1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
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0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4291P
Date: Friday, December 07, 2007 Sheet 48 of 49
5 4 3 2 1
5 4 3 2 1
Version Change List (Power P. I. R. List )
Request
Item Page# Title Date Owner Issue Description Solution Description Rev.
D D
1
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power-Change History 1
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
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0.1
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-4291P
Date: Friday, December 07, 2007 Sheet 49 of 49
5 4 3 2 1
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