Module - 5

ARM Microcontrollers

Dr. Soumitra K Nayak

Assistant Professor
School of Electrical & Electronics Engineering
 ARM Microcontrollers

• Necessity of RISC Processor

• ARM processor fundamentals - ARM7TDMI features, Register set

• Operational Modes – ARM Core Data Flow Model

• Pipelining: ARM 3 stage Pipeline, ARM 5 stage Pipeline, Pipeline

Hazards.
 ARM : Advance RISC Machine
• Founded in 1990
– Spun out of Acorn Computers
• Designs the ARM range of RISC processor
• Licenses ARM core for Design Partners
– ARM does not fabricate Silicon on own
• Develops technology to assist with ARM Arch.
– Software Tools
– Boards | Debug Hardware | Peripherals
– Application Software | Bus Architecture
• Shipped in excess of 10 billion units since 1990.
• Over 1300 new chip designs with ARM IP in 2007
• Licensed by majority of world’s leading Semiconductor manufacturers
• At least 90 processors are shipped every second.
ARM Applications
 Why ARM
• Built in architecture extensions
 THUMB®2 - Greatly improved code density
 DSP - Signal process directly in the RISC core
 Jazelle® - Java acceleration
 Trustzone™ - Maximum Security Environment

• Core Performance
• Tools of Choice
• Wide Support
• Low Power Consumption
 ARM – Advanced RISC Processor
• Unlike CISC processors, RISC engines generally execute each instruction in a single
clock cycle, which typically results in faster execution than on a CISC processor with the
same clock speed.

• A RISC processor typically needs more memory than a CISC does to store the same
program.

• Except in the most speed-critical of embedded devices, the cost of memory is much
more critical than the execution speed of the processor.

• To reduce memory requirements and, thereby, cost, Advanced RISC Machines (ARM)
created the Thumb instruction set(16-bit) as an option for their RISC processor cores.
ARM7 Family
 ARM7TDMI
ARM7TDMI stands for:

• T: THUMB instruction

• D: On-chip Debug support, enabling the processor to halt in

response to a debug request

• M: Enhanced Multiplier, yield a full 64-bit result, high performance

• I: Embedded ICE hardware (In Circuit emulator)

 Features of ARM7TDMI
• ARM7 is a 32-bit architecture

• Data Paths and Instructions (ARM) are 32 bits wide

• Von-Neumann Architecture
– Instructions and Data use same bus

• Thumb Mode
– Subset of 16-bit instructions

– Code density optimization

 Features of ARM7TDMI
• 32-bit microprocessors.

• The ARM family offers high performance for very low-power consumption and gate count.
• The ARM7TDMI processor has a Von Neumann architecture, with a single 32-bit data bus
carrying both instructions and data.

• Only load, store, and swap instructions can access data from memory.
• The ARM7TDMI processor uses a three stage pipeline- FETCH, DECODE, EXECUTE to
increase the speed of the flow of instructions to the processor.
• This enables several operations to take place simultaneously, and the processing, and
memory systems to operate continuously. In the three-stage pipeline the instructions are
executed in three stages.
 Architectural Features of ARM7TDMIS
The typical RISC architectural features of ARM are :
• A large uniform register file
• A load/store architecture, where data-processing operations only operate on register contents,
not directly on memory contents
• Simple addressing modes, with all load/store addresses being determined from register
contents and instruction fields only uniform and fixed-length instruction fields, to simplify
instruction decode.
• Control over both the Arithmetic Logic Unit (ALU) and shifter in most data-processing
instructions to maximize the use of an ALU and a shifter
• Auto-increment and auto-decrement addressing modes to optimize program loops
• Load and Store Multiple instructions to maximize data throughput
• Conditional execution of almost all instructions to maximize execution throughput.
 Architecture of ARM7
• The ARM 7 processor has a single bus for both data and instructions
• The single bus system decreases the performance of ARM, it can overcome by the pipe line
concept.
• ARM uses the Advanced Microcontroller Bus Architecture (AMBA) bus architecture.
 This AMBA include two system buses: the AMBA High-Speed Bus (AHB) or the Advanced
System Bus (ASB), and the Advanced Peripheral Bus (APB).
• The ARM processor consists of
Arithmetic Logic Unit (32-bit)
One Booth multiplier(32-bit)
One Barrel shifter
One Control unit
Register file of 37 registers each of 32 bits.
Architecture of ARM7
 Architecture Operation
• Most of the ARM instructions typically have two source registers and a single result or
destination register. However, move, comparison and branch instructions do not support such 3-
address format.
• The source operands are read from register bank using the internal buses A and B respectively.
The second operand, which is passed to the barrel shifter through the internal bus B, is shifted.
• Then the ALU takes the registers values from the internal bus A and barrel shifter and computes
the result. The data processing instructions write the result directly to the destination register of
the register bank using the ALU bus.
• The load and store instructions use the ALU to generate an address, which is sent to the address
register using the ALU bus.
• The PC value in the address register is incremented before the next register value from or to the
next memory location is read or written. This process continues until the interrupt or exception
occurs
Barrel Shifter
 Architecture of ARM7
In addition to the 37 registers, ARM also consists of
• One Program status register of 32 bits,
• Special registers like:
instruction register,
memory data read and write register
memory address register ,
one Priority encoder which is used in the multiple load and store
instruction to indicate which register in the register file to be loaded or
stored and Multiplexers etc.
 Register in ARM7
• ARM has 37 registers all of which are 32 bits long (31 general Purpose and 6 Status
registers)
– 1 dedicated Program Counter
– 30 General Purpose Register
– 1 dedicated Current Program Status Register (CPSR)
– 5 dedicated Saved Program Status Register (SPSR)
• The current processor mode governs the access of register banks
– A particular set of r0-r12 registers
– A particular r13 (stack pointer) and r14 (link register, LR)
– The program counter (PC)
– The current program status register (CPSR)
• Privileged Mode can access
– A particular SPSR (Saved Program Status Register)
 Register in ARM7
• The Arm processor has 37 registers in total, each registers are 32 bits in size.

• These include a program counter, six program status registers and 30 general-
purpose registers.

• At any point of time, only 18 of these registers: 16 data registers and 2 processor
status registers are visible depending upon the processor mode.

• Each processor mode can use the r0-r12 general-purpose registers, r13 - stack
pointer and r14-link register, r15-the program counter and program status
register.
ARM Processor Modes
ARM Processor Modes
 Register in ARM7
• The general-purpose registers r0-r8 are available no matter which mode is
the processor.

• A few registers r8-r12 are common to all the processor modes except in
the fast interrupt request mode.

• When the processor is in the fast interrupt mode, these registers r8-r12
are replaced with different set of registers r8_q-r12_q.
 Register in ARM7
• There are two program status registers: current program status register (CPSR) and saved
program status register (SPSR).
• The SPSR can only be modified and read in the privileged mode and the CPSR is common to
all the modes.

• However, there is no SPSR available in the user mode.

• The CPSR contains the current status of the processor. It is used to monitor and control
internal operations. It is 32-bit register.

• The CPSR has four different fields with 8 bits width each. They are flags, status, extension
and control. The saved program status register contains the copy of CPSR when a processor
enters a new privileged mode.
Register Organization for Processor Modes
Processor Modes- Register Visible
Program Status Register
 Program Counter (r15)
• When the processor is executing in ARM state:
– All instructions are 32 bits wide
– All instructions must be word aligned
– Therefore the PC value is stored in bits [31:2] with bits [1:0] undefined (as
instruction cannot be halfword or byte aligned).
• When the processor is executing in Thumb state:
– All instructions are 16 bits wide
– All instructions must be halfword aligned
– Therefore the PC value is stored in bits [31:1] with bit [0] undefined (as instruction
cannot be byte aligned).
• When the processor is executing in Jazelle state:
– All instructions are 8 bits wide
– Processor performs a word access to read 4 instructions at once
 Features of ARM7TDMI
• The ARM7TDMI core uses a pipeline
– Increase the speed of the flow of instructions

– Enables several operations to take place simultaneously

– Program Counter (PC) points to instruction being fetched rather than that being
executed

• During normal pipelined operation

– An instruction x is executed

– Instruction (x-1) is being decoded

– Instruction (x-2) is being fetched

Pipelining in ARM7TDMIS
Pipelining in ARM7TDMIS
3-Stage Pipelining ARM7
3-Stage Pipelining ARM7
3-Stage Pipelining ARM7
5-Stage Pipelining
5-Stage Pipelining
5-Stage Pipelining
Pipeline Hazards
Pipeline Hazards – Structural Hazards
Pipeline Hazards – Structural Hazards
Pipeline Hazards – Structural Hazards
Pipeline Hazards – Structural Hazards
Pipeline Hazards – Data Hazards
Pipeline Hazards – Data Hazards
Pipeline Hazards – Control Hazards
Thank You