BSC EEE 3.
2 DIGITAL ELECTRONICS 2
LAB EXPERIMENT 1: TTL NAND GATE CIRCUIT STRUCTURE
Objectives:
• Be familiar with the Transistor –Transistor Logic TTL circuits.
• Studying the internal connection of a NAND gate
Transistors Pin-out:
Circuit Components/Equipment:
1. NPN silicon transistors (5 Nos.)
2. Resistors (R1=4KΩ, R2=1.4K, R3=1K, R4=130Ω 1 No.)
3. A IN 4004 Rectifier Diode
4. D.C. Power supply (5V)
5. 1 LED
6. Connecting wires
7. Breadboard
Refer the following figure to make a multi-emitter Transistor.
Notice that this circuit looks similar to those found in analogue push pull amplifiers, except
that the transistors here are driven either into cut-off or saturation, rather than working in their
linear operating condition. Also, being constructed within an IC, it can use a device not
normally found in conventional analogue amplifiers, a multi emitter transistor.
Fig. 3.2.2 shows a typical schematic for a TTL NAND gate. R1 is a low value resistor (about
4K) and as the base current of T1 is small, the base voltage is about +5V. If both emitters of
T1 are at logic 1, (also around +5V), there will be very little potential difference between base
and emitter, and T1 will be turned off. As T1 is not conducting, its collector will also be at
about 5V, and due to this high potential, T2 base will have a higher potential than its emitter,
which will cause T2 to conduct heavily and go into saturation.
T2 collector will therefore fall to a low potential, and the emitter voltage of T2 will rise due to
the current flow through R3. The voltage across R3 will rise to a sufficient level (about 0.7V) to
fully turn on T3. As T3 saturates, its collector voltage will fall to about 0.2V, thus giving a logic
0 state at the output terminal.
T4 emitter voltage is made up of T3 VCE (about 0.2V) plus the forward voltage drop across
D1, which will be about 0.7V, giving an emitter potential of 0.2V + 0.7V = 0.9V, the same as its
base voltage.
The base potential of T4 is made up of T3 base/emitter potential VBE (about 0.7V), plus the
collector/emitter, potential (VCE) of T2, (about 0.2V), giving a base voltage for T4 of about
0.9V. Therefore the base and emitter voltages on T4 are approximately equal, so T4 will be
turned off.
With BOTH input terminals are at logic 1 therefore, the output terminal will be at logic 0, the
correct operation for a NAND gate.
If either one of the inputs is taken to logic 0 however, this will make T1 conduct, as the emitter
that is at logic 0 will be at a lower voltage than that supplied to the base by R1. This will cause
T1 to saturate, taking its collector to a low potential (less than 0.8V) and as this is also
connected to T2 base T2 will turn off, making its collector voltage and T4 base voltage, rise to
very nearly +Vcc.
As virtually no current (ICE) is flowing through T2 collector/emitter circuit, practically no
voltage is developed across the emitter resistor R3, reducing T3 base voltage to 0V, and so
T3 is turned off. However, sufficient current will be flowing out of the output terminal (feeding
the next gate input circuit) to cause T4 emitter to be held at about 4.1V. This is 0.9V below
+Vcc, made up of the voltage across D1 (0.7V) plus the saturation voltage VCE of T4 (0.2V).
This places about 4V or logic 1 (between 2.4V and 5V) on the output terminal.
1. Construct the circuit shown in the Figure above, V = 5V, R1= 4K, R2=1.4K, R3=1K,
R4=100ohms
2. Find the truth table filling the following table.
Scenario 1:
VA=VB=0V VA=0, VB=5V VA=VB=5V
CALCULATED MEASURED CALCULATED MEASURED CALCULATED MEASURED
VBT1
VBT2
VBT3
VBT4
VCE1
VCE2
VCE3
VCE4
VR1
VR2
VR3
V OUT
Fill the following Truth Table:
VA VB V OUT
0V 0V
0V 5V
5V 0V
5V 5V
