UNIT II: Verilog HDL

 Introduction to Verilog, Verilog fundamentals, levels of design description

 Module representation, timing and delays in modelling, Hierarchical module
representation,
 Test bench formation in Verilog and structure of test bench file, displaying test results
 Verilog data types and operators: data types, net and variable data types, data values,
Naming a net or variable
 defining constants and parameters
 defining vectors
 arithmetic, Concatenation and replication operators
 application on data types and operators
 Verilog HDL is a hardware description language that can be used to model a digital
system at many levels of abstraction ranging from the algorithmic level to the gate-
level to the switch-level.
 The language not only defines the syntax but also defines very clear simulation
semantics for each language construct.

Design methodology:
• Based on Design Hierarchy:

 Top Down Methodology

 Bottom Up Design Methodology

Logic Value System: The common values used in modeling hardware and mapping between
the Verilog HDL values and the hardware modeling values:
Syntax of a module:

module module_name (port_list);

declarations:

reg, wire, parameter,

input, output, inout,

function, task, …..

statements:
initial statement

always statement

module instantiation

gate instantiation

UDP instantiation

Continuous assignment

endmodule
Example:

Within a module, a design can be described in the following styles:

i. Dataflow style of modeling

ii. Behavioral style of modeling
iii. Structural style of modeling
iv. Any mix of above

Bit-widths:

1. Data types: In Verilog HDL, a variable belongs to one of the two data types:
i. net data type: the size of a net is explicitly specified in a net declaration.
When no size is explicitly specified, the default size is one bit. Different
kinds that are supported for synthesis are:
wire wor wand tri supply0 sypply1

The wire net is the most commonly used net type. The wor and wand nets are
used when multiple driver resolution needs to be performed using or-logic and
and-logic. Upon synthesis, multiple drivers of such a net are connected
together by an or gate (for a wor net) and by an and gate (for a wand net).
Example:
 The tri net synthesizes just like the wire net. A supply0 net synthesizes to wire
that is permanently connected to 0 (logic-0), while a supply1 net synthesizes
to a wire that is permanently connected to 1 (logic-1)

ii. register data type: the different kinds of register types that are supported for
synthesis are: reg integer
A reg declaration explicitly specifies the size, the corresponding
number of bits of the variable in hardware.
Example: reg [1:25] a // 25-bit variable.
reg b //1-bit variable.

For an integer type the maximum size is 32 bits and the number is
assumed to be in 2’s compliment form. Optionally a synthesis
system may perform data flow analysis of the model to determine
the maximum size of an integer.
Example: wire [1:5] a, b;
integer y; --------
y = a + b; // the size of y is 6 bits, the left most bit is
the carry.
Note: the register types: real and time are not supported for synthesis.
Describing in Dataflow Style: The basic mechanism used to model a design in
the dataflow style is the continuous assignment, here a value is assigned to a
net.
Syntax of a continuous assignment:
assign [delay] LHS_net = RHS_expression;
Example: assign #2 Y = A & B; //the delay values correspond to 2ns
Continuous assignments can be explicit assignment and implicit assignment statements as
show below:

Describing in Behavioral Style: described using procedural constructs. These

are:

i. Initial statement: executes only once.

ii. Always statement: always executes in a loop, i.e., the statement is
executed repeatedly.
Only a register data type can be assigned a value in either of these
statements. Such data type retains its value until a new value is assigned.
All initial statements and always statements begin execution at time 0
concurrently.
Example: always @ ( A ^ B) ^ Cin;
There are two kinds of procedural assignment statements:
i. Blocking procedural assignment:
ii. Non-blocking procedural assignment
A procedural assignment may optionally have a delay. Delays can be
specified in two different forms:
 ‘wire’ and ‘reg’ are in unsigned-format by default. These can be used for
synthesis and simulation.
 ‘integer’ is in signed-format by default. This should be used for simulation.

Signed numbers: integer is signed number and can be defined for reg and wire by using
signed keywords

reg signed wire signed

and shown in above table.

Also, ‘signed numbers’ can be converted into ‘unsigned numbers’ using ‘$unsigned()’
keyword e.g. if ‘a = -3 (i.e. 101 in 2’s complement notation)’, then ‘$unsigned(a)’ will be ‘5
(i.e. value of 101)’. Similarly, ‘unsigned numbers’ can be converted into ‘signed numbers’
using ‘signed()’ keyword.

Verilog Operators:
Shift operators

Verilog provides 4 types of shif operators i.e. >>, <<, >>>, <<<. Let ‘a = 1011-0011’, then
we will have following results with these operators,

 a >>3 = 0001-0110 i.e. shift 3 bits to right and fill the MSB with zeros.
 a << 3 = 1001-1000 i.e. shift 3 bits to left and fill the LSB with zeros.
 a >>>3 = 1111-0110 i.e. shift 3 bits to right and fill the MSB with sign bit i.e. original
MSB.
 a <<<3 = 1111-0110 i.e. same as a<<3.

Concatenation and replication operators

Concatenation operation ‘{ }’ is used to combine smaller arrays to create a large array as

shown below,

wire[1:0] a = 2b'01;
wire[2:0] b = 3b'001;
wire[3:0] c ;
assign c = {a, b} // c = 01001 is created using a and b;
Replication operator is used to repeat certain bits as shown below,
assign c = { 2{a}, 1'b0 } // c = 01010 i.e. a is repeated two times i.e. 01-01
Verilog Test Bench:

• Once the design of a chip is completed its correctness must be verified or checked.
• A test bench is defined as a HDL code to check the correctness of a chip, that
provides the stimulus (input vectors to the design).
• Structure of Verilog Test Bench: Here the input vectors which are (stimulus) to the
DUT (Design Under Test) are applied and the output is captured by the monitor .
Steps involved in writing a Verilog testbench
1. Declare a testbench as a module.

2. Declare set signals that have to be driven to the DUT. The signals which are
connected to the input of the design can be termed as ‘driving signals’ whereas the
signals which are connected to the output of the design can be termed as
 ‘monitoring signals’. The driving signal should be of reg type because it can hold a
value and it is mainly assigned in a procedural block (initial and always blocks). The
monitoring signals should be of net (wire) type that get value driven by the DUT.
Note: The testbench signal nomenclature can be different the DUT port.

3. Instantiate top-level design and connect DUT port interface with testbench variables
or signals.

4. Use an initial block to set variable values and it can be changed after some delay
based on the requirement. The initial block execution starts at the beginning of the
simulation and updated values will be propagated to an input port of the DUT. The
initial block is also used to initialize the variables in order to avoid x propagation to
the DUT.
Example: Initialize clock and reset variables.

5. An always block can also be used to perform certain actions throughout the
simulation.
Example: Toggling a clock

6. The system task $finish is used to terminate the simulation based on the
requirement.

7. The endmodule keyword is used to complete the testbench structure .

Example: Verilog Test bench code for full adder