Data path: The path wherein data traverses is known as data path. Data path is a pure combinational path. It ean have any basic combinational gates or group of gates. 13. Explain about PD flow? Ans: INPUTS: ‘NETLIST: lib, lef, SDC It is the combination of sequential element and their logical connectivity. Netlist contains- Input and output information of the design. * Wire information. + Cell and instance information. * Module information, * Hierarchy information, * Port information, LIBRARY file: Ithas time, power and functionality of a cell Time- input delays, output delays, setup and hold Power- leakage power and internal power Cell fumetionality For eg:- (A+B)"(B+C) PVT (process voltage and temperature) conditions LEF(library exchange format) Ithas physical information of the design Two types, 3. Technology lef 4. Cell/macro let 3. Technology lef It contains metal layer and via information likeMetal layer: + Direction © Pitch * Width © Area Spacing table ‘+ Min enclosure area ‘+ Diag spacing ‘© Diag min edge length © Resistance © Capacitance © Thickness ‘+ Antenna model and antenna area ratio © DC current density: VIA information: + Spacing © Width * Antenna model * Antenna area ratio * DC current Density 4. Cell/Macro lef © Class © Origin © Size © Symmetry © Pin: © Antenna gate area © Direction © Usage © Port SDC (Synopsys design constraint > Clock definition Create clock Create virtual clock Create generated clock Create clock uncertainty > External delaysInput delays Output delays > DRV’s Max tran, max cap and max fanout > Timing path exceptions False path Multi eyele path Max delay Min delay SANITY CHECKS: 1. Library checks + Missing cell information + Missing pin information + Duplicate cells 2. Design checks + Inputs with floating’ pins Nets with tri-state drivers Nets with multiple drivers Combinational loops Empty modules + Assign statements 3. Constraint checks * All flops are clocked or not + There should not be unconstraint paths + Input and output delays FLOORPLAN: 1. Utilization factor decides the size of the block. 2. Aspect ratio gives shape of the block. 3. After utilization and aspect ratio we go for pin placement. in pin placement we have to place pins legally 4. Macros should be placed according to guidelines Place macros around chip periphery. Ifyou don’t have reasonable rationale to place the macro inside the core area, then place macros around the chip periphery. Placing a macro inside the core can invite serious consequence during routing due to a lot of detour routing, because macros are equal to a large obstacle for routing. Another advantage to placing the hard macros around the core periphery is it's easier to supply power to them, and reduces the change of IR drop problems to macros consuming high amounts of power. b, Consider connections to fixed cells when placing macros. When you decide macro position, you have to pay attention to connections to fixed elements such as I/O and perplaced macros. Place macros near their associate fixed element. Check connections by displaying flight lines in the GUL ©, Orient macros to minimize distance between pins. When you decide the orientation of macros, you also have to take account of pins positions and their connections.d. Reserve enough room around macros. For regular net routing and power grid, you have to reserve enough routing ‘space around macros. In this case estimating routing resources with precision is very important. Use the congestion map from trialRoute to identity, hot spots between macros and adjust their placement as needed. . Reduce open fields as much as possible. Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing different aspect ratio (if that option is available) can eliminate open fields. {, Reserve space for power grid. The number of power routes required can change based on power consumption. You have to estimate the power consumption and reserve ‘enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems 5. After macro placement we will place physical cells like endcap and welltap cells POWER PLANNING: Power planning is to supply power fo thé'standard cells and macros. Power pads Power rings Power stripes—> Macros Follow pins Standard cells PLACEMENT: Two stages- 1, Course placement 2, Detail placement 1. Course placement: a. First tool will place standard cells based on hierarchy b. Itwill do High fanout net synthesis ‘Adding buffers to the high fanouts . Scan chain reordering Ina less complex design, you don’t usually do scan reordering. However, sometimes it may become difficult to pass scan timing constraints once the placement is done. The scan flip flop placements may create lengthier routes if the consecutive flops in scan chain ate placed far apart due to a functional requirement. In this ease, the Pn tool can reconnect the sean chains, to make routing easier. A prerequisite for this, ‘option is a scan DEF for the tool to recognize the chains. d. Logical optimization Sizing VT swapping BufferingLogic restructuring Pin swapping Cloning Rebutfering Trail route 2. Detail placement a. Area recovery b. Congestion driven ©. Time driven PLACEMENT OPTIMIZATION: In optimization tool will optimize DRV's and setup timing Here we will not see hold because clock is ideal. Checks in placement: Cells legalization Utilization Area Timing Congestion CLOCK TREE SYNTHESIS: Before CTS we need to check: 1. All cells should be legalized. 2. All power nets are prerouted, 3. All pins should legalized. 4, Congestion, timing should control GOALS OF CTS: 1, To minimize the logical DRCs. 2. Balancing the skew. 3. Minimum Insertion Delay. INPUTS OF CTS: 1, spc 2. SPEC FILE 3. PLACE! WHATIS CTS? To distribute a clock from Clock port to Clock pin WHY CTS? To minimize skew and insertion delay to build the clock tree.Here we are generating SPEC file using clockbuffers and clock inverters. SPEC file consists of Buffers list Max skew Min and Max Insertion delay Max trans, Cap, Fanout Inverters list Clock tree leaf pin, exclude pin, stop pin Clock name 8. Clock period COMMANDS USED IN CTS: clockdesign optDesign -postTS CHECKS IN CTS: Timing numbers 1 2. Utilization numbers 3. Congestion 4, All-cells should legalize ROUTING: INPUTS: CTS database Captables GOAL: ‘We need to interconnect all the nets without leaving shots and Spacing violations. STEPS INVOLVED IN ROUTING: 1. Global Routing ‘Track Assignment 3 Detailed Routing GLOBALROUTING: Router breaks the routing portion of the design into rectangles called geells and assigns signalnets to geells.lls but docs not make The global router attempts to find shortest path through g actual connection or assign nets to specific nets and to specific track within geell TRACK ASSIGNMENT: In this step the nets are properly assigned on tracks. DETAILED ROUTING: Nanoroute follows global routing plan and lays down actual wires that connect pins to their corresponding nets. It creates shorts and opens or spacing violations rather than leaving unconnected nets. We can route detailed routing on entire design, a specified area of design on selected nets, Router runs SEARCH AND REPAIR ROUTING during detail routing. It locates shorts and opens and spacing violations so, it reroutes the effected area to eliminate violations, CHECKS: 1 Verify connectivity 2. Verify geometry 3. timing numbers 4. utilization numbers, 5. All cells should legalize 6. Congestion mands: Routedesign optDesign —postRoute 14, how will you place macros according to hierarchy? Ans: According to hierarchy communicating macros will be in same color, based on that we can place 15. if we do macro abutment, what happens? Ans: There are two cases 1, If two macros communicating only with each other we can abutment the macros 2. If the macros communicating with other cells(std cells and IO ports) then we must should provide a proper channel spacing between the macros or else we can see the routing issue 16. Can we place macros 90 and 270dergees orientation? ‘Ans: It depends on which technology you are working on. 45nm & below there are orientation requirements by foundry. Poly orientation should be same throughout the chip. So Macro poly orientation should match with the poly orientation of the standard cells 17. In power planning for rings and stripes which metal layers used and why? Ans: For rings and stripes we use top metal layers because for top metal layers we have low resistivity,