OPA

433
6
OPA336
OPA
336
OPA2
336
OPA2336
OPA4336
SBOS068C – JANUARY 1997 – REVISED JANUARY 2005

SINGLE-SUPPLY, microPower
CMOS OPERATIONAL AMPLIFIERS
microAmplifier ™ Series

FEATURES DESCRIPTION
● SINGLE-SUPPLY OPERATION OPA336 series microPower CMOS operational amplifiers
● RAIL-TO-RAIL OUTPUT (within 3mV) are designed for battery-powered applications. They
operate on a single supply with operation as low as 2.1V.
● microPOWER: IQ = 20µA/Amplifier
The output is rail-to-rail and swings to within 3mV of the
● microSIZE PACKAGES supplies with a 100kΩ load. The common-mode range
● LOW OFFSET VOLTAGE: 125µV max extends to the negative supply—ideal for single-supply
● SPECIFIED FROM VS = 2.3V to 5.5V applications. Single, dual, and quad versions have identical
specifications for maximum design flexibility.
● SINGLE, DUAL, AND QUAD VERSIONS
In addition to small size and low quiescent current
(20µA/amplifier), they feature low offset voltage
APPLICATIONS (125µV max), low input bias current (1pA), and high open-
loop gain (115dB). Dual and quad designs feature
● BATTERY-POWERED INSTRUMENTS completely independent circuitry for lowest crosstalk and
● PORTABLE DEVICES freedom from interaction.
● HIGH-IMPEDANCE APPLICATIONS OPA336 packages are the tiny SOT23-5 surface mount
● PHOTODIODE PRE-AMPS and SO-8 surface-mount. OPA2336 come in the miniature
MSOP-8 surface-mount, SO-8 surface-mount, and DIP-8
● PRECISION INTEGRATORS
packages. The OPA4336 package is the space-saving
● MEDICAL INSTRUMENTS SSOP-16 surface-mount. All are specified from
● TEST EQUIPMENT –40°C to +85°C and operate from –55°C to +125°C.
A macromodel is available for download (at www.ti.com)
OPA336 for design analysis.
Out 1 5 V+ OPA4336
V– 2
Out A 1 16 Out D
+In 3 4 –In
–In A 2 15 –In D
A D
SOT23-5 +In A 3 14 +In D
OPA336 OPA2336
V+ 4 13 V–
NC 1 8 NC Out A 1 8 V+ +In B 5 12 +In C
A B C
–In 2 7 V+ –In A 2 7 Out B –In B 6 11 –In C
+In 3 6 Output +In A 3 B 6 –In B Out B 7 10 Out C
V– 4 5 NC V– 4 5 +In B NC 8 9 NC

SO-8 DIP-8, SO-8, MSOP-8 SSOP-16

NC = No Connection NC = No Connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 1997-2005, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

www.ti.com
PACKAGE/ORDERING INFORMATION(1)
PACKAGE
DRAWING PACKAGE
PRODUCT PACKAGE-LEAD DESIGNATOR MARKING
Single
OPA336N SOT23-5 DBV A36(2)
OPA336NA SOT23-5 DBV A36(2)
OPA336NJ SOT23-5 DBV J36
OPA336U SO-8 Surface-Mount D OPA336U
OPA336UA SO-8 Surface-Mount D OPA336UA
OPA336UJ SO-8 Surface-Mount D OPA336UJ

Dual
OPA2336E MSOP-8 Surface-Mount DGK B36(2)
OPA2336EA MSOP-8 Surface-Mount DGK B36(2)
OPA2336P DIP-8 P OPA2336P
OPA2336PA DIP-8 P OPA2336PA
OPA2336U SO-8 Surface-Mount D OPA2336U
OPA2336UA SO-8 Surface-Mount D OPA2336UA

Quad
OPA4336EA SSOP-16 Surface-Mount DBQ OPA4336EA

NOTES: (1) For the most current package and ordering information, see the package option addendum at the end of this data sheet. (2) Grade will be marked on
the Reel.

ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC

Supply Voltage ................................................................................... 7.5V
Signal Input Terminals, Voltage(2) ..................... (V–) –0.3V to (V+) +0.3V
DISCHARGE SENSITIVITY
Current(2) .................................................... 10mA
Output Short-Circuit(3) .............................................................. Continuous
This integrated circuit can be damaged by ESD. Texas
Operating Temperature .................................................. –55°C to +125°C Instruments recommends that all integrated circuits be handled
Storage Temperature ..................................................... –55°C to +125°C with appropriate precautions. Failure to observe proper han-
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C
dling and installation procedures can cause damage.
ESD Rating: ESD damage can range from subtle performance degrada-
Charged Device Model, OPA336 NJ and UJ only (CDM)(4) ....... 1000V
Human Body Model (HBM)(4) ......................................................... 500V tion to complete device failure. Precision integrated circuits
Machine Model (MM)(4) .................................................................. 100V may be more susceptible to damage because very small
NOTES: (1) Stresses above these ratings may cause permanent damage. parametric changes could cause the device not to meet its
Exposure to absolute maximum conditions for extended periods may published specifications.
degrade device reliability. These are stress ratings only. Functional opera-
tion of the device at these conditions, or beyond the specified operating
conditions, is not implied. (2) Input terminals are diode-clamped to the power
supply rails. Input signals that can swing more than 0.3V beyond the supply
rails should be current-limited to 10mA or less. (3) Short-circuit to ground,
one amplifier per package. (4) OPA336 NJ and UJ have been tested to CDM
of 1000V. All other previous package versions have been tested using HBM
and MM. Results are shown.

2
OPA336, 2336, 4336
www.ti.com SBOS068C
ELECTRICAL CHARACTERISTICS: VS = 2.3V to 5.5V
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

OPA336NA, UA
OPA336N, U OPA2336EA, PA, UA
OPA2336E, P, U OPA4336EA OPA336NJ, UJ

PARAMETER CONDITION MIN TYP(1) MAX MIN TYP MAX MIN TYP MAX UNITS

OFFSET VOLTAGE
Input Offset Voltage VOS ±60 ±125 ✻ ±500 ±500 ±2500 µV
vs Temperature dVOS/dT ±1.5 ✻ ✻ µV/°C
vs Power Supply PSRR VS = 2.3V to 5.5V 25 100 ✻ ✻ ✻ ✻ ✻ µV/V
Over Temperature VS = 2.3V to 5.5V 130 ✻ ✻ ✻ µV/V
Channel Separation, dc 0.1 ✻ ✻ µV/V
INPUT BIAS CURRENT
Input Bias Current IB ±1 ±10 ✻ ✻ ✻ ✻ pA
Over Temperature ±60 ✻ ✻ pA
Input Offset Current IOS ±1 ±10 ✻ ✻ ✻ ✻ pA
NOISE
Input Voltage Noise, f = 0.1 to 10Hz 3 ✻ ✻ µVp-p
Input Voltage Noise Density, f = 1kHz en 40 ✻ ✻ nV/√Hz
Current Noise Density, f = 1kHz in 30 ✻ ✻ fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range VCM –0.2 (V+) –1 ✻ ✻ ✻ ✻ V
Common-Mode Rejection Ratio CMRR –0.2V < VCM < (V+) –1V 80 90 76 86 76 86 dB
Over Temperature –0.2V < VCM < (V+) –1V 76 74 74 dB
INPUT IMPEDANCE
Differential 1013 || 2 ✻ ✻ Ω || pF
Common-Mode 1013 || 4 ✻ ✻ Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain AOL RL = 25kΩ, 100mV < VO < (V+) – 100mV 100 115 90 ✻ 90 ✻ dB
Over Temperature RL = 25kΩ, 100mV < VO < (V+) – 100mV 100 90 90 dB
RL = 5kΩ, 500mV < VO < (V+) – 500mV 90 106 ✻ ✻ ✻ ✻ dB
Over Temperature RL = 5kΩ, 500mV < VO < (V+) – 500mV 90 ✻ ✻ dB
FREQUENCY RESPONSE
Gain-Bandwidth Product GBW VS = 5V, G = 1 100 ✻ ✻ kHz
Slew Rate SR VS = 5V, G = 1 0.03 ✻ ✻ V/µs
Overload Recovery Time VIN • G = VS 100 ✻ ✻ µs
OUTPUT
Voltage Output Swing from Rail(2) RL = 100kΩ, AOL ≥ 70dB 3 ✻ ✻ mV
RL = 25kΩ, AOL ≥ 90dB 20 100 ✻ ✻ ✻ ✻ mV
Over Temperature RL = 25kΩ, AOL ≥ 90dB 100 ✻ ✻ mV
RL = 5kΩ, AOL ≥ 90dB 70 500 ✻ ✻ ✻ ✻ mV
Over Temperature RL = 5kΩ, AOL ≥ 90dB 500 ✻ ✻ mV
Short-Circuit Current ISC ±5 ✻ ✻ mA
Capacitive Load Drive CLOAD See Text ✻ ✻ pF
POWER SUPPLY
Specified Voltage Range VS 2.3 5.5 ✻ ✻ ✻ ✻ V
Minimum Operating Voltage 2.1 ✻ ✻ V
Quiescent Current (per amplifier) IQ IO = 0 20 32 ✻ ✻ 23 38 µA
Over Temperature IO = 0 36 ✻ 42 µA
TEMPERATURE RANGE
Specified Range –40 +85 ✻ ✻ ✻ ✻ °C
Operating Range –55 +125 ✻ ✻ ✻ ✻ °C
Storage Range –55 +125 ✻ ✻ ✻ ✻ °C
Thermal Resistance θJA
SOT-23-5 Surface-Mount 200 ✻ ✻ °C/W
MSOP-8 Surface-Mount 150 ✻ °C/W
SO-8 Surface-Mount 150 ✻ ✻ °C/W
DIP-8 100 ✻ °C/W
SSOP-16 Surface-Mount 100 ✻ °C/W
DIP-14 80 ✻ °C/W

✻Specifications same as OPA2336E, P, U.

NOTES: (1) VS = +5V. (2) Output voltage swings are measured between the output and positive and negative power-supply rails.

OPA336, 2336, 4336 3

SBOS068C www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

POWER-SUPPLY and COMMON-MODE

OPEN-LOOP GAIN/PHASE vs FREQUENCY REJECTION RATIO vs FREQUENCY
100 100
CMRR
G
80 0
80

PSRR, CMRR (dB)

Voltage Gain (dB)

60 –45
60

Phase (°)
40 –90 PSRR
Φ
40
20 –135

0 –180 20

–20 0
1 10 100 1k 10k 100k 1M 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

QUIESCENT CURRENT vs SUPPLY VOLTAGE QUIESCENT CURRENT vs TEMPERATURE

30 30
Per Amplifier Per Amplifier
VS = +5V
25
Quiescent Current (µA)

Quiescent Current (µA)

25
20

20 15

10 VS = +2.3V
15
5

10 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –75 –50 –25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)

SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE SHORT-CIRCUIT CURRENT vs TEMPERATURE

±6 8

7
±5 VS = +5V
Short-Circuit Current (mA)

Short-Circuit Current (mA)

6
±4 +ISC –ISC
5

±3 4 +ISC
+ISC
3
±2
–ISC 2 VS = +2.3V –ISC
±1
1

0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 –75 –50 –25 0 25 50 75 100 125
Supply Voltage (V) Temperature (°C)

4
OPA336, 2336, 4336
www.ti.com SBOS068C
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

INPUT VOLTAGE AND CURRENT NOISE

SPECTRAL DENSITY vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY
1k 1k 150

Voltage Noise

Channel Separation (dB)

Voltage Noise (nV/√Hz)

Current Noise (fA/√Hz)

140
100 100

130

10 10 Dual and Quad devices, G = 1, all

120 channels. Quad measured channel A
to D or B to C—other combinations
Current Noise yield improved rejection.
1 110
1 10 100 1k 10k 100k 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

MAXIMUM OUTPUT VOLTAGE vs FREQUENCY AOL, CMRR, PSRR vs TEMPERATURE

6 120
AOL

5 VS = +5.5V
110

AOL, CMRR, PSRR (dB)

Output Voltage (Vp-p)

4
100

3 PSRR
VS = +2.3V 90
2 CMRR

80
1

0 70
100 1k 10k 100k –75 –50 –25 0 25 50 75 100 125
Frequency (Hz) Temperature (°C)

OFFSET VOLTAGE OFFSET VOLTAGE DRIFT MAGNITUDE

PRODUCTION DISTRIBUTION PRODUCTION DISTRIBUTION
25 25
Typical production Typical production
distribution of distribution of
20 packaged units. 20 packaged units.
Percent of Amplifiers (%)

Percent of Amplifiers (%)

15 15

10 10

5 5
0.1% 0.3% 0.2% 0.1%

0 0
–500

–400

–300

–200

–100

100

200

300

400

500

0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
3.75
4

Offset Voltage (µV) Offset Voltage Drift (µV/°C)

OPA336, 2336, 4336 5

SBOS068C www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, and RL = 25kΩ connected to VS/2, unless otherwise noted.

INPUT BIAS CURRENT

INPUT BIAS CURRENT vs TEMPERATURE vs INPUT COMMON-MODE VOLTAGE
1k 4

Input Bias Current (pA)

Input Bias Current (pA)

100 3

VS = +5V

10 2

1 1

0.1 0
–75 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5
Temperature (°C) Common-Mode Voltage (V)

OUTPUT VOLTAGE SWING vs OUTPUT CURRENT OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
5 –2.5
VS = ±2.5V
VS = +5V
4 –2.0
Sourcing –55°C Sinking
+125°C
Output Voltage (V)

Output Voltage (V)

Current +25°C Current

3 –1.5
VS = +2.3V +125°C
2 +125°C –1.0

–55°C –55°C
1 –0.5 +25°C

+25°C
0 0
0 1 2 3 4 5 6 7 8 –0 –1 –2 –3 –4 –5 –6 –7 –8
Output Current (mA) Output Current (mA)

SMALL-SIGNAL STEP RESPONSE LARGE-SIGNAL STEP RESPONSE

G = 1, CL = 200pF, VS = +5V G = 1, CL = 620pF, VS = +5V
500mV/div
20mV/div

50µs/div 200µs/div

6
OPA336, 2336, 4336
www.ti.com SBOS068C
APPLICATIONS INFORMATION Normally, input bias current is approximately 1pA. How-
ever, input voltages exceeding the power supplies can
OPA336 series op amps are fabricated on a state-of-the-art cause excessive current to flow in or out of the input pins.
0.6 micron CMOS process. They are unity-gain stable and Momentary voltages greater than the power supply can be
suitable for a wide range of general-purpose applications. tolerated as long as the current on the input pins is limited
Power-supply pins should be bypassed with 0.01µF ceramic to 10mA. This is easily accomplished with an input resis-
capacitors. OPA336 series op amps are protected against tor, as shown in Figure 2.
reverse battery voltages.

OPERATING VOLTAGE
+5V
OPA336 series op amps can operate from a +2.1V to +5.5V IOVERLOAD
single supply with excellent performance. Most behavior 10mA max
OPAx336 VOUT
remains unchanged throughout the full operating voltage
VIN
range. Parameters which vary significantly with operating 5kΩ
voltage are shown in the typical characteristics. OPA336
series op amps are fully specified for operation from +2.3V FIGURE 2. Input Current Protection for Voltages Exceeding
to +5.5V; a single limit applies over the supply range. In the Supply Voltage.
addition, many parameters are ensured over the specified
temperature range, –40°C to +85°C.
CAPACITIVE LOAD AND STABILITY
OPA336 series op amps can drive a wide range of capaci-
INPUT VOLTAGE
tive loads. However, all op amps under certain conditions
The input common-mode range of OPA336 series op amps may become unstable. Op-amp configuration, gain, and
extends from (V–) – 0.2V to (V+) – 1V. For normal load value are just a few of the factors to consider when
operation, inputs should be limited to this range. The determining stability.
absolute maximum input voltage is 300mV beyond the
When properly configured, OPA336 series op amps can
supplies. Thus, inputs greater than the input
drive approximately 10,000pF. An op amp in unity-gain
common-mode range but less than maximum input volt-
configuration is the most vulnerable to capacitive load. The
age, while not valid, will not cause any damage to the op
capacitive load reacts with the op amp’s output resistance,
amp. Furthermore, the inputs may go beyond the power
along with any additional load resistance, to create a pole in
supplies without phase inversion, as shown in Figure 1,
the response which degrades the phase margin. In unity gain,
unlike some other op amps.
OPA336 series op amps perform well with a pure capacitive
load up to about 300pF. Increasing gain enhances the
amplifier’s ability to drive loads beyond this level.
One method of improving capacitive load drive in the
6V unity-gain configuration is to insert a 50Ω to 100Ω resistor
inside the feedback loop, as shown in Figure 3. This reduces
ringing with large capacitive loads while maintaining DC
VOUT

RS
100Ω
OPAx336 VOUT
0V VIN
CL RL

FIGURE 1. No Phase Inversion with Inputs Greater than the

Power-Supply Voltage.
FIGURE 3. Series Resistor in Unity-Gain Configuration
Improves Capacitive Load Drive.

OPA336, 2336, 4336 7

SBOS068C www.ti.com
accuracy. For example, with RL = 25kΩ, OPA336 series op Direct Current (DC) error at the output; however, this error
amps perform well with capacitive loads in excess of 1000pF, may be insignificant. For instance, with RL = 100kΩ and
as shown in Figure 4. Without RS, capacitive load drive is RS = 100Ω, there is only about a 0.1% error at the output.
typically 350pF for these conditions, as shown in Figure 5. Figure 5 shows the recommended operating regions for the
OPA336. Decreasing the load resistance generally improves
capacitive load drive. Figure 5 also illustrates how stability
RS = 100Ω, Load = 2kΩ || 1000pF, VS = +5V differs depending on where the resistive load is connected.
With G = +1 and RL = 10kΩ connected to VS/2, the OPA336
can typically drive 500pF. Connecting the same load to
ground improves capacitive load drive to 1000pF.
20mV/div

10k
Operation Above Selected Gain
Curve Not Recommended

G = +2

Capacitive Load (pF)

G = +1 RL to Ground
RL to Ground

1k
50µs/div

FIGURE 4. Small-Signal Step Response Using Series Re-

sistor to Improve Capacitive Load Drive.
G = +1
RL to VS/2 VS = +5V, VO = VS/2
Alternatively, the resistor may be connected in series with 100
the output outside of the feedback loop. However, if there is 5 10 100
Resistive Load (kΩ)
a resistive load parallel to the capacitive load, it and the
series resistor create a voltage divider. This introduces a
FIGURE 5. Stability—Capacitive Load vs Resistive Load.

8
OPA336, 2336, 4336
www.ti.com SBOS068C
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

HPA00779NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA2336E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B36
& no Sb/Br)
OPA2336E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B36
& no Sb/Br)
OPA2336E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B36
& no Sb/Br)
OPA2336EA/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B36
& no Sb/Br)
OPA2336EA/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B36
& no Sb/Br)
OPA2336EA/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 B36
& no Sb/Br)
OPA2336P ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 OPA2336P
& no Sb/Br)
OPA2336PA ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 OPA2336P
& no Sb/Br) A
OPA2336U ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U
OPA2336U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U
OPA2336U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U
OPA2336UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U
A
OPA2336UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U
A
OPA2336UA/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U
A
OPA2336UG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 2336U

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA336N/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336N/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336N/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336N/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336NA/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336NA/250G4 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336NA/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336NA/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM A36
& no Sb/Br)
OPA336NJ/250 ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 J36
& no Sb/Br)
OPA336NJ/3K ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 J36
& no Sb/Br)
OPA336NJ/3KG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 J36
& no Sb/Br)
OPA336U ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR OPA
& no Sb/Br) 336U
OPA336U/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR OPA
& no Sb/Br) 336U
OPA336UA ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR OPA
& no Sb/Br) 336U
A
OPA336UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR OPA
& no Sb/Br) 336U
A
OPA4336EA/250 ACTIVE SSOP DBQ 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 4336EA
OPA4336EA/250G4 ACTIVE SSOP DBQ 16 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 4336EA

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

OPA4336EA/2K5 ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 4336EA
OPA4336EA/2K5G4 ACTIVE SSOP DBQ 16 2500 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA
& no Sb/Br) 4336EA

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA336 :

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

www.ti.com 24-Aug-2018

• Enhanced Product: OPA336-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2336E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2336E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2336EA/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2336EA/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
OPA2336U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2336UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA336N/250 SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA336N/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA336N/3K SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA336NA/250 SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA336NA/3K SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA336NA/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA336NJ/250 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
OPA336NJ/3K SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA336NJ/3K SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
OPA336U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA336UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4336EA/250 SSOP DBQ 16 250 180.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA4336EA/2K5 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2336E/250 VSSOP DGK 8 250 210.0 185.0 35.0
OPA2336E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0
OPA2336EA/250 VSSOP DGK 8 250 210.0 185.0 35.0
OPA2336EA/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0
OPA2336U/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA2336UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA336N/250 SOT-23 DBV 5 250 180.0 180.0 18.0
OPA336N/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA336N/3K SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA336NA/250 SOT-23 DBV 5 250 180.0 180.0 18.0
OPA336NA/3K SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA336NA/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA336NJ/250 SOT-23 DBV 5 250 180.0 180.0 18.0
OPA336NJ/3K SOT-23 DBV 5 3000 203.0 203.0 35.0
OPA336NJ/3K SOT-23 DBV 5 3000 180.0 180.0 18.0
OPA336U/2K5 SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Aug-2017

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA336UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
OPA4336EA/250 SSOP DBQ 16 250 210.0 185.0 35.0
OPA4336EA/2K5 SSOP DBQ 16 2500 367.0 367.0 35.0

Pack Materials-Page 3
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/E 09/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/E 09/2019

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/E 09/2019

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DBQ0016A SCALE 2.800
SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

SEATING PLANE

.228-.244 TYP
[5.80-6.19] .004 [0.1] C
A PIN 1 ID AREA
14X .0250
[0.635]
16
1

2X
.189-.197
[4.81-5.00] .175
NOTE 3 [4.45]

8
9
16X .008-.012
B .150-.157 [0.21-0.30] .069 MAX
[3.81-3.98] [1.75]
NOTE 4 .007 [0.17] C A B

.005-.010 TYP
[0.13-0.25]

SEE DETAIL A

.010
[0.25]
GAGE PLANE

.004-.010
0 -8 [0.11-0.25]
.016-.035
[0.41-0.88] DETAIL A
(.041 ) TYPICAL
[1.04]

4214846/A 03/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6] SEE
SYMM
DETAILS
1
16

16X (.016 )
[0.41]

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL
OPENING OPENING

.002 MAX .002 MIN

[0.05] [0.05]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214846/A 03/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBQ0016A SSOP - 1.75 mm max height
SHRINK SMALL-OUTLINE PACKAGE

16X (.063)
[1.6]
SYMM
1
16

16X (.016 )
[0.41]
SYMM

14X (.0250 )
[0.635] 8 9

(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X

4214846/A 03/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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