Tessent® Integrated Flow

Lab2:
IJTAG Introduction; Exercise 1

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Table of Contents
Before you Begin ...............................................................................................................................2

Lab2 – Exercise 1: IJTAG Introduction .................................................................................................4

Objectives ................................................................................................................................................ 4
Introduction ............................................................................................................................................. 4
Exercise 1: Create a Basic ICL for the PLL................................................................................................. 5
Appendix A ............................................................................................................................................... 8

Notes.................................................................................................................................................9

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Before you Begin

If this is the first time you are launching this VM (Virtual Machine), you must download and extract
the lab data as described in the "Obtaining Lab Data section below.

Whenever you are using the VM for lab exercises and are finished with your session, please use the
Caution
"Disconnect" feature of the Desktop Viewer before the VM times out to preserve the data from one
session to the next. Failure to do so will remove the VM, and its contents.

If the VM was removed, you will be presented with a new VM requiring you to follow the download
and extract process. This allows you to "refresh" the lab data so you can go through the labs again
with a new database.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables
already setup.

Obtaining Lab Data

If the flow_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the flow_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_flow_data_v2020.3_20201025.tgz.

3. In the resultant window, select the Download button, enable the Save File button, then, select the
OK button to download the file.

4. Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_flow_data_v2020.3_20201025.tgz .

5. In a terminal window, extract the files from the compressed tar file using the command:
IJTAG Introduction – Ex1 2
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tar xzvf ./tessent_flow_ data_v2020.3_20201025.tgz

You should now have a directory named flow_data in your Home directory. That directory contains all
the files you need to perform the exercises, in this learning path.

You are now ready to proceed with lab exercises.

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Lab2 – Exercise 1:
IJTAG Introduction

Objectives
Upon completing this lab, you should be able to

• Discuss primitive ICL instruments

• Use the commands required to gain access to an instrument

• Create and write out pattern sets

• Perform a basic ICL network extraction

• Retarget PDL and access instruments on the IJTAG network

Introduction
This lab is comprised of several exercises. In one exercise, you will create a basic ICL description for a
PLL and generate a PDL for the PLL ICL.

In exercises 2 and 3, you will invoke Tessent IJTAG within Tessent Shell in order to extract the ICL
network accessing the instruments, then create a pattern set to access an instrument in the IJTAG
network.

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Exercise 1: Create a Basic ICL for the PLL

In this exercise you will create a basic ICL model for a PLL. In an upcoming section, you will create a .pdl
model.

1. Change to the $FLOW_LABS/Lab2/Exercise1 directory

$ cd $FLOW_LABS/Lab2/Exercise1

2. Review the basic PLL Verilog model by opening, in a text editor of your choice, and exploring
the file design/PLL.v.
Port Input/Output Include in ICL
[7:0] CTRL Input Yes
RESET Input Yes
FB Input No
REF Input No
LOCK Output Yes
VCO Output No
VCO_X Output No

3. Open the setup_design.do file noticing that it only contains 3 commands. One which sets the
context, one which loads the PLL.v file, and one which elaborates the design and sets the
current design to PLL.

4. You will now use the short setup script to setup Tessent Shell and load the PLL.v so we can
investigate the tool view of this module.
$ tessent -shell -dofile setup_design.do \
-logfile logfiles/Lab2_ex1.log -replace

5. Query the design for modules that are currently loaded using the introspection command
get_modules.
SETUP> get_modules

Notice that even though we only read in the Verilog for the PLL, we get a long list of modules.
These are read in by default when we are in dft -rtl context. Depending on the operation, these
additional modules would be used for a "quick synthesis" of an RTL design.

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6. Query the design for instances that are currently loaded in the design
SETUP> get_instances -silent

Since the Verilog we read in was only for the PLL, and this Verilog is only a module declaration
and not functionality, there are no instances in the design.

7. Query the design for the “current” design name, noticing that {PLL} is displayed as the only the
PLL.v design loaded,
SETUP> get_current_design

8. Now query the design to report the module ports or the PLL module.
SETUP> get_ports -of_module PLL
This of course is the same information you noted from the PLL.v file.

9. In a separate terminal window

a. Navigate to the directory $FLOW_LABS/Lab2/Exercise1

$ cd $FLOW_LABS/Lab2/Exercise1

b. Open the “starter file”, PLL_template.icl, in a text editor.

c. Add the module name PLL to the appropriate position in the file

d. Using the port function keyword list is provided in Appendix A and the table in step 2, add the
Ports to the ICL file for the PLL module

The form of the port declarations is:

<func>Port <port_name> ;
Note
Where <func> describes the function of the port such a ShiftInPort and
<port_name> is the logical name you are assigning to the port.

e. Save it as PLL_Models/PLL.icl, and close the editor.

10. Verify ICL syntax by reading the newly created .icl into the Tessent Shell session.
SETUP> read_icl PLL_Models/PLL.icl -force
The -force in required since you have already issued set_current_design.

11. Elaborate the design, which will also elaborate/check the ICL.
SETUP> set_current_design PLL

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12. Correct any errors and recheck the model syntax.

Create a PDL for the PLL.icl

1. Reset the Tessent Shell context to generate IJTAG patterns.
SETUP> set_context patterns -ijtag

2. Set the design level to chip as we wish to generate the IJTAG patterns at this level.
SETUP> set_design_level chip
3. Verify that the ICL ports defined in PLL.icl are recognized in Tessent Shell.
SETUP> get_icl_ports
You should see only the port names that were defined in PLL.icl.
4. Run design rules checking to get to Analysis system mode.
SETUP> check_design_rules
5. Create a PDL pattern set.
ANALYSIS> open_pattern_set example
ANALYSIS> iWrite CTRL[0] 0b1
ANALYSIS> iApply
ANALYSIS> iWrite CTRL[1] 0b1
ANALYSIS> iWrite RESET 0b0
ANALYSIS> iApply
ANALYSIS> iRunLoop 100
ANALYSIS> iWrite RESET 0b1
ANALYSIS> iApply
ANALYSIS> close_pattern_set
ANALYSIS> write_patterns PLL_Models/PLL.pdl -pdl -replace
5. Exit the Tessent Shell session.
ANALYSIS> exit
6. Review the patterns you just generated.
There is a correct and working PLL.icl model in the solutions directory.

This is the end of Exercise 1.

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Appendix A
ICL Port Keywords

Input Port Functions Output Port Functions

ScanInPort ReadEnPort

ShiftEnPort ScanOutPort

CaptureEnPort DataOutPort

UpdateEnPort ToShiftEnPort

DataInPort ToUpdateEnPort

SelectPort CaptureEnPort

ResetPort ToSelectPort

TmsPort ToResetPort

TckPort ToTckPort

ClockPort ToTmsPort

TrstPort ToClockPort

AddressPort ToTrstPort

WriteEnPort ToIRSelectPort

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Notes

IJTAG Introduction – Ex1 9