electronics

Article
Switching Capacitor Filter with Multiple Functions, Adjustable
Bandwidth in the Range of 5 Hz–10 kHz
Fan He 1,2 , Yubo Yuan 2 , Jinjin Xiao 3, *, Zehao Han 3 , Yingchun Fu 2 and Shuilong Huang 3

1 Beijing Smart-Chip Microelectronics Technology Co., Ltd., Beijing 100192, China; [email protected]
2 Zhongguancun Xin Hai Ze You Technology Co., Ltd., Beijing 100094, China;
[email protected] (Y.Y.); [email protected] (Y.F.)
3 Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China; [email protected] (Z.H.);
[email protected] (S.H.)
* Correspondence: [email protected]

Abstract: This article proposes a second-order switch-capacitor filter that integrates low-pass, high-
pass, band-pass, band-stop, and all-pass, and achieves flexible bandwidth adjustment of the filter
through clock rate and capacitance ratio. The final filter design consists of two completely inde-
pendent second-order switch-capacitor filter channels, and a 4-order Butterworth low-pass filter
is designed through two-stage cascades. The two completely independent second-order switch-
capacitor filters are integrated on a single chip and manufactured using the Huahong BCD350GE
high-voltage 24 V process. The measurement results indicate that the proposed switch-capacitor filter
achieves various functional filtering characteristics and achieves a bandwidth of 5 Hz to 10 kHz. The
chip area is 5.1 × 3.1 mm2 , powered by a dual power supply of ± 5 V, and the power consumption is
80 mW.

Keywords: switch-capacitor; second-order filter; rate; bandwidth; dual power

1. Introduction
Citation: He, F.; Yuan, Y.; Xiao, J.;
Han, Z.; Fu, Y.; Huang, S. Switching In wireless communication systems, filters are essential to obtain accurate signals. The
Capacitor Filter with Multiple multiple standardization of today’s communication protocols makes the filter operating
Functions, Adjustable Bandwidth in frequency band no longer monolithic, and considering compatibility, filters are required to
the Range of 5 Hz–10 kHz. Electronics achieve the filtering of harmful signals in different frequency ranges, so the bandwidth of
2023, 12, 4862. https://doi.org/ the filter needs to be adjustable [1,2]. Currently, continuous-time analog filters often use an
10.3390/electronics12234862 active resistor–capacitor structure, which is mainly composed of operational amplifiers,
resistors R, and capacitors C, and can be applied to higher frequencies [3,4]. But in modern
Academic Editor: Costas
Psychalinos
integrated circuit processes, the absolute values of resistors and capacitors are not precise
enough, and there is a large absolute tolerance value, which limits the processing of high-
Received: 10 October 2023 precision analog signals. However, a switch-capacitor is used to simulate and replace the
Revised: 27 November 2023 resistor so that the ratio of the capacitance is directly related to the accuracy of the signal,
Accepted: 28 November 2023 where the relative error between two capacitors can be minimized in a standard CMOS
Published: 1 December 2023
process [5]. Moreover, considering the area of the silicon wafer, a small capacitor can be
simulated and replace a large resistance resistor, which can save a lot of area. Therefore,
the analog filter implemented in the form of switch-capacitor can achieve the advantages
Copyright: © 2023 by the authors.
of low power consumption, high accuracy, and small area [6–8]. At the same time, switch-
Licensee MDPI, Basel, Switzerland. capacitor filters also offer programmability options, making it possible to achieve modular
This article is an open access article and flexible architectures [9]. References [10–13] describe the design of switch-capacitor
distributed under the terms and filters, but only the filtering characteristics of a certain function are designed separately, the
conditions of the Creative Commons range of applications is limited, and the bandwidth is not adjustable. References [14–16]
Attribution (CC BY) license (https:// describe the design with an adjustable bandwidth, but the range of adjustment is limited.
creativecommons.org/licenses/by/ In this paper, a second-order switch-capacitor filter based on the relationship between the
4.0/). transfer function characteristics of each function filter is designed by using switch-capacitor

Electronics 2023, 12, 4862. https://doi.org/10.3390/electronics12234862 https://www.mdpi.com/journal/electronics

Electronics 2023, 12, 4862 2 of 27

technology, which integrates low-pass, high-pass, band-pass, band-stop, and all-pass. The
programmable capacitance ratio method can flexibly adjust the bandwidth over a wide
range and achieve different quality factor Q values. The second-order filter can be cascaded
to form a higher-order filter.
The rest of this article is organized as follows: In Section 2, a second-order filter struc-
ture that integrates low-pass, high-pass, band-pass, band-stop, and all-pass is constructed
based on the transfer functions of each power filter. Section 3 provides a specific design
for the internal circuit and achieves adjustable bandwidth and Q value design. Section 4
completes the design of the fourth-order Butterworth low-pass filter by cascading the
designed second-order filter. Section 5 completes the chip testing results. Sections 6 and 7
provide discussions and conclusions, respectively.

2. Circuit Structure
Starting from the theory of standard response of second-order filters, we study the
response of second-order filters. It is not only important for the design of second-order
filters, but also a fundamental requirement for designing high-order filters. Among all
filtering function functions, the second-order filter response can be written as follows:

N (s)
H (s) = 2
(1)
(s/ω0 ) + 2ζ (s/ω0 ) + 1

In the equation, N (s) determines the functional characteristics of the filter, which is a
polynomial of order 2 or less, ω0 is the undamped natural frequency, and ζ is the damping
coefficient. From the denominator of the above equation, it can be seen that this transfer
function has two poles related to ζ:
 q 
p1,2 = −ζ ± ζ 2 − 1 ω0 (2)

When ζ > 1, the poles are two negative real poles, and the natural response of the
system consists of two decaying exponential terms. The system is stable and is referred to
as overdamping. When 0 < ζ < 1, a pair of conjugate negative poles will be generated, and
the natural response of the system consists of a decaying sine term. The system is stable
and is called underdamped. When ζ = 0, the poles appear on the imaginary axis, and the
natural response of the system consists of a constant amplitude with a frequency of ω0 sine
term. When ζ < 0, a pole appears in the right half plane, and the natural response of the
system reveals that the system is unstable. Therefore, in filter design, we must ensure that
ζ > 0 to ensure the stability of the filter system.
The transfer functions of the second-order low-pass, band-pass, high-pass, band-stop,
and all-pass filters in the s-domain are as follows:
low-pass:
H0
Hl p (s) = 2 (3)
s 1 s
ω 2 + Q ω0 + 1
0

band-pass:
H0 ωs0 Q
1
Hbp (s) = (4)
S2 1 S
ω02
+ Q ω0 + 1

high-pass:
2
H0 ωs 2
0
Hhp (s) = (5)
s2 1 s
ω02
+ Q ω0 +1
Electronics 2023, 12, 4862 3 of 27

band-stop:  
s2 ωz2
H0 ω02
+ ω02
Hnp (s) = (6)
s2 1 s
ω02
+ Q ω0 +1

all-pass:  
s2 1 s
H0 ω02
− Q ω0 +1
Hap (s) = (7)
s2 1 s
ω02
+ Q ω0 +1

where H0 is the DC gain, ω0 is the cutoff frequency (the center frequency of the band-pass
and the band-stop filter), also known as the −3 dB frequency, Q is the quality factor of the
filter, and ωz is a zero introduced by the band-stop filter. According to the relationship of
ωz and ω0 , band-stop filters can be divided into three types: standard band-stop, low-pass
band-stop, and high-pass band-stop. If the zero frequency is the same as the pole frequency,
it is a standard band-stop. If the zero frequency is greater than the pole frequency, it
is a low-pass band-stop. If the zero frequency is less than the pole frequency, it is a
high-pass band-stop.
From the above Formulas (3)–(7), it can be seen that their denominator contains the
2nd term of the complex frequency s, and an integrator circuit unit can generate the 1st
term of the complex frequency s, as well as the 1st term circuit of s containing the value
of Q. Therefore, the filter must contain two integrator circuits and arithmetic operation
circuits. And the integrator circuits need to be connected in series to form the 2nd term
of s. From the molecular point of view, the simplest is the low-pass filter, the DC gain
is extracted beyond the fractional equation, and the molecular term is only 1. From the
comparison of Equations (3) and (4), Hbp = Hl p × ωs0 Q1 , it can be seen that the transfer
function of the integrator circuit is ωs0 , which is the inverse function of the above equation,
so the low-pass can be realized by the band-pass output and then through the integrator
circuit. And the input signal and Q1 of the band-pass signals attenuated are summed up,
then standard band-stop filter can be realized, as shown in Figure 1.

Vbp

1/Q ʃ ω0/s ʃ ω0/s

Vlp
∑
−
+
Vnp
−1

+
∑

Vin

Figure 1. Structure of second-order filters (low-pass, band-pass, and standard band-stop).

The corresponding s-domain transfer function is:

low-pass:
Vl p 1
= − s2 (8)
Vi 2 +
1 s
+1 ω0 Q ω0
Electronics 2023, 12, 4862 4 of 27

band-pass:
s
Vbp ω0
=− s2
(9)
Vi + 1 s
+1
ω02 Q ω0

band-stop (standard type):

s2
Vnp ω0 2
+1
=− 2 (10)
Vi s
+ Q1 ωs0 + 1
ω02

According to Formulas (5)–(7), it can be seen that the high-pass band-stop, high-pass,
and all-pass filtered outputs can also be obtained through arithmetic operations on the
low-pass and band-pass outputs, and their structures are shown in Figures 2a, 2b and 2c,
respectively.

Vbp Vbp Vbp

1/Q ʃ ω0/s ʃ ω0/s 1/Q ʃ ω0/s ʃ ω0/s 1/Q ʃ ω0/s ʃ ω0/s

Vlp
∑ Vlp ∑ ∑
− − −
+ + +
Vnp Vhp Vap

−1 −1 −1

+ + Vlp +
∑ ∑ ∑
+ + +
+ + +
Vin Vin Vin
(a) (b) (c)

Figure 2. Structure of second-order filters: (a) high-pass band-stop, (b) high-pass, (c) all-pass.

In Figure 2a, its corresponding s-domain transfer function is:

low-pass:
1
Vl p 2
= − s2 (11)
Vi 2 +
1 √s
+1
2ω0 Q 2ω0

band-pass:
1 s
Vbp 2 ω0
=− s2
(12)
Vi + 1 √s
+1
2ω02 Q 2ω0

band-stop (high-pass type):

1 s2
Vnp 2 ( ω0 2 + 1)
= s2
(13)
Vi + 1 √s
+1
2ω02 Q 2ω0

In Figure 2b, its corresponding s-domain transfer function is:

low-pass:
Vl p 1
= − s2 (14)
Vi 2 +
1 s
+1 ω0 Q ω0
Electronics 2023, 12, 4862 5 of 27

band-pass:
s
Vbp ω0
=− s2
(15)
Vi + 1 s
+1
ω02 Q ω0

high-pass:
s2
Vhp ω0 2
= s2
(16)
Vi + 1 s
+1
ω02 Q ω0

In Figure 2c, its corresponding s-domain transfer function is:

low-pass:
Vl p 2
= − s2 (17)
Vi 2 +
1 s
+1
ω0 Q ω0

band-pass:
Vbp 2 ωs0
=− s2
(18)
Vi + 1 s
+1
ω02 Q ω0

all-pass:
s 2
Vap ω0 2
− Q1 ωs0 + 1
= − s2 (19)
Vi 2 +
1 s
+1
ω0 Q ω0

In order to save area, this article adopts the method of introducing taps at different
positions in the same filter loop to achieve low-pass, high-pass, band-pass, band-stop, and
all-pass filtering functions. The overall architecture is shown in Figure 3, where the module
mode select is controlled by the two bit control words M0 and M1 to control the conduction
states of switches S1, S2, and S3. The corresponding relationships are shown in Table 1,
and the four operating modes, mode 1, mode 2, mode 3, and mode 4, correspond to the
four filtering structures mentioned above. Compared
√ to mode 1, mode 2 achieves the same
functionality, but the Q value in mode 2 is 2 that in mode 1, which improves the quality
factor and has a wider range of adaptation. The dashed boxes in Figure 3 represent the
bandwidth and quality factor Q adjustment sections, respectively.

NP/HP/AP

Width adjust
S1
SCN
BP

−
IN SCN − +
∑ ʃ ʃ LP
+
−

S1 S2 S3 S2

MODE
SELECT SCN

S3
M0 M1 SCN

Q adjust Q0～Q6 F0～F5

Figure 3. Overall structure of second-order filter.

Electronics 2023, 12, 4862 6 of 27

Table 1. Working mode selection.

M1, M0 S3, S2, S1 Mode Functions

00 000 mode 1 low-pass, band-pass, band-stop (standard)
01 100 mode 2 low-pass, band-pass, band-stop (high pass)
10 110 mode 3 low-pass, band-pass, high-pass
11 001 mode 4 low-pass, band-pass, all-pass

In order to achieve the fast simulation speed of AC characteristics and easy observation
of impact response in transient simulation, the overall architecture adopts active RC mode
for the switch-capacitor module SCN and integrator module, and then replaces resistors
with capacitors. In the circuit, all devices adopt an ideal model without parasitic parameters,
and the operational amplifier gain is set to 100 dB without bandwidth limitation. The
corresponding simulation results under the four operating modes are shown in Figure 4.
From the simulation results, it can be seen that this structure can fully achieve low-pass,
high-pass, band-pass, band-stop, and all-pass filter functions.

(a) (b)

(c) (d)

Figure 4. Simulation results: (a) working mode 1, (b) working mode 2, (c) working mode 3, (d) work-
ing mode 4.

3. Circuit Design
3.1. Switching Capacitance of Analog Resistors
Figure 5 shows the most common parallel switch-capacitor structure, which consists
of two independent voltage sources V1 and V2, two controlled switches S1 and S2, and
capacitor C [17]. This structure is simple and flexible in application, but there are various
parasitic capacitors in the capacitors manufactured by CMOS technology. Among them, the
Electronics 2023, 12, 4862 7 of 27

parasitic capacitance Ctp between the top plate and ground and the parasitic capacitance
Cbp between the bottom plate and ground are the most difficult to handle, which can
significantly affect the sampling accuracy and circuit performance [18–20]. In order to
reduce this impact, a new structure has been designed based on the above structure, which
is insensitive to parasitic capacitance. The circuit structure is shown in Figure 6, and
two sets of controlled switches S3 and S4 have been added. Then, four sets of controlled
switches are composed of two non-overlapping clocks φ1 and φ2 controls, with a clock
frequency of f clk .

ϕ1 ϕ2
V1 V2

S1 S2

Figure 5. Structure of parallel switch-capacitors.

ϕ1 C ϕ2
S1 S2
+ +

V1 S4 S3 V2

ϕ2 ϕ1

- -

Figure 6. Switch-capacitor structure insensitive to parasitic capacitance.

At that time, the clock φ1 is at a high level, switches S1 and S3 are on, S2 and S4 are off,
and C is charged to V1. At that time, the clock φ2 is at a high level, switches S2 and S4 are
on, S1 and S3 are off, and C is discharged to V2. This results in an average current of:

∆q C (V1 − V2)
I= = (20)
T T
According to Ohm’s theorem, the equivalent resistance between V1 and V2 is:

V1 − V2 1
Req = = (21)
I C f clk

If the clock frequency f clk is 200 kHz, simulating a large resistor with a resistance
value of 10 MΩ requires a capacitance value of 0.5 pF and consumes only 1% of the area of
the silicon formed resistor made by the standard CMOS process [21]. In addition, filters
implemented using switch-capacitor technology have higher accuracy than traditional RC
structure filters, where the time constant is:

τ = RCF (22)

Therefore, the error of the time constant comes from the error of the capacitance and re-
sistance values during the chip manufacturing process. As the manufacturing process is
separate, the error generated by the capacitance and resistance during the chip manufac-
Electronics 2023, 12, 4862 8 of 27

turing process can be calculated separately. Below, we will calculate the error of the time
constant caused by the resistance and capacitance separately as follows:

dτ d( RCF ) dR dCF
= = + (23)
τ ( RCF ) R CF

Under existing process conditions, the error in the capacitance and resistance values
brought about during the chip casting process can be controlled below 10%. However,
for the overall filter circuit, there may be a 20% error in the process production process,
which is unbearable for many application systems. When using switch-capacitor simulation
resistance technology, the time constant τ can be expressed as:

CF
τ = RCF = (24)
C I f clk

Therefore, its error can be calculated as:

   
T CF
dτ d CI C F dT dC dC d CI
=   = + F− I ≈   (25)
τ T
C T C F C I C F
CI F CI

From the above equation, it can be seen that the precision of the time constant τ
depends on the clock cycle and the matching degree of the two capacitors. In the existing
process environment, the error of the crystal oscillator clock can be controlled within 0.001%,
then dT
T = 0. Hence, compared to traditional active filters, the error of the time constant of
switch-capacitor filters is only affected by the ratio of the two capacitors [22–24]. Under
existing process conditions, the relative error caused by manufacturing two capacitors with
precise ratios is very small, not exceeding 0.05%. Switching capacitor technology greatly
optimizes the accuracy of the filter.

3.2. Switch-Capacitor Integrator

The switch-capacitor integrator adopts a switch-capacitor structure that is not sensitive
to parasitic capacitance [25,26], as shown in Figure 7. In order to facilitate the analysis of
the impact of parasitic capacitance, parasitic capacitance has been added to the figure. The
clock timing diagram of two non-overlapping phases is shown in Figure 8.

CF

CI
clk1d clk2
S3 −
Vin S1 Vout

+
S4 S2
clk2d CA CB clk1

Figure 7. Switch-capacitor integrator with parasitics.

Electronics 2023, 12, 4862 9 of 27

clk1

clk1d

clk2

clk2d

Figure 8. Two-phase non-interleaved clock timing diagram.

In Figure 7, C A and CB are the parasitic capacitances of the sampling capacitor C I at

the upper and lower plates A and B, respectively. The clock signals clk1, clk2, and their
respective delay signals clk1d and clk2d control different switches. The two phases are as
follows:
(1) Sampling phase. From the timing diagram, it can be seen that the arrival of clk1 causes
the S2 switch to close first, causing a short circuit at both ends of the parasitic capacitor
CB . The charge on it is cleared, and then S1 closes. The input signal Vin charges the
C I until clk1 flips to 0. S2 first opens, and point B is suspended. The charge stored at
point B will not lose or change, and then switch S1 opens. The injection effect caused
by switch S1 will not cause any change in the integral charge.
(2) Integration stage. From the timing diagram, it can also be seen that the switch S3
controlled by clk2 is first closed. Due to the virtual short circuit of the ideal operational
amplifier (i.e., the closed-loop feedback of the operational amplifier), the parasitic
capacitance CB is shorted at both ends, and the charge only exists at the left end of C I .
When S4 is closed, C A is shorted, the virtual short circuit of the operational amplifier
causes the C I to be shorted as well. The charge at the A end is discharged to the
ground, and the charge at the B end is fully forced to the integrating capacitor CF ,
thus this realizes integration operation. In the final stage, S3 is disconnected first, so
that the injection effect caused by the disconnection of the previous stage S4 does not
change the integration result [27].

3.3. Switch Circuit

During the operation of MOS switches, there are three mechanisms that generate
corresponding errors, namely, channel charge injection, clock feedthrough, and switch
thermal noise. They will generate gain errors, DC offset, and nonlinear errors to varying
degrees. Below, we will discuss these error factors separately and then complete the design
of the switch circuit based on the analysis.

3.3.1. Switch Error

When the MOS switch is on, Vin charges the sampling capacitor to make Vin = Vout ,
and after charging is completed, there is still an inversion layer charge in the channel. After
the switch is disconnected, this part of the charge will be randomly injected into the source
and drain stages. Taking NMOS as an example, as shown in Figure 9, this will make the
charge on the sampling capacitor CH not equal to Vin CH . The amount of charge in the
channel is:
Qch = W LCox (VDD − Vin − VTH ) (26)
Electronics 2023, 12, 4862 10 of 27

CLK

Vin Vout
Q
CH

Figure 9. Channel injection effect.

If channel charges are uniformly injected into the source and drain electrodes, a bias
voltage difference of 4V is generated on the sampling capacitor CH :

W LCox (VDD − Vin − VTH )

4V = (27)
2CH

This voltage error will cause a negative step in the voltage drop across the sampling
capacitor CH . Similarly, if the switch is PMOS, the output voltage drop will have a positive
step. The steps of these two voltage drops are exactly opposite, so the design of the
switching circuit utilizes this to improve the consequences of channel charge injection effect.
Due to the difficulty in determining the distribution of channel charge Qch between
the source and drain terminals, considering the worst-case condition where all channel
charges are injected into the sampling capacitor CH , the final result of Vout is:

W LCox (VDD − Vin − VTH )

 
W LCox W LCox
Vout = Vin − = Vin 1 + − (VDD − VTH ) (28)
CH CH CH
The above equation indicates that the channel charge injection effect can bring both gain
error and DC offset [28]. According to the above formula, we can reduce the deviation of the
output voltage by reducing the size of the MOS transistor switch or increasing the sampling
capacitor CH . However, both of these methods will slow down the circuit speed and cause
greater performance damage in high-frequency operating environments. Therefore, we
cannot use this method to reduce the channel charge injection effect.
The second error caused by the switch is clock feedthrough. Due to the presence of
gate source and gate drain capacitors in MOS switches, when the clock flips, these two
capacitors will also transfer the charges stored on them to the sampling capacitor, resulting
in sampling error, as shown in Figure 10.

CLK

Vin Vout
M1

CH

Figure 10. Clock feedthrough effect.

The error caused by clock feedthrough can be expressed as:

WCOV
4V = VCK (29)
WCOV + CH
Electronics 2023, 12, 4862 11 of 27

Among them, COV is the unit overlap area capacitance at the gate source interface or the
gate drain interface, and VCK is the clock pulse voltage. From the above equation, it can be
seen that reducing the width of MOS switches can weaken the impact of clock feedthrough
effect, but this also reduces the switching speed.
The third error caused by a switch is the thermal noise of the switch. As long as there is
a resistance in the circuit, thermal noise will be generated, and the switch has a conducting
resistance. During the sampling and integration stages, thermal noise can have an impact,
which can affect the output voltage. However, the magnitude of the noise is not related to
the switch conduction resistance value, but rather to the position of the noise generating
module. The closer to the input port, the greater the noise, so the sampling capacitance
should be larger. However, this directly affects the area of the chip capacitance.

3.3.2. Switch-Circuit Design

In the above three mechanisms, except for the third type of thermal noise, the other
two types of error are directly related to the size of the switch MOS. The smaller the size
of the switch MOS, the smaller the error caused. So usually, the length is chosen to be
close to the minimum size of the process. To ensure a certain speed, the width is chosen
to be several to several tens of times the length. In CMOS switches, due to the opposite
channel charges between PMOS and NMOS transistors, this can compensate for most of
the errors caused by channel charge injection. At the same time, the conduction switches of
PMOS and NMOS transistors complement each other, and the clock feedthrough effect can
also be mutually suppressed. If PMOS and NMOS choose the same size, the errors caused
by channel charge injection and clock feedthrough can completely cancel each other in
the first-order approximation. That is to say, CMOS switch transistors can provide higher
accuracy than single MOS transistors. Meanwhile, due to the fact that CMOS switches
connect two single MOS switches in parallel, the conduction resistance of CMOS switches
is smaller than that of single MOS switches, and its conduction resistance should also be
small as the input signal changes. Therefore, the switch circuit adopts a transmission gate
switch, and its circuit structure is shown in Figure 11.

CLK

M2
Vin Vout
M1

CLKN
Figure 11. Transmission gate switch.

According to the derivation in Section 3.3.1, NMOS and PMOS transistors will generate
two steps with opposite polarity directions. To eliminate the steps, the parameters of NMOS
and PMOS transistors in the transmission gate must meet the following equation:

W1 L1 Cox (VCK − Vin − VTHN ) = W2 L2 Cox (Vin − |VTHP |) (30)

By optimizing and adjusting the size of NMOS and PMOS transistors, the steps brought by
switch sampling are minimized. Figure 12 shows the steps brought by the NMOS transistor
switch, Figure 13 shows the steps brought by the PMOS transistor switch, and Figure 14
shows the steps brought by the transmission gate switch.
Electronics 2023, 12, 4862 12 of 27

Figure 12. Steps brought by NMOS transistor switches.

Figure 13. Steps brought by PMOS transistor switches.

Electronics 2023, 12, 4862 13 of 27

Figure 14. Steps brought by the transmission gate switch.

From the above figure, it can be seen that the negative step size brought by the NMOS
transistor switch is 33.96 mV, the positive step size brought by the PMOS transistor switch
is 32.32 mV, and the step size brought by the complementary use of the transfer gate switch
is 4.07 mV, greatly reducing the impact of the switch channel charge injection effect on the
overall circuit.

3.4. Operational Amplifier

In previous system architectures and simulations, operational amplifiers were consid-
ered an ideal component. In practical situations, operational amplifiers are not ideal. Thus,
it is necessary for us to analyze the impact of some non-ideal characteristics of operational
amplifiers on switch-capacitor filters [29] in order to help us obtain reasonable design
indicators for operational amplifiers and guide design.

3.4.1. The Impact of Limited DC Gain

The most basic unit of a cascaded switch-capacitor filter is a switch-capacitor integrator.
Figure 7 shows a parasitic capacitor insensitive inverse integrator. The limited DC gain
of the operational amplifier is A0 , and the most direct impact to the integrator is that the
potential at the inverting input end of the operational amplifier is no longer zero, but
−Vout /A0 , which is related to the output signal.
Considering VX =−Vout /A0 , the calculated transfer function is:
   
H e jωT = [1 + m(ω )]e jθ (ω ) · H0 e jωT (31)

Among them, H0 e jωT is the integrator transfer function for ideal operational amplifiers,

m(ω ) and θ (ω ) represent the amplitude error and phase error, respectively. We assume
that m(ω )  1, θ (ω )  1, ωT  1, then near the cutoff frequency there are:
 
1 C 1
m(ω ) ≈ − 1+ I ≈− (32)
A0 2CF A0

1 C I /CF 1
θ (ω ) ≈ ≈ (33)
A0 ωT A0
Electronics 2023, 12, 4862 14 of 27

Among them, the amplitude error m(ω ) can be directly equivalent to the ratio error of
capacitance C I and CF . For an integrating circuit with an operational amplifier gain
A0 = 1000, the amplitude error is 0.1%, which is on the same order of magnitude as the
capacitance mismatch, so the amplitude error can be ignored. However, phase error is
not the case, as it can affect the pole position of the integrator, thereby affecting the pole
distribution of the filter. Phase error will affect the center frequency of the filter ω0 and
quality factor Q. When the operational amplifier gain A0 = 1000, the impact of phase error
on the center frequency can be ignored, while the impact on the quality factor Q is not the
same. The quality factor Q when considering the finite gain of the operational amplifier
is approximately related to the quality factor Q0 when considering the ideal operational
amplifier, as follows:
1 1 2
= + (34)
Q Q0 A0
For filters with higher Q values, this impact cannot be ignored. Assuming Q0 = 20 and
A0 = 1000, we can calculate Q =19.2, which is a relatively large error. We may be able to
increase the DC gain of the operational amplifier a bit. When A0 = 10,000, Q = 19.92 can be
calculated, which is a relatively satisfactory result. Therefore, in our subsequent design, de-
signing the DC gain of the operational amplifier to be above 80 dB is a reasonable indicator.

3.4.2. The Impact of Limited Unit Gain Bandwidth

We still analyze the impact of limited unit gain bandwidth from the perspective of
integrators. Firstly, similar to limited DC gain, a limited unit gain bandwidth can bring
amplitude error m(ω ) and phase error θ (ω ) to the transfer function of the integrator. Here,
we directly cite the conclusions of the literature, and in the worst-case scenario:
   
ωGB T π f GB
|m(ω )| ≈ |θ (ω )| ≈ ω Texp − = ω Texp − (35)
2 fc

Among them, ω is the angular frequency of the signal, f GB is the unit gain bandwidth of the
operational amplifier, and f c is the clock frequency. When f GB ≥ 5 f c , the error is already
much less than one-thousandth. From this perspective, f GB ≥ 5 f c is sufficient.
Another more important impact of limited unit gain bandwidth is speed, which
directly affects the linear establishment speed of small signals. For a single pole operational
amplifier, considering the finite unit gain bandwidth, its open-loop transfer function is:

− A0
H (s) = (36)
1 + 1/ω1

ω1 is the main pole of the operational amplifier. After being connected into a closed loop,
the step response of the output voltage is established in exponential form:

−t
 
Vout = 1 − exp (37)
τ

The time constant τ directly affects the establishment speed, and the expression is:

1 1
τ= = (38)
βωGB 2πβ f GB

Among β = CF /(C I + CF ) is the feedback coefficient (in switched-capacitor filters, the

integral capacitor CF is often much larger than the switching capacitor C I , and the feedback
coefficient is close to 1). In our design, β has a minimum of approximately 0.8. For a 0.1%
small signal establishment accuracy, the required establishment time tset is approximately
Electronics 2023, 12, 4862 15 of 27

7τ. We hope that tset cannot exceed half of the clock cycle T; perhaps tset = T/3 is a good
choice, which is 7τ = T/3. Bringing it into Equation (38) and selecting β = 0.8 can obtain:

21
T = 21τ = (39)
0.8 ∗ 2π ∗ f GB

It can be concluded that:

21
f GB = ≈ 4.2 f c (40)
0.8 ∗ 2π ∗ T
Therefore, considering both accuracy and speed, the unit gain bandwidth of the
operational amplifier needs to meet f GB ≥ 5 f c . However, due to the presence of parasitic
capacitance, the feedback coefficient of the integrator β becomes less than 0.8, the unit
gain bandwidth of the operational amplifier also needs to be correspondingly increased to
meet the requirements of establishment speed. These are relative to single pole operational
amplifiers, and in practice we may use two-stage operational amplifiers, namely, dual
pole operational amplifiers. For bipolar operational amplifiers, due to the signal passing
through two RC delays, the step response speed will be slower compared to single pole
operational amplifiers. This requires the operational amplifier to have a higher unit gain
bandwidth. However, a higher unit gain bandwidth means a wider white noise spectrum
and higher white noise energy. We know that noise folding is inevitable in switch-capacitor
circuits. Thus, a higher unit gain bandwidth will result in higher white noise energy being
generated within the passband. This is not what we hope for. Therefore, considering all
factors, we choose 5 f c ≤ f GB ≤ 10 f c .

3.4.3. Operational Amplifier Circuit Design

For the analysis of the above operational amplifier, we adopt a two-stage operational
amplifier, whose structure is shown in Figure 15. It consists of a two-stage amplifier and
a phase compensation circuit. The first stage amplifier consists of M1, M2, M3, M4, and
M5, which convert the differential mode input voltage into a differential mode current.
This differential mode current acts on the current mirror load composed of M3 and M4 to
restore the differential mode voltage. The second stage amplifier is composed of M6 and
M7, with M6 as the input and amplifier tube of the second stage amplifier and M7 as the
load of the current source. C is the compensation circuit. Figure 16 shows the amplitude
frequency phase frequency characteristic curve of the amplifier. The low-frequency gain of
the amplifier is 93 dB, the unit gain bandwidth is 6.3 MHz, and the phase margin is 64°.

M3 M4
M6

Vin+ M1 M2 Vin-
Vout

Vbias M5 M7

Figure 15. Operational amplifier structure.

Electronics 2023, 12, 4862 16 of 27

Figure 16. Operational amplifier Bode diagram.

3.5. Clock Circuit

The design of the switch-capacitor integrator adopts a structure that is insensitive to
capacitors, so its clock requirements are very important. The design introduces two-phase
non-interleaved clocks, and in order to eliminate the uncertainty of the input clock duty
cycle, the input clock signal is processed in 2-division frequency with a duty cycle of 50%.
The schematic structure of clock generation is shown in Figure 17.

clk2d

D Q
fclk clk1d
CK QB

clk2

clk1

Figure 17. Clock circuit.

This structure starts with a D flip-flop for division by 2, followed immediately by

inverters, NOR gates, and AND gate to accomplish a two-phase non-interleaved clock
output. The series inverters constitute a delay circuit, and the more inverters in series, the
longer the time the pulses do not overlap. When designing the size of the inverter, the
driving problem needs to be considered. In order to improve the driving ability, the size
of the series inverter link should be gradually increased, especially for the inverter at the
output position.
Electronics 2023, 12, 4862 17 of 27

3.6. Adjustable Bandwidth Design

The combination of switch and capacitor realizes the simulation of resistance; the prin-
ciple of operation is essentially to simulate the process of resistance “carrying” charges. Due
to the clock signal being divided by 2, the equivalent impedance of the switch-capacitor is:

1
Req = (41)
C I × 21 f clk

The pole formula of the integrator circuit is:

1
ω0 = (42)
Req × CF

Bringing Equation (41) into Equation (42) yields

ω0 C × f clk
f0 = = I (43)
2π 4π × CF

where C I is the sampling capacitance of the integrator and CF is the holding capacitance
of the integrator. According to the above Equation (43), it can be seen that bandwidth can
be adjusted by changing the ratio of clock frequency to capacitance without changing the
original structure of the circuit [30]. The CF value in this article adopts programmable
output, and its structure is shown in Figure 18. The six switches connected to the output
end of the operational amplifier use complementary CMOS transmission gates due to
signal passage. The six switches connected to the ground wire only require a single NMOS
transistor. The switch group is jointly controlled by control positions F5∼F0 and their
reverse positions F5∼ F0. In order to obtain accurate ratio relationships and layout, 1/8C I
is set as the minimum unit capacitance Cunit , and the CF value can be programmed as an
integer multiple of the fixed unit capacitance, with a range of 64Cunit to 127Cunit . Therefore,
the calculation formula for frequency and control words is as follows, where N is an integer
from 0 to 63.
In mode 1, mode 3, and mode 4 operating states:

f clk π
= (64 + N ) ∗ (44)
f0 2

In mode 2 operating states:

f clk 1 π
= √ ∗ (64 + N ) ∗ (45)
f0 2 2

F0 F1 F2 F3 F4 F5
8CI

1/8CI 1/4CI 1/2CI CI 2CI 4CI +

`F0 `F1 `F2 `F3 `F4 `F5

GND1

Figure 18. Switching integral capacitor.

Electronics 2023, 12, 4862 18 of 27

Set f clk to 200 kHz and Q to 1. Under operating mode 1, change CF to simulate the
low-pass, band-pass, and band-stop outputs of the second-order switch-capacitor filter as
shown in Figure 19. Red represents N = 0, green represents N = 32, and blue represents
N = 63.

Figure 19. Bandwidth adjustment simulation.

3.7. Q-Adjustable Design

In order to make the designed filter more adaptable, the Q value is also adjustable.
The Q value affects the attenuation speed of the filter transition band. The larger the Q,
the faster the attenuation, the steeper the amplitude frequency curve, and the faster the
phase change. The Q-value adjustable method is the same as the bandwidth adjustment
method, and it is also obtained through different capacitance ratios. The structure of the
adjustable capacitance part is shown in Figure 20, where the switches controlled by Q6
to Q0 adopt the same structure as in Figure 18, and 128 levels of Q-value adjustable are
achieved through 7-bit control bits. In order to save area, C1 in the figure is set to 32Cunit .
The relationship between Q value and control word is as follows, where N is 0∼127 (where
switches Q6∼Q0 are low level and the switch is conductive).
In mode 1, mode 3, and mode 4 operating states:

64
Q= (46)
128 − N
In mode 2 operating states:
√ 64
Q= 2∗ (47)
128 − N
Electronics 2023, 12, 4862 19 of 27

1/64C1

Q0 1/64C1

Q1 1/32C1

Q2 1/16C1

1/8C1
Q3

Q4 1/4C1

1/2C1
Q5

Q6 C1

Figure 20. Q-value adjustable capacitor structure.

Set f clk = 200 kHz, f 0 = 2 kHz, and adjust the Q value under working mode 1. The
band-stop output is shown in Figure 21. Red represents N = 0 (Q = 0.5), green represents
N = 64 (Q = 1), blue represents N = 96 (Q = 2), and black represents N = 124 (Q = 16).

Figure 21. Q-value adjustment simulation.

Electronics 2023, 12, 4862 20 of 27

4. Fourth-Order Butterworth Low-Pass Filter

Based on the above second-order filter characteristics, a fourth-order Butterworth
low-pass filter is designed by cascading dual second-order filters, and its structure is shown
in Figure 22. The input signal is input from the IN port of Filter A, with the low-pass output
LP of Filter A as the input of Filter B, and the low-pass output LP of Filter B as the output
of a fourth-order low-pass filter. The digital module is the digital interface part, which
realizes the selection of working modes and the assignment of CF and quality factor Q. The
digital interface part is composed of address lines A3 to A0, data lines D1 and D0, and
write enable control bit W. When the write enable bit is at a low level, data are written to
the register corresponding to the address line, and when the write enable bit is high, the
value in the register remains unchanged.The correspondence between register functions
and address lines is shown in the Table 2.

INPUT OUTPUT

IN LP HP BP IN LP HP BP
+
V Filter A Filter B

GND

V- Digital
D1,D0
A3,A2,A1,A0
`W

CLKA CLKB

Figure 22. Fourth-order Butterworth low-pass filter.

Table 2. Correspondence between Registers and Address Lines.

D0, D1 A3, A2, A1, A0 LOCATION

M0A, M1A 0000 0
F0A, F1A 0001 1
F2A, F3A 0010 2
F4A, F5A 0011 3
Q0A, Q1A 0100 4
Q2A, Q3A 0101 5
Q4, Q5A 0110 6
Q6A, X 0111 7
M0B, M1B 1000 8
F0B, F1B 1001 9
F2B, F3B 1010 10
F4B, F5B 1011 11
Q0B, Q1B 1100 12
Q2B, Q3B 1101 13
Q4B, Q5B 1110 14
Q6B, X 1111 15

The configuration of the filter is as follows: the clock signal frequency f clk is 200 kHz,
the operating mode is mode 1, and the cutoff frequency f 0 is 2 kHz. Then the ratio of
capacitance is determined in the two-stage filter according to Formula (43). Using the Filter
Electronics 2023, 12, 4862 21 of 27

Solutions software, we obtain the transfer function H (S) of the filter, as well as the transfer
functions H A (S) and HB (S) for each stage:

H ( S ) = H A ( S ) · HB ( S ) (48)

1.579e8
H A (S) = , Q1 = 0.542 (49)
S2 + 2.323e4 S + 1.579e8

1.579e8
HB ( S ) = , Q2 = 1.306 (50)
S2 + 9.61e3 S + 1.579e8
The internal circuit structures of Filter A and Filter B are the same. Figure 23 shows
the internal circuit of Filter A. Based on the requirements of f 0 , Q1 , and Q2 , the component
values and register configurations of each level of filter are determined, as shown in
Tables 3 and 4.
The selection of unit capacitance Cunit is a compromise considering speed, layout area,
matching degree, and noise. From the perspective of circuit speed and layout area, the
smaller the unit capacitance, the better. However, if the capacitance per unit area is too
small, it will have a negative impact on matching and noise. We know that the mismatch
between capacitors (without considering layout factors) is inversely proportional to the
capacitance area. In order to achieve sufficient matching, the side length of a unit capacitor
is designed to be above 20 µm. The KT/C noise is directly related to the capacitance value.
During
√ the switching capacitor charging process, a total root mean square noise voltage of
KT/C is generated on the capacitor
√ charging resistor, where the component distributed
within the cutoff frequency is KT/MC, and M is the oversampling rate. Taking into
account the above performance parameters, the side length of Cunit is selected as 30 µm.
C2 and C3 are adjustable capacitors that adjust the Q value and bandwidth respectively.
They can be obtained from Equations (51) and (52).

C1
Q= (51)
C2

f clk C
= 3 × 4π (52)
f0 C0

NP/HP/AP

BP
C1 S1 C3 C3
SCN

C1
−
IN SCN − + C0
∑ − −
+ SCN LP
− + +

S1 S2 S3 S2

MODE C2
SELECT

C1
S3
M0 M1 SCN

Figure 23. Internal circuit structure of filter A.

Electronics 2023, 12, 4862 22 of 27

Table 3. Circuit parameter values.

Filter Parameter Value (Cunit = 380.1 fF)

C0 8 × Cunit
C1 32 × Cunit
Filter A
C2 59 × Cunit
C3 64 × Cunit
C0 8 × Cunit
C1 32 × Cunit
Filter B
C2 24.5 × Cunit
C3 64 × Cunit

Table 4. Register configuration.

Filter Register D1, D0 A3, A2, A1, A0

M1, M0 00 0000
F1, F0 00 0001
F3, F2 00 0010
F5, F4 00 0011
Filter A
Q1, Q0 10 0100
Q3, Q2 10 0101
Q5, Q4 00 0110
X, Q6 00 0111
M1, M0 00 1000
F1, F0 00 1001
F3, F2 00 1010
F5, F4 00 1011
Filter B
Q1, Q0 11 1100
Q3, Q2 11 1101
Q5, Q4 00 1110
X, Q6 01 1111

The fourth-order low-pass filter operates in mode 1, with an input frequency of 2 kHz
sine wave and an amplitude of 2 V. Transient simulation is completed at a clock frequency
of 200 kHz, and the simulation results are shown in Figure 24.

Figure 24. Transient simulation results.

Electronics 2023, 12, 4862 23 of 27

5. Test Results
Based on the Huahong BCD350GE 1P4M layout process, the layout design of a two-
stage second-order switch-capacitor filter is completed. As shown in Figure 25, the layout
area of this circuit is 5.1 × 3.1 mm2 .

switch
Filter B

capacitor

Filter A
amplifier

Figure 25. Layout design.

The photos of the testing environment and printed circuit board (PCB) are shown
in Figure 26. The power supply provides +5 V power to the PCB board, and the signal
generator generates input signals. An oscilloscope is used to observe the waveform of the
filter output point. The chip adopts a dual power supply of ±5 V, with a power consumption
of approximately 80 mW. The traversal of working frequency, center frequency, and quality
factor are completed based on different configuration data. The test results are shown in
Table 5, and the bandwidth can be adjusted from 5 Hz to 10 kHz.
The structure of filters A and B in the chip is identical. Filter A is tested under four dif-
ferent operating modes, and the input and output waveforms are shown in Figure 27a–d.
The clock frequency is 200 kHz, and the input signal is 2 kHz. Through configuration,
f 0 = 2 kHz and Q = 1 are achieved. According to the test results, the output characteristics
fully cover low-pass, high-pass, band-pass, band-stop, and all-pass filtering functions.

signal generator

power supply

oscilloscope

Test PCB

Figure 26. Test environment and the PCB.

Electronics 2023, 12, 4862 24 of 27

Table 5. Bandwidth adjustability test.

Q Mode Fclk f0
1 1 500 Hz–500 kHz 5 Hz–5 kHz
1.41 2 500 Hz–500 kHz 5 Hz–6 kHz
1 3 500 Hz–500 kHz 5 Hz–5 kHz
1 4 500 Hz–500 kHz 5 Hz–5 kHz
64 1 1 kHz–1000 kHz 10 Hz–10 kHz
90.5 2 5 kHz–500 kHz 50 Hz–10 kHz
64 3 500 Hz–500 kHz 5 Hz–5 kHz
64 4 500 Hz–1000 kHz 5 Hz–10 kHz

(a) (b)

(c) (d)

Figure 27. Transient test results in 4 modes: (a) mode 1, (b) mode 2, (c) mode 3, (d) mode 4.

6. Discussion
The test results show that our second-order switch-capacitor filter is powerful and
can cover all functional filtering characteristics, including low-pass, high-pass, band-pass,
band-stop, and all-pass functional filtering. In addition, it also has other advantages. On
the chip, 64 level center frequency and 128 level Q value can be independently programmed
and adjusted without affecting each other. When switching frequency points, different
frequency points can be achieved without the need for many external devices, making
adjustment flexible. It has a wide range of applications, with two independent second-
order switch-capacitor filters on the chip that can be used separately or cascaded into a
fourth-order filter. It can also use a weighted structure of chip and chip cascading to achieve
higher-order filters. For example, in railway transportation systems, the track frequency
shift automatic blocking system achieves an automatic blocking function through frequency
shift signals, such as the UM71 standard uplink carrier frequency center frequencies of
2000 Hz and 2600 Hz, respectively, and the center frequencies of the downlink carrier
frequency are 1700 Hz and 2300 Hz, respectively. Before detecting frequency shift signals,
preprocessing of the signal is necessary. Usually, there are several methods to achieve
switching between multiple frequency points in the low frequency range. The first method
Electronics 2023, 12, 4862 25 of 27

is to use a multi-stage frequency selection circuit in series. Due to the discreteness of device
parameters, this method requires that all frequency selection circuits have a small deviation
in the center frequency, making it difficult to change the multi-stage center frequency
uniformly. The second method uses multiple analog switches, operational amplifiers,
resistors, capacitors, and other discrete components to form an active filter for frequency
selection. However, the circuit uses a large number of components, making parameter
adjustment very difficult. Our universal filter has a dual second-order universal switch-
capacitor active filter that is easy to program and can switch between different frequency
points without the need for many external devices. It can be used as a signal filtering unit
in the front end of railway frequency shift signal detection instruments. Currently, the chip
has completed board level testing, and the next step will be system-level testing in the
railway system.
Table 6 summarizes the performance comparison results between this article and other
references, indicating that the switch-capacitor filter designed in this article has strong
functionality. Foreign countries have always had an advantage in the field of high-precision,
low-power, and low-offset switch-capacitor filters. In recent years, domestic research has
mainly focused on high-order switch-capacitor filters, N-path switch-capacitor filters, and
Gm-C filters, while there is relatively little research on universal filters. We have designed
a second-order universal switch-capacitor filter, hoping to complete some work to fill the
gap. However, we believe that we still need to optimize the switch-capacitor filter chip
from the following aspects: (1) Power consumption. From the test results, using a ±5 V
power supply voltage, the power consumption is 80 mW, which is higher than traditional
continuous time filters. We need to further optimize the power consumption based on the
characteristics of the process, cost, etc. (2) Optimization of internal circuit structure. As
one of the important units, the performance of the operational amplifier directly affects the
performance of the switch-capacitor filter. From the design of the operational amplifier
structure, the structure is simple, but the bandwidth is small. For CMOS operational
amplifiers, the bandwidth will be limited by the characteristic frequency f T of the MOS
transistor, where the characteristic frequency f T is proportional to the gate length L2 of the
MOS transistor. We adopt the 24 V high-voltage transistor process, where the minimum
gate length of NMOS is 3 µm, while the minimum gate length of PMOS is 4 µm, which
greatly limits the bandwidth of the amplifier. The next step is to optimize the structure to
achieve a high bandwidth operational amplifier.

Table 6. Performance comparison.

Parameter Reference [3] Reference [4] Reference [15] This Paper

implementation
active RC active RC switched capacitor switched capacitor
method
low-pass, high-pass,
function low-pass low-pass low-pass band-pass, band-stop,
all-pass
1 MHz∼32 MHz 0.3 MHz∼10 MHz 100 Hz∼500 Hz 5 Hz∼10 kHz
cut-off frequency
adjustable adjustable adjustable adjustable
filter order 6 8 2 4
2P2M 1.2 µm N-well BCD350GE high
technology TSMC0.18 µm GSMC0.18 µm
MOS process voltage 24 V process
supply voltage 1.8 V 1.8 V - ±5 V
consumption 20 mW 15.48 mW - 80 mW

7. Conclusions
In this paper, a bandwidth adjustable filter is designed by using switch-capacitor
technology, which integrates low-pass, high-pass, band-pass, band-stop, and all-pass. The
Electronics 2023, 12, 4862 26 of 27

circuit has a simple structure and can independently achieve 64 level bandwidth and
128 level Q value adjustable through programming, without affecting each other. Two
second-order switch-capacitor filtering channels with the same structure are integrated
into the chip and manufactured using the Huahong BCD350GE high-voltage 24 V process.
The measurement results indicate that the proposed switch-capacitor filter can achieve
multifunctional filtering characteristics, including low-pass, high-pass, band-pass, band-
stop, and all-pass. Meanwhile, it can achieve a bandwidth of 5 Hz to 10 kHz. The chip area
is 5.1 × 3.1 mm2 , powered by a dual power supply of ±5 V, and the power consumption is
80 mW. The chip can be used alone and can also be cascaded to achieve high-order filtering.

Author Contributions: Conceptualization, F.H. and Y.Y.; methodology, F.H., Z.H. and S.H; software,
F.H. and J.X.; validation, F.H., J.X. and Z.H.; formal analysis, F.H., Y.F. and S.H.; investigation, F.H.;
resources, F.H.; data curation, F.H.; writing—original draft preparation, F.H.; writing—review and
editing, F.H., Y.Y. and Y.F.; visualization, F.H.; supervision, F.H.; project administration, F.H.; funding
acquisition, Y.Y. All authors have read and agreed to the published version of the manuscript.
Funding: The authors declare that this study received funding from the Laboratory Open Fund
Project of the Power Chip Design and Analysis Laboratory. The funder was not involved in the study
design, collection, analysis, interpretation of data, the writing of this article or the decision to submit
it for publication.
Data Availability Statement: The data presented in this study are available on request from the
corresponding author. The data are not publicly available due to privacy restrictions.
Conflicts of Interest: Author Fan He was employed by the companys Beijing Smart-chip Microelec-
tronics Technology Co.,Ltd, and Zhongguancun Xin Hai Ze You Technology Co., Ltd. Authors Yubo
Yuan and Yingchun Fu were employed by the company Zhongguancun Xin Hai Ze You Technology
Co., Ltd. The remaining authors declare that the research was conducted in the absence of any
commercial or financial relationships that could be construed as a potential conflict of interest.

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