Async_fifo

Async_fifo

Submitted by

Sherin C George

(sherindft5)

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 Async_fifo

CONTENTS
TITLE PAGE.NO:

Objective of Project ..................................................................................... 4

1. Scan Insertion ......................................................................................... 5

Script for scan insertion ................................................................... 6
2. Scan compression .................................................................................. 23
script for scan compression ............................................................. 23
3. Atpg pattern generation .......................................................................... 28
script for atpg pattern generation for stuck_at fault model............... 28
script for atpg pattern generation for at speed-loc fault model ......... 29
4. Atpg pattern generation-edt .................................................................... 31
script for atpg pattern generation for stuck_at fault model-edt ......... 31
script for atpg pattern generation for at speed-loc fault model-edt ... 33
5. Pattern simulation .................................................................................. 36
Stuck_at chain serial Simulation ..................................................... 36
Stuck_at chain parallel Simulation ................................................... 37
Stuck_at scan serial Simulation ........................................................ 38
Stuck_at scan parallel Simulation ................................................... 39
Atspeed-loc chain serial Simulation ................................................. 40
Atspeed-loc chain parallel Simulation ............................................. 41
Atspeed-loc scan serial Simulation ................................................. 42
Atspeed-loc scan parallel Simulation ...............................................43
6. Pattern simulation-EDT.......................................................................... 45
Stuck_at chain serial Simulation ......................................................45
Stuck_at chain parallel Simulation ................................................... 46
Stuck_at scan serial Simulation ........................................................ 47
Stuck_at scan parallel Simulation ................................................... 48
Atspeed-loc chain serial Simulation ................................................. 49
Atspeed-loc chain parallel Simulation ............................................. 50

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Atspeed-loc scan serial Simulation ................................................ 51
Atspeed-loc scan parallel Simulation ..............................................52
7. Simulation Debug ................................................................................. 54
Stuck_at chain serial Simulation ...................................................... 54
Stuck_at chain parallel Simulation .................................................... 57
Stuck_at scan serial Simulation......................................................... 58
Stuck_at scan parallel Simulation ..................................................... 63
Atspeed-loc scan serial Simulation .................................................... 66
Atspeed-loc scan parallel Simulation .................................................69
8. Conclusion ............................................................................................. 73

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 Async_fifo

OBJECTIVE OF PROJECT

Perform Scan insertion, Scan compression, ATPG pattern generation, simulation and
simulation Debug for the Input File async_fifo.vg (netlist), async_fifo_edt.vg (Synthesized
EDT), and adk.tcelllib (ATPG Library), Adk.v (Simulation Library).

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1. SCAN INSERTION
Tool used: Mentor Graphics- Tessent scan pro

# putty window #

Directory name: GLS_PROJECT

Working path: /workarea/dftclass/sherindft5/GLS_PROJECT/PROJECT_2/1.SCAN_INSERTION

Xterm & // to open xming window

# Xming window #

tessent –shell –log SCAN .log // This command is used to invoke the tool

Scan insertion:
Scan insertion involves replacing sequential elements with scannable sequential
elements (scan cells) and then stitching the scan cells together into scan registers,
or scan chains. Then use these scan cells to shift data in and out when the design is
in scan mode.

Scan insertion flow

Invoke the tool

Set the context
Read the synthesized non scan inserted netlist
Read cell library
Define scan signals
Define clock
Define chain length/counts
Check for DRC violations
If we fix all DRC violations it comes to analysis mode
Scan insertion
Generate output files

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SCRIPT FOR SCAN INSERTION:

######################## SCRIPT FOR SCAN INSERTION AND STITCHING

##########################################

#Set context to perform scan insertion #

set_context dft –scan

#Read the synthesized non scan inserted netlist#

read_verilog async_fifo.vg

#Read the tessent cell library#

read_cell_library adk.tcelllib

#Set the top module name#

set_current_design a_fifo

# Set the design level as sub-block/physical block

set_design_level physical_block

#Set Mode to insertion to create the TESTMODE

set_system_mode insertion

create_port TESTMODE -direction input

create_port SCAN_EN -direction input

#Set mode to setup Again to add the DFT configuration
set_system_mode setup
#to initialize value of clock signal as 0,
add_clocks 0 w_clk r_clk

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here using two clocks w_clk and r_clk

#to initialize value of reset signal as 0

add_clocks 0 reset
#To set initial value of SCAN_EN as active high

set_scan_enable SCAN_EN -active high

# Define the internal scan chain number.

Given, MCL=54

set_scan_insertion_options -chain_length 54
#check DRC’s
check_design_rules

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Here, having 10 S1 violations.

#to see schematic tessent visualizer window

open_visualizer

S1_1 violations:

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Note: Clock is the issue: Clock should be controllable from the top level. Here, clock is
coming from other flop. We can fix the problem by using mux.

S1_2 violations:

Note: In this Clock is tied to (x), no connection to the clock pin. We can fix this issue by
using an MUX

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S1_3 violations:

S1_4 violations

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:

S1_5 violations:

Note: Here a feedback loop is presented. We can fix this by using mux.

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S1_6 violations:

S1_7 violations:

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Note: In this Reset is tied to (x), no connection to the Reset pin. We can fix this issue
by using MUX

S1_8 violations:

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Note: A feedback loop is presented from Q to Clock. We can fix this issue by using a
mux.

S1_9 violations:

Note: Clock and Reset is coming from same output Y(x): Clock and Reset should be
controllable from the top level. We can fix the problem by using mux.
S1_10 violations:

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#to initialize testmode as 1

add_input_constraints -c1 TESTMODE

set_system_mode insertion

DRC FIX 1:
delete_connections \ f_memory_reg[62][7]/CLK

create_instance mux_drc_fix1 -of_module mux21

create_connections mux_drc_fix1/Y \ f_memory_reg[62][7]/CLK

create_connections mux_drc_fix1/A0 \ io_pad_u0/PAD

create_connections mux_drc_fix1/A1 w_clk

create_connections mux_drc_fix1/S0 TESTMODE

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DRC FIX 2:

delete_connections f_memory_reg[62][1]/CLK
create_instance DRC_MUX_FIX2 -of_module mux21
create_connections DRC_MUX_FIX2/Y f_memory_reg[62][1]/CLK
create_connections DRC_MUX_FIX2/A0 -constant {0}
create_connections DRC_MUX_FIX2/A1 w_clk
create_connections DRC_MUX_FIX2/S0 TESTMODE

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DRC FIX 3:
delete_connections \ f_memory_reg[62][0]/CLK

create_instance mux_drc_fix3 -of_module mux21

create_connections mux_drc_fix3/Y \ f_memory_reg[62][0]/CLK

create_connections mux_drc_fix3/A0 \ f_memory_reg[62][1]/Q

create_connections mux_drc_fix3/A1 w_clk

create_connections mux_drc_fix3/S0 TESTMODE

DRC FIX 4:
delete_connections \ d_out_reg[4]/CLK

create_instance mux_drc_fix4 -of_module mux21

create_connections mux_drc_fix4/Y \ d_out_reg[4]/CLK

create_connections mux_drc_fix4/A0 \ d_out_reg[5]/Q

create_connections mux_drc_fix4/A1 r_clk

create_connections mux_drc_fix4/S0 TESTMODE

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DRC FIX 5:
delete_connections \ r_b_counter/\c_out_reg[1]/CLK

create_instance mux_drc_fix5 -of_module mux21

create_connections mux_drc_fix5/Y \ r_b_counter/\c_out_reg[1]/CLK

create_connections mux_drc_fix5/A0 \ r_b_counter/\c_out_reg[1]/Q

create_connections mux_drc_fix5/A1 r_clk

create_connections mux_drc_fix5/S0 TESTMODE

DRC FIX 6:
delete_connections \ r_b_counter/\c_out_reg[2]/CLK

create_instance mux_drc_fix6 -of_module mux21

create_connections mux_drc_fix6/Y \ r_b_counter/\c_out_reg[2]/CLK

create_connections mux_drc_fix6/A0 \ r_b_counter/\c_out_reg[3]/QB

create_connections mux_drc_fix6/A1 r_clk

create_connections mux_drc_fix6/S0 TESTMODE

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DRC FIX 7:
delete_connections r_b_counter/\c_out_reg[7]/R
create_instance DRC_MUX_FIX7 -of_module mux21
create_connections DRC_MUX_FIX7/Y r_b_counter/\c_out_reg[7]/R

create_connections DRC_MUX_FIX7/A0 -constant {0}

create_connections DRC_MUX_FIX7/A1 reset
create_connections DRC_MUX_FIX7/S0 TESTMODE

DRC FIX 8:
delete_connections \ w_b_counter/\c_out_reg[0]/CLK

create_instance mux_drc_fix8 -of_module mux21

create_connections mux_drc_fix8/Y \ w_b_counter/\c_out_reg[0]/CLK

create_connections mux_drc_fix8/A0 \ w_b_counter/\c_out_reg[0]/Q

create_connections mux_drc_fix8/A1 w_clk

create_connections mux_drc_fix8/S0 TESTMODE

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DRC FIX 9:
delete_connections \ w_b_counter/\c_out_reg[1]/R

create_instance mux_drc_fix9 -of_module mux21

create_connections mux_drc_fix9/Y \ w_b_counter/\c_out_reg[1]/R

create_connections mux_drc_fix9/A0 w_b_counter/U4/Y

create_connections mux_drc_fix9/A1 reset

create_connections mux_drc_fix9/S0 TESTMODE

DRC FIX 10:

delete_connections \ w_b_counter/\c_out_reg[1]/CLK

create_instance mux_drc_fix10 -of_module mux21

create_connections mux_drc_fix10/Y \ w_b_counter/\c_out_reg[1]/CLK

create_connections mux_drc_fix10/A0 w_b_counter/U4/Y

create_connections mux_drc_fix10/A1 w_clk

create_connections mux_drc_fix10/S0 TESTMODE

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set_system_mode setup

set_scan_insertion_options -

chain_length 54 check_design_rules

analyze_scan_chains

report_scan_chains

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#Scan insertion command

insert_test_logic

#Write the scan inserted DRC free netlist

write_design -output_file SCAN_INSERTED.vg

# Write the Test procedure file and other dofiles required for ATPG pattern
generation

write_atpg_setup SCAN_ATPG

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 Async_fifo

2. SCAN COMPRESSION

The scan compression technique which reduces the test time and tester memory
in whole test cost without loss in the test coverage.
Working path:
/workarea/dftclass/sherindft5/GLS_PROJECT/PROJECT_2/2.SCAN_COMPRESSION

Tool used: Mentor- Test kompress

a. Inputs: - Scan inserted Netlist - Library - Test procedure or do files
b. Outputs: - Scan technique and EDT files - Setup files - Do files

SCRIPT FOR SCAN COMPRESSION:

#Set the context to scan

set_context dft –edt

## Read the scan inserted netlist and Libarary ##

SCAN_INSERTED.vg

read_cell_library adk.tcelllib

set_current_design a_fifo

dofile SCAN_ATPG.dofile

tessent_scan_setup

### Scan compression configuaration ###

set_edt_options -input_channels 4

set_edt_options -output_channels

2 check_design_rules

### Generate EDT reports ###

write_edt_files a_fifo

report_scan_chains

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report_edt_instance

s report_edt_pins

report_edt_pins >

edt_pins_info.rpt

report_edt_configurations

report_edt_configurations > edt_config.rpt

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Compression Ratio: It is a ratio between number of internal scan chains to number

of external scan channels.

Here, Number of internal scan chains =10

Number of external scan channels = 2

Compression Ratio =number of internal scan chain

Number of external scan chain

= 10/2 =5x

### To see EDT visualizer ###

set_context dft –edt // Set the context to scan

compression read_verilog a_fifo_edt_top.v // Read the edt top

netlist read_verilog a_fifo_edt.v // Read the edt

netlist read verilog SCAN_INSERTED.vg // Read the scan inserted

netlist read_cell_library adk.tcelllib //Read cell library

set_current_design a_fifo_edt_top // Set the edt top module

name open_visualizer

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i. EDT ARCHITECTURE

EDT-DECOMPRESSOR,COMPACTOR, CONTROLLER, BYPASS LOGIC

The components of scan compression logics are decompressor, compactor, controller and
bypass logic and they are part of scan path.

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 Async_fifo

3. ATPG PATTERN GENERATION

ATPG stands for Automatic Test Pattern Generation, this is basically the generation
of test patterns.
Tool used: Mentor-Fast scan
Working path: /workarea/dftclass/sherindft5/GLS_PROJECT/PROJECT_2/3.ATPG

ATPG PATTERN GENERATION FLOW:

Read scan inserted netlist

Read library
Define current design
Source dofile
Read procedure file
Add scan chains
Define clocks
Check ATPG DRC- To check whether ATPG tools can generate pattern
successfully. If don’t have ATPG DRC, then proceed for pattern generation.
Check coverage

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SCRIPT FOR ATPG PATTERN GENERATION FOR
STUCK_AT FAULT MODEL:
set_context patterns –scan / / Set context

read_verilog SCAN_INSERTED.vg #Read the scan inserted netlist

read_cell_library adk.tcelllib # Read cell library

set_current_design a_fifo #Set the top module name

dofile SCAN_ATPG.dofile # Read the dofile

tessent_scan_setup #Read proc file, add scan chains , Define clocks

set_system_mode analysis # Set mode to setup Again to add the DFT configuration
set_fault_type stuck # Set the fault models to stuck_at

add_faults –all # add the faults for entire design

report_faults -all #to write out the faults

report_faults -all > faults.rpt # Report faults write in to one file

create_patterns #To generate pattern

report_statistics -detail # To see statistics report

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report_statistics -detail > stuck_at.rpt

### create directory for storing the pattern###

exec mkdir -p Sim_Debug_Files

exec mkdir -p Sim_Debug_Files/Stuck_Chain_Patterns

exec mkdir -p Sim_Debug_Files/Stuck_Scan_Patterns

write_patterns Sim_Debug_Files/Stuck_Chain_Patterns/stuck_chain_serial.v -
pattern_sets chain -verilog –serial // create chain-serial pattern in Verilog format
write_patterns Sim_Debug_Files/Stuck_Chain_Patterns/stuck_chain_parallel.v -
pattern_sets chain -verilog -parallel // create chain-parallel pattern in Verilog format
write_patterns Sim_Debug_Files/Stuck_Chain_Patterns/stuck_chain_serial.stil -
pattern_sets chain -stil -serial // create chain-serial pattern in stil format

write_patterns Sim_Debug_Files/Stuck_Chain_Patterns/stuck_chain_parallel.stil -
pattern_sets chain -stil -parallel // create chain-parallel pattern in stil format

write_patterns Sim_Debug_Files/Stuck_Scan_Patterns/stuck_scan_serial.v -
pattern_sets scan -verilog -serial // create scan-serial pattern in Verilog format
write_patterns Sim_Debug_Files/Stuck_Scan_Patterns/stuck_scan_parallel.v -
pattern_sets scan -verilog -parallel // create scan-parallel pattern in Verilog format
write_patterns Sim_Debug_Files/Stuck_Scan_Patterns/stuck_scan_serial.stil -
pattern_sets scan -stil -serial // create scan-serial pattern in stil format

write_patterns Sim_Debug_Files/Stuck_Scan_Patterns/stuck_scan_parallel.stil -
pattern_sets scan -stil -parallel // create scan-parallel pattern in stil format

write_flat_model
Sim_Debug_Files/Stuck_Chain_Patterns/a_fifo_netlist.flat_stuckat.gz
write_flat_model
Sim_Debug_Files/Stuck_Scan_Patterns/a_fifo_netlist.flat_stuckat.gz

SCRIPT FOR ATPG PATTERN GENERATION FOR AT

SPEED-LOC FAULT MODEL:
set_context patterns -scan
read_verilog SCAN_INSERTED.vg

read_cell_library adk.tcelllib
set_current_design a_fifo
set_edt_options off

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 Async_fifo
dofile SCAN_ATPG.dofile

tessent_scan_setup
add_black_boxes –auto // add the blackbox

set_system_mode analysis
set_fault_type transition #Set loc fault type transition

add_faults -all
report_faults -all > faults_ATspeed.rpt

create_patterns
report_statistics -detail

report_statistics -detail > ATspeed.rpt

exec mkdir -p Sim_Debug_Files

exec mkdir -p Sim_Debug_Files/Atspeed_LOC_Chain_Patterns

exec mkdir -p Sim_Debug_Files/Atspeed_LOC_Scan_Patterns

write_patterns Sim_Debug_Files/Atspeed_LOC_Chain_Patterns/loc_chain_serial.v -
pattern_sets chain -verilog -serial

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 Async_fifo
write_patterns Sim_Debug_Files/Atspeed_LOC_Chain_Patterns/loc_chain_parallel.v
-pattern_sets chain -verilog -parallel

write_patterns Sim_Debug_Files/Atspeed_LOC_Chain_Patterns/loc_chain_serial.stil
-pattern_sets chain -stil -serial
write_patterns
Sim_Debug_Files/Atspeed_LOC_Chain_Patterns/loc_chain_parallel.stil -pattern_sets
chain -stil -parallel

write_patterns Sim_Debug_Files/Atspeed_LOC_Scan_Patterns/loc_scan_serial.v -
pattern_sets scan -verilog -serial

write_patterns Sim_Debug_Files/Atspeed_LOC_Scan_Patterns/loc_scan_parallel.v -
pattern_sets scan -verilog -parallel
write_patterns Sim_Debug_Files/Atspeed_LOC_Scan_Patterns/loc_scan_serial.stil -
pattern_sets scan -stil -serial
write_patterns Sim_Debug_Files/Atspeed_LOC_Scan_Patterns/loc_scan_parallel.stil
-pattern_sets scan -stil –parallel

write_flat_model
Sim_Debug_Files/Atspeed_LOC_Chain_Patterns/a_fifo_netlist_LOC.flat.gz -replace
write_flat_model
Sim_Debug_Files/Atspeed_LOC_Scan_Patterns/a_fifo_netlist_LOC.flat.gz –replace
Note: The value of Atspeed-loc is less when compared to stuck. This is due to
the presence of false paths and multicycle paths.

4. ATPG PATTERN GENERATION-EDT

SCRIPT FOR ATPG PATTERN GENERATION FOR

STUCK_AT FAULT MODEL-EDT:
set_context patterns –scan #Set context

read_cell_library adk.tcelllib #Read cell library

read verilog SCAN_INSERTED.vg #Read the scan inserted netlist
read_verilog async_fifo_edt.vg # Read the edt netlist
read_verilog a_fifo_edt_top.v # Read the edt top netlist
set_current_design a_fifo_edt_top #Set the edt top module name

set_edt_options on #set edt option on for compressed type

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 Async_fifo
dofile a_fifo_edt.dofile // Read dofile

set_system_mode analysis // Set mode to setup Again to add the DFT configuration
set_fault_type stuck // Set the fault models to stuck_at

add_faults –all // add the faults for entire design

report_faults -all // to write out the faults

report_faults -all > faults_edt_stuck.rpt // Report faults write in to one file

create_patterns // To generate pattern

report_statistics -detail // To see statistics report

report_statistics -detail > stuck_at_edt.rpt

### create directory for storing the pattern###

exec mkdir -p Sim_Debug_Files1
exec mkdir -p Sim_Debug_Files1/Stuck_Chain_Patterns

exec mkdir -p Sim_Debug_Files1/Stuck_Scan_Patterns

## create chain-serial/parallel pattern in Verilog and stil format ##

write_patterns Sim_Debug_Files1/Stuck_Chain_Patterns/stuck_chain_serial.v -
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pattern_sets chain -verilog -serial -replace
write_patterns Sim_Debug_Files1/Stuck_Chain_Patterns/stuck_chain_parallel.v -
pattern_sets chain -verilog -parallel -replace
write_patterns Sim_Debug_Files1/Stuck_Chain_Patterns/stuck_chain_serial.stil -
pattern_sets chain -stil -serial -replace
write_patterns Sim_Debug_Files1/Stuck_Chain_Patterns/stuck_chain_parallel.stil -
pattern_sets chain -stil -parallel -replace

## create scan-serial/parallel pattern in Verilog and stil format ##

write_patterns Sim_Debug_Files1/Stuck_Scan_Patterns/stuck_scan_serial.v -
pattern_sets scan -verilog -serial -replace
write_patterns Sim_Debug_Files1/Stuck_Scan_Patterns/stuck_scan_parallel.v -
pattern_sets scan -verilog -parallel -replace

write_patterns Sim_Debug_Files1/Stuck_Scan_Patterns/stuck_scan_serial.stil -
pattern_sets scan -stil -serial -replace
write_patterns Sim_Debug_Files1/Stuck_Scan_Patterns/stuck_scan_parallel.stil -
pattern_sets scan -stil -parallel –replace

SCRIPT FOR ATPG PATTERN GENERATION FOR

ATSPEED-LOC FAULT MODEL-EDT:
set_context patterns -scan

read_cell_library adk.tcelllib
read verilog SCAN_INSERTED.vg
read_verilog async_fifo_edt.vg
read_verilog a_fifo_edt_top.v
set_current_design a_fifo_edt_top
set_edt_options on

dofile a_fifo_edt.dofile

set_system_mode analysis
set_fault_type transition
add_faults -all

report_faults -all > faults_edt_LOC.rpt

report_statistics -detail

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report_statistics -detail > LOC_edt.rpt

create_patterns

exec mkdir -p Sim_Debug_Files1

exec mkdir -p Sim_Debug_Files1/Atspeed_LOC_Chain_Patterns

exec mkdir -p Sim_Debug_Files1/Atspeed_LOC_Scan_Patterns

write_patterns Sim_Debug_Files1/Atspeed_LOC_Chain_Patterns/loc_chain_serial.v
-pattern_sets chain -verilog -serial -rep

write_patterns
Sim_Debug_Files1/Atspeed_LOC_Chain_Patterns/loc_chain_parallel.v -pattern_sets
chain -verilog -parallel -rep
write_patterns

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 Async_fifo
Sim_Debug_Files1/Atspeed_LOC_Chain_Patterns/loc_chain_serial.stil -pattern_sets
chain -stil -serial -rep

write_patterns
Sim_Debug_Files1/Atspeed_LOC_Chain_Patterns/loc_chain_parallel.stil -
pattern_sets chain -stil -parallel -rep

write_patterns Sim_Debug_Files1/Atspeed_LOC_Scan_Patterns/loc_scan_serial.v -
pattern_sets scan -verilog -serial -rep

write_patterns Sim_Debug_Files1/Atspeed_LOC_Scan_Patterns/loc_scan_parallel.v
-pattern_sets scan -verilog -parallel -rep
write_patterns Sim_Debug_Files1/Atspeed_LOC_Scan_Patterns/loc_scan_serial.stil
-pattern_sets scan -stil -serial -rep

write_patterns
Sim_Debug_Files1/Atspeed_LOC_Scan_Patterns/loc_scan_parallel.stil -pattern_sets
scan -stil -parallel -rep

Note: If don’t have ATPG DRC, then proceed for pattern generation. We can use
sim_Debug_Files1 for checking serial and parallel pattern.

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5. PATTERN SIMULATION
Simulation is used for design verification, Generating efficient test patterns with
maximum test coverage by using ATPG, and then verifying test patterns in simulation.

Tool used: Mentor-Questa sim

Simulation follow 3 steps:
Compilation: In compilation it will take all the netlist and compile it. It checks
syntax of all netlist and Unresolved references modules.
Elaboration: here, map all the netlist gates and libraries. Some primitives and
some standard cells are present in library
Simulation: here, apply the pattern and check the design.

1. Stuck_at chain serial Simulation

rm -rf work //To remove the existing work

vlib work //For creating new work – It keep all the compiled objects

vlog Adk.v // compile the library (Verilog

formats)

vlog SCAN_INSERTED.vg // compile the netlist which is used for pattern

generation

vlog ./stuck_chain_serial.v // compile serial test bench, from this we get top
module name (ATPG pattern simulation output)

vsim -c -voptargs="+acc" a_fifo_stuck_chain_serial_v_ctl -l sims_chain_serial.log

+nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo _stuck_chain_serial_v_ctl -l
sims_chain_serial.log +nospecify +nowarmTSCALE

Note:

vlog-command to compile
Vsim- for elaboration and simulation
vsim –c // To know any mismatch run in command mode, then it shows “NO
error between simulated and expected pattern”
-voptargs="+acc" // Simulation Switches based on the tool
A_fifo_stuck_chain_serial_v_ctl // Top module name
-l sims_chain_serial.log // Simulation log files (Observe for simulation
mismatches). All details is recorded in the log file.

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vsim –gui // To see the waveform in questasim window need to run in gui
mode
+nospecify +nowarmTSCALE // Additional switches for running no-timing
simulation.

Waveform:

This is generally 0011 pattern.

Here, have 10 scan in and 10 scan out signals
In this, si and so patterns are looks similar.

Here we are taking compare fail, pattern count, procedure string, reset, clock, Test mode,
scan_en, si and so for generating waveform. Add some test bench signals to wave.

Note: Compare fail // when having mismatch from which patterns

the mismatch starts, from that pattern this compare fail will incremented.

Procedure string // Number of loading/unloading cycles are

defined.

Si // scan input

So // scan output

2. Stuck_at chain parallel Simulation

rm -rf work //To remove the existing work

vlib work //For creating new work – It keep all the compiled objects
DFT-5 Page 37
 Async_fifo
vlog Adk.v // compile the library (Verilog
formats)
vlog SCAN_INSERTED.vg // compile the netlist which is used for
pattern generation
#vlog ./stuck_chain_parallel.v

#vsim -c -voptargs="+acc" a_fifo_stuck_chain_parallel_v_ctl -l

sims_chain_parallel.log +nospecify +nowarmTSCALE -do "run -all"

#vsim -gui -voptargs="+acc" a_fifo_stuck_chain_parallel_v_ctl -l

sims_chain_parallel.log +nospecify +nowarmTSCALE

Waveform:

Data will be directly loaded to ‘si’ pins, data will be loaded before scan clocks
come, then unloaded at the output.
Here, having w_clk and r_clk for loading and w_clk and r_clk for unloading
and scan_en is ‘1’ throughout.

3. Stuck_at scan serial Simulation

rm -rf work

vlib work
vlog Adk.v

vlog SCAN_INSERTED.vg
vlog ./stuck_scan_serial.v

DFT-5 Page 38
 Async_fifo
vsim -c -voptargs="+acc" a_fifo_stuck_scan_serial_v_ctl -l sims_scan_serial.log
+nospecify +nowarmTSCALE -do "run -all"

vsim -gui -voptargs="+acc" a_fifo_stuck_scan_serial_v_ctl -l sims_scan_serial.log

+nospecify +nowarmTSCALE

Waveform: This patterns have random values.

4.Stuck_at scan parallel Simulation

rm -rf work

vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg

vlog ./stuck_scan_parallel.v

vsim -c -voptargs="+acc" a_fifo_stuck_scan_parallel_v_ctl -l

sims_verilog_parallel.log +nospecify +nowarmTSCALE -do "run -all"

vsim -gui -voptargs="+acc" a_fifo_stuck_scan_parallel_v_ctl -l

sims_verilog_parallel.log +nospecify +nowarmTSCALE

DFT-5 Page 39
 Async_fifo

Waveform: Here, one loading cycle, one capture and one unloading is present.

5.ATspeed-loc chain serial Simulation

rm -rf work
vlib work

vlog Adk.v
vlog SCAN_INSERTED.vg

vlog ./loc_chain_serial.v

vsim -c -voptargs="+acc" a_fifo_loc_chain_serial_v_ctl -l

sims_loc_chain_serial.log +nospecify +nowarmTSCALE -do "run -all"
#vsim -gui -voptargs="+acc" a_fifo_loc_chain_serial_v_ctl -l
sims_loc_chain_serial.log +nospecify +nowarmTSCALE

DFT-5 Page 40
 Async_fifo

Waveform : In this, si and so patterns are looks similar.

6.ATspeed-loc chain parallel Simulation

rm -rf work

vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg

vlog ./loc_chain_parallel.v

vsim -c -voptargs="+acc" a_fifo_loc_chain_parallel_v_ctl -l

sims_LOC_chain_parallel.log +nospecify +nowarmTSCALE -do "run -all"

vsim -gui -voptargs="+acc" a_fifo_loc_chain_parallel_v_ctl -l

sims_LOC_chain_parallel.log +nospecify +nowarmTSCALE

DFT-5 Page 41
 Async_fifo
Waveform: Here, w_clk and r_clk for loading and w_clk and r_clk for unloading and
scan_en is ‘1’ throughout.

7.ATspeed-loc scan serial Simulation

rm -rf work

vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg

vlog ./loc_scan_serial.v
vsim -c -voptargs="+acc" a_fifo_loc_scan_serial_v_ctl -l
sims_scan_loc_serial.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_loc_scan_serial_v_ctl -l
sims_scan_loc_serial.log +nospecify +nowarmTSCALE &
Waveform: Here, First two pattern is reset pattern then, 2 atspeed clock pulse
presented at the capture cycle.

DFT-5 Page 42
 Async_fifo

8.ATspeed-loc scan parallel Simulation

rm -rf work

vlib work
vlog Adk.v

vlog SCAN_INSERTED.vg
vlog ./loc_scan_parallel.v

vsim -c -voptargs="+acc" a_fifo_loc_scan_parallel_v_ctl –l

sims_scan_loc_parallel.log +nospecify +nowarmTSCALE -do "run -all"

vsim -gui -voptargs="+acc" a_fifo_loc_scan_parallel_v_ctl -l

sims_scan_loc_parallel.log +nospecify +nowarmTSCALE

DFT-5 Page 43
 Async_fifo

Waveform: Here, First two pattern is reset pattern then, atspeed clock pulse
presented at the capture cycle.

DFT-5 Page 44
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6. PATTERN SIMULATION –EDT

Scan compression is mandatory in order to significantly reduce the overall test time. It results
of two different scan modes that can be used for a given design: bypass and compress mode.

Only bypass pattern are transiting as it along the scan chain, meaning that a data shift from a
scan input can be easily followed flip-flop after flip-flop until the data is going out of the design
through a scan output. When validated that the bypass shift is working as expected, can move
to compression bypass capture simulation and other scan modes (compressed) simulation. All
those simulation are performed in serial mode; most of the patterns are then simulated in
parallel mode since only the capture phase is then to verify.

1. Stuck_at chain serial Simulation-EDT

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./stuck_chain_serial.v
vsim -c -voptargs="+acc" a_fifo_edt_top_stuck_chain_serial_v_ctl -l
sims_stuck_chain_edt_serial.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_stuck_chain_serial_v_ctl -l
sims_stuck_chain_edt_serial.log +nospecify +nowarmTSCALE

DFT-5 Page 45
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Note: In serial, here the chain pattern is not 0011 when compared to without EDT.
EDT compressed stimulai reached at decompressor. The pattern which reached at
decompressor is shuffled and it gives to internal chains. 8 chain pattern is presented
here.
2. Stuck_at chain parallel Simulation-EDT

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./stuck_chain_parallel.v
vsim -c -voptargs="+acc" a_fifo_edt_top_stuck_chain_parallel_v_ctl -l
sims_chain_parallel.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_stuck_chain_parallel_v_ctl -l
sims_chain_parallel.log +nospecify +nowarmTSCALE

Note: In chain parallel input values are forced directly to the SI pin of each flip-flop
and the output is directly measured from the Q pin of each flop.

DFT-5 Page 46
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3. Stuck_at scan serial Simulation-edt

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./stuck_scan_serial.v
vsim -c -voptargs="+acc" a_fifo_edt_top_stuck_scan_serial_v_ctl -l
sims_scan_serial.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_stuck_scan_serial_v_ctl -l
sims_scan_serial.log +nospecify +nowarmTSCALE
Note: here, the output does not follow the input. The output value depends the output
from the functional combinational logic.

DFT-5 Page 47
 Async_fifo

4.Stuck_at scan parallel Simulation

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./stuck_scan_parallel.v
vsim -c -voptargs="+acc" a_fifo_edt_top_stuck_scan_parallel_v_ctl -l
sims_verilog_parallel.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_stuck_scan_parallel_v_ctl -l
sims_verilog_parallel.log +nospecify +nowarmTSCALE

DFT-5 Page 48
 Async_fifo

Waveform: Here, one loading cycle, one capture and one unloading is present.

5.ATspeed-loc chain serial Simulation

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./loc_chain_serial.v
vsim -c -voptargs="+acc" a_fifo_edt_top_loc_chain_serial_v_ctl -l
sims_loc_chain_serial.log +nospecify +nowarmTSCALE -do "run -all"

DFT-5 Page 49
 Async_fifo
vsim -gui -voptargs="+acc" a_fifo_edt_top_loc_chain_serial_v_ctl -l
sims_loc_chain_serial.log +nospecify +nowarmTSCALE

Note: From this, we get the Top module name a_fifo_edt_top_loc_chain_serial_v_ctl.

6.ATspeed-loc chain parallel Simulation

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./loc_chain_parallel.v
vsim -c -voptargs="+acc" a_fifo_edt_top_loc_chain_parallel_v_ctl -l
sims_LOC_chain_parallel.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_loc_chain_parallel_v_ctl -l
sims_LOC_chain_parallel.log +nospecify +nowarmTSCALE

DFT-5 Page 50
 Async_fifo

7.ATspeed-loc scan serial Simulation

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./loc_scan_serial.v
vsim -c -voptargs="+acc" a_fifo_edt_top_loc_scan_serial_v_ctl -l
sims_scan_loc_serial.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_loc_scan_serial_v_ctl -l
sims_scan_loc_serial.log +nospecify +nowarmTSCALE &

DFT-5 Page 51
 Async_fifo

8.ATspeed-loc scan parallel Simulation

rm -rf work
vlib work
vlog Adk.v
vlog SCAN_INSERTED.vg
vlog async_fifo_edt.vg
vlog a_fifo_edt_top.v
vlog ./loc_scan_parallel.v
vsim -c -voptargs="+acc" a_fifo_edt_top_loc_scan_parallel_v_ctl -l
sims_scan_loc_parallel.log +nospecify +nowarmTSCALE -do "run -all"
vsim -gui -voptargs="+acc" a_fifo_edt_top_loc_scan_parallel_v_ctl -l
sims_scan_loc_parallel.log +nospecify +nowarmTSCALE &

DFT-5 Page 52
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DFT-5 Page 53
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7. SIMULATION PATTERN –DEBUG

SIMULATION DEBUG:
Most possible reasons for Simulation mismatches could be due to the DRC violations,
Library Problems, Timing violations and Netlist problem.

There some steps to find simulation mismatch:

Step1. Try to debug which pin/port is having miscompare and which pattern causes the
failure.
Step2. Use waveform viewer to easily debug the failure. Add clocks, SCAN_EN,
Pattern count and output chains (mismatch happened) in waveform. Try to find the root
cause of having miscompare value (expected to be 1 was 0) on that particular pin. Well
from the waveform viewer already know at what time instance and for what signal the
expect verses the actual values are failing. One way could be to open this signal/signals
in the schematic viewer and keep tracing it backwards to the point where its change
occurs. In the path we might detect an anomaly which can then further investigate.
Step3.Also need to know which kind of simulation are running Serial or parallel. Check
that ATPG Flat model. Also check that the simulation tool is also running the
simulation in that particular mode.
In serial simulation pattern is shifted in to FFs in scan chain through scan-ports. So,
more the no. of FFs more time it will take to shift in the pattern. Note that, here,
simulator will apply patterns at scan-ports
In parallel simulation values that should have actually reached the D input of FFs in
a scan-chain by shifting through scan-inputs are directly forced at the D input of FFs
by simulator. So here, simulator will save time to load-unload the patterns as it is
directly forcing patterns at D input of flops
so, as parallel simulation reduces the time for shifting the pattern.

1. Stuck_at chain serial Simulation debug

rm -rf work

vlib work
vlog adk.v

vlog SCAN_INSERTED.vg
vlog ./stuck_chain_serial.v

vsim -debugDB -c -voptargs="+acc" a_fifo_stuck_chain_serial_v_ctl -l

sims_chain_serial_batch.log +nospecify +nowarmTSCALE -do "run -all" // -
debugDB command is used for schematic view.
DFT-5 Page 54
 Async_fifo
vsim -debugDB -gui -voptargs="+acc" a_fifo_stuck_chain_serial_v_ctl -l
sims_chain_serial.log +nospecify +nowarmTSCALE

Note: Simulation debugging happening only when an error is presented between

simulated and expected patterns.

Note: here we add top module. add log –r a_fifo_stuck_chain_serial_v_ctl/* then run
all the mismatches or give some time instance like, run 10000ns. Then it load
corresponding time instance mismatches and its shows scan chain output, chain name,
pattern number and simulated and expected values.

DFT-5 Page 55
 Async_fifo
Here, we add pattern count, clocks, scan_en, so and si to the waveform. From this
waveform we can find that si is like 0011 pattern format and so is 1100 pattern
format. So there is an error occurred.

Consider so [0] with corresponding input value si [0]. Here so is ‘1’ and si is ‘0’, so a
mismatch is occurred at 2370ns. We add s0 [0] pin to schematic for tracing.

First we found a lockup latch and add lockup latch signals Q, D, CLK and check.

DFT-5 Page 56
 Async_fifo

Here, Q and D is fine. It will operate the neg-edge of clock, at the neg-edge it seen 1.
Then we trace back through D and we found a FF as SFF. Add SFF signals SE, SI,
CLK, Q and we are trace back through SI path.

In SFF-57[2], SI is one at the posedge Q also one, so 1 cycle delay is there. Then trace
back through SI in schematic. We keep on the trace back and while we reach at SFF-
57[3] we found a mismatch.

2. Stuck_at chain parallel Simulation debug

rm -rf work
vlib work

vlog adk.v
vlog SCAN_INSERTED.vg
vlog ./stuck_chain_parallel.v

vsim -debugDB -c -voptargs="+acc" a_fifo_stuck_chain_parallel_v_ctl -l

sims_chain_parallel_batch.log +nospecify +nowarmTSCALE -do "run -all"

DFT-5 Page 57
 Async_fifo
vsim -debugDB -gui -voptargs="+acc" a_fifo_stuck_chain_parallel_v_ctl -l
sims_chain_parallel.log +nospecify +nowarmTSCALE

Note: here, In stuck_at chain parallel simulation it shows that there is no error
between simulated and expected patterns. So in this case there is no need of
simulation debugging.

3. Stuck_at scan serial Simulation debug

rm -rf work

vlib work
vlog adk.v

vlog SCAN_INSERTED.vg
vlog ./stuck_scan_serial.v

vsim -debugDB -c -voptargs="+acc" a_fifo_stuck_scan_serial_v_ctl -l

sims_scan_serial.log +nospecify +nowarmTSCALE -do "run -all"
vsim -debugDB -gui -voptargs="+acc" a_fifo_stuck_scan_serial_v_ctl -l
sims_scan_serial.log +nospecify +nowarmTSCALE
DFT-5 Page 58
 Async_fifo

Note: From this transcript we get scan chain output, time of mismatch in ns, pattern
number and simulated and expected value. Here I am considering 5490ns mismatch
ts_so[4] with simulated 1 and expected 0. First we adding pattern count, w_clk, r_clk,
scan_en and so[4] signals to the waveform.

DFT-5 Page 59
 Async_fifo

Set the cursor to 5490ns to show where the mismatch is present.

From this we found that at 5490ns output of so [4] is 1. Here the mismatch is
happened at the 23 rd unloading and we can find the flop name from this by using
scan cell report which we generated at the atpg.
We want to compare this value of simulated 1 with expected value 0 of atpg patterns.
For comparing this we need an ATPG flat model.

Command for ATPG: By Using the ATPG Flat model, we compare simulated value
with expected value of ATPG.

tessent -shell -log stuck_scan_debug.log

set_context patterns -scan
read_flat_model a_fifo_netlist.flat_stuckat.gz // this is get from ATPG pattern
generation

read_patterns stuck_scan_parallel.stil // stil(pattern) file which already generated into

the testbench file to help understanding testbench file which patterns we want to
simulate.

report_scan_cells > scan_cells.rpt

From the ATPG scan_cells report we get Flipflop register name. At the wave we
found that mismatch happened at 23rd unloading and in scan_cells report we take
number 22 because it is starting from 0. here we have 54 loading and unloading cycle
(0-53). So from chain4-22 we get FF name as f_memory_reg[33][0].

DFT-5 Page 60
 Async_fifo

open_vis

By using the visualiser Instance browser we load the f_memory_reg[33][0]. Set the
gate report, external pattern as 1.

DFT-5 Page 61
 Async_fifo

Note: Here, the expected value Q is 0.

Add the signals of FF to waveform. Signals like D, SI, SE, CLK, Q, and QB.

DFT-5 Page 62
 Async_fifo

4. Stuck_at scan parallel Simulation debug

rm -rf work
vlib work

vlog adk.v
vlog SCAN_INSERTED.vg
vlog ./stuck_scan_parallel.v

vsim -debugDB -c -voptargs="+acc" a_fifo_stuck_scan_parallel_v_ctl -l

sims_verilog_parallel.log +nospecify +nowarmTSCALE -do "run -all"

vsim -debugDB -gui -voptargs="+acc" a_fifo_stuck_scan_parallel_v_ctl -l

sims_verilog_parallel.log +nospecify +nowarmTSCALE

DFT-5 Page 63
 Async_fifo

Note: In parallel simulation it directly shows which flop is failing. Here consider
\f_memory_reg[63][6] at chain0, 14 th pattern. In this at Q is simulated ‘0’ and
expected ‘1’.

Note: In parallel simulation through SI we loading the data and Q we are strobing.

DFT-5 Page 64
 Async_fifo

By using atpg we compare our simulated data with expected one.

Note: At atpg we found a buffer from the SI pin but in the simulator schematic a NOT
gate is coming from corresponding SI pin. So the error is happened due to the NOT
gate.

DFT-5 Page 65
 Async_fifo

Note: A NOT gate, often called an inverter is a digital logic gate. A NOT gate
performs logical negation on its input that is, if the input is true, then the output will
be false. Similarly, a false input results in a true output.

5. ATspeed-loc scan serial Simulation debug

rm -rf work
vlib work
vlog adk.v

vlog SCAN_INSERTED.vg
vlog ./loc_scan_serial.v
vsim -debugDB -c -voptargs="+acc" a_fifo_loc_scan_serial_v_ctl -l
sims_scan_loc_serial.log +nospecify +nowarmTSCALE -do "run -all"
vsim -debugDB -gui -voptargs="+acc" a_fifo_loc_scan_serial_v_ctl -l
sims_scan_loc_serial.log +nospecify +nowarmTSCALE &

DFT-5 Page 66
 Async_fifo
Note: From the x-terminal also we can find the mismatch

Note: Here, consider ts_so[0] at 2370ns and it shows simulated 1 at first unloading cycle.

First unloading cycle means 0 cell, because here the value is starts from 0-53 and
from this we get flop name.

DFT-5 Page 67
 Async_fifo

From the atpg shows that it expect o value.

DFT-5 Page 68
 Async_fifo

6. ATspeed-loc scan parallel Simulation debug

rm -rf work
vlib work

vlog adk.v
vlog SCAN_INSERTED.vg

DFT-5 Page 69
 Async_fifo
vlog ./loc_scan_parallel.v

vsim -debugDB -c -voptargs="+acc" a_fifo_loc_scan_parallel_v_ctl -l

sims_scan_loc_parallel.log +nospecify +nowarmTSCALE -do "run -all"
vsim -debugDB -gui -voptargs="+acc" a_fifo_loc_scan_parallel_v_ctl -l
sims_scan_loc_parallel.log +nospecify +nowarmTSCALE &

DFT-5 Page 70
 Async_fifo

Note: A buffer is presented at the atpg visualiser of f_memory_reg[23][3] SI pin.

DFT-5 Page 71
 Async_fifo

Conclusion: For simulation debugging we are using different library format when
compared to atpg pattern generation. From the atpg visualizer we find a buffer in
between the top level scan input and the first flop of every scan chains but when comes to
simulation the buffer act as a NOT gate (an inverter). So the mismatch is happened due
to this NOT gate.

DFT-5 Page 72
 Async_fifo

8. CONCLUSION

In this project, we will insert scan to some digital core and then stitching the scan cells together
into scan registers, or scan chains. Then use these scan cells to shift data in and out when the
design is in scan mode. Further, the scan compression technique is used to scan cells which
reduces the test time and tester memory in whole test cost without loss in the test coverage.
After that, develop an algorithm and run ATPG to create patterns. Then build a test model that
simulates scan test and test the chip with various vectors. Finally debug the simulation
mismatches.

DFT-5 Page 73
 Async_fifo

THANK
YOU…

DFT-5 Page 74