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Jagadeesh Kurumilli – 406

V S Kiran Pemmanaboidi - 417

§ DRV constraints exist in .lib.

§ DRV constraints can’t be relaxed. They can be chosen from .lib. These constraints are imposed upon the design

by requirements specified in the target technology library.

§ These precedence over optimization constraints to realize a functional design.

DRV Constraints are :

q Max Transition

q Max Capacitance

q Max Fan-out

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§ Set a max transition time on ports or design .

§ If any path having larger transition which are greater than defined max_transition value, then it reports max

transition violation.

§ Command to set max transition value is

set_max_transition

§ Specifies the maximum output capacitance of a cell.

§ The maximum capacitance(CL) of a cell is the sum of output pin capacitance of the driver, net capacitance
and input pin capacitance of the driven cell.

CL = Cdriver + Cnet + Cdriven

§ If any path having larger capacitance which are greater than defined max_capacitance value, then it reports
max capacitance violation.

§ Command to set max capacitance value is

§ set_max_capacitance

§ Set_max_capacitance provides an opportunity to directly specify and control the output capacitance which

indirectly controls transition. So it is enough to specify either of these.

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§ The number of loads a pin or port can drive.

§ Limits the number of components that can be driven by the input port.

§ It is useful for signals that drive many blocks (e.g. global buses,reset).

§ Fanout can be reduced by Cloning (or) Buffering.

§ Upsizing

§ Buffer Insertion

§ Logic Restructuring

§ VT Swapping

§ Cloning

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q Timing Optimization Techniques

§ Upsizing
q Power Optimization Techniques.
§ Insertion of buffers
§ Pin swapping
§ VT Swapping
§ Logic restructuring
§ Down sizing
§ Cloning(or) Load splitting
§ Logic restructuring
§ VT Swapping
§ Clock gating(to minimize the dynamic power
q Area Optimization Techniques dissipation)
§ Multi VDD technique
§ Down sizing
§ Logic Restructuring

§ Upsizing is nothing but increasing the drive strength.

§ By this delay gets reduced.

§ Area and Power is increased.

§ It is used to fix the following violations:

q Setup
q Max Transition by making transitions sharper.
q Max Capacitance by increasing the load.

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§ Downsizing refers to decrease in the drive strength.

§ By this delay gets increased.

§ It is used to fix the hold violations.

§ By downsizing we can claim area as well as power.

§ Buffer Insertion has been an optimization technique widely used to increase the performance of the advanced VLSI

digital circuits and systems.

§ Generally we use this technique when the net delay is more.

§ Insertion of buffer requires extra area and power.

§ Buffer Insertion is used to fix :

q Setup

q Max Transition

q Max Capacitance

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§ Logic Restructing is a technique in which the logic is optimized to decrease the no. of gates without the

change in logic.

§ It is used to fix the timing violations.

§ And also to claim the area, thereby reduce power.

§ Cloning is a optimization technique where a driver cell is duplicated , so that the total fanout is splitted

among the two cells.

§ If the max_fanout is 2, then the total number of buffers are splitted among the two buffers.

§ It is used to fix the max_fanout, thereby fixes timing.

§ Because of added buffer area and power are increased.

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§ Pin Swapping is a timing optimization technique in which the input pins of a gate or a cell is swapped in such

a way that,

q High switching net is swapped with low capacitive pin.

q Low switching net with high capacitive pin.

§ Multi is an optimization technique in which different sources of power supplies are given in the
design.
§ We can observe from the below figure one block is using VDD1 and other is using VDD2, which are
in the same design.

§ By using this technique power can be optimized.

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§ Generally VT Swapping is used for optimizing both power and timing.

§ By using this technique for optimization, the area remains unchanged.

q For Timing :
§ If the design is timing constrained, then we use HVT cells for the design.
§ For the timing critical paths we swap,
HVT with SVT
(or)
SVT with LVT
q For Power :
§ If it is a low power design, then we use LVT cells for the design.
§ For high switching cells we swap,
LVT with SVT
(or)
SVT with HVT

§ Clock gating limits the clock from being given to every register or flops in the processor. It disables the clock of an

unused device.

§ It is used for reducing DYNAMIC POWER by controlling switching activities on the clock path.

§ Generally gate or latch or flip flop based block gating cells are used for implementing clock gating.

§ 50% of dynamic power is due to clock buffer. Since clock has highest toggle rate and often have higher drive strength

to minimize clock delay. And the flops receive clocks dissipates some dynamic power even if input and output remains
the same. Also clock buffer tree consumes power. One of the techniques to lower the dynamic power is clock gating.

§ We can find these Clock Gating cells in .lib file.

§ Command for inserting clock gating is

set_db/ .lp_insert_clock_gating true

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§ In load enabled flops, the output of the flops switches only when the enable is on. But clock switches continuously,

increasing the dynamic power consumption.

glitch

§ By converting load enable circuits to clock gating circuit dynamic power can be reduced. Normal clock gating

circuit consists of an AND gate in the clock path with one input as enable. But when enable becomes one in
between positive level of the clock a glitch is obtained.

§ To remove the glitches due to AND gate, integrated clock gate is used. It has a negative triggered latch and an AND

gate.

Glitch free Gated Clock

clock

ICG

CLK

En

Gated CLK

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