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Mathematics and Computers in Simulation xxx (2012) xxx–xxx

Original article

Optimized FPGA design, verification and implementation of a

neuro-fuzzy controller for PMSM drives
Hsin-Hung Chou a , Ying-Shieh Kung b,∗ , Nguyen Vu Quynh b , Stone Cheng a
a Department of Mechanical Engineering, National Chiao-Tung University, 1001 University Road, East District, Hsinchu City 300, Taiwan, ROC
b Department of Electrical Engineering, Southern Taiwan University, 1 Nan-Tai Street, Yong-Kang District, Tainan City 710, Taiwan, ROC

Received 24 October 2011; received in revised form 22 June 2012; accepted 23 July 2012

Abstract
The work presents a neural fuzzy controller (NFC) for speed loop of permanent synchronous motor (PMSM) drives based on
the technology of field programmable gate array (FPGA). Firstly, a mathematic model of the PMSM drive is derived; then to
increase the performance of the PMSM drive system, a fuzzy controller (FC) which its parameters are adjusted by a radial basis
function neural network (RBF NN) is applied to the speed controller for coping with the effect of the system dynamic uncertainty.
Secondly, very high speed IC hardware description language (VHDL) is adopted to describe the behavior of the speed controller
of PMSM drives which includes the circuits of space vector pulse width modulation (SVPWM), coordinate transformation, NFC,
etc. Besides, to reduce the resource usage while implementing in field programmable gate array (FPGA), a sequential execution
using finite state machine (FSM) is applied. Thirdly, based on electronic design automation (EDA) simulator link, a simulation
work is constructed by MATLAB/Simulink and ModelSim co-simulation mode which the PMSM, inverter and speed command
are performed in Simulink as well as the speed controller of PMSM drives is executed in ModelSim. Finally, some co-simulation
results validate the effectiveness of the proposed NFC-based speed controller for PMSM drives.
© 2012 IMACS. Published by Elsevier B.V. All rights reserved.

Keywords: PMSM; Neural fuzzy control; VHDL; FPGA; ModelSim; Finite state machine; Simulink; Co-simulation

1. Introduction

PMSM has been increasingly used in many automation control fields as actuators, due to its advantages of superior
power density, high-performance motion control with fast speed and better accuracy. But in industrial applications,
there are many uncertainties, such as system parameter uncertainty, external load disturbance, friction force, and
unmodeled uncertainty, which always diminish the performance quality of the pre-design of the motor driving system.
To cope with this problem, in recent years, many intelligent control techniques [1,5,7,11,17], such as fuzzy control,
adaptive PID control, neural networks control, adaptive fuzzy control and other control method, have been developed
and applied to the speed control of servo motor drives to obtain high operating performance. Although fuzzy control
has been successfully applied in several industrial automation, however, it is not an easy task to obtain an optimal set
of fuzzy membership functions and rules in FC. In this paper, a neural fuzzy controller (NFC) is proposed which RBF

∗
Corresponding author.
E-mail addresses: [email protected] (H.-H. Chou), [email protected] (Y.-S. Kung), [email protected] (N. Vu Quynh),
[email protected] (S. Cheng).

0378-4754/$36.00 © 2012 IMACS. Published by Elsevier B.V. All rights reserved.

http://dx.doi.org/10.1016/j.matcom.2012.07.012

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NN is firstly used to real-time identify the plant dynamic (Jacobian transformation term: (∂ωr /∂i∗q )) and provided more
accuracy plant information; then based on the gradient descent method and the real-time identified plant information,
parameters of FC can be tuned to a near-optimal condition.
In implementation, although the execution of NFC requires many computations, FPGA can provide a solution in
this issue. Especially, FPGA with programmable hard-wired feature, fast computation ability, shorter design cycle,
embedding processor, low power consumption and higher density is very suitable for the implementation of the
digital system [14–16]. Although the digital signal processor (DSP) is another solution to provide a flexible skill in
the intelligent control technique, it suffers from a long period of development and exhausts many resources of the
CPU [18]. However, FPGA implementation of a RBF NN has been developed in literatures [2,6]. Brassai et al. [2]
applied the RBF NN in the area of robotics and control. The computations of neurons in hidden layer of RBF NN and
weight adaption module adopt typical parallel implementation on FPGA. In addition, table look up method is used to
develop the activation function. Kim et al. [6] firstly develop a floating-point processor on FPGA. Then based on this
floating-point processor, a microprogram is written to implement the RBF NN with on-line learning back-propagation
algorithm. The Taylor series is considered to compute the Gaussian function. However, a floating-point processor
consumes FPGA resources and the executing speed might be slow. Further, in the hardware realization of an intelligent
control algorithm, except the parallel processing method, the sequential execution method is alternative. The former
method with continuous and simultaneous operation has the advantage of fast computation ability, but consumes much
more FPGA resources. The latter method separates the overall computation with several steps and the resources with
same function in each step will be common use; therefore it can greatly save much FPGA resources. In this paper,
a method mixed with parallel processing and sequential execution is adopted to compute the NFC algorithm. Except
that the computation of neurons in the hidden layer of RBF NN is applied by the parallel processing method, others
computation, such as the Gaussian function, weight adaption module and Jacobian function in RBF NN as well as
the fuzzy control algorithm are all presented by the sequential execution method. Although the sequential execution
method needs to spend more computation time, it does not loss any control performance due to the fast computation
power in FPGA. In this paper, finite state machine (FSM), which behavior is easy to describe by VHDL, is applied to
model the computation process of sequential execution method.
Recently, a co-simulation work by electronic design automation (EDA) simulator link has been gradually applied to
verify the effectiveness of the Verilog and VHDL code in the motor drive system [3,4,8–10]. The EDA simulator link
[12] provides a co-simulation interface between MALTAB or Simulink and HDL simulators-ModelSim [13]. Using
it you can verify a VHDL, Verilog, or mixed-language implementation against your Simulink model or MATLAB
algorithm [12]. Therefore, EDA simulator link lets you use MATLAB code and Simulink models as a test bench that
generates stimulus for an HDL simulation and analyzes the simulation’s response [12]. In this paper, a co-simulation
by EDA simulator link is applied. The PMSM, inverter and speed command are performed in Simulink and the NFC-
based speed controller described by VHDL code is executed in ModelSim. Finally, some simulations results validate
the effectiveness of the proposed NFC-based speed controller of PMSM drives.

2. System description of PMSM drive and speed controller design

The simulation architecture of NFC-based speed control for PMSM drive is shown in Fig. 1. The modeling of
PMSM and the algorithm of the neural fuzzy controller are introduced as follows.

2.1. Mathematical model of PMSM

The typical mathematical model of a PMSM is described, in two-axis d–q synchronous rotating reference frame,
as follows
did Rs Lq 1
= − id + ω e iq + vd (1)
dt Ld Ld Ld

diq Ld Rs λf 1
= −ωe id − iq − ω e + vq (2)
dt Lq Lq Lq Lq

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Fig. 1. The simulation architecture of NFC-based speed control for PMSM drive.

where vd and vq are the d and q axis voltages; id and iq , are the d and q axis currents; Rs is the phase winding resistance;
Ld and Lq are the d and q axis inductance; ωe is the rotating speed of magnet flux; and λf is the permanent magnet flux
linkage.
The current loop control of PMSM drive in Fig. 1 is based on a vector control approach. That is, if the id is
controlled to 0 in Fig. 1, the PMSM will be decoupled and controlling a PMSM like to control a DC motor. Therefore,
after decoupling, the torque of PMSM can be written as the following equation,
3P
Te = λ f iq  K t i q (3)
4
with
3P
Kt = λf (4)
4
Considering the mechanical load, the overall dynamic equation of PMSM drive system is obtained by
d
Jm ω r + B m ωr = Te − TL (5)
dt
where Te is the motor torque, Kt is torque constant, Jm is the inertial value, Bm is damping ratio, TL is the external
torque, and ωr is rotor speed.

2.2. Design of neural fuzzy controller (NFC)

The dash rectangular area in Fig. 1 presents the architecture of an NFC for the PMSM drive. It consists of a FC, a
reference model and a RBF NN based parameter adjusting mechanism. Detailed description of these is as follows.

2.2.1. Fuzzy controller (FC)

The FC in this study uses singleton fuzzifier, triangular membership function, product-inference rule and central
average defuzzifier method. In Fig. 1, the tracking error e and the error change de are defined by
e(k) = ωm (k) − ωr (k) (6)
de(k) = e(k) − e(k − 1) (7)
where uf represents the output of the FC and ωm is the output of reference model. The design procedure of FC algorithm
is as follows. Firstly, the linguist value of E and dE are {A0 , A1 , A2 , A3 , A4 , A5 , A6 } and {B0 , B1 , B2 , B3 , B4 , B5 , B6 },

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μ(e) Input of e (for i=3)

A0 A1 A2 A3 A4 A5 A6
1
μA4(e)=1- μA3(e)

μB2(de)=1- μB1(de)
μA3(e)
e
-e3 -e2 -e1 0 e1 e2 e3
e

μB1(de)
E A A1 A2 A3 A4 A5 A6
μ(de) 0

1
dE

0 -de1 -de2 -de3

B0
B1 B0 c00 c01 c02 c03 c04 c05 c06

B1 c10 c11 c12 c13 c14 c15 c16

Input of de (for j=1)

de
c20 c21 c22 c23 c24 c25 c26
B2

B2

c30 c31 c32 c33 c34 c35 c36

B3

B3

c40 c41 c42 c43 c44 c45 c46

de2 de1
B4

B4

c50 c51 c52 c53 c54 c55 c56

B5

B5

B6 c60 c61 c62 c63 c64 c65 c66

de3
B6

Fuzzy Rule Table

de

Fig. 2. The symmetrical triangular membership function of e and de and fuzzy rule table.

respectively. Each linguist value of E and dE is based on the symmetrical triangular membership function, which is
shown in Fig. 2. Secondly, the computation of the membership degree for e and de are done. Fig. 2 shows that the only
two linguistic values are excited (resulting in a non-zero membership) in any input value, and the membership degree
is obtained by
ei+1 − e
μAi (e) = and μAi+1 (e) = 1 − μAi (e) (8)
ei+1 − ei
Similar results can be obtained in computing the membership degree μBj (de). Thirdly, the selection of the initial
FC rules refers to the dynamic response characteristics, such as,

IF e is Ai and e is Bj THEN uf is cj,i , (9)

where i and j are from 0 to 6, Ai and Bj are fuzzy numbers, and cj,i is the real number. Finally, to construct the fuzzy
system uf (e, de), the singleton fuzzifier, product-inference rule, and central average defuzzifier method is adopted.
Although there are total 49 fuzzy rules in Fig. 2 will be inferred, actually only 4 fuzzy rules can be effectively excited
to generate a non-zero output. Therefore, if an error e is located between ei and ei+1 , and an error change de is located
between dej and dej+1 , only four linguistic values Ai , Ai+1 , Bj , Bj+1 and corresponding consequent values cj,i , cj+1,i ,
cj,i+1 , cj+1,i+1 can be excited, and the output of the fuzzy system can be inferred by the following expression:
i+1 j+1
n=i m=j cm,n [μAn (e) × μBm (de)]

i+1 
j+1
uf (e, de) = i+1 j+1  cm,n × dn,m (10)
n=i m=j μAn (e) × μBm (de) n=i m=j

where dn,m  μAn (e) × μBm (de). And those cm,n are adjustable parameters. In addition, by using (8), it is straightforward
 j+1
to obtain i+1
n=i m=j dn,m = 1 in (10).

2.2.2. Radial basis function neural network (RBF NN)

The RBF NN adopted here is a three-layer architecture which is shown in Fig. 3 and comprised of one input layer,
one hidden layer and one output layer.

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ωr (k )
h1 enn +

w1 -
iq* ( k )
h2
ωr (k − 1) w2 Σ ωrbf
wp
ωr (k − 2) hp

Input layer Hidden layer Output layer

Fig. 3. The architecture of RBF NN.

The RBF NN has three inputs by i∗q (k), ωr (k − 1), ωr (k − 2) and its vector form is represented by

X = [i∗q (k), ωr (k − 1), ωr (k − 2)]T (11)

Furthermore, the multivariate Gaussian function is used as the activated function in hidden layer of RBF NN, and its
formulation is shown as follows.
 
||X − cr ||2
hr = exp − , r = 1, 2, 3, 4, . . . p (12)
2σr2
where cr = [cr1 , cr2 , cr3 ]T , p is the number of neuron in hidden layer, σ r denotes the node center and node variance of
rth neuron, and ||X − cr || is the norm value which is measured by the inputs and the node center at each neuron. And
the network output in Fig. 3 can be written as

p
ωrbf = wr h r (13)
r=1
where ωrbf is the output value; wr and hr are the weight and output of rth neuron, respectively.
The instantaneous cost function is defined as follows.
1 1
J = (ωrbf − ωr )2  e2nn (14)
2 2
According to the gradient descent method, the learning algorithm of weights, node center and variance are as follows:
wr (k + 1) = wr (k) + ηenn (k)hr (k) (15)
Xs (k) − crs (k)
crs (k + 1) = crs (k) + ηenn (k)wr (k)hr (k) (16)
σr2 (k)
||X(k) − cr (k)||2
σr (k + 1) = σr (k) + ηenn (k)wr (k)hr (k) (17)
σr3 (k)
where r = 1,2,. . .p, s = 1, 2, 3 and η is a learning rate. Further, the (∂ωr /∂i∗q ) is Jacobian transformation and can be
derived from Fig. 3 and (12)
∂ωr ∂ωrbf  p
cr1 − i∗q (k)
≈ = w r h r (18)
∂i∗q ∂i∗q σr2
r=1

2.2.3. Reference model (RM)

Second order system as follows is usually considered as the RM in the adaptive control system
ωm (s) ωn2
∗
= 2 (19)
ωr (s) s + 2ςωn s + ωn2

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where ωn is natural frequency and ς is damping ratio. Furthermore, applying the bilinear transformation, (19) can be
transformed to a discrete model by
ωm (z−1 ) θ0 + θ1 z−1 + θ2 z−2
= (20)
ωr∗ (z−1 ) 1 + φ1 z−1 + φ2 z−2
and the difference equation is written as.
ωm (k) = −φ1 ωm (k − 1) − φ2 ωm (k − 2) + θ0 ωr∗ (k) + θ1 ωr∗ (k − 1) + θ2 ωr∗ (k − 2) (21)

2.2.4. Adjusting mechanism of FC

The gradient descent method is used to derive the NFC learning law in Fig. 1. The adjusting mechanism of FC
parameters is to minimize the square error between the rotor speed and the output of the reference model. The
instantaneous cost function is firstly defined by
1 2 1
Je  e = (ωm − ωr )2 (22)
2 2
and the parameters of cm,n are adjusted according to
∂Je ∂Je
cm,n ∝ − = −α (23)
∂cm,n ∂cm,n
where α represents learning rate. Secondly, the chain rule is used, and the partial differential equation for Je in (22)
can be written as
∂Je ∂ωr ∂uf
= −e (24)
∂cm,n ∂uf ∂cm,n
Further, from (10) and using the Jacobian formulation from (18), we can, respectively, get
∂uf (k)
= dn,m (25)
∂cm,n (k)
and,
∂ωr ∂ωrbf  cr1 − i∗q (k)
p
≈ (KP + Ki ) ∗ = (KP + Ki ) wr hr (26)
∂uf ∂iq σr2
r=1

Therefore, substituting (25) and (26) into (24), the parameters cm,n of fuzzy controller described in (10) can be adjusted
by the following expression.

p
cr1 − i∗q (k)
cm,n (k) = αe(k)(Kp + Ki )dn,m w r hr (27)
σr2
r=1

with m = j, j + 1 and n = i, i + 1.

3. Design of FPGA-based speed controller for PMSM drive

The internal architecture of the proposed FPGA-based speed controller for PMSM drive is shown in Fig. 4. The
inputs of this controller are speed command ωr∗ , rotor speed ωr , flux angle θ e , measured three-phase currents (ia ,
ib , ic ), and the output is PWM command. The speed controller mainly includes a NFC-based speed controller, a
current controller and coordinate transformation (CCCT), a SVPWM generation, frequency divider, etc. The sampling
frequency of current and speed control is designed with 16 kHz and 2 kHz, respectively. The input clock is 50 MHz and
the frequency divider generates 50 MHz (Clk) and 12.5 MHz (Clk-step) clock to supply all modules of the FPGA-based
speed controller. All modules in Fig. 4 are described by VHDL and simulated in ModelSim. The FPGA resource usages
of CCCT, SVPWM and NFC controller in Fig. 4, with the example of Altera – Cyclone EP2C70, need 647 LEs (logic
elements) and 196,608 RAM bits, 1200 LEs and 0 RAM bit, 13,806 LEs and 0 RAM bit, respectively. The circuit

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FPGA-Based Speed Controller

Clk
ModelSim Clk-step Frequency CK
divider
Clk
Clk
Clk-step ia [11..0]
Clk-step
NFC iq* [11..0] ib [11..0]
ωr* [15..0] controller ic [11..0]
ωr [15..0] Current controllers
Clk and coordinate
Clk-sp transformation
PWM 1
PWM 2 SVPWM v ref 1 [11..0] (CCCT)
PWM 3
PWM 4 v ref 2 [11..0] θe [11..0]
PWM 5
generation
PWM 6 v ref 3 [11..0]

Fig. 4. Internal circuit of the proposed FPGA-based speed controller for PMSM drive.

designs of CCCT and SVPWM refer to [7]. The following paragraphs focus on the description of circuit design in
NFC with detail.

3.1. Finite state machine (FSM) method

To reduce the use of the hardware resource, finite state machine (FSM) is adopted to model the computing process
of algorithm. Herein, the computation of the sum of product (SOP) shown below is taken as an example to present the
advantage of FSM.
Y = a1 × x1 + a2 × x2 + a3 × x3 (28)
Two kinds of design method are presented to realize the computation of SOP. There are parallel processing method and
sequential execution method. Parallel processing with the designed SOP circuit is shown in Fig. 5(a), which will operate
continuously and simultaneously. The SOP circuit requires 2 adders, 3 multipliers, and merely near one clock time
to complete the overall computation. With the advantage of fast computation ability, the parallel processing method,
however, consumes much more FPGA resources. To solve this problem, a sequential execution method using FMS to
model SOP circuit is adopted and shown in Fig. 5(b). The FSM method uses one adder, one multiplier and manipulates
5 steps (or 5 clocks time) machine to carry out the overall computation of SOP. Compared to parallel processing
method, the FSM method requires more operation time (if one clock time is 80 ns, 5 clocks needs 0.4 ␮s) in executing
SOP circuit; nevertheless, it does not loss any computation power. As a result, the more complicated computation in
algorithm, the more FPGA resources will be saved by applying FSM method. Besides, the state diagram in Fig. 5(a)
is easy to be described by VHDL.

(a) (b) x1
a1
x1 x a1
x +
+ a2
x
a2 y
x2 x + y x3 +
x2
a3
a3 x
x3 x s0 s1 s2 s3 s4

Fig. 5. Computation of SOP by using (a) parallel operation and (b) sequential execution method using FMS.

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hr = 0
a12 a11 r a10 r a9 r a8 r a7 r
Y
N r y1
u u≥4 SR(2) x + x + x + x + x + x

s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12

a6 r a5 r a4 r a3 r a2 r a1 r a0
y1 hr
+ x + x + x + x + x + x + SL(4)

s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27

Fig. 6. State diagram of an FSM for describing the exponential function.

3.2. Behavior description of exponential function

According to the architecture of hidden layer in RBF NN in (12), it needs to compute the exponential function and
is defined as follows
 
||X − cr ||2
hr = exp −  exp(−u) (29)
2σr2
To simplify the computation, the input of exponential function is limited within 0–4 because if u ≥ 4 the output
hr ≤ exp(− 4) = 0.0183 will approximate to zero, otherwise if 0 ≤ u < 4, (29) can be computed by using Taylor expansion
series.
∝
 n 
12
nu un
hr = exp(−u) = (−1) ≈ (−1)n (30)
n! n!
n=0 n=0
The 12th order is selected in (30). To normalize the input value, we define (r = u/4) and to avoid the numerical overflow
condition during computation, (30) is divided by 16. Therefore, (30) becomes

exp(−4r)  4n−2 r n
12  12
hr = 16 ≈ 16 (−1)n  16 an r n (31)
16 n!
n=0 n=0

where an (−1)n (4n−2 /n!) by a0 = 0.00625, a1 = − 0.25, . . ., a12 = 0.00218909.

Sequential execution is herein adopted to evaluate the polynomial of degree twelve in (31), and we transfer the form
of (31) as follows for easy sequential computation.
hr = 16((((((((((((a12 r + a11 )r + a10 )r + a9 )r + a8 )r + a7 )r + a6 )r + a5 )r + a4 )r + a3 )r (32)
+ a2 )r + a1 )r + a0 )
FSM is employed to model the polynomial form in (32) and it is shown in Fig. 6, which uses one adder, one multiplier,
one comparator and two shifters as well as manipulates 28 steps machine to carry out the overall computation. The
SR(2) and SL(4) in Fig. 6 represent right shift with 2-bit and left shift with 4-bit, respectively. The multiplier and adder
apply Altera LPM (library parameterized modules) standard. The FSM can be easily described by VHDL. Moreover,
the operation of each step in Fig. 6 can be completed within 80 ns (12.5 MHz clock); therefore total 28 steps only need
2.24 ␮s operational times.

3.3. Behavior description of a neuron in RBF NN

After describing the behavior of exponential function, we further apply it in the behavior description of computing
a neuron in RBF NN. In each neuron in Fig. 3, it needs to perform the function of computing the mutivariate Gaussian

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− cr 1 η
d1 hr
iq* ( k ) + x wr x wr
− cr 2
norm or
d2 u hr lhe
ωr ( k − 1 ) + x + + ÷ exp( • ) x enn x + wr
− cr 3
d3
ωr ( k − 2 ) + x
σ r2 − d1 ÷ x Jr σ r2 x σ r3
σr x SL (1)
σ r2 σr

s0 s1 s2 s3 s4 s5 s6~s33 s34 s35 s36 s37 s38

Computation of norm value by the inputs Outputs of RBF NN and Jacobian Update the weight
and node centers at rth neuron value

wr cr 2
σr lhew
lhew
lhe x x + σr lhew
cr 1
d2 ÷ x + cr 2 lhew cr 3

norm ÷ d1 ÷ x + cr1 σ r2 d3 ÷ x + cr 3

σ r3 σ r2 σ r2

s39 s40 s41 s42 s43 s44 s45 s46 s47 s48 s49 s50 s51

Update the variance Update the node center

Fig. 7. State diagram of an FSM for describing rth neuron computation in RBF NN.

function in (12), individual network output in (13), individual Jacobian value in (18) and individual parameters learning
in (15)–(17). According to this requirements, FSM for describing rth neuron computation in RBF NN is presented in
Fig. 7 which the inputs are i∗q (k), ωr (k − 1), ωr (k − 2) and outputs are Or (individual network output) and Jr (individual
Jacobian value). Further, in Fig. 7, steps s0 –s5 execute the computation of norm value; steps s6 –s35 describe the
computation of exponential function and the outputs of individual network output and Jacobian value; steps s36 –s38 are
the weight update; steps s39 –s41 are the variance update and s42 –s51 are the node center update. The operation of each
step in Fig. 7 can be completed within 80 ns (12.5 MHz clock); therefore total 52 steps only need 4.16 ␮s operational
times. In Fig. 7, except exponential function, the divider is also a complicated component in hardware implementation.
Herein, we directly adopt Altera LPM standard to realize it. Fig. 8 shows a VHDL example to describe the divider
computation of Y = A/B. The data format of two inputs A, B and one output Y all belong to the 16 bits, Q15 and signed
number. The divider component adopts 32 bits operation with signed representation. The inputs A, B firstly need to
sign-extension to 32 bits, then sent to the divider component and obtain a 32 bits output of sat. Finally, the divider
output of Y is extracted from 16th bit down to 1st of sat. The resource usage of a 32 bits divider component in Fig. 8,
with the example of Altera – Cyclone EP2C70, needs 980 LEs.

3.4. Behavior description of NFC

After describing the behavior of a neuron in RBF NN, we further apply it in the behavior description of computing
a NFC. In the proposed system, the number of neuron in hidden layer is chosen by three. The FSM employed to model
the NFC-based speed controller is shown in Fig. 9, which uses one adder, one multiplier, three neuron computational
blocks (the detail for each one is shown in Fig. 7), some registers, etc. and manipulates 92 steps machine to carry out the
overall computation. The data types are designed with 16-bit length, two complements and Q15 format. The multiplier

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LIBRARY IEEE; GEN:BLOCK

USE IEEE.std_logic_1164.all; BEGIN
USE IEEE.std_logic_arith.all; PROCESS(CLK_D)
USE IEEE.std_logic_signed.all; BEGIN
LIBRARY lpm; IF clk_D'EVENT and clk_D='1' THEN
USE lpm.LPM_COMPONENTS.ALL; CNT<=CNT+1;
IF CNT=X"00" THEN
ENTITY Devider IS
devideA<=A&X"0000";
port ( clk,clk_D : IN STD_LOGIC;
IF B(15)='0' THEN
A,B : IN STD_LOGIC_VECTOR(15 downto 0);
devideB<=X"0000"&B;
Y : OUT STD_LOGIC_VECTOR(15 downto 0) );
ELSE
END Devider;
devideB<=X"FFFF"&B;
ARCHITECTURE Devide_arch OF Devider IS END IF;
SIGNAL devideA,devideB :STD_LOGIC_VECTOR(31 downto 0); ELSIF CNT=X"01" THEN
SIGNAL sat :STD_LOGIC_VECTOR(31 downto 0); Y<=sat(16 downto 1);
SIGNAL CNT :STD_LOGIC_VECTOR(7 downto 0); CNT <=X"00";
BEGIN END IF;
m1: lpm_divide END IF;
GENERIC END PROCESS;
MAP (LPM_WIDTHN=>32, LPM_WIDTHD=>32, LPM_PIPELINE=>1, END BLOCK GEN;
LPM_NREPRESENTATION=>"SIGNED", LPM_DREPRESENTATION=>"SIGNED") END Devide_arch;
PORT MAP (numer=>devideA,denom=>devideB,clock =>clk,quotient=>sat);

Fig. 8. Example of divider computation using VHDL.

and adder apply Altera LPM standard. Although the algorithm of the NFC is high complexity, the FSM can give a
very adequate modeling and easily be described by VHDL. In Fig. 9, steps s0 –s5 execute the computation of reference
model output; steps s6 –s7 are for the computation of speed error and error change; steps s8 –s12 execute the fuzzification
and look-up fuzzy table; s13 –s21 are for the defuzzification; s22 –s25 are the computation of current command; s26 –s81
describe the computation of RBF NN and Jacobian value by using three parallel neuron computational block; finally
s82 –s91 execute the tuning of fuzzy rule parameters. The operation of each step in Fig. 9 can be completed within 80 ns
(12.5 MHz clock); therefore total 92 steps only need 7.36 ␮s operational times. It does not loss any control performance
for the overall system because the operation time with 7.36 ␮s is less than the sampling interval, 500 ␮s (2 kHz), of the
speed control loop in Fig. 1. Finally, the execution time of NFC in software by using Nios II processor is evaluated and
it is 1190.8 ␮s. It shows that the computational power in hardware of FPGA is about 160 times faster than in software
by using Nios II processor.

4. Simulation results

The NFC-based speed control block diagram for PMSM drive is shown in Fig. 1 and its Simulink/ModelSim co-
simulation architecture is presented in Fig. 10. The SimPowerSystem blockset in the Simulink executes the PMSM
and the inverter. The EDA simulator link for ModelSim executes the co-simulation using VHDL code running in
ModelSim program with two works. The work-1 of ModelSim in Fig. 10 performs the function of speed loop neural
fuzzy controller (NFC) and the work-2 executes the function of current controller and coordinate transformation
(CCCT) and SVPWM. All works in ModelSim are described by VHDL. The sampling frequency of current and speed
control is designed with 16 kHz and 2 kHz, respectively. The clocks of 50 MHz and 12.5 MHz will supply all works
of ModelSim. The designed PMSM parameters used in simulation are that pole pairs is 4, stator phase resistance is
1.3 , stator inductance is 6.3 mH, inertia is J = 0.000108 kg m2 and friction factor is F = 0.0013 N m s.
To evaluate the effectiveness of the proposed control algorithm, three tested cases with various PMSM parameters
are conducted, in which
Case 1: (normal-load condition)
J = 0.000108, F = 0.0013 (33)
Case II: (light-load condition)
J = 0.000108/3, F = 0.0013/3 (34)
Case III: (heavy-load condition)
J = 0.000108 × 3, F = 0.0013 × 3 (35)
The co-simulation is carried out in Fig. 10. The control objective is to control the rotor speed of PMSM to track the
output of the reference model. In the case of the FC design, the membership function and the fuzzy rule table are

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Fig. 9. State diagram of an FSM for describing the NFC in speed loop controller of PMSM drive.

designed in Fig. 11. Besides, the parameters of PI controller in Fig. 1 are selected as Kp = 1 and Ki = 0.025. Square
waves with period of 0.16 s and magnitude variation from 0 to 500 rpm up to 1000 to 1500 rpm is adopted as a tested
input command. To evaluate the tracking performance of FC at various system conditions, the system parameters are
initially designed at the normal-load condition (Case I), and the simulation result is shown in Fig. 12. It presents
a good speed following response in Fig. 12(a) and a complete current decoupled effect in Fig. 12(b). Therefore, a
desired rotor speed response with the characteristics of no overshoot, 0.017 s rising time and zero steady-state value,
which approximates the speed response curve in Fig. 12(a), is considered as a comparator curve while PMSM runs
at different condition. However, when the system parameters change to the light-load (Case II) and heavy-load (Case

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Fig. 10. Simulink and ModelSim co-simulation architecture for NFC-based speed control of PMSM drive.

III) condition, the speed and current responses are shown in Figs. 13 and 14. The rotor speed response in Fig. 13 lags
behind the desired rotor speed response with a large overshoot condition and in Fig. 14 is ahead of the desired rotor
speed response with a small overshoot condition. It shows that the rotor speed response is greatly affected by system
parameters variation if the speed controller uses FC only.
To cope with the system uncertainty problem, a NFC is adopted in Fig. 1. The NFC consists of a FC, a RM and a
RBF NN based adjusting mechanism. The RBF NN is applied to real-time identify the plant dynamic for providing an
exact plant information to the learning algorithm of FC. The desired rotor speed response with the characteristics of no

Fig. 11. Fuzzy membership function and the initial fuzzy-rule table.

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Fig. 12. Simulation results when FC is used and PMSM is operated at normal-load condition.

Fig. 13. Simulation results when FC is used and PMSM is operated at heavy-load condition.

Fig. 14. Simulation results when FC is used and PMSM is operated at light-load condition.

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Fig. 15. Simulation results when NFC is used and PMSM is operated at heavy-load condition.

overshoot, 0.017 s rising time and zero steady-state value in Fig. 12 is considered to design the transfer function of the
RM. According to the required specifications, a second order system with the natural frequency of 230 rad/s and the
damping ratio of 1 is chosen. Then, after applying the bilinear transformation with sampling frequency of 2 kHz, the
parameters of the difference equation in (21) are obtained by θ 0 = 0.00295, θ 1 = 0.0059, θ 2 = 0.00295, φ1 = −1.7825,
and φ2 = 0.7943. In NFC design, the initial fuzzy parameters in Fig. 11 is the same as the FC, but the fuzzy parameters
of the cm,n can be tuned using (27) if the output of rotor speed cannot follow the output of RM. The learning rate α is set
as 0.3. The initial parameters in RBF NN are chosen by wr = 10, σ r = 250, cr1 = cr2 = cr3 = 250, where r = 1, 2, 3. The
learning rate η in RBF NN is set as 0.15. In simulation, square waves with magnitude variation from 0 to 500 rpm up
to 1000 to 1500 rpm is adopted as a tested input command and its simulation results under heavy-load and light-load
condition are presented in Figs. 15 and 16, respectively. In Fig. 15, in the beginning time, the FC is applied to the
speed loop of PMSM drive system and the rotor speed shows a lag and an overshoot response. After 0.14 s, the NFC is
adopted. Meanwhile, the cm,n parameters are tuned to an adequate value for reducing the error between the rotor speed
and the output of RM. Finally, the rotor speed can accurately track well after one cycle learning. In Fig. 15(b), it exhibits
that the current iq need to generate a larger current value to force the motor running speed to fast track the output of
RM. Similar results appear in the light-load condition in Fig. 16. Additionally, two another transition conditions, which

Fig. 16. Simulation results when NFC is used and PMSM is operated at light-load condition.

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Fig. 17. Simulation results when NFC is used and PMSM is operated varying from normal-load condition to heavy-load condition.

Fig. 18. Simulation results when NFC is used and PMSM is operated varying from normal-load condition to light-load condition.

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extern load is changed from normal-load to heavy-load and from normal-load to light-load condition, are considered
and evaluated, and the simulated results are shown in Figs. 17 and 18. In the former case, the control current iq in
transition conditions of Fig. 17(b) is apparently increased to speed up the motor running, but in the latter case, the
control current iq in transition conditions of 18(b) is decreased to slow down the motor running. However, it shows
that due to the tuning of control current iq by NFC, the output of rotor speed in Figs. 17(a) and 18(a) can track the
desired speed well. Therefore, the simulation results in Figs. 12–18 demonstrate that the proposed NFC-based speed
controller for PMSM drive is effective and robust.

5. Conclusions

This study has presented a FPGA-based NFC controller for PMSM drives and successfully demonstrated its per-
formance through co-simulation by using Simulink and ModelSim. In control algorithm, to cope with the system
uncertainty, a NFC is proposed and a RBF NN is used to identify the plant dynamic and provided more accuracy plant
information for parameters tuning of FC. In realization, a sequential execution using FSM is applied to model the
computing process of NFC for reducing the FPGA resource usage. Under the proposed design method, the execution
time and FPGA resource usage for computing a NFC spend only 7.36 ␮s and 13,806 LEs, respectively. It not only
does not loss any control performance for the overall system, but also can greatly save the FPGA resource usage.
At last, some simulation results demonstrate that in step response, the speed of PMSM can fast track the prescribed
dynamic response accurately after the proposed controller has been conducted. However, after confirming the effective
of VHDL code of NFC-based speed controller in co-simulation by using Simulink and ModelSim, the VHDL code
except A/D and QEP interface circuit, can be directly used in the experimental FPGA-based PMSM drive system for
further verifying its function in the future work.

Acknowledgment

This work was supported by National Science Council of the R.O.C. under grant no. NSC 100-2221-E-218-001.

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Please cite this article in press as: H.-H. Chou, et al. Optimized FPGA design, verification and implementation of a neuro-fuzzy
controller for PMSM drives, Math. Comput. Simul. (2012), http://dx.doi.org/10.1016/j.matcom.2012.07.012