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Cad Lab 4

1) The document describes designing a 2048x8 bit RAM and testing it for read and write operations. 2) The RAM was synthesized and the enable rate was checked. The initial enable rate was 100%, indicating high power consumption. 3) Power optimization using clock gating was then applied in the tool, reducing the enable rate to 75% and lowering power consumption without changing functionality.

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SABUJ CHAKI
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10 views

Cad Lab 4

1) The document describes designing a 2048x8 bit RAM and testing it for read and write operations. 2) The RAM was synthesized and the enable rate was checked. The initial enable rate was 100%, indicating high power consumption. 3) Power optimization using clock gating was then applied in the tool, reducing the enable rate to 75% and lowering power consumption without changing functionality.

Uploaded by

SABUJ CHAKI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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CAD FOR IC DESIGN LAB REPORT

EXPERIMENT-4

Group – 3
Sambuddha Basu – 2023H1230166H
Sabuj Chaki – 2023H1230184H
DATE – 19-02-2024
AIM –
1. Design a 2048×8 bit RAM as shown in Figure 1. Assume that the RAM works on
positive clock edge. If WE = 0, the RAM displays the data stored in the location (addr) to
the output (data out), else, it writes the input (data in) to the location indicated by “addr”
and also displays the same to the output.

2. Synthesize the design and check for “Enable rate” of the RAM.

3. Apply power optimization technique and report the change(s) observed in the
implemented design.

Software Used – Xilinx Vivado2017


Theory – If there is a direct connection of VDD(power source) to the ground then we have power
loss due direct connection of from source to ground .Also dynamic power is dependent of
switching frequency , we must use clock gating circuits to reduce that.
Clock gating refers to the process of switching off clock dynamically for inactive modules using
a clock enable signal. Clock gating aids in reduction of dynamic power consumption and
dissipation. In Xilinx Vivado, power optimization is an optional step that optimizes dynamic power
using clock gating. Power optimization includes clock gating solutions that can reduce dynamic
power in the design, without altering functionality.

1. Memory code :
2. Memory testbench code :
3. Memory waveform :

WE = 1

WE = 0

4. Timing constraints :

Best case Time Period = 5ns


5. RTL schematic :

6. Synthesized Netlist :
7. Power utilization and Enable Rate :

8. Power Optimization :
In order to reduce the power consumption, we have used clock gating technique. By using the
clock gating technique we were able to reduce the enable rate to 75%.
Go to implementation settings and click on the check box is_enabled under Power Opt Design and
then run the implementation again.
9. Power Utilization and Enable Rate post optimization :

For optimizing the power consumption here, we have directly made use of the CAD tool without
going for any optimization in the code, we have been able to achieve considerable amount of
reduction in power consumption by the help of tool which employs clock gating technique to
reduce the enabling rate of the design

10. Inferences :
• From the above implementation of RAM architecture using behavior modelling, we are
able to observe the read and write operations in memory location successfully.
• After synthesis of the verilog code, when we observed the power report , the enabling
rate of the logic is found to be 100%, which turns out to high power consumption.
• After implementation of the verilog code, when we have observed this power report, the
enabling rate of the logic is found to be 75%, turning out to less power consumption. This
is possible as the tool uses clock gating techniques to optimize the power .

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