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Reg No.: Name:

APJ ABDUL KALAM TECHNOLOGICAL I.INIVERSITY $-,

Fourth Semester B.Tech Degree Examination July 2021 (2019 Scheme

Course Code:CSTz0z
' Course Name: Computer Organization and Architecture
Max. I\z{arks: 100 Duration: 3 Hours
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PART
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n6 A^
(Answer all questions; each question corries 3 marks) Marks

lq Compare auto increment and auto decrement addressing modes with examples
a
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a
2 Outline the steps involved in the execution of an instruction. J
rt
a
J How is the two port memory organization of processor unit better when J

compared to scratch pad memory organization?

a
4 Give the block diagram of circuit that implements following statements in J

' register transfer logic:

T1; C <-A
Ti: C -R
5 Draw the flow chart for Booth's Multiplication Algorithm 3

6 Illustrate Read After Write (RAW) hazard *'ith an example 3

7 Explain PLA based control organization with the help of a diagram 3

8.t Differentiate between horizontal and vertical microinstructions 3

9 List and explain the different types of ROMs 3

l0 Explain the term locality of reference. How is this related to cache memory? 3

PART B
(Answer onefull question from each module, each question carries 14 morks)
Module -1
l l a) Identify the addressing modes that can be used for representing the following 4
higher level language constructs in machine level. Illqstrate each addressing
mode using an example.
l) Anays
2) Pointers
3) Constants
4) Variables

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b) Illustrate the single bus organization of processor unit with the help of suitable l0
diagrams. Explain, listing the control signals, how the following operations are
handled in this organization.
i) Transfer contents of register R5 to Rl
ii) Move (R6), R2 (Fetch a wordfrom memory and move it to register R2, when
the memory address is stored in register R6 )

OR
'q2 a) Outline the differences in instruction execution during straight line sequencing 7
and branching using suitable examples.

(. b) Differentiate between big endian and little endian byte ordering. T

Consider a computer that has a byte addressable memory organized as 32 bit
words' A program reads ASCII characters entered at a key board and stores
them in successive bye locations, starting at location 1000. Show the contents
of the two memory words at locations 1000 and 1004 after the name Johnson
has been entered in case:

i) Big Endian Byte ordering is used.

ii) Linle Endian B1,re ordering is used

(ASCII equivalent of charaeters in Johnsor in hex rvill be 44, 6F. 6& 6E.

\ 73,6F,6E. You can indicate unused bye locations using XX).

Module -2
I 13 a) Illustrate and explain the organization of a processor unit where processor 7
registers and ALU are connected through common buses. Explain how the
micro operation R2 <-- R3+R4 would be performed using this organization,
where R2, R3 and R4 are processor registers.
b) Explain with the help of a block diagram the design of a 4 bit status register for 7
an 8 bit ALU. The four status bits are c (carry), s(sign), z(zero) and v
(overflow). Clearly indicate the purpose of each sf,atus bit and how they are set
or reset.
,OR

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14 a) Design and draw a combinational logic shifter using multiplexers with two l0
selection variables, H1 and Hn. The operations of shifter should be as specified
in the followins table:

Hr H6 Operation Function
0 0 S<-0 Transfer 0's to S

0 I S.-shl F Shift left F into S

I 0 S.-shr F Shift right F into S

I I S.-F No shift

q b) Describe about arithmetic, logic and shift micro operations, listing the available

operations in each category.

,i
Module -3
' 15 a) Outline the hardware requirement for multiplying two binary numbers in sign 8
magnitude format and specify a flowchart for same. Illustrate the algorithm,
' showing the contents of registers, for the multiplication of 11111 by fOf 01
b) Explain the various pipeline structures available inside a computer 6

OR
16 a) Design and drarv the block diagram for a 4 by 3 array multiplier. 8

b) Explain the various method available to get rid of data hazards inside the 6
system

, Module -4

. 17 a) Illustrate the working of a micro program sequencer with the help of diagrams 7
., b) Outline with the help of a block diagram, how a micro program control unit can 7
: 6" used for controlling the processor unit.
OR
l8 Illustrate the steps for designing a micro programmed control circuit for the t4
addition and subtraction of binary numbers in sign magnitude form. Specify the
block diagram of control circuitry and the binary -i"ro prograrn for control
memory.

Module -5
19 a) Explain with examples the three types of mapping functions used in cache
memory

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wtlaf ffe brt€["r"w6? odline the actions taking place in a processor offi€ an 7

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;2b,,'s),",!Vtrs is a'trRAM? Corryre'the trvo types of DRAMs, highlighti*g t{Eir 7

differences.

b)'Ottlire',lowDirytMernoryAccessisimplemented?Dil Terentiate betw€€n 7

cycle stealing ilMA and burst mode'DMA'

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