APW7301

3A 24V 340kHz synchronous Buck Converter

Features General Description

• Wide Input Voltage from 4.5V to 24V APW7301 is a 3A synchronous buck converter with inte-
• 3A Continuous Output Current grated 85mΩ power MOSFETs. The APW7301 design
• Adjustable Output Voltage from 0.925V to 20V with a current-mode control scheme, can convert wide
input voltage of 4.5V to 24V to the output voltage adjust-
• Intergrated High/Low Side MOSFET
able from 0.925V to 20V to provide excellent output volt-
• PFM/PWM mode Operation
age regulation.
• Fixed 340kHz Switching Frequency
The APW7301 is equipped with an automatic PFM/PWM
• Stable with Low ESR Ceramic Output Capacitors mode operation. At light load, the IC operates in the PFM
• Power-On-Reset Detection mode to reduce the switching losses. At heavy load, the
• Programmable Soft-Start IC works in PWM.
• Over-Temperature Protection The APW7301 is also equipped with Power-on-reset, soft-
• Current-Limit Protection with Frequency Foldback start, and whole protections (over-temperature, and cur-
• Enable/Shutdown Function rent-limit) into a single package.
This device, available SOP-8P, provides a very compact
• Small SOP-8P Package
system solution external components and PCB area.
• Lead Free and Green Devices Available
(RoHS Compliant)

Applications Pin Configuration

APW7301
• LCD Monitor/TV
BS 1 8 SS
• Set-Top Box VIN 2 9 7 EN
• DSL, Switch HUB LX 3 GND 6 COMP
• Notebook Computer GND 4 5 FB

SOP-8P
(Top View)

Simplified Application Circuit

9 Exposed Pad
The pin 4 must be connected to the pin 9 (Exposed Pad)
VIN

VOUT
APW7301

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

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Rev. A.2 - Apr., 2013
APW7301

Ordering and Marking Information

APW7301 Package Code
KA : SOP-8P
Assembly Material Temperature Range
I : -40 to 85 oC
Handling Code Handling Code
Temperature Range TR : Tape & Reel
Assembly Material
Package Code G : Halogen and Lead Free Device
APW7301
APW7301 KA : XXXXX XXXXX - Date Code

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit
VIN VIN Supply Voltage (VIN to GND) -0.3 ~ 30 V
VLX LX to GND Voltage -1 ~VIN+0.3 V
EN, FB, COMP, SS to GND Voltage -0.3 ~ 6 V
VBS BS to GND Voltage VLX-0.3 ~ VLX+6 V
PD Power Dissipation Internally Limited W
o
TJ Junction Temperature 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C

Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability

Thermal Characteristics
Symbol Parameter Typical Value Unit
(Note 2)
Junction-to-Ambient Resistance in Free Air
θJA
o
C/W
SOP-8P 75
Junction-to-Case Resistance in Free Air (Note 3)
θJC
o
C/W
SOP-8P 15

Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
is soldered directly on the PCB.
Note 3: The case temperature is measured at the center of the exposed pad on the underside of the SOP-8P package.

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APW7301

Recommended Operating Conditions (Note 4)

Symbol Parameter Range Unit
VIN VIN Supply Voltage 4.5 ~ 24 V
VOUT Converter Output Voltage 0.925~20 V
IOUT Converter Output Current 0~3 A
o
TA Ambient Temperature -40 ~ 85 C
o
TJ Junction Temperature -40 ~ 125 C
Note 4 : Refer to the typical application circuit.

Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, VEN=3V and TA=25°C.

APW7301
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SUPPLY CURRENT
IVIN VIN Supply Current VFB=1V, VEN=3V, LX=NC - 1.9 - mA
IVIN_SD VIN Shutdown Supply Current VEN=0V - 0.3 - µA
POWER-ON-RESET (POR)
VIN POR Voltage Threshold VIN Rising 3.8 4.05 4.4 V
VIN POR Hysteresis - 0.3 - V
REFERENCE VOLTAGE
VREF Reference Voltage Regulated on FB pin 0.9 0.925 0.943 V
OSCILLATOR AND DUTY CYCLE
FOSC Oscillator Frequency 300 340 380 kHz
Foldback Frequency VFB=0V - 110 - kHz
Maximum Converter’s Duty VFB=0.925V - 90 - %
(Note 5)
Minimum On Time - 220 - ns
PFM MODE OPERATION
IPK_PFM PFM Mode Current Limit - 0.8 - A
IPK_TH PWM to PFM Inductor Peak Threshold - 0.6 - A
POWER MOSFET
High/low Side MOSFET On Resistance - 110 - mΩ
High/Low Side MOSFET Leakage
VEN=0V, VLX=0V - - 10 µA
Current
CURRENT-MODE PWM CONVERTER
GEA Error Amplifier Transconductance - 820 - µA/V
Error Amplifier Voltage Gain - 80 - V/V
Switch Current to COMP Voltage
- 5.2 - A/V
Transresistance

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APW7301

Electrical Characteristics (Cont.)

Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V, VEN=3V and TA= 25°C.

APW7301
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PROTECTIONS
ILIM High Side MOSFET Current-Limit Peak Current - 5.6 - A
TOTP Over-Temperature Trip Point - 160 - °C
Over-Temperature Hysteresis - 50 - °C
Over-Voltage Protection - 120 - %
SOFT-START, ENABLE AND INPUT CURRENTS
ISS Soft-Start Current - 6 - µA
EN Under-Voltage Lockout (UVLO)
VEN rising 2.2 2.5 2.7 V
Threshold
EN UVLO Hysteresis - 100 - mV

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APW7301

Typical Operating Characteristics

Efficiency vs. Output Current Efficiency vs. Output Current
100 100
90 90
80 80
70 70
Efficiency (%)

VOUT = 1.2V

Efficiency (%)
60 60
50 50
VIN = 19V VOUT = 1.8V
40 40
30 VIN = 12V 30 VOUT = 2.5V
20 20
10 VOUT = 5V 10 VOUT = 3.3V VIN = 12V
0 0
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10
Output Current (A) Output Current (A)
VIN Supply Current vs. VIN Supply Soft Start Time vs. SS pin to GND
Voltage Capacitance
1.90 80
TA=25oC VIN =12V, VOUT =3.3V, TA=25oC,
70
The time of 10%~90%VOUT
VIN Supply Current, IVIN (mA)

1.85
Soft Start Time, tSS (ms)

60

1.80 50

40
1.75
30

20
1.70

10

1.65
0
5 10 15 20 25 0 100 200 300 400 500

VIN Supply Voltage (V) SS pin to GND Capacitance (nF)

EN UVLO Threshold Voltage vs. Reference Voltage vs. VIN Supply

VIN Supply Voltage Voltage
2.6 0.928
EN UVLO Threshold Voltage, VEN (V)

TA=25oC
2.5
Reference Voltage, VREF (V)

0.927

2.4
VEN Rising 0.926

2.3

0.925
2.2
VEN Falling

0.924
2.1

2.0 0.923
5 10 15 20 25 5 10 15 20 25

VIN Supply Voltage (V) VIN Supply Voltage (V)

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APW7301

Typical Operating Characteristics

Switching Frequency vs. Switching Frequency vs. VIN
Junction Temperature Supply Voltage
360 360

355 VIN = 12V TA = 25oC

Switching Frequency, FOSC(kHz)

Switching Frequency, FOSC(kHz)

358
350

345
356
340

335 354

330
352
325

320 350
-50 0 50 100 150 5 10 15 20 25
o VIN Supply Voltage (V)
Junction Temperature ( C)

Reference Voltage vs. Junction

Temperature
0.941

VIN = 12V
0.937
Reference Voltage, VREF(V)

0.933

0.929

0.925

0.921

0.917
-50 0 50 100 150
o
Junction Temperature ( C)

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APW7301

Operating Waveforms
The test condition is VIN=12V, TA= 25oC unless otherwise specified.

Power On Power Off

V IN
VIN
V OUT VOUT

1 1

2 2
IL
IL

3 3

VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, no VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, no
load load
CH1: VIN, 5V/Div, DC CH1: VIN, 5V/Div, DC
CH2: VOUT , 2V/Div, DC CH2: VOUT , 2V/Div, DC
CH3: IL, 0.5A/Div, DC CH3: IL, 0.5A/Div, DC
TIME: 10ms/Div TIME: 50ms/Div

Enable Shutdown

VEN
VEN
1 1
VOUT
V OUT
2 2

IL
IL
3
3

VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
RLOAD =2Ω RLOAD =2Ω
CH1: VEN, 5V/Div, DC CH1: VEN, 5V/Div, DC
CH2: VOUT , 2V/Div, DC CH2: VOUT , 2V/Div, DC
CH3: IL, 2A/Div, DC CH3: IL, 2A/Div, DC
TIME: 5ms/Div TIME:50µs/Div

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Rev. A.2 - Apr., 2013
APW7301

Operating Waveforms
The test condition is VIN=12V, TA= 25oC unless otherwise specified.

Current Limit & Frequency Normal Operation in Heavy

Foldback Load

VOUT VOUT

1 VLX
VLX
1

2 3

IL

IL

3 2

VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
Ramp up IOUT into current limit IOUT =3A
CH1: VOUT , 2V/Div, DC
CH1: VEN, 5V/Div, DC
CH2: IL, 2A/Div, DC
CH2: VLX, 10V/Div, DC
CH3: IL, 2A/Div, DC CH3: VLX, 10V/Div, DC
TIME: 2µs/Div
TIME: 50µs/Div

Normal Operation in Light

Load Load Transient

VOUT

VLX VOUT
1 1

IOUT
IL

2 2

VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
IOUT =100mA COMP=6.8kΩ+3.9nF, IOUT =300mA-3A-300mA
CH1: VOUT , 2V/Div, DC CH1: VOUT , 0.5V/Div, offset=3.3V
CH2: IL, 1A/Div, DC CH2: IOUT , 2A/Div, DC
CH3: VLX, 10V/Div, DC TIME: 50µs/Div
TIME: 5µs/Div

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APW7301

Operating Waveforms
The test condition is VIN=12V, TA= 25oC unless otherwise specified.

Load Transient Short Circuit

VOUT

VLX
VOUT
1 1

VLX

2
IOUT

IL

2 3

VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH, VIN =12V, VOUT =3.3V, COUT =22uF, L =10uH,
COMP=6.8kΩ+3.9nF, IOUT =1A-3A-1A VOUT short to ground.
CH1: VOUT , 0.5V/Div, offset=3.3V CH1: VOUT , 2V/Div, DC
CH2: IOUT , 2A/Div, DC CH2: VLX, 10V/Div, DC
TIME: 50µs/Div CH3: IL, 5A/Div, DC
TIME: 10µs/Div

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APW7301

Pin Description
PIN FUNCTION

SOP-8P Name

High-Side Gate Drive Boost Input. BS supplies the voltage to drive the high-side N-channel
1 BS
MOSFET. At least 10nF capacitor should be connected from LX to BS to supply the high side switch.
Power Input. VIN supplies the power (4.5V to 24V) to the control circuitry, gate drivers and step-down
2 VIN converter switches. Connecting a ceramic bypass capacitor and a suitably large capacitor between
VIN and GND eliminates switching noise and voltage ripple on the input to the IC.
Power Switching Output. LX is the Drain of the N-Channel power MOSFET to supply power to the
3 LX
output LC filter.
4 GND Ground. Connect the exposed pad on backside to Pin 4.
Output feedback Input. The APW7301 senses the feedback voltage via FB and regulates the voltage
5 FB at 0.925V. Connecting FB with a resistor-divider from the converter’s output sets the output voltage
from 0.925V to 20V.
Output of the error amplifier. Connect a series RC network from COMP to GND to compensate the
6 COMP
regulation control loop. In some cases, an additional capacitor from COMP to GND is required.
Enable Input. EN is a digital input that turns the regulator on or off. EN threshold is 2.5V with 0.2V
7 EN
hysteresis. Pull up with 100kΩ resistor for automatic startup.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND to set
8 SS the soft-start period. A 0.1µF capacitor sets the soft-start period to 15ms. To disable the soft-start
feature, leave SS unconnected.
Connect the exposed pad to the system ground plan with large copper area for dissipating heat into
9 Exposed Pad
the ambient air.

Block Diagram
VIN
2

Current Sense
LOC
Amplifier
Over Power-On- Current 5V
Temperature Reset Limit
Protection
1 BS

5V POR
OTP
6µA
120%VREF Gate
SS 8 Fault
OVP Logics Driver

Inhibit
Gate 3 LX
Control

5V
FB 5 Gm
Current
VREF Error Compartor
Amplifier Gate
Driver 4 GND
COMP 6
2.5/2.3V UVLO Slope LOC
Compensation

Oscillator Current Sense

EN 7 Enable
Internal 5V 340kHz/
FB Amplifier
1.5V Regulator 110kHz
0.6V
VIN

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APW7301

Typical Application Circuit

VIN
4.5V~24V

C1 C2 2 1
10µF (option*) C3
10nF
VIN BS
R4
100k VOUT
7 3 3.3V/3A
EN LX
L1
10µH
C4
8 APW7301 22µFx2
SS

6 5
COMP FB
C5
0.1µF R1
24K
GND
R3
6.8k 4
R2
C6 9.1K
3.9nF

* For cirtical condition, like plug in, the large capacitace and high voltage rating are needed to avoid the high spike
voltage.

Recommended Feedback Compensation Value

Vin(V) VOUT(V) L1(µH) C4(µF) R1(KΩ) R2(KΩ) R3(KΩ) C6(nF)
24 5 10 22(Ceremic) 39 9.1 6.8 3.9
12 5 10 44 (Ceremic) 39 9.1 5 1.5
12 3.3 10 22 (Ceremic) 24 9.1 6.8 3.9
12 2.5 10 22 (Ceremic) 15 9.1 6.8 3.9

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APW7301

Function Description
Main Control Loop Enable/Shutdown
The APW7301 is a constant frequency current mode Driving EN to ground places the APW7301 in shutdown.
switching regulator. During normal operation, the inter- When in shutdown, the internal N-Channel power MOSFET
nal N-channel power MOSFET is turned on each cycle turns off, all internal circuitry shuts down and the quies-
when the oscillator sets an internal RS latch and would cent supply current reduces to 0.3µA.
be turned off when an internal current comparator (ICMP)
Current-Limit Protection
resets the latch. The peak inductor current at which ICMP
resets the RS latch is controlled by the voltage on the The APW7301 monitors the output current, flowing
COMP pin, which is the output of the error amplifier through the N-Channel power MOSFET, and limits the
(EAMP). An external resistive divider connected between IC from damages during overload, short-circuit and over-
VOUT and ground allows the EAMP to receive an output voltage conditions.
feedback voltage VFB at FB pin. When the load current
increases, it causes a slight decrease in VFB relative to Frequency Foldback
the 0.925V reference, which in turn causes the COMP
The foldback frequency is controlled by the FB voltage.
voltage to increase until the average inductor current
When the FB pin voltage is under 0.6V, the frequency of
matches the new load current.
the oscillator will be reduced to 110kHz. This lower fre-
VIN Power-On-Reset (POR) and EN Under-voltage quency allows the inductor current to safely discharge,
Lockout thereby preventing current runaway. The oscillator’s fre-
quency will switch to its designed rate when the feedback
The APW7301 keep monitoring the voltage on VIN pin to
prevent wrong logic operations which may occur when voltage on FB rises above the rising frequency foldback
VIN voltage is not high enough for the internal control threshold (0.6V, typical) again.
circuitry to operate. The VIN POR has a rising threshold
of 4.05V (typical) with 0.3V of hysteresis. Over-Voltage Protection
An external under-voltage lockout (UVLO) is sensed at The over-voltage function monitors the output voltage by
the EN pin. The EN UVLO has a rising threshold of 2.5V
FB pin. When the FB voltage increase over 120% of the
with 0.2V of hysteresis. The EN pin should be connected reference voltage, the over-voltage protection compara-
a resistor divider from VIN to EN .
tor will force the high-and low-side MOSFET gate driver
After the VIN and EN voltages exceed their respective off. As soon as the output voltage is within regulation, the
voltage thresholds, the IC starts a start-up process and
OVP comparator is disengaged. The chip will restore its
then ramps up the output voltage to the setting of output normal operation.
voltage.

Over-Temperature Protection (OTP)

The over-temperature circuit limits the junction tempera-
ture of the APW7301 When the junction temperature ex-
ceeds TJ =+160oC, a thermal sensor turns off the power
MOSFET, allowing the device to cool down. The thermal
sensor allows the converter to start a start-up process
and regulate the output voltage again after the junction
temperature cools by 50oC.
The OTP designed with a 50 oC hysteresis lowers the
average T J during c ontinuous thermal overload
conditions, increasing life time of the IC.

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APW7301

Application Information
T=1/FOSC
Setting Output Voltage
The regulated output voltage is determined by:
VLX
DT I
R1 IOUT
VOUT= 0.925 × (1 + ) ⋅ ( V)
R2 IL
To prevent stray pickup, please locate resistors R1 and IOUT
R2 close to APW7301.
IQ1
I
ICOUT
Input Capacitor Selection
Use small ceramic capacitors for high frequency VOUT

decoupling and bulk capacitors to supply the surge cur-

rent needed each time the N-channel power MOSFET VOUT
(Q1) turns on. Place the small ceramic capacitors physi-
Figure 1. Converter Waveforms
cally close to the VIN and between the VIN and GND.
The important parameters for the bulk input capacitor are
In critical condition, like input voltage plug in, it will cause
the voltage rating and the RMS current rating. For reliable
the high spike voltage. It is recommended to place large
operation, select the bulk capacitor with voltage and
capacitance and higher voltage rating to reduce the spike
current ratings above the maximum input voltage and
voltage. In general, to parallel a electrolytic capacitor with
largest RMS current required by the circuit. The capacitor
large capacitance can reduce the spike voltage in critical
voltage rating should be at least 1.25 times greater than
condition. This electrolytic capacitor must also be short
the maximum input voltage and a voltage rating of 1.5
pin wire to make it as close as to the power plane or trace.
times is a conservative guideline. The RMS current (IRMS)
of the bulk input capacitor is calculated as the following
equation:
VIN
VIN
CIN1 CIN2
IRMS = IOUT D × (1 − D) ⋅ ( A ) 10uF/
MLCC APW7301
where D is the duty cycle of the power MOSFET.
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tanta-
Output Capacitor Selection
lum capacitors can be used, but caution must be exer-
An output capacitor is required to filter the output and sup-
cised with regard to the capacitor surge current rating.
ply the load transient current. The filtering requirements
are the function of the switching frequency and the ripple
VIN current (DI). The output ripple is the sum of the voltages,
VIN
IQ1 having phase shift, across the ESR and the ideal output
CIN
capacitor. The peak-to-peak voltage of the ESR is calcu-
Q1 ated as the following equations:
IL IOUT
VOUT V OUT
L D = ........... (1)
LX V IN
ESR
Q2 ICOUT
V OUT × (1 − D ) ........... (2)
COUT ∆I =
F OSC × L

V ESR = ∆ I × ESR ........... (3)

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APW7301

Application Information(Cont.)
Output Capacitor Selection (Cont.)
Inductor Value Calculation
The peak- to-peak voltage of the ideal output capacitor is The operating frequency and inductor selection are inter-
calculated as the following equations: related in that higher operating frequencies permit the
use of a smaller inductor for the same amount of inductor
∆I
∆VCOUT = ........... (4) ripple current. However, this is at the expense of efficiency
8 × FOSC × COUT
due to an increase in MOSFET gate charge losses. The
For the applications using bulk capacitors, the ∆VCOUT is equation (2) shows that the inductance value has a direct
much smaller than the VESR and can be ignored. Therefore, effect on ripple current.
the AC peak-to-peak output voltage(∆VOUT) is shown below: Accepting larger values of ripple current allows the use of
low inductances, but results in higher output voltage ripple
∆VOUT = ∆I × ESR ⋅ ( V ) ........... (5) and greater core losses. A reasonable starting point for
setting ripple current is ∆I< 0.4 x IOUT(max). Please be no-
For the applications using bulk capacitors, the VESR is ticed that the maximum ripple current occurs at the maxi-
much smaller than the ∆V COUT and can be ignored. mum input voltage. The minimum inductance of the in-
Therefore, the AC peak-to-peak output voltage(∆VOUT) is to uctor is calculated by using the following equation:
∆VCOUT.
VOUT ·(VIN - VOUT)
The load transient requirements are the function of the ≤ 1.2
340000 ·L ·VIN
slew rate (di/dt) and the magnitude of the transient load
VOUT ·(VIN - VOUT)
urrent. These requirements are generally met with a L≥ (H) ........... (6)
408000 ·VIN
mix of capacitors and careful layout. High frequency ca-
pacitors initially supply the transient and slow the current where VIN = VIN(MAX)
load rate seen by the bulk capacitors. The bulk filter ca-
Table2 Inductor Selection Guide
pacitor values are generally determined by the ESR Inductance DCR Current
Vender Part number
(Effective Series Resistance) and voltage rating require- (µH) (mΩ) Rating(A)
ments rather than actual capacitance requirements. CYNTEC PCMB063T-100MS 10 62 4
High frequency decoupling capacitors should be placed Chilisin MHCC10040-100M 10 30 6.5
as close to the power pins of the load as physically Gausstek PL94P051M-10U 10 38 3.8
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
capacitor’s ESR value is related to the case size with lower
ESR available in larger case sizes. However, the Equiva-
lent Series Inductance (ESL) of these capacitors increases
with case size and can reduce the usefulness of the ca-
pacitor to high slew-rate transient loading.

Table1 Capacitor Selection Guide

Capacitance Voltage
Vender Model TC Si2e
(µF) Rating(V)
muRata GRM31CR61E106K 10 X5R 25 1206
muRata GRM31CR61C226K 22 X5R 16 1206

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APW7301

Application Information (Cont.)

Thermal Consideration 1. Begin the layout by placing the power components first.
The APW7301 maximum power dissipation depends on Orient the power circuitry to achieve a clean power flow
path. If possible, make all the connections on one side of
the thermal resistance and temperature difference be-
tween the die junction and ambient air. The power dissi- the PCB with wide, copper filled areas.
2. In Figure 3, the loops with same color bold lines con-
pation PD across the device is:
duct high slew rate current. These interconnecting im-
PD = (TJ - TA) / θJA
pedances should be minimized by using wide and short
where (TJ-TA) is the temperature difference between the printed circuit traces.
junction and ambient air. θJA is the thermal resistance 3. Keep the sensitive small signal nodes (FB, COMP)
between Junction and ambient air. away from switching nodes (LX or others) on the PCB
For normal operation, do not exceed the maximum junc- and it should be placed near the IC as close as possible.
tion temperature rating of TJ = 125 oC. The calculated Therefore, place the feedback divider and the feedback
power dissipation should less than: compensation network close to the IC to avoid switching
PD = (125-25)/75=1.33(W) --- (SOP-8P) noise. Connect the ground of feedback divider directly to
the GND pin of the IC using a dedicated ground trace.
4. Place the decoupling ceramic capacitor C1 near the
VIN as close as possible. Use a wide power ground plane
2.5
Maximum Power Dissipation, PD(W)

to connect the C1, C2, and Schottky diode to provide a low

2 impedance path between the components for large and
high slew rate current.
1.5
+
VIN
1 - VIN BS C1
SOP-8P L1
C3
EN LX +
0.5 U1
Compensation
Network APW7301 C2 Load VOUT
COMP
0 -
R3
0 25 50 75 100 125 FB
C5 GND R1
Ambient Temperature, TA( oC) R2 Feedback
Divider

Figure 2. Current Path Diagram

Sensitive node (FB, COMP) should be away from
switching node(LX) and it should be placed near
Layout Consideration the IC with short trace

In high power switching regulator, a correct layout is

important to ensure proper operation of the regulator. In Numerous vias connected from Ground
the thermal pad to the APW7301
general, interconnecting impedance should be minimized solderside ground plane(s)
8

7
6

should be used to enhance heat

by using short, wide printed circuit traces. Signal and dissipation

power grounds are to be kept separating and finally SOP-8

combined using the ground plane construction or single

point grounding. Figure 3 illustrates the layout, with bold Input Capacitor C1 should be
1

VOUT
near the IC as close as possible
lines indicating high current paths. Components along L1
VIN VLX
the bold lines should be placed close together. Below is
C1

a checklist for your layout:

C2

Power path should be short and wide

Figure 3. Recommended Layout Diagram

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw

Rev. A.2 - Apr., 2013
APW7301

Package Information
SOP-8P
D

SEE VIEW A

D1

E2
THERMAL

E1

E
PAD

h X 45o
e b c
A2

0.25
A1

GAUGE PLANE
SEATING PLANE
L

θ
VIEW A

S SOP-8P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.60 0.063
A1 0.00 0.15 0.000 0.006
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.50 3.50 0.098 0.138
E 5.80 6.20 0.228 0.244
E1 3.80 4.00 0.150 0.157
E2 2.00 3.00 0.079 0.118
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
0 0oC 8o C 0o C 8oC

Note : 1. Followed from JEDEC MS-012 BA.

2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. A.2 - Apr., 2013
APW7301

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
SOP-8P P0 P1 P2 D0 D1 T A0 B0 K0

4.0±0.10 8.0±0.10 2.0±0.05 1.5+0.10 1.5 MIN. 0.6+0.00 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40

(mm)

Devices Per Unit

Package Type Unit Quantity
SOP-8P Tape & Reel 2500

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. A.2 - Apr., 2013
APW7301

Taping Direction Information

SOP-8P

USER DIRECTION OF FEED

Classification Profile

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. A.2 - Apr., 2013
APW7301

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. A.2 - Apr., 2013
APW7301

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

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Rev. A.2 - Apr., 2013