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EEC 234 Lectures - Lecture notes 1-12

ELECTRONICS II (Bayero University Kano)

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1.0 FIELD EFFECT TRANSISTORS

The Field Effect Transistor is a three terminal unipolar semiconductor device that has very
similar characteristics to those of the Bipolar Junction Transistor (BJT). The three terminals
are named Gate, Drain and Source, similar to Base, Collector and Emitter terminals of BJT.
The gate is the control terminal, while the Source and the Drain are at the either side of the
channel through which the current is passing. Being a unipolar semiconductor device, the
FET depends only on the conduction of electrons (as in the case of N-channel FET) or holes
(as in the case of P-channel FET).

The FET has one major advantage over BJT, in that their input impedance, (R in) is very high,
(about 1,000,000,000Ω or higher), while that of the BJT is comparatively low. This very high
input impedance makes them very sensitive to input voltage signals, but the price of this high
sensitivity also means that they can be easily damaged by static electricity.

There are two main types of field effect transistor, the Junction Field Effect Transistor or
JFET and the Insulated-gate Field Effect Transistor or IGFET, more commonly known
as the Metal Oxide Semiconductor Field Effect Transistor or MOSFET. The MOSFET
can also be sub-divided into Enhancement type and Depletion type. All forms are
available in both N-channel and P-channel versions.

The Field Effect Transistor (FET)

Junction FET Metal Oxide Semiconductor (FET)

Depletion Type Depletion Type Enhancement Type

N - Channel P - Channel N - Channel P - Channel N -channel P - Channel

Fig 1.1: Field Effect Transistors

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1.2 THE JUNCTION FIELD EFFECT TRANSISTOR, JFET

An N – channel JFET is made with an N –type silicon material that contains two layers of P
– type silicon material embedded on either side. The gate is connected to the p – type
material while the drain and the source terminals are connected to either end of the N – type
channel. When there is no voltage on the gate, the N – channel JFET has two PN junctions
under no bias condition (Fig. 1 (a)), the result is a depletion region at each junction that
resembles diode under no bias condition. As such, current flows freely from D to S terminal
and this is the maximum possible current that can flow through the JFET. It is termed drain
current for zero bias, IDSS.

The P – channel JFET is just the opposite of N-channel in construction, it works the same
way but with the opposite voltages.

Depletion region

Fig. 1.2 (a): N-channel JFET; VGS = Fig. 1.2 (b): N-channel JFET; VGS set at a negative potential
0V

However, if the gate is set to a negative voltage relative to the source, the area between the P
– type material and the center of the N – channel will form two reverse biased junction. This
reverse biased condition makes the depletion region to extend into the channel. The more
negative the gate voltage the larger the depletion region and hence the harder it is for
electrons to flow through the channel. The amount of the gate-source voltage that makes the
depletion layers touch each other and makes it impossible for current to flow through the
channel is called pinch off voltage, VP.

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1.3 JFET CHARACTERISTICS

The V-I characteristics of a JFET help us understand the behavior of the device. The
important characteristics are:

 Output characteristics
 Transfer characteristics

ID (mA)
ID (mA)
Saturation region
Breakdown region
D Linear
region
VGS = 0V
ID IDS IDSS
G +VDS

VG VGS = -1V
S

N-Channel JFET
VGS = -2V

VGS = -3V
VGS = -5V
VGS = -4V
VGS = VP = -6V, ID = 0mA
VP= -
VGS (V) 0 0 Cut off
VDS (V)
region

Fig 1.3(a): Transfer characteristics Fig 1.3(b): Output characteristics

1.3.1 Transfer Characteristics (Mutual Characteristics)

Transfer characteristics which is depicted in fig 1.2 (a) is the plot of the output current I D
against the input controlling quantity VGS. For a bipolar transistor the relation between the
output current IC and input controlling quantity IB is given by

𝐼𝐶 = 𝛽𝑑𝑐𝐼𝐵

Where βdc is considered to be a constant.

Therefore the transfer characteristics of a BJT is a straight line indicating a linear relationship
between IC and IB.

However, the relation between ID and VGS is not linear. It is defined by the Shockley’s
equation which states that:
2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

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Where, IDSS is the maximum drain current or source saturation current

VP is the pinch off voltage.

The IDSS and VP are constants, control variable is VGS. The relationship between ID and VGS is
therefore a squared relationship which grows exponentially.

1.3.2 Output or Drain Characteristics

The output characteristics or drain characteristics is a plot of drain current ID versus drain to
source voltage VDS at different values of gate to source voltage VGS. It is depicted in fig
1.2(b).

Observations:
 Maximum current flows through the JFET when the V GS is set to zero volts. This current is
called drain current for zero bias or IDSS
 Now notice how the ID varies with the VDS for a fixed value of VGS. The region of the graph
in which this occurs is called ohmic region or linear region. In this region the JFET behaves
like a voltage – controlled resistor.

Notice also the section of the graph where the curve flattens out. This region is called the
saturation or active region, and here the drain current ID is hardly influenced by the VDS.
 Another thing to note is that with increase in negative VGS, bias, the channel width decreases
and the ID decreases proportionally. The value of VGS that causes the JFET to turn off (point
where ID is practically zero) is called cut off voltage or pinch off voltage and is expressed as
VGS,OFF or VP.
 Notice also that as VDS increases, there is a point where ID skyrockets. The JFET at this point
loses its ability to resist current because too much voltage is applied across its drain – source
terminals. This effect is referred to as drain – source breakdown and the breakdown voltage
is expressed as BVDS.

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1.4 INSULATED GATE FIELD EFFECT TRANSISTOR, IGFET

The most common type of insulated gate is called the Metal Oxide Semiconductor Field
Effect Transistor, MOSFET. MOSFET is a voltage controlled field effect transistor that
differs from a JFET in that its Gate electrode is electrically insulated from the main
semiconductor N-channel or P-channel by a thin layer of insulating material usually silicon
dioxide (commonly known as glass). This insulated metal gate electrode can be thought of
as one plate of a capacitor. The isolation of the controlling Gate makes the input resistance
of the MOSFET extremely high thereby making it almost infinite. This very high input
resistance can easily accumulate large amounts of static charge resulting in the MOSFET
becoming easily damaged unless carefully handled or protected. Always store your FETs in
anti-static foam. When buying FETs, keep them in their antistatic bag or tube and leave them
there until you’re ready to use them.
MOSFETs are available in two basic forms: Depletion MOSFET and Enhancement
MOSFET

1.5 DEPLETION MOSFET

The Depletion MOSFET, which is less common than the enhancement types is normally
switched "ON" when the gate-source voltage V GS=0V. When VGS increases positively, the
conductance increases, because of the accumulation of electrons in the P-type material near
the n-channel. Similarly, when the VGS increases negatively the conductance decreases due to
the repulsion of electrons by the negative potential at the gate (like charges repel) creating a
depletion region as shown in fig 1.4(b). The repelled electrons tend to recombine with the
holes from the p – type material. Depending on the magnitude of the negative bias
established by the VGS, a level of recombination between electrons and holes will occur that
will reduce the number of free electrons in the N – channel to support conduction, thereby
making the drain current zero.

e +
D N ee +
N
Silicon oxide

+
Substra

+
layer

Substr
P

–
P

G N G +
ee
+
ee
+
N e
S

Fig 1.4 (a): Depletion MOSFET; VGS = 0V Fig 4 (b): VGS set at negative potential

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1.5.1 Depletion MOSFET Characteristics

ID (mA) ID(mA)
Saturation region
Breakdown region
Linear
D region
Enhancement VGS = +1V
mode
Depletion
G ID +VDS mode

VGS =0V
IDSSI DSS
VGSS

VGS = -1V
N-channel Depletion MOSFET
VGS = -2V VGS = -3V

VGS = -4V

VGS = VP = -5V, ID = 0mA

VGS (V) VP= - 5V 0 0 Cut off region VDS (V)

Fig 1.5(a): Transfer characteristics Fig 1.5(b): Output characteristics

Notice a difference in the characteristics of depletion MOSFET as compared to that of JFET.

For positive values of VGS, the positive gate will draw additional electrons (free carriers) from
the p-type substrate in to the N-type material thereby increasing the density of the charge
carriers (electrons). As a result, more current higher than IDSS can flow through the channel.
As the gate-to-source voltage continues to increase in the positive direction, Fig. 1.5(a)
reveals that the drain current will increase at a rapid rate for the reasons listed above. The fact
that more current is made to flow through the channel as a result of a positive VGS makes the
depletion MOSFET to work in enhancement mode at the positive VGS.

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1.6 ENHANCEMENT MOSFET

The Enhancement-mode MOSFET is the reverse of the depletion-mode type. Here the
conducting channel is lightly doped or even undoped making it non-conductive. When there
is no voltage on the gate, there is no current between D (Drain) and S (Source). This results
in the device being like a normally "OFF" switch when the gate is not biased. The P substrate
has holes as charge carriers, but also a few free electrons as minor charge carriers. When a
positive voltage is applied on the gate with reference to the source terminal, (i.e. +V GS), the
minor charge carriers (the free electrons) of the P-substrate are attracted to the gate. They
accumulate near the gate thereby creating an n-type channel and the MOSFET get enough
electrons to support conduction. The higher the VGS is, the greater is the electrons density and
the greater is ID. It is called an enhancement mode device because the gate voltage V GS
enhances the channel.

D
N
- Substrate

G
P

Fig 1.6: Enhancement MOSFET

Fig 1.7: Transfer and Output characteristics of Enhancement MOSFET

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1.7 IMPORTANT PARAMETERS OF FETS

There are three important parameters of the FET:

 Input resistance (ri)

 Drain resistance (rd)
 Transconductance (gm)
 Amplification factor (µ)

Input resistance (ri)

The input impedance of FETs is extremely; about 1010Ω for JFETs and up to about 1014Ω for
MOSFETs. Which means they draw no gate current at all (IG = 0mA).

𝑟𝑖 = ∞Ω

Drain Resistance (rd)

The drain resistance, rd (also called the output resistance of the FET) is obtained from the
output characteristic curve. It is defined as the ratio of the change in VDS to the relative
change in ID at a constant VGS.

𝑟𝑑 = ∆𝑉𝐷𝑆 , 𝑎𝑡 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑉𝐺𝑆

∆𝐼𝐷

The more horizontal the curve is the greater is the drain resistance. It usually lies in the range
of 20kΩ to a few hundred kΩ.

Transconductance gm

Transconductance, also known as mutual conductance, is a measure of how well the FET can
amplify a signal. It is defined on the transfer characteristic curve of an FET as a slope of a
line tangent to the curve. i.e. the ratio of the output current ID to the corresponding input
voltage VGS at constant drain – source voltage VDS.

𝑔𝑚 = ∆𝐼𝐷 , 𝑎𝑡 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑉𝐷𝑆

∆𝑉𝐺𝑆

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ID (mA)

∆ID

0
VGS (V)
∆VGS

Fig 1.8: Graphical method of determining the Transconductance gm of a JFET

However, the slope of the curve is not constant everywhere along the curve. It depends on the
value of VGS at which it is desired. Therefore transconductance has larger values near the top
of the transfer characteristics. It has a unit of A/V or Semens, S.

Mathematically,

𝑔𝑚 = ∆𝐼𝐷 , 𝑎𝑡 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝑉𝐷𝑆

∆𝑉𝐺𝑆

𝑉𝐺𝑆 1
= −2 × 𝐼 (1 − ) ×
𝐷𝑆𝑆
𝑉𝑃 𝑉𝑃

𝐼𝐷𝑆𝑆
𝑔𝑚 = 2 |𝑉 | (1 −
𝑃 𝑉𝐺𝑆
)
𝑔 =𝑔
𝑉𝑉𝐺𝑆𝑃
(1 − )
𝑚 𝑚0
𝑉𝑃

𝑔𝑚 = 𝑔𝑚0 √ 𝐼𝐼𝐷
𝐷𝑆𝑆

Where 𝑔𝑚0 is the transconductance for shorted gate and is expressed as

𝑔𝑚0 𝐼𝐷𝑆𝑆
= 2 |𝑉 |
𝑃
Notice that the minus sign in the derivation is abandoned because the transconductance
should not be negative.

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Amplification factor (µ)

It is defined as the ratio of change in the drain-source voltage VDS to the change in the gate-
source voltage VGS at constant value of ID.
∆𝑉𝐷𝑆
𝜇= , 𝑎𝑡 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡 𝐼
∆𝑉𝐺𝑆 𝐷

∆𝐼𝐷 ∆𝑉𝐷𝑆
=∆𝑉𝐺𝑆 × ∆𝐼𝐷

∴ 𝜇 = 𝑔𝑚 × 𝑟 𝑑

Example 1:

The datasheet of a certain N-channel JFET indicates that the IDSS=8mA, VGS(off)= - 3V, find
the values of ID and gm at (a) VGS= 0V, (b) VGS= -1V, (c) VGS= -2V, (d) VGS= -3V.

Solution:

Given: IDSS=8mA
VP= VGS(off) = - 3V

(a)
VGS= 0V,
𝑉𝐺𝑆
2 0
𝐷 𝐷𝑆𝑆 ) = 8 × 10−3 (1 − ) 2= 8𝑚𝐴
𝐼 = 𝐼 (1 𝑉
𝑃 −3
𝐼𝐷𝑆𝑆 𝑉𝐺𝑆 8 × 10−3 0
𝑔𝑚 = 2 (1 − )=2× (1 − ) = 5.33𝑚𝑆
|𝑉 | 𝑉 3 −3
𝑃 𝑃

(b)
VGS= -
2
1V, 𝑉𝐺𝑆 −1 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
) = 8 × 10 (1 − 3 = 3.56𝑚𝐴
−3

𝑉𝑃 −
𝐼𝐷𝑆𝑆
𝑉𝐺 8 × 10−3 −1
𝑆
𝑔𝑚 = 2 (1 − )=2 (1 − ) = 3.56𝑚𝑆
|𝑉𝑃| 𝑉𝑃 3 −3
×

(c)
VGS= -
2
2V, 𝑉𝐺𝑆 −2 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
) = 8 × 10 (1 − 3 = 0.89𝑚𝐴
−3

𝐼𝐷𝑆𝑆 𝑉𝐺𝑃 −
8 × 10−3 −2
𝑆
𝑔𝑚 = 2 (1 − )=2× (1 − ) = 1.78𝑚𝑆
|𝑉 | 𝑉 3 −3
𝑃 𝑃

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(d)
VGS= -3V,
2
𝑉𝐺𝑆 −3 2
= 8 × 10−3 (1 − ) = 0𝑚𝐴
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝐼𝐷𝑆𝑆 𝑉𝑉𝑃𝐺 −3
8 × 10−3 −3
𝑆
𝑔𝑚 = 2 (1 − )=2 (1 − ) = 0𝑚𝑆
|𝑉𝑃| 𝑉𝑃 3 −3
×

Example 2:
Sketch the transfer curve for a JFET defined by IDSS = 12mA and VP = -6V

Solution:
Two points are defined by ID = 0mA at VGS = Vp = -6V
ID = IDSS= 12mA at VGS = 0V
2
Now, at
V
(1 − 𝑉𝐺𝑆
GS = -1V, 𝐼𝐷 = 𝐼𝐷𝑆𝑆 )
𝑉𝑃
−1 2
= 12 × 10 −3
(1 − ) = 8.33𝑚𝐴
At V = -2V, 2
−6
−3 −2
GS 𝐼𝐷 = 12 × (1)− = 5.33𝑚𝐴
10
−6
At V = -3V,
−3 −3 2
GS 𝐼𝐷 = 12 × (1)− = 3𝑚𝐴
10
−6
At V = -4V,
−3 −4 2
GS 𝐼𝐷 = 12 × (1)− = 1.33𝑚𝐴
10
−6
At V = -5V,
−3 −5 2
GS 𝐼𝐷 = 12 × (1)− = 0.33𝑚𝐴
10
−6

VGS(V) -6 -5 -4 -3 -2 -1 0
ID(mA) 0 0.33 1.33 3 5.33 8.33 12

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Exercises:
1)
The manufacturers specification sheet of a certain JFET reveals that IDSS = 14mA
and the VGS(off) = 6V. Sketch the transfer characteristic of the JFET.
2)
On a transfer characteristic of a certain JFET, the following values are read: IDSS =
20mA, VP = -8V. Calculate ID, gmo and gm at VGS = -5V.

SUMMARY

 Field Effect Transistors or FET's are "Voltage Operated Devices" and can be divided
into two main types: Junction-gate devices called JFET's and Insulated-gate devices
called IGFET´s or more commonly known as MOSFETs.
 Insulated-gate devices can also be sub-divided into Enhancement types and
Depletion types. All forms are available in both N-channel and P-channel versions.
 FET's have very high input resistances so very little or no current (MOSFET types)
flows into the input terminal making them ideal for use as electronic switches.
 The input impedance of the MOSFET is even higher than that of the JFET due to the
insulating oxide layer and therefore static electricity can easily damage MOSFET
devices so care needs to be taken when handling them.
 When no voltage is applied to the gate of an enhancement MOSFET the transistor is in
the "OFF" state similar to an "open switch".
 The depletion MOSFET is inherently conductive and in the "ON" state when no voltage
is applied to the gate similar to a "closed switch".
 FETs have very large current gain compared to bipolar junction transistors.
 They can be used as ideal switches due to their very high channel "OFF" resistance,
low "ON" resistance.
 To turn the N-channel JFET "OFF", a negative voltage must be applied to the gate.
 To turn the P-channel JFET "OFF", a positive voltage must be applied to the gate.
 N-channel depletion MOSFETs are put "OFF" when a negative voltage is applied to the
gate to create the depletion region.
 P-channel depletion MOSFETs, are put "OFF" when a positive voltage is applied to the
gate to create the depletion region.
 N-channel enhancement MOSFETs are put "ON" when a positive voltage is applied
to the gate.
 P-channel enhancement MOSFETs are put "ON" when a negative voltage is applied to
the gate.

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FET type VGS = - ve VGS = 0V VGS = + ve

N – Channel JFET OFF ON -

P – Channel JFET - ON OFF

N – Channel depletion OFF ON ON

P – Channel depletion ON ON OFF

N – Channel Enhancement OFF OFF ON

P – Channel Enhancement ON OFF OFF

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2.0 BIPOLAR JUNCTION TRANSISTORS

Fig 2.1: PNP and NPN bipolar transistor symbols

The Bipolar Junction Transistor (BJT) is a three layer device made from silicon or
germanium material. There are two main types of bipolar junction transistors: the NPN and
the PNP transistor. BJTs are "Current Operated Devices" where a much smaller Base
current causes a larger Emitter to Collector current to flow. The arrow in a transistor
symbol represents conventional current flow.
A transistor can be used as an electronic switch or as an amplifier. It requires a biasing
voltage for amplifier operation such that the base-emitter junction is forward biased whereas
the collector-base junction is reverse biased. The NPN transistor requires the base to be more
positive than the Emitter while the PNP type requires that the Emitter is more positive than
the base to achieve the biasing.

2.1 BJT CHARACTERISTICS

The characteristics of a BJT are usually presented in the form of a set of graphs relating
voltage and current present at the transistors terminals.

Figure 2.1 shows a typical output characteristic (IC plotted against VCE) for an NPN
transistor operating in common-emitter mode. Each curve corresponds to a different value of
base current IB.

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IC (mA)
Active region
30
IB=50µA
25

20 IB=40µA

Saturation IB=30µA
15
region
10 IB=20µA

5 IB=10µA
IB=0µA
0 5 10 15 20 25 30 35 VCE (V)

VCE(SAT) Cut off

region VCE(MAX)

Fig 2.2: Output characteristics of bipolar junction transistor

As shown in the figure, there are three regions of operation namely cutoff region, active
region and saturation region.
Cut off region: In this region, IB is set at zero by reverse biasing the BE junction. No current
flows through the collector-emitter circuit. In this condition the transistor acts as an open
switch.
Active region: To operate the transistor in this region the BE junction is forward biased and
CB junction is reverse biased. The collector current, IC increases slightly with increase in the
voltage VCE. However, the IC is largely dependent on the base current IB. At a fixed value of
VCE, if IB is increased then it will cause IC to increase substantially, this is because IC = βdcIB,
and this relation is true only for the active region of operation. The transistor operates as
current amplifier in this region.
Saturation region: The BE and CB junction must both be forward biased to operate the
transistor in the saturation region. The transistor acts as a closed switch in this condition.
The following equations are true for bipolar junction transistors (BJT)
IE = IB + IC ……………………… (2.1)

And… IC = βIB ……………………… (2.2)

Also… IC ≅ IE ……………………… (2.3)

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2.2 AMPLIFIERS

Amplifier can be classified according to the following:

 Based on the its input:
Large signal or small signal amplifier
 Based on its output:
Voltage amplifier or power amplifier
 Based on its frequency response:
Audio frequency (AF), intermediate frequency (IF) or radio frequency (RF)
amplifier.
 Based on its biasing conditions:
Class A, class B, class AB, class C or class D amplifier.
 Based on the transistor configuration:
Common base (CB), common collector (CC) or common emitter (CE) amplifier.

If we say: small signal, class A, CE, voltage amplifier, we mean the input signal is small, the
biasing condition is class A, the transistor configuration is common emitter and the output
concerns voltage amplification.

2.2.1 DC Biasing
The ac operation of amplifier depends on the dc biasing of the transistor. The purpose of the
dc biasing is to turn the device ON by setting a fixed (steady) level of current through the
device with a desired fixed voltage drop across it so that it operates in the active region of its
characteristics. Therefore the dc biasing involves setting the initial dc values of I B, IC and
VCE. When the ac signal is applied, the IB will vary around its dc initial value, consequently,
IC and VCE would vary around their initial values.

2.2.2 DC Load Line

A dc load line is a straight line graph that represents all possible combinations of I C and VCE
for a given amplifier. Its significance is that regardless of the behavior of the transistor, I C
and VCE must always lie on it. The equation of the dc load line is derived from the output
circuit of the amplifier.

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Consider the common emitter amplifier circuit of fig. 2.3 below.

VCC Fig 2.3 (b): DC equivalent circuit

IB IC
RC
RB

RL
IE
Fig 2.3: Common emitter amplifier circuit

Applying KVL at the output

circuit, 𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐸 = 0
1
I𝐶 = − 𝑉 +𝑉 … … … … (2.4)
𝑅𝐶 𝐸 𝐶 𝐶𝐶
𝑅𝐶

This resembles the equation of a straight line 𝑦 = 𝑚𝑥 + 𝑐

We need any two points to plot this

graph. At IC = 0, VCE = VCE(SAT) = VCC

At VCE = 0, = IC(SAT) = 𝑉𝐶𝐶

𝑅𝐶
IC

IC (mA) IC (mA)

𝑉𝐶𝐶 𝑉𝐶𝐶
𝑅𝐶 𝑅𝐶 IB6

IB5
Q-pointIB4 IB3 IB2
IB1

VCE (V) VCE (V)

VCC VCC

Fig 2.4 (a): DC Load line Fig 2.4 (b): DC Load line superimposed on the output characteristics

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2.2.3 Quiescent Point (static operating point) Q-point

When a transistor does not have an ac input it will have specific dc values of IC and VCE.
These values correspond to a specific point on the dc load line. This point is called the Q-
point. The intersection of the dc bias value with the dc load line determines the Q-point. See
fig. 2.4 (b).

2.2.4 Amplifier operation

When ac signal is applied to the base of the transistor, IB will vary, IC and VCE will both vary
consequently around their Q-point values.

When the Q-point is positioned at a mid point on the dc load line, I C and VCE can both make
the maximum possible transitions below and above their initial values as depicted in fig. 2.5
(a)

When the Q-point is positioned above the mid-point on the dc load line, the input signal may
cause the transistor to saturate. When this happens, a part of the output signal will be clipped
off. See fig. 2.5 (b).

When the Q-point is positioned at a point below the mid-point on the dc load line the input
signal may cause the transistor to cut off. This will cause a position of the output signal to be
clipped off as in fig. 2.5 (c).

IC (mA)
ac input signal
IC (mA) ac input signal

ICQ Q-point ICQ Q-point

VCE (V)
VCEQ VCE (V)
VCEQ

Fig 2.5 (a): centered Q-point; maximum undistorted signal Fig 2.5 (b): Q-point above center; output signal limited by saturation

IC (mA)

ac input signal

ICQ
Q-point
VCE (V)
VCEQ

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Fig 2.5 (c): Q-point below center; output signal limited by cut off

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2.2.5 AC Load Line

The ac load line represents the ac conditions of the circuit. It does not follow the plot of the
dc load line because the ac load is different from the dc load. To draw the ac load line it is
necessary to calculate the ac load resistance. The ac load line is then drawn so that its slope is
the negative reciprocal of the ac load resistance (-1/rc) and it passes through the operating
point set by the dc condition.

IC (mA)
ac load line

𝑉𝐶𝐶
IB6
𝑅𝐶
Where 𝑟𝑐 = 𝑅𝐶ǀǀ𝑅𝐿 IB5
vce rc Q-point IB4
Rb IB3
IB2 dc load line
IB1
VCE (V)
VCC

Fig 2.6 (a): AC condition of the network in fig. 2.3 Fig 2.6 (a): AC load line

2.3 BIASING ARRANGEMENT FOR TRANSISTOR AMPLIFIERS

Ideally the Q-point is supposed to be “stable” and should not shift up or down on the dc load
line. But practically the Q-point is quite unstable and keeps changing its position. This
introduces distortion in the amplified signal. The factors affecting the stability of the Q-point
are:

 Changes in temperature: VBE decreases with increase in temperature and therefore IBQ
increases and causes ICQ to increase.
 Changes in the value of β

So we need to understand each biasing arrangement and its effect on the stability of the Q-
point on the load line.

2.3.1 Fixed Bias Circuit (Base Resistor Method)

This is simplest of all the biasing circuits. RB is the single base biasing resistor hence this
circuit is called single base resistor biasing.

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VCC

RC
RB C2

C1
ac output

ac input

Fig. 2.7 (a): Fixed bias circuit

VCC VCC

IC

RB RC
VCC VCC
RC VCC + VCE
RB
_
IB IB
+
IC VBE _

Fig. 2.7 (c): Base circuit Fig. 2.7 (d): Collector circuit
Fig. 2.7 (b): DC Equivalent

The dc analysis:

For the dc analysis the capacitors replaced with an open circuit equivalent so as to isolate the
network from the indicated ac levels. Also, the dc supply VCC can be separated into two
supplies (for analysis purposes only) as shown in the dc equivalent circuit in Fig. 2.7 (b) to
permit a separation of input and output circuits.

Consider the base circuit in fig 2.7 (c).

The KVL equation of the circuit reveals:

VCC – IBRB – VBE = 0

Rearranging,

𝑉𝐶𝐶 −
𝐼𝐵 =
𝑉𝐵𝐸 … … … … … … (2.5)
𝑅𝐵

VBE = 0.7V for silicon and 0.3V for germanium transistors.

This is the expression for the base current corresponding to the Q-point i.e. IBQ. In this
equation, VCC and RB are both fixed values. Therefore the base current IB remains constant.
Hence the name fixed bias circuit.

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The collector current corresponding to the Q-point is therefore:

ICQ = β.IBQ

Now consider the collector circuit in fig. 2.7 (d).

KVL equation of the circuit

reveals:
VCC – ICRC – VCE = 0

Rearranging, VCE = VCC – ICRC......................................(2.6)

This is the equation of the collector-emitter voltage at Q-point i.e. VCEQ

Example 2.1

Determine the following for the fixed bias configuration of fig. 2.8.
(a)
IBQ and ICQ (b) VCEQ (c) VB and VC (d) VBE

VCC = 12V

RC 2.2kΩ
240kΩ C2
RB
C1
10µF
β = 50
10µF VCE

Fig. 2.8: Fixed bias circuit for example 2.1

Solutions:

Draw the dc equivalent circuit.

VCC = +12V VCC = +12V
(a)
Apply KVL at the input circuit to get IB:
IB IC

RC2.2kΩ VCC – IBQRB – VBE = 0

RB 240kΩ

12 – 240×103 IBQ – 0.7 = 0

+
VBE
12 − 0.7
_ 𝐼 = =
𝐵𝑄 47µ𝐴 240 ×
3
10

The collector current, ICQ

ICQ = β.IBQ = 50×47×10-6 =2.35mA

(b)
Apply KVL at the output circuit to get the VCEQ.

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VCC – ICRC – VCE = 0

12 – 2.35×10-3×2.2×103 – VCEQ = 0

VCEQ = 12 – 2.35×10-3×2.2×103 =

6.83V

c) VB and VC:
VB = VBE = 0.7V
VC = VCE = 6.83V
d) VBC = VB – VC = 0.7 – 6.83 = - 6.13V

Exercise 2.1

Repeat example 2.1 with β = 75 (50% increase)

Advantages of fixed bias circuit

1) The fixed bias circuit is simple and has less number of components.
2) It gives very good flexibility as the Q-point can be set at any point in the active
region by just adjusting the values of RB.

Disadvantage of fixed bias circuit

It has very poor thermal stability so β increases with increase in temperature. Consequently,
ICQ increases and VCEQ decreases.

2.3.2 Fixed Bias Circuit with Emitter Feedback

This is also called the modified fixed bias circuit. The emitter resistor R E is added to the
ground terminal of the fixed bias circuit to serve as a negative feedback so as to improve the
bias point stability.
VCC VCC
VCC

IB IC
RC RC
RB C2 RB
1
C
ac output

ac input
IE
RE RE

Fig. 2.9(a): Fixed bias circuit with emitter feedback

Fig. 2.9(b): DC equivalent circuit

DC Analysis:

KVL at the base circuit:

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VCC – IBRB – VBE – IERE = 0

Recall that: IE = IB + IC (2.1)

and IC = βIB (2.2)

∴ IE = IB + βIB = IB(1+β).......................(2.7)

Substituting…

VCC – IBRB – VBE – IB(1+β)RE = 0

Therefore,

IBQ VCC − VBE … … … … … … … (2.8)

=
RB + (1 + β)RE

Also, ICQ = βIBQ

KVL equation of the collector circuit:

VCC – ICRC – VCE – IERE = 0

But IC ≅ IE (2.3)

Therefore… VCC – ICRC – VCE – ICRE = 0

Or VCEQ = VCC + ICQ(RC + RE)..............................(2.9)

Example 2.2:

Calculate the dc conditions of ICQ and VCEQ for the circuit of fig. 2.9, take VCC = 20V, VBE =
0.7V, RC = 2kΩ, RB = 430kΩ, , RE = 1kΩ, C1 = C2 = 10µF and β = 100.

Exercise 2.2:

Repeat example 2.2 with β = 150 (50% increase)

Advantage of Fixed Bias With Emitter Feedback on Q-point

The introduction of the emitter feedback resistor RE improved the stability of the fixed bias
as follows:

If β increases due to temperature,

Collector current (IC = βIB) increases,
Emitter current (IE = IC + IB) increases

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Voltage drop on RE (VE = IERE) increases,

𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝑉𝐸
Base current, = , decreases.
𝐼𝐵 𝑅𝐵

Hence the increased collector current will be reduced with decrease in IB.

2.3.3 Collector to Base Bias Circuit (Collector Feedback Bias)

The collector to base bias circuit is an improvement over the fixed bias circuit. The base
resistor is now connected to the collector and not to the supply voltage VCC directly. The
current flowing through the RC is the sum of IC and IB as shown in fig. 2.11. As the RB is
connected between the collector (output) and base (input), a part of the output is being
feedback to the input. Therefore this bias is also called as voltage feedback bias circuit.

VCC
VCC
IC + IB IC + IB

RB IB RC C2 RB IB RC C
IC
C1 + ac output IC
C1 +
VCE ac
VCE
+ _
ac input + _
VBE _
IE ac input VBE _
IE
RE RE

Fig. 2.10 (a): Collector-base bias circuit

Fig. 2.10 (b): DC equivalent circuit

DC Analysis

Applying KVL at the base circuit,

VCC – (IC + IB)RC – IBRB – VBE – IERE = 0

But recall that (IC + IB)= 𝐼𝐸 ≅ IC (equations 2.1 and 2.3)

And… IC = βIB (equation 2.2)

∴ VCC – ICRC – IBRB – VBE – ICRE = 0

VCC – βIBRC – IBRB – VBE – βIBRE = 0

IBQ = VCC − VBE … … … … … … (2.10)

RB + β(RC + RE)

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Applying KVL at the collector circuit,

VCC – (IC + IB)RC – VCE – IERE = 0

VCE = VCC – (IC + IB)RC – IERE

Since IE ≅ IC and IC + IB ≅ IC,

VCEQ = VCC – ICQ(RC + RE) (Similar to equation 2.9)

Advantage of Collector to Base Bias on Q-point Stability

If β increases due to temperature,

Collector current (IC = βIB) increases,
Emitter current (IE = IC + IB) increases
Voltage drops on RC and RE (VC = (IC + IB) RC and VE = IERE) increase,
𝑉𝐶𝐶 − 𝑉𝐵𝐸 − 𝑉𝐶 − 𝑉𝐸
Base current, = , decreases.
𝐼𝐵 𝑅𝐵

Hence the collector current will be maintained constant to some extent. Therefore the Q-point
is stabilized.

Example 2.3

For the circuit of fig. 2.11(a), take VCC = 10V, VBE = 0.7V, RC = 4.7kΩ, RB = 250kΩ, , RE =
1.2kΩ, C1 = C2 = 10µF and β = 90. Calculate the quiescent levels of ICQ and VCEQ.

Solution:

Equation (2.11.2)
VCC − VBE
IBQ =
RB + β(RC + RE)

IBQ = 10 − 0.7 = 11.91μA

250 × 10 + 90(4.7 × 103 + 1.2 × 103)
3

ICQ = βIBQ = 90 × 11.91 × 10−6 =

1.07mA Equation (2.11.2): VCEQ = VCC – ICQ(RC + RE)

= 10 – 1.07 × 10−3(4.7 × 103 + 1.2 × 103) = 3.69V

Exercise 2.3:
Repeat example 2.2 with β = 135 (50% increase)

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2.3.4 Voltage Divider Bias

In the previous bias circuits IBQ and VCEQ were dependent on the current gain (β) of the
transistor. Since the current gain, β is temperature sensitive and its actual value is not fixed, it
will be desirable to develop a circuit that is independent on the transistor β. Voltage divider
bias of fig. 2.12(a) is almost independent.
+VCC +VCC
+VCC

RC
RC R1 C2
R1 C2

C1 C
ac output ac

ac input ac
R2
R2 RE
RE

Fig. 2.11 (a): Voltage divider bias configuration Fig. 2.11 (b): DC equivalent circuit

+ +VC + +VC
V V
C C

RC R
C2 C
C2

R1
C a R1
C a
+

a CC a CC
V R2 VTH
V R2
RE RTH
b b _

Fig. 2.11 (c): DC equivalent circuit redrawn Fig. 2.11 (d): Portion of the Base circuit

+ +VCC
+ +VC
V V
C CC

RC
R C2 C2
C

CTHa C
R RTH a
+ ac

a ac IB
VTH R V VTH
T RE
b _ b

Fig. 2.11 (e): Thevenin equivalent Fig. 2.11 (f): DC equivalent circuit 2

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The analysis of the voltage divider network requires the application of Thevenin’s theorem.
The Thevenin equivalent circuit is as shown in fig. 2.11 (f).

The RTH can be found by replacing the voltage source VCC in fig. 2.11 (d) with a short circuit.
RTH is then the equivalent resistance “seen” between terminals “a” and “b”.

𝑅𝑇𝐻 = 𝑅1ǀǀ𝑅2.................................................. (2.11)

The VTH is the voltage across terminals “a” and “b” which is essentially the voltage on
resistor R2.
𝑅2
𝑉 = 𝑉
… … … … … .. (2.12)
𝑇𝐻 𝐶𝐶
𝑅1 + 𝑅2
Applying KVL at the base circuit of fig. 2.11 (f)

𝑉𝑇𝐻 − 𝐼𝐵𝑅𝐵 − 𝑉𝐵𝐸 − 𝐼𝐸𝑅𝐸 = 0

Substituting IE = IB + IC = IB + βIB = (1+β)IB,

𝑉𝑇𝐻 − 𝐼𝐵𝑅𝐵 − 𝑉𝐵𝐸 − (1 + β)𝐼𝐵𝑅𝐸 = 0

𝐼𝐵𝑄 = 𝑉𝑇𝐻 − 𝑉𝐵𝐸 … … … … … (2.14)

𝑅𝐵 + (1 + β)𝑅𝐸

Applying KVL at the output circuit in fig. 2.11 (f)

𝑉𝐶𝐶 − 𝐼𝐶𝑅𝐶 − 𝑉𝐶𝐸 − 𝐼𝐸𝑅𝐸 = 0

𝑉𝐶𝐸𝑄 = 𝑉𝐶𝐶 − 𝐼𝐶𝑄(𝑅𝐶 + 𝑅𝐸) (Similar to equation 2.9)

Example 2.4
With reference to the voltage divider network of fig. 2.11(a), determine the static values of
ICQ and VCEQ if VCC = 22V, R1 = 39kΩ, R2 = 3.9kΩ, RC = 10kΩ, RE = 1.5kΩ and β = 140.

Exercise 2.4
Repeat example 2.4 with value of β = 95 and comment on your answers.

2.3.5 JFET Self Bias

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In JFETs amplifiers the approach for obtaining the quiescent point parameters, IDQ and VDSQ
is a bit different from the BJT amplifiers. JFETs are voltage-controlled transistors, the
controlling quantity is VGS. The relationship between the controlling quantity and the drain
current ID is not linear; it is defined by the Shockley’s equation.

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − … … … … … … (2.13)
𝑉𝑃 )
The approach therefore requires the solution of two equations; the Shockley’s and the one
established by the network in order to determine the quiescent level of IDQ. The solution can
be obtained graphically of mathematically. The VDSQ can then be obtained in the same way
as VCEQ in BJT amplifiers.

One of the simple biasing circuits is the self bias configuration is depicted in fig. 2.12 (a).

VDD VDD
ID
ID
RD +
RD
C2

C1 D D+
IG G ac output GVDS
IG +_
ac input
S VGS _ S
R S IS
RG RG
RS

IS

Fig 2.12 (a): JFET Self bias configuration Fig 2.12 (b): DC equivalent circuit of Fig 2.12 (a)

The resistor RG is present to ensure that vi appears at the input to the JFET amplifier for the
ac analysis.
Taking into consideration that:
IG = 0A
Therefore… IS = ID.................................................................................(2.14)

The dc analysis can be done as follows:

Applying KVL at the input circuit (fig. 2.12 (b))

𝑉𝑅𝐺 − 𝑉𝐺𝑆 − 𝑉𝑅𝑆 = 0

But 𝑉𝑅𝐺 = 𝐼𝐺𝑅𝐺 = 0 since IG = 0A.

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Therefore… 𝑉𝐺𝑆 = −𝑉𝑅𝑆

Or… 𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆 ……….. (2.15)

Equation 2.15 is defined by the network configuration, and Shockley’s equation (2.13)
relates the input and the output quantities of the device. Both equations relate the same two
variables, permitting either a mathematical or graphical solution.
A mathematical solution could be obtained simply by substituting equation 2.15 into
Shockley’s equation as shown below:

𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − 2
−𝐼𝐷𝑅𝑆
𝑉𝑃 )
𝐼𝐷𝑅𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 + )
𝑉𝑃
By performing the squaring process and rearranging the terms, an equation of the following
form can be obtained:
𝑎𝐼2 + 𝑏𝐼𝐷 + 𝑐 = 0 …………..2.16
�

The quadratic equation can then be solved for the appropriate solution of IDQ.

The graphical method requires the plot of Shockley’s equation and the equation of the
network on the same graph, the point of intersection between the two plots gives the solution
of the two equations.

The level of VDS can be determined using KVL at the output circuit. Thus:

𝑉𝐷𝐷 − 𝑉𝑅𝐷 − 𝑉𝐷𝑆 − 𝑉𝑅𝑆 = 0

𝑉𝐷𝐷 − 𝐼𝐷𝑅𝐷 − 𝑉𝐷𝑆 − 𝐼𝐷𝑅𝑆 = 0

Or… 𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝐷 + 𝑅𝑆).........................2.17

Example 2.4

With reference to the network of fig. 2.12, determine the following:

(a)
VGSQ (b) IDQ (c) VDSQ (d) VS (e) VG (f) VD

Take VDD = 20V, IDSS = 8mA, VP = -6V, RD =3.3kΩ, RG = 1MΩ, and RS = 1kΩ, C1 = C2 =
10µF.

Solution:
Using the mathematical approach:
(Starting with question (b))

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Equation (2.15) 𝑉𝐺𝑆 = −𝐼𝐷𝑅𝑆

𝑉𝐺𝑆 = −(1 × 103)𝐼𝐷......................(i)

2
Equation (2.13) 𝐼 = (1 − 𝑉𝐺𝑆
𝐼 𝐷 𝐷𝑆𝑆 )
𝑉𝑃

Inserting (i) into (2.13):

−(1 × 103)𝐼𝐷 2

𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

−(1 × 103)𝐼𝐷 2
𝐼𝐷 = 8 × 10 −3
(1 − )
−6

𝐼𝐷 = 8 × 10−3(1 − 166.67𝐼𝐷)2
Squaring: 𝐼𝐷 = 8 × 10−3(1 − 333.33𝐼𝐷 + 27777.78𝐼2)
�
𝐼𝐷 = 0.008 − 2.67𝐼𝐷 + 222.22𝐼2)
�
Rearranging: 222.22𝐼2 − 3.67𝐼𝐷 + 0.008 = 0
�
Solving the quadratic equation reveals that:
𝐼𝐷 = 13.9𝑚𝐴 𝑜𝑟 𝐼𝐷 = 2.58𝑚𝐴
𝐼𝐷 = 13.9𝑚𝐴 is beyond the value of IDSS of the JFET, we therefore neglect it and take
the value of IDQ to be:
IDQ = 2.58mA.
(a)
Substituting IDQ = 2.58mA in equation (i):

𝑉𝐺𝑆 = −(1 × 103)𝐼𝐷 = −(1 × 103) × 2.58 × 10−3

𝑉𝐺𝑆𝑄 = −2.58𝑉
(c) Equation (2.1.7) 𝑉𝐷𝑆𝑄 = 𝑉𝐷𝐷 − 𝐼𝐷(𝑅𝐷 + 𝑅𝑆)
= 20 − 2.58 × 10−3(3.3 × 103 + 1 × 103)
= 8.9𝑉
(d) 𝑉𝑆 = 𝐼𝐷𝑅𝑆 = (2.58𝑚𝐴) × (1𝑘Ω) = 2.58𝑉
(e) 𝑉𝐺 = 𝐼𝐺𝑅𝐺 = 0𝑉
(f) 𝑉𝐷 = 𝑉𝑆 + 𝑉𝐷𝑆 = 2.58 + 8.9 = 11.48𝑉

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2.4 AC EQUIVALENT CIRCUITS

We shall examine the ac equivalent circuit and determine with it the voltage gain A V, the current gain
Ai, input impedance Zi, and the output impedance Zo for the configurations observed so far.

The model for the BJT in the ac domain can be seen in figure 2.13(a).

C b c

B
βre βIb ro
E e e

Fig. 2.13(a): BJT ac equivalent

The control of Ic by Ib is represented by the current source βIb. The values of β and ro are directly
obtained from the manufacturer specification sheet (data sheet). re is determined from the dc analysis
of the amplifier circuit. It is given as:

𝒓𝒆 = 𝟐𝟔𝒎𝑽 … … … … … … … … … . (2.18)
𝑰𝑬

The model for the FET in ac domain is seen in fig 2.13(b).

G D
D +
VGS
G
gmVGS rd

S _
S S

Fig 2.13(b): JFET ac equivalent circuit

The dependence of ID on VGS is included as a current source gmVGS connected from drain to source as
shown in the figure. The high input impedance is represented by the open circuit at the input
terminals and the output impedance by the resistor rd from drain to source. The value of rd is given by
the manufacturer as 1/yos.

To draw an ac equivalent circuit, voltage sources and capacitors are short circuited.

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2.4.1 Fixed Bias Circuit:

VCC

RC
RB C2 Ic
IiIb
C1 Vi Vo
Io
ac output

Zi RB βre βIb ro RC Zo
ac input
RE CE

e e

Fig. 2.14(a): Fixed bias circuit with emitter feedback

Fig. 2.14(b): ac equivalent circuit

Fig 2.14 (b) shows the ac equivalent model for the common emitter amplifier such as the one shown
in fig 2.14 (a). The RE is shorted by the capacitor C E. The applied signal is represented by V i and the
output signal across RC by Vo.

Looking at fig 2.14(b), we can see the following:

 The input impedance

𝒁𝒊 = 𝑹𝑩//𝖰𝒓𝒆 … … … … … … … … . (2.19)

 The output impedance Zo: This can be obtained by “putting off” the input source and then looking
at the impedance of the circuit from the output side.

Vo

RB βre βIb roRC Zo

e e
Fig. 2.14(c): Determining the output impedance

We can clearly see that RB and βre will reduce to zero for being in parallel with a short circuit. The
current source which is a function of Ib will also reduce to zero because the voltage producing the Ib is
not present.

The output impedance

𝒁𝒐 = 𝒓𝒐//𝑹𝑪 … … … … … … … … (2.20)

 The Voltage Gain (AV)

𝐴𝑉 = 𝑉𝑜
𝑉𝑖

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But

𝑉𝑜 = −𝛽𝐼𝑏(𝑅𝐶//𝑟𝑜)
And
𝐼𝑏 = 𝑉𝑖
𝛽𝑟𝑒
So.. 𝑉𝑖
𝑉 = −𝛽( )(𝑅 //𝑟 )
𝑜 𝐶 𝑜

Therefore… 𝛽𝑟𝑒
𝑉𝑜 (𝑅𝐶//𝑟𝑜)
𝑉𝑖 = − 𝑟𝑒

(𝑹𝑪//𝒓𝒐)
𝑨𝑽 = − … … … … … … … (2.21)
𝒓𝒆

 The Current Gain (Ai)

𝐴𝑖 = 𝐼𝑜
𝐼𝑖

−𝑉𝑜/𝑅𝐶 𝑉𝑜 𝑍𝑖
𝐴𝑖 = = ×
𝑉𝑖/𝑍𝑖 𝑉𝑖 𝑅𝐶

𝒁𝒊
𝑨𝒊 = 𝑽 … … … … … … … . (2.22)
𝑨
𝑹𝑪

Example 2.5

With reference to the circuit of fig 2.14(a), take VCC = 12V, RB = 470kΩ, RC = 3kΩ, RE =1kΩ, C1 =
C2 = 10µF, β = 100 and ro =50kΩ. Calculate the following:

a)
re
b)
Zi
c)
Zo
d)
AV
e) Ai

Solution:

We have to calculate the value of IE from the dc analysis.

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VCC VCC
KVL at the input circuit:

IB IC VCC – IBRB – VBE – IERE = 0

RC
RB
But IE = IC + IB = βIB +IB

IE = IB(1+β) …….(i)
IE
RE
Therefore,

VCC – IBRB – VBE - IB(1+β)RE = 0

VCC − VBE
IB = RB + (1 + β)RE

12 − 0.7
B
I 470 × 103 + (1 + 100) × 1 × 103 = 19.8μA

Inserting IB into equation (i)

IE = 19.8×10-6×(1+100) = 2mA

𝑡ℎ𝑒𝑟𝑒𝑓𝑜𝑟𝑒:
26 × 10−3
𝑟𝑒 =
= 13Ω
2 × 10−3
b) 𝑍𝑖 = 𝑅𝐵//𝛽𝑟𝑒 = (470 × 103)//(100 × 13) = 1.29kΩ

c) 𝑍𝑜 = 𝑟𝑜//𝑅𝐶 = (50 × 103)//(3 × 103) = 2.83𝑘Ω

d)

(3 × 103)//(50 × 103)
𝐴𝑉 = − (𝑅𝐶//𝑟𝑜)
𝑟𝑒 =− = −217.7
13
e)
𝑍𝑖 3
𝐴 =𝐴 = 217.7 × 1.29 × 10
𝑖 𝑉
𝑅𝐶 = 94.25
3 × 103

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2.4.2 JFET Self Bias Circuit

VDD
ID

RD

C2

C1 D
IG G ac output G D
+
ac input Vgs Zo
S Zi
RG gmVgs rd RD
RG
RS C s
_
S S

Fig 2.15(b): ac equivalent circuit of the network

Fig 2.15 (a): JFET Self bias configuration

Note that both capacitors and voltage sources are replaced with short circuits. Also note the define
polarity of Vgs which defines the direction of gmVgs. If Vgs is positive (as in p-channel JFET) the
direction of gmVgs current source reverses.

 Input Impedance Zi:

𝒁𝒊 = 𝑹𝑮 … … … … … … … … . (2.23)

 Output impedance Zo:

Setting Vi = 0 as required by the definition of output impedance will result in Vgs = 0. The result is
gmVgs = 0mA and the current can be replaced by an open circuit equivalent.

Vo

gmVgs = 0mA RD Zo
rd

 Voltage gain AV:

The output voltage 𝑉𝑜 = −𝑔𝑚𝑉𝑔𝑠(𝑟𝑑//𝑅𝐷)
The input voltage 𝑉𝑖 = 𝑉𝑔𝑠
Therefore 𝑉𝑜 = −𝑔𝑚𝑉𝑖(𝑟𝑑//𝑅𝐷)
The voltage gain: 𝑉𝑜
𝐴 = = −𝑔 (𝑟 //𝑅 )
𝑉 𝑚 𝑑 𝐷
𝑉𝑖
 The current gain Ai:

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𝐴𝑖 = 𝐼𝑜
𝐼𝑖
𝐼𝑜 = , 𝑉𝑖
𝑉𝑜 = 𝑍𝑖
𝑅𝐶 𝐼𝑖
Therefore..
𝑉𝑜 𝑉 𝑍
⁄𝑅
𝐴𝑖 = 𝑜 𝑖
𝑉 𝐶
= ×
𝑖⁄ 𝑉 𝑖 𝑅𝐶
�𝑖
𝐴𝑖 = 𝑍𝑖
× 𝑅𝐶
𝐴𝑉
Example 2.6
Given that VGSQ = -2V, IDQ = 5.625mA and yos =40µS, determine the following:
(a) gm (b) rd (c) Zi (d) Zo (e) AV (f) Ai

VDD
ID

2kΩ

10µF

10µF D
G ac output
ac input
S

1MΩ
1kΩ 100µ F

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2.4.3 Effect of RS And RL On The Gain Of The Amplifier.

The source internal resistance may have effect on the overall gain of the amplifier. The larger the
resistance the larger the effect.

VCC

RC C2
RB VO
RS C1
Vi

RL
VS
RE CE

Fig. 2.16(a): Effect of RS and RL on the gain

Ii R Vi Ib Ic Vo
Io

RB βre ro RC
Zi βIb RL Zo
V

Fig. 2.16(b): ac equivalent circuit

The Voltage gain AV:

𝑉𝑜 𝑉𝑜 𝑉𝑖
𝐴 = = × = 𝑉𝑖
𝐴 ×
𝑉𝑆
𝑉 𝑉 𝑉 𝑉
𝑉𝑠
𝑠 𝑖 𝑠

By voltage divider rule

𝑍𝑖
𝑉 = 𝑉 𝑽𝒊 𝒁𝒊
𝑖 𝑠 ⟹ =
𝑍𝑖 + 𝑅𝑠 𝑽 𝒔 𝒁𝒊 + 𝑹 𝒔

Therefore..

𝑨𝑽𝑺 = 𝑨𝑽 × 𝒁𝒊
𝒁𝒊 + 𝑹 𝒔

The current gain Ai:

𝑉𝑜
𝐼 𝑅 𝑍
𝐴𝑖 = 𝑜 = 𝐿⁄ = 𝐴𝑉 × 𝑖
𝑆
𝐼𝑖 𝑉𝑖 𝑅𝐿
𝑍𝑖

3.0 CLASSIFICATION OF AMPLIFIERS

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Depending on the position of the Q-point or the operating point on the load line, the amplifiers are
classified into the following four categories:

S/No Type of Amplifier Position of Q-point

1 Class A At the center of the load line
2 Class B At the cut off region
3 Class AB Just above the cut off
4 Class C Below the cut off

3.1 Class A Amplifiers:

An amplifier is referred to as class A amplifier if its Q-point is set to be at the center of the load line
and as such the transistor used for the amplification conducts for the full cycle duration of the input ac
signal. Hence the output signal is obtained for the full cycle of the input signal.

As the ac signal is applied to the base of the transistor, the base current changes sinusoidally above
and below the quiescent base current IBQ as shown in fig 3.1.

In response to the changes in IB, the collector current changes sinusoidally above and below its
quiescent value ICQ. The collector current and the base current are in phase with each other.

Due to change in IC, the voltage VCE will also fluctuate sinusoidally below and above its quiescent
value VCEQ as shown in the fig 3.1. The VCE and IC are 180o out of phase.

IC(mA)

IBmax
IBQ ωt
IBmin
IBmax
IBmin ICmax
IBQ
ICmax
ICQ ωt
ICQ Q
ICmin
ICmin

VCEmax
VCE(V)
ωt
VCEQ

VCEmin
VCEmin

VCEmax

Fig 3.1: Graphical representation of class A amplifier operation

Observations for class A amplifier

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 The transistor conducts for the complete 360o of the input sinal.
 The output waveform is therefore a faithful amplification of the input waveform. No distortion
is introduced.
 As the transistor continuously operates in the active region, the V CE across it and the current through
it are both simultaneously high. Therefore the a large power is dissipated in the form of heat which
consequently renders the efficiency of the class A amplifier low.
 Typically the efficiency of a class A amplifier lies between 25% to 50%.

3.2 Class B Amplifier

A class B amplifier is the one whose Q-point is set at the cut off and as a result produces only one
half cycle of the input signal as the output.

IC(mA)

IBmax
IBQ ωt
IBmin

ICmax

ICQ ωt

VCEQ ωt
Q
ICQ VCE(V)
VCEmin

VCEQ

Fig 3.2: Graphical representation of class B amplifier operation

Observations for class B amplifier

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 As the ac input signal is applied to the base of the transistor, the B-E junction of the transistor is
forward biased only during the positive half cycle of the input signal and the base current starts
flowing.
 During the negative half cycle the transistor remains in the off state. Thus, the collector current
conducts for only 180o of the input signal. This means that only one half cycle is obtained for a full
cycle of the input signal. Therefore the output wave form is distorted because it does not resemble the
input wave form.
 As the transistor remains off for a complete half cycle, the power dissipation in the transistor is
reduced as compared to that of class A amplifier. Therefore the efficiency of class B amplifier
is higher than that of class A. The maximum efficiency of a class B amplifier is 78.5%

3.2.1 push-pull operation of class B amplifier

In order to obtain a complete 360o output wave form with class B amplifier, a connection known as
push-pull configuration is employed. The configuration involves the use of two transistors in alternate
half cycles of the input signal such that one transistor responds to the positive and the other responds
to the negative half cycles. The resulting two halves are put back together again at the output
terminal. The circuit is referred to as a push-pull circuit because one part of the circuit pushes the
signal high during one half-cycle and the other part pulls the signal low during the other half-cycle.

VCC

R1
C1 Cross over distortion
NPN
C3
R2
C2
PNP RL
R3

Fig 3.3: Push –pull configuration of class B amplifier

3.2.2 Crossover Distortion

Crossover distortion refers to the fact that during the signal crossover from positive to negative (or
vice versa) there is some nonlinearity in the output signal. This results from the fact that the circuit
does not provide exact switching of one transistor OFF and the other ON at the zero-voltage
condition. Both transistors may be partially OFF so that the output voltage does not follow the input
around the zero-voltage condition. Biasing the transistors in class AB improves this operation by
biasing both transistors to be ON for more than half a cycle.

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3.3 Class AB Amplifier

An amplifier is referred to as class AB if the Q-point is set slightly above the cut off region so that the
output signal is obtained for more than 180o but less than 360o of the input signal.
IC(mA)

IBmax
IBQ ωt
IBmin

ICmax

ICQ ωt

VCEQ ωt
ICQ VCE(V)
Q VCEmin

VCEQ

Fig 3.4: Graphical representation of class AB amplifier operation

Observation for class AB operation

 The transistor conducts for a complete positive half cycle and a part of negative half cycle of the input
signal.
 The output signal is distorted but the distortion can be eliminated by the use of two transistors that
conduct in the alternate half cycles of the input signal. the class AB operation is helpful in eliminating
the cross-over distortion.
 The Q-point lies somewhere between that of class A and that of class B, hence the name class AB. Te
transistor conducts for more than 180o (class A) but less than 360o (class B), therefore the power
dissipation in the transistor is less than that in class A but more than that in the class B amplifier.
Hence the efficiency of class AB amplifier is higher than that of class A but less than that of class B
amplifier.
 Class AB amplifier is preferred in all the audio systems, radio, TV, receivers and so on.

3.4 Transformer coupled class A Amplifier

Transformer coupling in class A amplifier is used to increase the efficiency to 50%. The transformer
is used to couple the output signal to the load as shown in fig 3.4. The power dissipation by the
collector resistor RC is eliminated. The primary winding of an ideal transformer is assumed to have
zero resistance.

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A transformer can increase or decrease voltage or current levels according to the turns ratio, as
explained below. In addition, the impedance connected to one side of a transformer can be made to
appear either larger or smaller (step up or step down) at the other side of the transformer, depending
on the square of the transformer winding turns ratio.
Remember:
𝑁1 𝑉1 𝐼2
𝑁2 = 𝑉2 = 𝐼1

Since the voltage and current can be changed by a transformer, an impedance “seen” from either side
(primary or secondary) can also be changed. An impedance RL is connected across the transformer
secondary. This impedance is changed by the transformer when viewed at the primary side to be R L’.
This can be shown as follows:

𝑉1 𝑉 𝐼 𝑁 𝑁
𝑅′ 𝐼 ⁄
2
𝑁
𝐿 1 1 2 1 1 1
= = × = × =( )
𝑉 𝑉 𝐼 𝑁 𝑁 𝑁2
𝑅𝐿 2⁄
𝐼 1 2 1 2 2

′
𝑅 = (𝑁 2
� 1)
𝑅𝐿 𝑁2
Example 3.1:
Calculate the effective resistance seen looking into the primary of a 15:1 transformer connected to an
8Ω load.

Solution
𝑅 �′= (𝑁1)2
𝑅𝐿 𝑁2
𝑅′ = (
𝑁1)2 𝑅𝐿
� 𝑁2
′
15 2

𝑅𝐿 = ( ) 8 = 1.8𝑘Ω
1
Exercise 3.1
What transformer turns ratio is required to match a 16Ω speaker load so that the effective load
resistance seen at the primary is 10 kΩ?

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