Radiation-hardened electronics, also called rad-hard electronics, are

electronic components (circuits, transistors, resistors, diodes,

capacitors, etc.), single-board computer CPUs, and sensors that are
designed and produced to be less susceptible to damage from
exposure to radiation and extreme temperatures
In this paper, a highly stable and low-cost 12T (HSLC12T) radiation hardened

static-random-access-memories (SRAM) cell is proposed in 55 nm CMOS technology.

Having the maximum read static noise margin (RSNM) and lower static hold power,

as well as excellent write speed and write-ability.

Though the HSLC12T cell exhibits a larger read delay, it has the best overall performance of all other

cells. This is proven by having the highest electrical quality metric (EQM)

value, thus making the proposed HSLC12T cell a better choice for aerospace

applications.

Introduction :

(SRAM) currently occupy a sizable component of today's system-on-chips (SoCs) due to

their high packing density and enhanced logic performance in digital processing and the control system

Reducing the power consumption of latches (including flip-flops) and SRAM is a critical way to reduce the
energy consumption of the SoCs. Latches power reduction is often achieved by adding clock-gating
structures,2 while the most effective way to reduce the energy consumption of SRAM is to reduce power
by scaling down the supply voltage (VDD). However, as VDD is scaled down, the operational delay
increases, yield decreases, and critical charge decreases.

If the charge collected exceeds the critical charge of the original logic state of a sensitive node, it will
lead to a large current/voltage transient fault (TF) known as a single event transient (SET). Once the SET
is captured or generated in a memory element, it becomes a single event upset (SEU) and a soft error is
produced, creating a significant reliability concern for the circuit utilized in aerospace applications

standard 6T SRAM may not offer sufficient reliability in the radiation environment of space.

Slide3:

To mitigate soft errors, researchers have developed error correction codes (ECCs) and radiation
hardening by design (RHBD) approaches
However, due to additional encoding and decoding circuitry, ECC was shown to have more area, power,
and latency overhead than soft error tolerant cells, which may make them unsuitable for aerospace

applications

the Quatro10T cell, which has a much lower soft error rate (SER) compared

with the standard 6T cell and a 50% rate ECC-protected

it is possible to conclude that soft error tolerant cells with high critical charge (Q crit) may be better
choices for highly reliable applications. However, Quatro10T is capable of recovering from a “1” -> “0”
SEU only.

Slide4:

Furthermore, Quatro10T exhibits a longer write latency and a higher

write failure probability, especially at low supply voltage. To deal with these issues, a writability-
enhanced Quatro12T cell is proposed

However, we-Quatro12T is also partially immune to SEU.

Jung et al proposed

the NMOS stacked 10T (NS10T) and PMOS stacked 10T (PS10T), which provide partial tolerance in the
case of two distinct types of SEUs: from “1” to “0” or from “0” to “1”. Jiang et al. demonstrated two more
radiation hardened cells,

QUCCE10T and QUCCE12T, to recover SEUs of both polarities at the storage nodes

Slide5:

The RHD12T cell with favorable radiation hardness

Besides the toleration for SEUs on any of its internal single nodes, it can also offer partial single event
double-node-upsets (SEDNUs) immunity. Unfortunately, its use is restricted by its slow writing speed. To
address this problem, the RSP14T cell was proposed

the use of a vast number of PMOS transistors has caused an

increase in area while also making them less resistant to soft errors. According to Amusan the PMOS
transistor
has higher parasitic bipolar amplification compared to that of the NMOS transistor. Because the RSP14T
cell uses more

PMOS transistors, the soft error generated will be more serious.

Slide6:

to solve these two problems, the SIS10T cell was proposed by Pal et al.17 The SIS10T cell includes 2
PMOS

transistors and 8 NMOS transistors, thus providing better soft error tolerance and better circuit
performance with low area cost.

Yan et al.19 proposed the QCCS12T cell and its reliability-improved version, the SCCS18T cell,

where the QCCS12T cell can only tolerate SEU and the SCCS18T cell can tolerate partial SEDNUs but at a
very high cost in terms of power consumption and area.

Slide7:

FIGURE1 / In order to overcome these aforementioned drawbacks, we proposed a highly stable and low-
cost 12T (HSLC12T) radiation hardened SRAM cell (as shown in Figure 1A). The major contributions of
HSLC12T are summarized as

follows:

1. Since only 2 PMOS transistors are used, the proposed cell mitigates the parasitic bipolar effect and
provides better soft error tolerance.

2. Based on its polarity-reversal design, HSLC12T can recover from any SEU induced at all the sensitive
nodes and even from SEDNU induced at its internal node pairs Q-QN.

3. Because of the 4 access transistors for writing and the smaller transistor size in the memory cell,
HSLC12T shows the shortest write delay and lower static hold power consumption than all other
comparison radiation hardened

cells.

4. Among all radiation hardened cells compared, the proposed HSLC12T cell has the highest electrical
quality metric

(EQM).

In addition to the two above, Pal et al.18 have also presented the RHMD10T cell which is based on
polarity reversal and circuit capacitance.

the RHMD10T cell has a reduced static power consumption.

Figure 1A shows the schematic of the proposed HSLC12T cell, and the corresponding layout is shown in
Figure 1B.

The HSLC12T cell has four storage nodes: S0, S1, Q, and QN, which are connected to the bit lines BL and
BLB through

access transistors N7, N8, N9, and N10, respectively. WL and WRL control access transistors and enable
them when

WL or WRL is at high logic state.

PROPOSED HSLC12T CELL DESIGN AND ITS OPERATION

2.1 | Cell structure and normal working principles

is a description of the basic working principle of the proposed

HSLC12T cell, and for convenience, the case of the cell's stored “1” state is taken into consideration,
which means the

logic states of nodes Q, QN, S0, and S1 are “1,” “0,” “1,” and “0”, respectively.

1. In hold mode, access transistors N7-N10 are turned OFF by setting WL and WRL to “0,” and the bit-
lines BL and

BLB are pre-charged to VDD to reduce wake-up time. Transistors N2, N4, N5, and P1 are turned ON while
N1, N3,

N6, and P2 are turned OFF. Therefore, the data is steadily maintained in the cell.

2. In read operation, both bit-lines BL and BLB will be pre-charged to VDD in the first step, and access
transistors N9

and N10 are activated by setting WL to “0” and WRL to “1” afterwards. Thus, BLB will be discharged
because N4

and N10 are turned ON, creating two paths from BLB to GND. Because N3 is still OFF, BL remains at VDD.
Then,

the voltage difference obtained from BL and BLB will be amplified by a differential sense amplifier and
output the

data stored in this memory cell. For a reliable read operation, the pull-down (N3, N4)-to-access (N9, N10)
ratio
CRPDA should be set properly to acquire a good read static noise margin (RSNM) and ensure integrated
density at

the same time.

3. In write operation, in order to change the initial stored data “1” of the HSLC12T cell in Figure 1A, BL is
set to be

“0” and BLB is set to be “1”. Once the access transistors N7-N10 are activated by setting WL and WRL to
“1” simul-

taneously, BL pulls down the potential at nodes Q and S0 through N7 and N9, so that N2, N4, and N5 are
turned

OFF and P2 is turned ON. BLB pulls up the potential at nodes S0 and Q through N8 and N10 to VDD-
VthN, so N1,

N3, and N6 are partially turned ON and P1 is partially turned OFF. The cross-coupled feedback structures
in the cell

will further amplify the voltage difference between nodes Q, QN, S0, and S1, accelerating the change of
voltage.

Eventually, the nodes will be modified to new data, and Q, QN, S0, and S1 will be set to be “0,” “1,” “0,”
and “1”,

respectively. It is worth noting that in order to realize the above functions, N10 should be stronger than
P2. Considering the PMOS transistor has smaller carrier mobility than the NMOS transistor, the related
pull-up (P1, P2)-to-

access (N9, N10) ratio CRPUA can be set to 0.7. This will also save more areas.

Slide8:

In Figure 2A, “write 1,” “read 1,” “write 0,” and “read 0” operations are simulated to verify the whole
functionality

of the proposed HSLC12T cell.

F I G U R E 2 (A) Post-layout function simulation results for the highly stable and low-cost 12T (HSLC12T)
cell.

(B) Generation of the transient pulse when a high-energy particle strikes the NMOS of an inverter in an
integrated circuit.

(C) Positive transient voltage pulse is generated when a high-energy particle strikes a PMOS.
(D) Negative transient voltage pulse is generated when a high-energy particle strikes

an NMOS.

Slide9:

SEU recovery analysis

The SEU recovery analysis results for the proposed HSLC12T cell are presented as follows: Based on
previous research, the sensitive areas of semiconductor devices are the strongly reverse-biased diffusion
areas where the induced transient

current flows from the N-type diffusion to the P-type diffusion20 (as shown in Figure 2B).

As a result, when a heavy ion

strikes the sensitive region, which is surrounded by the reverse-biased drain diffusion region of PMOS, a
positive transient pulse will be generated and produce a “0” ! “1” or “1” ! “1” glitch (as shown in Figure
2C). On the contrary, if

it strikes the sensitive region, which is surrounded by the reverse-biased drain diffusion region of NMOS,
a negative

transient pulse will be generated and produce a “1” ! “0” or “0” ! “0” glitch (as shown in Figure
2D).17,20,21 It should

be noted that the “1” ! “1” and “0” ! “0” glitches do not affect the stored data. Therefore, considering
the state when

HSLC12T stores “1,” as shown in Figure 1A, nodes Q, QN, and S0 are the sensitive nodes

1. If node Q is affected by an SEU, node Q will be changed to “0”. In this case, P2 is temporarily turned
ON and N5 is

turned OFF. And owing to the capacity effect, S0 also retains its value. Although the transistor P2 is
turned ON,

node QN can still maintain its value because N4 is stronger than P2. As a result, P1 is kept ON and pulls
up node Q

to “1”. Therefore, Q regains its initial value (as shown in Figure 3A).

2. If node QN is affected by an SEU, node QN will be changed to “1”. As a consequence, P1 will be

temporarily turned

OFF and N6 will be temporarily turned ON. As N2 is stronger than N6, the logic state at node S1 stays
unchanged.
Furthermore, if N4 is kept ON and P2 is kept OFF, N4 pulls down the node QN back to “0” and recovers
its initial

value (as shown in Figure 3B).

3. If node S0 is affected by an SEU and changed to “0”. Due to the capacity effect, N2 and N4 will be
temporarily

turned OFF, and the voltage pulse will not affect other nodes. Hence, N5 is kept ON and N1 is kept OFF,
resulting

in S0 being pulled up to “1”. Therefore, S0 recovers its initial value (as shown in Figure 3C).

4. If the node pair Q-QN is affected by an SEDNU, the data stored in Q and QN will be temporarily
changed to “0” and

“1”, respectively. As a consequence, P1 and N5 will be temporarily turned OFF and P2 and N6 will be
temporarily

turned ON. However, owing to the capacity effect, S0 stays at “1,” and further, S1 is contained at “0”
because N2 is

stronger than N6, and QN will be pulled down back to “0” because N4 is stronger than P2. As a result, P1
is ON and

pulls up the node Q back to “1.” Finally, Q and QN will regain their initial values (as shown in Figure 3D).

5. If the node pair S0-Q or S0-QN is affected by SEDNUs, the data stored in the cell will be changed. In
these cases, due to

the internal feedback structure, the switching states of all transistors will be changed. In order to
minimize the possibility

of these cases, the proposed cell is laid out by keeping such node pairs as physically apart as possible, as
shown in

Figure 1B. It is worth mentioning that a SEDNU scenario involving more than two nodes is unlikely to
result in a major

state change due to the considerable charge diffusion occurring in the storage element and the broader
spread of the

incident strike.22–24 In addition, the range of charge sharing is about 0.6, 1.62, and 2 μm between
PMOS–NMOS, PMOS–

PMOS, and NMOS–NMOS transistors.16,21 For the proposed HSLC12T cell, the distance between the
two key transistors

P1 and N1 in the sensitive node pair Q-S0 is 1.35 μm (wider than the range of charge sharing), and the
distance between
the two key transistors P2 and N1 in the sensitive node pair QN-S1 is 1.27 μm (wider than the range of
charge sharing).

However, the distance between two key transistors, P1 and P2, in the sensitive node pair Q-QN is 0.49
μm (smaller than the range of charge sharing). As a result, only the special sensitive case on node pair Q-
QN needs to be considered. Based on the above analysis, the proposed HSLC12T cell can completely
tolerate SEU and even SEDNU.

The supply voltage for this process is 1.2 V. The pull-down-to-access ratio CRPDA for read stability is set
to be 1.6, and the pull-

up-to-access ratio CRPUA for write-ability is set to be 0.7.

Figure 3E shows the simulation results with Hailey Simulation Program with Integrated Circuit Emphasis

(HSPICE) for the SEU injections of the HSLC12T cell. The lighting symbol in Figure 3E denotes the TF
induced by

SEU. Note that, in all the soft-error simulations, we used the double-exponential current source model
shown in (1) to

perform the SEU injections

slide10:

Implementation and SEU robustness verification

Qcrit is the amount of injected critical charge, τα represents the collection time constant of the junction,
and

τβ represents the time constant for initially establishing the ion track. τα and τβ were set to be 164 and
50 ps, respectively.

In Figure 3E slide 9, when Q =1, SEUs were injected on nodes Q, QN, and S0 at 80, 60, and 170 ns,
respectively. When

Q =0, in order to verify the SEU robustness of the node pair Q-QN, we use two simultaneously injected
TFs at 250 ns

into Q and QN. This method of simultaneous injection of TFs to simulate charge sharing has been widely
used

The simulation results in Figure 3E show that the proposed HSLC12T cell is resilient to any SEU and a
special

SEDNU (at internal node pair Q-QN).

Therefore,the soft-error tolerance of our proposed HSLC12T cell is the same as

that of SIS10T, RHMD10T, and SCCS18T.

Slide11:

Access time comparison

The memory cell's read access time Tra is defined as the time interval between the word-line reaching
50% VDD and

the voltage differential (‫)اختالف پتانسیل‬of bit-lines developing 10% VDD, which is regarded as a necessity
for reliable sensing.

As shown in Table 1, the Tra of the proposed HSLC12T cell is 563.96 ps, which is the slowest among all

other compared radiation hardened cells due to the use of only 2 access transistors for reading
operations, and the pull-

down transistors are smaller than those of all other radiation hardened cells.

The write access time Twa of the memory cell depicted in Table 1 is defined as the time interval between
when the

word-line reaches 50% VDD and the intersection of the two storage nodes Q and QN. In Table 1, the Twa
of the pro-

posed HSLC12T cell is 23.04 ps, which is the fastest of all cells. This is mainly due to two reasons. One is
the use of

4 access transistors for writing operations, and the second is that the pull-up NMOS of the same size
have a larger satu-

ration current compared to PMOS, making the pull-up transistors faster to write new signals.

Slide12:

For area comparison, we have drawn the layouts of all the considered cells. The layout of a block of 3 × 4
SRAM array

slide13:

It can be seen from Table 1 that, for the silicon area overhead, compared with the Quatro10T,
QUCCE10T, NS10T, PS10T, SIS10T, and RHMD10T cells, more redundant (‫)بیشتری‬silicon area has to be used
for the Quatro12T, QUCCE12T, and QCCS12T cells in order to provide faster read and write speed
characteristics. However ‫بااین حال‬, due to the use of smaller internal storage transistors, the proposed
HSLC12T cell consumes the least area compared with the RHD12T, RSP14T, SIS10T, RHMD10T, and
SCCS18T cells that can also provide SEDNU tolerance and all other radiation hardened cells. It can also be
seen from Table 1 that the static hold power of our proposed
HLSC12T cell is smaller than most of the radiation hardened cells. This is mainly due to two reasons. One
is that the size of the internal storage transistors we use is the smallest among all other compared cells,
and the other is the lower voltage (VDD-VthN) on the internal node S0 (S1) when storing “1.”

Therefore, the proposed HSLC12T cell is competitive in low-cost applications compared with other
radiation hard-

ened memory cells.

Slide14:

Read stability comparison

1. RSNM:
Static noise margins (SNMs) are widely used as a critical parameter in evaluating the stability of
SRAM
memory cells
The RSNM value is approximately
equal to the side length of the smaller square in the two largest squares that can be inserted in
the two closed areas
of the butterfly curve.

Figure 5A shows the RSNM from the measured VTC (voltage transfer characteristics)of all cells reviewed
in Section 1.

A lower pull-down to pull-up ratio CRDU produces a larger voltage at the “0” storing nodes. As a result,
the cell can

only endure a minimal amount of noise, and the cell's RSNM worsens

A higher CRDU produces a stronger pull-

down capability of the internal inverter of the cell, which means a larger slope of the VTC and thus a
larger RSNM.

Hence, it can be seen in this Figure that the RSNM of our proposed HSLC12T cell is 321 mV, which is the
largest

RSNM of all considered cells

Figure 5A shows that the RSNM of the SIS10T is the smallest because of its

special NMOS stacking structure, making its equivalent CRDU the smallest of all the radiation hardened
cells.

Slide15: Static voltage noise margin (SVNM) and static current noise margin (SINM)

The other metric used to characterize SRAM read stability makes use of the N-curve, which is obtained
by sweeping (‫)بردن‬the voltage at the storage

node Q (or QN) with BL, BLB, and WL biased at VDD while monitoring the current externally sourced into
the Q

(or QN) node. The read stability of a SRAM cell may be characterized by the N-curve using both voltage
and current

data. As the voltage at the storage node Q (or QN) is ramped up, the voltage difference between the first
two points

crossing the x-axis can be used to calculate the SVNM of a SRAM cell (as shown in Figure 5B)

Our proposed HSLC12T cell has a smaller SINM and a larger SVNM, as shown in Figure 5B, due to the
weak “1” stored in S0 (S1) and the small

size of internal storage transistors.

Slide16: Write-ability comparison

1. Write noise margin (WNM)

During a write operation, the access and pull-up transistors combine to generate a resistive voltage
divider(‫ )که ولتاژ را کاهش می دهد‬for the falling BLB and the storage node QN. A successful write
operation occurs if the voltage divider pulls VQN below the trip point of the inverter at storage node
Q.

Figure 5C shows the WNM of all considered cells, and the WNM of our proposed HSLC12T is only
slightly larger

than that of Quatro12T, QUCCE12T, and NS10T, which is mainly because the pull-up NMOS (N5 and
N6) transistors, have a stronger pull-up current than PMOS transistors of the same size, making the
cell easier to write new signals and more susceptible to signal disturbances.

Slide17:

2. Write-ability current (IW):

The N-curve can be used to characterize SRAM's write-ability. The N-curve for write-
ability characterization is measured by sweeping the voltage at the storage node Q (QN) with
BLB (BL) and WL
 biased at VDD and BL (BLB) biased at GND while monitoring the current externally sourced into
the Q (QN) node.
This effectively measures the current of the access transistor minus the current of the pull-up
transistor

From Figure 5D, we can see that the IW of our proposed HSLC12T cell is the largest of all the
other compared radiation hardened cells

Slide18:
3. Word-line write trip voltage (WWTV):

Recent studies show that the WWTV is a more reliable means to judge an SRAM cell's write-ability. To
estimate WWTV, the BL and BLB are configured with the desired data to be written,

and then the WL is ramped up(increase). The estimated WWTV is the difference between VDD and WL
voltages when the data is tripped.

As shown in Table 1(slide13), the WWTV of the proposed HSLC12T cell is 455 mV, which is the largest of
all cells. This is mainly due to two reasons. One is the use of 4 access transistors for write operations, and
the

second is that the pull-up NMOS transistors have a stronger pull-up current than PMOS transistors of the
same size,

making it easier to write new signals.

Slide19:

Overall evaluation and comparison:

The critical charge Qcrit of SRAM cells determines their use in aerospace

Along with this, additional significant design

parameters that are crucial for designing a SRAM cell for space applications include noise margin
(RSNM), write-ability

(WWTV), static hold power, area, and delay (Tra and Twa).

it is possible to improve one design metric while

deteriorating another. Therefore, we use a design metric called EQM,28 which can estimate the overall
performance of
an SRAM cell using the major design metrics. The used EQM is given by: ‫فرمول‬

An SRAM cell with a higher EQM has a better overall performance

In order to compare, the relative EQM

(EQM cell/EQM HSLC12T) of all the cells is shown in Table 1 and Figure 6. As can be seen from Figure 6,
our proposed

HSLC12T has the highest EQM. HPHS12T thus demonstrates its superiority over other cells.

CONCLUSION

In the nanoscale CMOS technology, integrated circuits are more likely to suffer the occurrence of SEU
and SEDNU due

to the aggressive reduction of transistor feature sizes. This paper proposes a HSLC12T radiation
hardened SRAM cell.

The proposed HSLC12T cell can recover from SEU induced at all its sensitive nodes. Furthermore, the
HSLC12T cell

can recover from SEDNU induced at its storage node pair (Q-QN). Additionally, our proposed HSLC12T
cell shows the

maximum RSNM and lower static hold power, as well as excellent write speed and write-ability. Though
the HSLC12T

cell exhibits a larger read delay, it has the best overall performance of all the other cells, thus making the
proposed cell

a better choice for highly stable and low-cost aerospace applications.