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Silvaco TCAD based Analysis of Cylindrical Gate -All-Around FET Having

Indium Arsenide as channel and Aluminium Oxide as Gate Dielectrics

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 Journal of Nanotechnology and its Applications in
Engineering
Volume 1 Issue 1

Silvaco TCAD based Analysis of Cylindrical Gate -All-Around

FET Having Indium Arsenide as channel and Aluminium Oxide
as Gate Dielectrics

1
Md. Iqbal Bahar Chowdhury, 2Muhammad Johirul Islam, 3Md. Mahmudul
Hasan, 4Md. Jahorul Islam, 5Sadia Ummey Farwah

1
Associate Professor, 2345Student
Department of Electrical and Electronics Engineering,
United International University, Dhaka, Bangladesh
E-mail: [email protected], [email protected]

Abstract
In this work, a cylindrical gate-all-around (CGAA) FET (field-effect transistor) structure
with Indium Arsenide (InAs) nanowire is used as channel instead of silicon nanowire, and
aluminium oxide is used as the gate dielectrics instead of silicon dioxide. The performance of
this setup was demonstrated using ATLAS simulator of Silvaco TCAD software. Indium
Arsenide is chosen due to its high electron velocity, high saturation velocity and low contact
resistance, whereas, aluminium oxide is chosen because of its higher permittivity. Simulation
results indicate that the proposed combination is superior to the CGAA structures having
channel-gate dielectrics that use combinations of silicon-silicon dioxide and Indium
Arsenide-silicon dioxide. The effects of variation of nanowire radius, channel length and
oxide thickness on the output and transfer characteristics curves, and also on the
performance parameters such as maximum drain current, maximum transconductance, on
resistance and inverse subthreshold slope are investigated to show the superiority of the
proposed structure.

Keywords: Cylindrical Gate All Around MOSFET; Indium Arsenide nanowire; Aluminium
Oxide; high-k dielectrics.

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INTRODUCTION different high-K gate oxides and high

Short channel effects (SCE) become one mobility channel materials are suggested
of the major challenges in scaling down of in the literature. For this, we have paid
MOSFET feature size in order to fulfil the paid attention to III-V semiconductors
requirements suggested by the such as InAs, SnAs, InGaAs etc. as
International Technology Roadmap for channel materials to get higher current
Semiconductor (ITRS) for improved drive for their extremely high electron
performance. Therefore, non-classical mobility and low effective mass [6]. Of
FET structures such as double-gate, triple- these, InAs is the most suitable as a
gate, FinFET, pi-gate, sigma-gate and gate channel material owing to its higher
all around FET structures are proposed in electron mobility (up to 30000 cm2/V-s),
the literature, mainly to reduce SCE and lower electron effective mass (0.023 m0),
hence, to extend the scalability of FET higher saturation velocity (2×107 cm/s)
devices. and low contact resistance [7,8]. On the
other hand, high-k dielectric materials are
However, gate all around (GAA) structure
strongly recommended to obtain higher
based on MOSFET devices becomes the
gate capacitance as well as lower gate
best alternative among these structures and
leakage current. Recently, some high-k
hence, draws increasingly more attention
dielectric constant materials such as
of the researchers for their immunity of
Al2O3, HfO2 etc. are paying considerable
SCE and ultra-scalability [1]–[4], and also
interest as gate oxide. Do et al. [9] showed
for their superb electrostatic control of the
that when Al2O3 is selected as gate oxide
gate over the channel region owing to the
with III-V based channel semiconductor
reduced electron scattering [5]. Although
layer during appropriate annealing process
GAA devices can be based of rectangular
[10] of fabrication steps, no surface
and cylindrical nanowires, the cylindrical
defects is observed and hence, a high
one is a better option. Indeed, rectangular
quality dielectric film is resulted.
GAA FETs suffer from the lower current
drive due to the fringing effects (also In the literature, a number of research
known as corner effects), but cylindrical works based on gate-all-around structures
devices have reduced corner effects. are proposed. Yi et al. [3] analyzed a GAA
structure with Si-nanowire on bulk Si-
In order to get better device performance
substrates. Sofia et al. [1] and proposed a
as well to reduce the fabrication cost,

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GAA structure with vertical InAs performance of this proposed structure,

nanowire on Si substrates. The first i.e. output and transfer characteristics and
CGAA structure based on InAs-nanowire the various performance parameters
as channel material and HfO2 as gate (figures of merit) are obtained and also,
oxide is proposed by Jahurul et al. [8]. the effects of channel length, channel
Although Al2O3 has lower permittivity radius, channel doping level and the oxide
than HfO2, gate oxide Al2O3 is still a thickness are investigated. The results are
better option as mentioned earlier. compared with other channel/gate oxide
Therefore, in this work, a novel CGGA combinations i.e. Si/SiO2 and InAs/SiO2
FET structure based on InAs-nanowire as to assess the superiority of the proposed
channel material and Al2O3 as gate oxide structure.
is proposed. The proposed device structure
DEVICE STRUCTURE AND
is implemented using the ATLAS
SIMULATION
simulator of Silvaco TCAD software. The

Fig. 1: 3D view of the proposed cylindrical gate-all-around MOSFET generated by

ATLAS.

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A. Device Structure simulates the structure so that its x-

direction is in the radial direction of the
The device structure proposed in this work
cylinder, its z-axis is at the center of the
has been simulated using ATLAS
cylinder, and its y-axis is in the downward
simulator of Silvaco TCAD. The
direction with origin at the top of the
generated 3-D view of this structure using
structure. The 2D radial cross-section
ATLAS is shown in Fig. (1), where InAs-
view is shown in Fig. (2). The device is
nanowire is shown as channel and Al2O3
implemented as doped source/drain type
as the gate oxide. Because of the
MOSFET. The channel length is varied in
cylindrical symmetry of the CGAA
the range of 100-200 nm, whereas, the
structure, quasi-3D model structure is used
channel radius is varied between 10-20
to simulate the structure in ATLAS. In the
nm. The gate oxide thickness is 4-12 nm.
'mesh' statement, this cylindrical
The channel doping level is varied from
symmetry is specified for which ATLAS
1×1017 to 5×1018 cm-3.

Fig. 2: 2D radial cross section view of the proposed cylindrical gate-all-around MOSFET
generated by ATLAS.

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 Journal of Nanotechnology and its Applications in
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B. Device Simulation of the proposed structure, this section also

presents a comparative analysis between
All the simulations are carried out using
the proposed structure with two other
ATLAS of Silvaco TCAD. Fermi-Dirac
GAA structures having the channel-gate
statistics is used instead of Boltzmann
oxide combinations of Si-SiO2 and InAs-
statistics. Since the channel length and
SiO2.
radius are of the order of 100 nm, field-
dependent mobility needs to be Figs (3), (5) and (7) show the output
considered. Therefore, field-dependent characteristics (ID vs. VD) and figs. (4),
mobility models are included in the (6) and (8) show the transfer
analysis. The band profile InAs is chosen characteristics (ID vs. VG) for three GAA
as 1D as suggested in [11]. For structures having different channel-gate
recombination models, Shockley–Read– oxide combinations. From all these
Hall (SRH) recombination mechanism is figures, it is clearly evident that the
considered. For the sake of simplicity, proposed CGAA structure having InAs as
simple drift-diffusion model is used. channel material and Al2O3 as gate
dielectrics outperforms the other CGAA
For numerical iterations, both Newton and
structures. This is because of the fact that
Gummel methods are applied. However,
the electron mobility (µn) in the InAs
in order to speed up the iteration process,
channel is more than 60 times higher than
automated Newton-Richardson procedure
that in the Si-channel (µn,InAs = 80000
is implemented.
compared to µn,si = 1300) and the relative
RESULTS AND DISCUSSION permittivity (εr) of Al2O3 is roughly three
times higher than that of SiO2 (εr,Al2O3
This section presents and analyses the
= 9.00 compared to εr,SiO2 = 3.90).
simulation results carried out by the
Indeed, the drain current of the GAA FET
ATLAS simulator of Silvaco TCAD
is directly proportional to both the electron
software for the output characteristics (ID
mobility in the channel and the
vs. VD) and the transfer characteristics
permittivity of the gate dielectrics.
(ID vs. VG) and for the various figures of
Therefore, the drain current is higher for
merit and also, discusses the effects of
GAA structure having InAs-SiO2 channel-
various parameters on these curves and
gate oxide combination and becomes the
figures of merit of the proposed CGAA
structure. In order to assess the superiority

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 Journal of Nanotechnology and its Applications in
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Volume 1 Issue 1

largest for InAs- Al2O3 channel-gate does not change the threshold voltage at
dielectrics combination. all.

An important observation has been made The effects of the variation of the channel
from the transfer characteristics curves radius on the output and the transfer
[Figs. (4), (6) and (8) that the threshold characteristics have been observed in Figs.
voltage (which is the minimum gate (3) and (4). In both of these figures, it is
voltage required to turn on the FET) is the seen that higher drain current can be
highest for GAA structures having the Si- obtained as channel radius increases. This
channel and SiO2-gate dielectrics is expected as the higher channel radius
combination and is lowered down for the creates the wider cross-section for the
GAA structures with InAs as channel current flow, thereby causing an increase
material. It is noteworthy that the change in the drain current.
of the gate dielectrics from SiO2 to Al2O3

Fig. 3: Effect of variation of channel radius on the output characteristics at VG = 0.5 V.

For all three structures, channel length is 200 nm, oxide thickness is 4 nm and channel
doping level is 1×1017 cm-3.

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Figs. (5) and (6) display the effects of the drain, the current for longer channels
channel length variation on the ID vs. VD is lowered. This fact of lowering drain
and ID vs. VG characteristics curves. current as channel length increases is
Since larger channel length provides a evident from both the output and the
longer path for the carriers to reach the transfer characteristic curves for all three
drain end and causes the same amount of GAA structures.

Fig. 4: Effect of variation of channel radius on the transfer characteristics at VD = 0.5 V.

For all three structures, channel length is 200 nm, oxide thickness is 4 nm and channel
doping level is 1×1017 cm-3.

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Fig. 5: Effect of variation of channel length on the output characteristics at VG = 0.5 V.

For all three structures, channel radius is 10 nm, oxide thickness is 4 nm and channel
doping level is 1×1017 cm-3.

The thickness of the gate oxide (TOX) has to the drain current. Therefore, decrease in
a strong effect on both of the output and the TOX increases the gate capacitance,
the transfer characteristics, since TOX is thereby causing an increase in the drain
inversely proportional to the oxide current. This phenomena can also be
capacitance, which is directly proportional observed in the Figs. (7) and (8).

Fig. 6: Effect of variation of channel length on the transfer characteristics at VD = 0.5 V.

For all three structures, channel radius is 10nm, oxide thickness is 4 nm and channel
doping level is 1×1017 cm-3.

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Fig. 7: Effect of variation of oxide thickness on the output characteristics at VG = 0.5 V.

For all three structures, channel radius is 10 nm, channel length is 200 nm and channel
doping level is 1×1017 cm-3.

Figures of Merit Since InAs has higher mobility and lower

electron mass and Al2O3 has higher
Transistor's performance can best be
permittivity, it is expected that the CGAA
described by the various figures of merit,
structure of InAs-Al2O3 channel-
which include maximum drain current
dielectric combination shows the highest
(Imax), maximum transconductance (gm,
level of Imax and gm,max and the lowest
max), on resistance (Ron) and inverse
values for Ron and ISS. Except for ISS,
subthreshold slope (Iss). Table 1 lists
values listed in Table 1 are consistent with
these parameter values for all the three
all these expectations.
CGAA FET structures mentioned in this
work, where channel radius, channel
length, oxide thickness and channel
doping level for all these structures are
identical and chosen as 10 nm, 200 nm, 4
nm and 1×1017respectively.

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 Journal of Nanotechnology and its Applications in
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Fig. 8: Effect of variation of oxide thickness on the transfer characteristics at VD = 0.5

V. For all three structures, channel radius is 10 nm, channel length is 200 nm and
channel doping level is 1×1017 cm-3.

Table 1. Comparative analysis of figures of merit for the three CGAA structures mentioned
in this work. For all three structures, channel radius is 10 nm, channel length is 200 nm,
oxide thickness is 4 NMAND channel doping level is 1×1017 cm-3.

CGAA Structures
Figures of Merit
Si-SiO2 InAs-SiO2 InAs-Al2O3
gm,max (mS/µm) 0.8562 0.75 1.2

Imax (mA/µm) 0.01015 0.164 0.197

RON (Ω-µm) 9927 1929 1433

ISS (mV/dec) 60.5 63.3 62.2

However, inconsistency in the ISS values excessive trap charges at the oxide-
can be attributed to the presence of semiconductor interface for InAs-channel

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based FETs compared to the Si-channel Frequency Gate-All-Around Vertical

based FETs. However, InAs-Al2O3 InAs Nanowire MOSFETs on Si
channel-dielectric combination based Substrates”, IEEE Electron Dev. Lett.,
CGAA structure is the best among all the vol. 35, no. 5, pp. 518-520, May 2014.
structures mentioned in this work. It has
ISS, although degraded, that is close to the II. Jimnez, J. J. Senz, B. Iguez, J. Su, L.
theoretical lowest limit of 60 mV/Dec. F. Marsal, and J. Pallars, “Modeling of
Nanoscale Gate-All-Around
CONCLUSION
MOSFETsg”, Electron Dev. Lett., vol.
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channel and Al2O3 as gate dielectrics
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Nanowire n- and p-Type MOSFETs
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Fabricated on Bulk Silicon Substrate”,
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IEEE Trans. Electron Dev., vol. 59,
replaced by InAs or the gate dielectrics are
no. 7, pp. 1885-1890, July 2012.
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simulations, the new structure shows the
IV. P. W. Li and W. M. Liao, “Design of
lower threshold voltage, the higher drain
high speed Si/SiGe heterojunction
current, comparatively lower inverse sub-
complementary metal oxide
threshold slope, lower on-resistance and
semiconductor field effect transistors
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