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TCA9406
SCPS221G – OCTOBER 2010 – REVISED NOVEMBER 2018

TCA9406 2-Bit Bidirectional 1-MHz, I2C Bus and SMBus Voltage-Level Translator With
8-kV HBM ESD
1 Features 3 Description
1• 2-Bit Bidirectional Translator for SDA and SCL The TCA9406 is a 2-bit bidirectional I2C and SMBus
Lines in I2C Applications voltage-level translator with an output enable (OE)
input. It is operational from 1.65 V to 3.6 V on the A-
• Provides Bidirectional Voltage Translation With No side, referenced toVCCA, and from 2.3 V to 5.5 V on
Direction Pin the B-side, referenced to VCCB. This allows the device
• High-Impedance Output SCL_A, SDA_A, SCL_B, to interface between lower and higher logic signal
SDA_B Pins When OE = Low or VCC = 0 V levels at any of the typical 1.8-V, 2.5-V, 3.3-V, and
• Internal 10-kΩ Pullup Resistor on All SDA and 5-V supply rails.
SCL Pins The OE input pin is referenced to VCCA, can be tied
• 1.65 V to 3.6 V on A port and 2.3 V to 5.5 V on B directly to VCCA, but it is also 5.5-V tolerant. The OE
port (VCCA ≤ VCCB) pin can also be controlled and set to a logic low to
place all the SCL and SDA pins in a high-impedance
• VCC Isolation Feature: If Either VCC Input Is at state, which significantly reduces the quiescent
GND, Both Ports Are in the High-Impedance State current consumption.
• No Power-Supply Sequencing Required: Either
Under normal I2C and SMBus operation or other
VCCA or VCCB Can Be Ramped First open-drain configurations, the TCA9406 can support
• Low Ioff of 2 µA When Either VCCA or VCCB = 0 V up to 2 Mbps; therefore, it is compatible with standard
• OE Input Can Be Tied Directly to VCCA Or I2C speeds where the frequency of SCL is 100 kHz
Controlled By GPIO (Standard-mode), 400 kHz (Fast-mode), or 1 MHz
(Fast-mode Plus). The device can also be used as a
• Latch-Up Performance Exceeds 100 mA Per general purpose level translator, and when the A- and
JESD 78, Class II B-side ports are both driven with push-pull devices
• ESD Protection Exceeds JESD 22 the TCA9406 can support up to 24 Mbps.
– A Port The TCA9406 features internal 10-kΩ pullup resistors
– 2500-V Human-Body Model (A114-B) on SCL_A, SDA_A, SCL_B, and SDA_B. Additional
– 250-V Machine Model (A115-A) external pullup resistors can be added to the bus to
reduce the total pullup resistance and speed up rising
– 1500-V Charged-Device Model (C101) edges.
– B Port
– 8-kV Human-Body Model (A114-B) Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
– 250-V Machine Model (A115-A)
SM8 (8) 2.95 mm × 2.80 mm
– 1500-V Charged-Device Model (C101)
TCA9406 US8 (8) 2.30 mm × 2.00 mm
2 Applications DSBGA (8) 1.90 mm × 0.90 mm

• I2C/SMBus (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• UART
• GPIO
Typical Application Block Diagram for TCA9406

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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SCPS221G – OCTOBER 2010 – REVISED NOVEMBER 2018 www.ti.com

Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 18
2 Applications ........................................................... 1 8.1 Overview ................................................................. 18
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 18
4 Revision History..................................................... 2 8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 20
5 Pin Configuration and Functions ......................... 5
6 Specifications......................................................... 6 9 Application and Implementation ........................ 21
9.1 Application Information............................................ 21
6.1 Absolute Maximum Ratings ..................................... 6
9.2 Typical Application ................................................. 21
6.2 ESD Ratings ............................................................ 6
6.3 Recommended Operating Conditions ...................... 7 10 Power Supply Recommendations ..................... 23
6.4 Thermal Information .................................................. 7 11 Layout................................................................... 23
6.5 Electrical Characteristics .......................................... 8 11.1 Layout Guidelines ................................................. 23
6.6 Timing Requirements (VCCA = 1.8 V ± 0.15 V) ......... 9 11.2 Layout Example .................................................... 23
6.7 Timing Requirements (VCCA = 2.5 V ± 0.2 V) ........... 9 12 Device and Documentation Support ................. 24
6.8 Timing Requirements (VCCA = 3.3 V ± 0.3 V) ........... 9 12.1 Receiving Notification of Documentation Updates 24
6.9 Switching Characteristics (VCCA = 1.8 V ± 0.15 V) . 10 12.2 Community Resources.......................................... 24
6.10 Switching Characteristics (VCCA = 2.5 V ± 0.2 V) . 12 12.3 Trademarks ........................................................... 24
6.11 Switching Characteristics (VCCA = 3.3 V ± 0.3 V) . 14 12.4 Electrostatic Discharge Caution ............................ 24
6.12 Typical Characteristics .......................................... 15 12.5 Glossary ................................................................ 24
7 Parameter Measurement Information ................ 16 13 Mechanical, Packaging, and Orderable
7.1 Voltage Waveforms................................................. 17 Information ........................................................... 24

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (October 2018) to Revision G Page

• Changed section title From: Pullup or Pulldown Resistors on I/O Lines To: Pullup Resistors on I/O Lines........................ 20
• Deleted text "An external pull down..." and Equation 1 from the Detailed Design Procedure section................................. 21
• Changed pin 1 From: To controller To: To system in Figure 13 ......................................................................................... 23
• Changed pin 5 From: To system To: To controller in Figure 13 ......................................................................................... 23

Changes from Revision E (August 2018) to Revision F Page

• Changed the Functional Block Diagram ............................................................................................................................... 18

• Changed the Enable and Disable section ............................................................................................................................ 19

Changes from Revision D (July 2018) to Revision E Page

• Changed the new DSBGA pinout drawing From: Bottom View to: Top View ....................................................................... 5

Changes from Revision C (December 2014) to Revision D Page

• Changed the updated pinout drawings .................................................................................................................................. 5

• Changed tdis no external load MAX values From: 50 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 10
• Changed tdis no external load MAX values From: 40 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 10
• Changed tdis no external load MAX values From: 35 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 11
• Changed tdis no external load MAX values From: 50 To: 200 ns in Switching Characteristics (VCCA = 2.5 V ± 0.2 V)........ 12
• Changed tdis no external load MAX values From: 40 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 12
• Changed tdis no external load MAX values From: 35 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 13
• Changed tdis no external load MAX values From: 40 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 14

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• Changed tdis no external load MAX values From: 35 To: 200 ns in Switching Characteristics (VCCA = 1.8 V ± 0.15 V)...... 14
• Changed the Parameter Measurement Information section................................................................................................. 16

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Changes from Revision B (June 2013) to Revision C Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision A (Febuary 2013) to Revision B Page

• Removed ordering information table, information now located in POA ................................................................................. 1

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5 Pin Configuration and Functions

8-PIN SM8 OR US8

(TOP VIEW) 8-PIN DSBGA
(TOP VIEW)
1 2

SDA_B 1 8 SCL_B

GND 2 7 VCCB A SDA_B SCL_B

VCCA 3 6 OE

SDA_A 4 5 SCL_A

B GND VCCB

Not to scale

C VCCA OE

D SDA_A SCL_A

Not to scale

Pin Functions
PIN
DCT, TYPE DESCRIPTION
NAME YZP
DCU
SDA_B 1 A1 I/O Input/output B. Referenced to VCCB.
GND 2 B1 GND Ground
VCCA 3 C1 Power A-port supply voltage. 1.65 V ≤ VCCA ≤ 3.6 V and VCCA ≤ VCCB
SDA_A 4 D1 I/O Input/output A. Referenced to VCCA.
SCL_A 5 D2 I/O Input/output A. Referenced to VCCA.
Output enable (active High). Pull OE low to place all outputs in 3-state mode. Referenced to
OE 6 C2 Input
VCCA.
VCCB 7 B2 Power B-port supply voltage. 2.3 V ≤ VCCB ≤ 5.5 V
SCL_B 8 A2 I/O Input/output B. Referenced to VCCB.

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6 Specifications
6.1 Absolute Maximum Ratings (1)
over recommended operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCCA Supply voltage range –0.5 4.6 V
VCCB Supply voltage range –0.5 6.5 V
A port –0.5 4.6
VI Input voltage range (2) V
B port –0.5 6.5
Voltage range applied to any output A port –0.5 4.6
VO V
in the high-impedance or power-off state (2) B port –0.5 6.5
A port –0.5 VCCA + 0.5
VO Voltage range applied to any output in the high or low state (2) (3) V
B port –0.5 VCCB + 0.5
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCCA, VCCB, or GND ±100 mA
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCCA and VCCB are provided in the recommended operating conditions table.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS- A-Port ±2500 V
001 (1)
Electrostatic B-Port ±8000 V
V(ESD)
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 V
Machine model (MM), A115-A ±250 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

VCCI is the supply voltage associated with the input port. VCCO is the supply voltage associated with the output port.
VCCA VCCB MIN MAX UNIT
VCCA Supply voltage (1) 1.65 3.6 V
VCCB Supply voltage 2.3 5.5 V
1.65 V to 1.95 V VCCI – 0.2 VCCI
A-port I/Os 2.3 V to 5.5 V
High-level 2.3 V to 3.6 V VCCI – 0.4 VCCI
VIH V
input voltage B-port I/Os VCCI – 0.4 VCCI
1.65 V to 3.6 V 2.3 V to 5.5 V
OE input VCCA × 0.65 5.5
A-port I/Os 0 0.15
Low-level
VIL (2) B-port I/Os 1.65 V to 3.6 V 2.3 V to 5.5 V 0 0.15 V
input voltage
OE input 0 VCCA × 0.35
A-port I/Os, push-
10
pull driving
Input transition
Δt/Δv B-port I/Os, push- 1.65 V to 3.6 V 2.3 V to 5.5 V ns/V
rise or fall rate 10
pull driving
Control input 10
TA Operating free-air temperature –40 85 °C

(1) VCCA must be less than or equal to VCCB (except during power-on transient time), and VCCA must not exceed 3.6 V.
(2) The maximum VIL value is provided to ensure that a valid VOL is maintained. The VOL value is VIL plus the voltage drop across the pass-
gate transistor.

6.4 Thermal Information

TCA9406
(1)
THERMAL METRIC DCT DCU YZP UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 182.6 199.1 105.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 113.3 72.4 1.6 °C/W
RθJB Junction-to-board thermal resistance 94.9 77.8 10.8 °C/W
ψJT Junction-to-top characterization parameter 39.4 6.2 3.1 °C/W
ψJB Junction-to-board characterization parameter 93.9 77.4 10.8 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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6.5 Electrical Characteristics (1) (2) (3)

over recommended operating free-air temperature range (unless otherwise noted)
TEST TA = 25°C –40°C to 85°C
PARAMETER VCCA VCCB UNIT
CONDITIONS TYP MIN MAX
IOH = –20 μA,
VOHA 1.65 V to 3.6 V 2.3 V to 5.5 V VCCA × 0.67 V
VIB ≥ VCCB – 0.4 V
IOL = 1 mA,
VOLA 1.65 V to 3.6 V 2.3 V to 5.5 V 0.4 V
VIB ≤ 0.15 V
IOH = –20 μA,
VOHB 1.65 V to 3.6 V 2.3 V to 5.5 V VCCB × 0.67 V
VIA ≥ VCCA – 0.2 V
IOL = 1 mA,
VOLB 1.65 V to 3.6 V 2.3 V to 5.5 V 0.4 V
VIA ≤ 0.15 V
II OE VI = VCCI or GND 1.65 V to 3.6 V 2.3 V to 5.5 V ±1 ±2 μA
A port 0V 0 V to 5.5 V ±1 ±2 μA
Ioff
B port 0 to 3.6 V 0V ±1 ±2 μA
IOZ A or B port OE less than VIL 1.65 V to 3.6 V 2.3 V to 5.5 V ±1 ±2 μA
1.65 V to VCCB 2.3 V to 5.5 V 2.4
VI = VO = open,
ICCA 3.6 V 0V 2.2 μA
IO = 0
0V 5.5 V –1
1.65 V to VCCB 2.3 V to 5.5 V 12
VI = VO = open,
ICCB 3.6 V 0V –1 μA
IO = 0
0V 5.5 V 1
VI = VO = open,
ICCA + ICCB 1.65 V to VCCB 2.3 V to 5.5 V 14.4 μA
IO = 0
CI OE 3.3 V 3.3 V 2.5 3.5 pF
A or B port 3.3 V 3.3 V 10
Cio A port 5 6 pF
B port 6 7.5

(1) VCCI is the VCC associated with the input port.

(2) VCCO is the VCC associated with the output port.
(3) VCCA must be less than or equal to VCCB, and VCCA must not exceed 3.6 V.

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6.6 Timing Requirements (VCCA = 1.8 V ± 0.15 V)

over recommended operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCCB = 2.5 V ± 0.2 V
Push-pull driving 21
Data rate Mbps
Open-drain driving 2
Push-pull driving 47
tw Pulse duration Data inputs ns
Open-drain driving 500
VCC = 3.3 V ± 0.3 V
Push-pull driving 22
Data rate Mbps
Open-drain driving 2
Push-pull driving 45
tw Pulse duration Data inputs ns
Open-drain driving 500
VCC = 5 V ± 0.5 V
Push-pull driving 24
Data rate Mbps
Open-drain driving 2
Push-pull driving 41
tw Pulse duration Data inputs ns
Open-drain driving 500

6.7 Timing Requirements (VCCA = 2.5 V ± 0.2 V)

over recommended operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCCB = 2.5 V ± 0.2 V
Push-pull driving 20
Data rate Mbps
Open-drain driving 2
Push-pull driving 50
tw Pulse duration Data inputs ns
Open-drain driving 500
VCC = 3.3 V ± 0.3 V
Push-pull driving 22
Data rate Mbps
Open-drain driving 2
Push-pull driving 45
tw Pulse duration Data inputs ns
Open-drain driving 500
VCC = 5 V ± 0.5 V
Push-pull driving 24
Data rate Mbps
Open-drain driving 2
Push-pull driving 41
tw Pulse duration Data inputs ns
Open-drain driving 500

6.8 Timing Requirements (VCCA = 3.3 V ± 0.3 V)

over recommended operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC = 3.3 V ± 0.3 V
Push-pull driving 23
Data rate Mbps
Open-drain driving 2
Push-pull driving 43
tw Pulse duration Data inputs ns
Open-drain driving 500
VCC = 5 V ± 0.5 V
Push-pull driving 24
Data rate Mbps
Open-drain driving 2
Push-pull driving 41
tw Pulse duration Data inputs ns
Open-drain driving 500

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6.9 Switching Characteristics (VCCA = 1.8 V ± 0.15 V)

over recommended operating free-air temperature range (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
VCCB = 2.5 V ± 0.2 V
Push-pull driving 5.3
tPHL
Open-drain driving 2.3 8.8
A B ns
Push-pull driving 6.8
tPLH
Open-drain driving 50
Push-pull driving 4.4
tPHL
Open-drain driving 1.9 5.3
B A ns
Push-pull driving 5.3
tPLH
Open-drain driving 5.3
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 9.5
trA A-port rise time ns
Open-drain driving 38 165
Push-pull driving 10.8
trB B-port rise time ns
Open-drain driving 34 145
Push-pull driving 5.9
tfA A-port fall time
Open-drain driving 6.9
ns
Push-pull driving 13.8
tfB B-port fall time
Open-drain driving 13.8
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 21
Max data rate Mbps
Open-drain driving 2
VCCB = 3.3 V ± 0.3 V
Push-pull driving 5.4
tPHL
Open-drain driving 2.4 9.6
A B ns
Push-pull driving 7.1
tPLH
Open-drain driving 40
Push-pull driving 4.5
tPHL
Open-drain driving 1.1 4.4
B A ns
Push-pull driving 4.5
tPLH
Open-drain driving 4.5
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 9.3
trA A-port rise time ns
Open-drain driving 30 132
Push-pull driving 9.1
trB B-port rise time ns
Open-drain driving 23 106
Push-pull driving 6
tfA A-port fall time ns
Open-drain driving 6.4
Push-pull driving 16.2
tfB B-port fall time ns
Open-drain driving 16.2
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 22
Max data rate Mbps
Open-drain driving 2

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Switching Characteristics (VCCA = 1.8 V ± 0.15 V) (continued)

over recommended operating free-air temperature range (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
VCCB = 5 V ± 0.5 V
Push-pull driving 6.8
tPHL
Open-drain driving 2.6 10
A B ns
Push-pull driving 7.5
tPLH
Open-drain driving 33
Push-pull driving 4.7
tPHL
Open-drain driving 1.2 4
B A ns
Push-pull driving 0.5
tPLH
Open-drain driving 0.5
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 7.6
trA A-port rise time ns
Open-drain driving 22 95
Push-pull driving 7.6
trB B-port rise time ns
Open-drain driving 10 58
Push-pull driving 13.3
tfA A-port fall time ns
Open-drain driving 6.1
Push-pull driving 16.2
tfB B-port fall time ns
Open-drain driving 16.2
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 24
Max data rate Mbps
Open-drain driving 2

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6.10 Switching Characteristics (VCCA = 2.5 V ± 0.2 V)

over recommended operating free-air temperature range (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
VCCB = 2.5 V ± 0.2 V
Push-pull driving 3.2
tPHL
Open-drain driving 1.7 6.3
A B ns
Push-pull driving 3.5
tPLH
Open-drain driving 3.5
Push-pull driving 3
tPHL
Open-drain driving 1.8 4.7
B A ns
Push-pull driving 2.5
tPLH
Open-drain driving 2.5
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 7.4
trA A-port rise time ns
Open-drain driving 34 149
Push-pull driving 8.3
trB B-port rise time ns
Open-drain driving 35 151
Push-pull driving 5.7
tfA A-port fall time
Open-drain driving 6.9
ns
Push-pull driving 7.8
tfB B-port fall time
Open-drain driving 8.8
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 20
Max data rate Mbps
Open-drain driving 2
VCCB = 3.3 V ± 0.3 V
Push-pull driving 3.7
tPHL
Open-drain driving 2 6
A B ns
Push-pull driving 4.1
tPLH
Open-drain driving 4.1
Push-pull driving 3.6
tPHL
Open-drain driving 2.6 4.2
B A ns
Push-pull driving 1.6
tPLH
Open-drain driving 1.6
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 6.6
trA A-port rise time ns
Open-drain driving 28 121
Push-pull driving 7.2
trB B-port rise time ns
Open-drain driving 24 112
Push-pull driving 5.5
tfA A-port fall time ns
Open-drain driving 6.2
Push-pull driving 6.7
tfB B-port fall time ns
Open-drain driving 9.4
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 22
Max data rate Mbps
Open-drain driving 2

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Switching Characteristics (VCCA = 2.5 V ± 0.2 V) (continued)

over recommended operating free-air temperature range (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
VCCB = 5 V ± 0.5 V
Push-pull driving 3.8
tPHL
Open-drain driving 2.1 5.8
A B ns
Push-pull driving 4.4
tPLH
Open-drain driving 4.4
Push-pull driving 4.3
tPHL
Open-drain driving 1.2 4
B A ns
Push-pull driving 1
tPLH
Open-drain driving 1
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 5.6
trA A-port rise time ns
Open-drain driving 24 89
Push-pull driving 6.1
trB B-port rise time ns
Open-drain driving 12 64
Push-pull driving 5.3
tfA A-port fall time ns
Open-drain driving 5.8
Push-pull driving 6.6
tfB B-port fall time ns
Open-drain driving 10.4
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 24
Max data rate Mbps
Open-drain driving 2

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6.11 Switching Characteristics (VCCA = 3.3 V ± 0.3 V)

over recommended operating free-air temperature range (unless otherwise noted)
FROM TO
PARAMETER TEST CONDITIONS MIN MAX UNIT
(INPUT) (OUTPUT)
VCCB = 3.3 V ± 0.3 V
Push-pull driving 2.4
tPHL
Open-drain driving 1.3 4.2
A B ns
Push-pull driving 4.2
tPLH
Open-drain driving 4.2
Push-pull driving 2.5
tPHL
Open-drain driving 1 124
B A ns
Push-pull driving 2.5
tPLH
Open-drain driving 2.5
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 5.6
trA A-port rise time ns
Open-drain driving 25 116
Push-pull driving 6.4
trB B-port rise time ns
Open-drain driving 26 116
Push-pull driving 5.4
tfA A-port fall time ns
Open-drain driving 6.1
Push-pull driving 7.4
tfB B-port fall time ns
Open-drain driving 7.6
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 23
Max data rate Mbps
Open-drain driving 2
VCCB = 5 V ± 0.5 V
Push-pull driving 3.1
tPHL
Open-drain driving 1.4 4.6
A B ns
Push-pull driving 4.4
tPLH
Open-drain driving 4.4
Push-pull driving 3.3
tPHL
Open-drain driving 1 97
B A ns
Push-pull driving 2.6
tPLH
Open-drain driving 2.6
ten OE A or B 200 ns
with external load 200 ns
tdis OE A or B
no external load 200 ns
Push-pull driving 4.8
trA A-port rise time ns
Open-drain driving 19 85
Push-pull driving 7.4
trB B-port rise time ns
Open-drain driving 14 72
Push-pull driving 5
tfA A-port fall time ns
Open-drain driving 5.7
Push-pull driving 7.6
tfB B-port fall time ns
Open-drain driving 8.3
tSK(O) Channel-to-channel skew 0.7 ns
Push-pull driving 24
Max data rate Mbps
Open-drain driving 2

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6.12 Typical Characteristics

700 700

600 600
Low-Level Output Voltage (mV)

Low-Level Output Voltage (mV)

500 500

400 400

300 300

200 200
VCCB = 2.7 V
100 VCCB = 3.3 V 100 VCCB = 3.3 V
VCCB = 5 V VCCB = 5 V
0 0
0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16
Low-Level Current (mA) D001 Low-Level Current (mA) D003
VCCA = 1.8 V VIL(A) = 150 mV VCCA = 2.7 V VIL(A) = 150 mV
Figure 1. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Figure 2. Low-Level Output Voltage (VOL(Bx)) vs Low-Level
Current (IOL(Bx)) Current (IOL(Bx))
700

600
Low-Level Output Voltage (mV)

500

400

300

200

100
VCCB = 3.3 V
0
0 2 4 6 8 10 12 14 16
Low-Level Current (mA) D002
VCCA = 3.3 V VIL(A) = 150 mV

Figure 3. Low-Level Output Voltage (VOL(Bx)) vs Low-Level Current (IOL(Bx))

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7 Parameter Measurement Information

VCCI VCCO

DUT

IN OUT
15 pF 1M

Figure 4. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement
Using a Push-Pull Driver

VCCI VCCO

DUT

IN OUT

15 pF 1M

Figure 5. Data Rate, Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time Measurement
Using an Open-Drain Driver

2 × VCCO

S1 Open
From Output 50 k
Under Test

15 pF 50 k

TEST S1
tPZL / tPLZ 2 × VCCO
tPHZ / tPZH Open

Figure 6. Load Circuit for Enable-Time and Disable-Time Measurement

1. tPLZ and tPHZ are the same as tdis.

2. tPZL and tPZH are the same as ten.
3. VCCI is the VCC associated with the input port.
4. VCCO is the VCC associated with the output port.

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Parameter Measurement Information (continued)

7.1 Voltage Waveforms
tw VCCI
Input VCCI / 2 VCCI / 2
VCCI
0V
Input VCCI / 2 VCCI / 2
tPLH tPHL
0V
VOH
0.9 × VCCO
Output VCCO / 2 VCCO / 2
0.1 × VCCO VOL
tr tf

Figure 7. Pulse Duration Figure 8. Propagation Delay Times

A. CL includes probe and jig capacitance.
B. Waveform 1 in Figure 9 is for an output with internal such that the output is high, except when OE is high (see
Figure 6). Waveform 2 in Figure 9 is for an output with conditions such that the output is low, except when OE is
high.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, dv/dt
≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
VCCA

OE input VCCA / 2 VCCA / 2

0V

tPZL tPLZ

Output VOH
Waveform 1 VCCO / 2
S1 at 2 × VCCO VOH × 0.1
VOL
(see Note 2)

tPZH tPHZ

Output VOH
Waveform 2 VOH × 0.9
S1 at GND VCCO / 2
(see Note 2) 0V
Figure 9. Enable and Disable Times

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8 Detailed Description

8.1 Overview
The TCA9406 device is a directionless voltage-level translator specifically designed for translating logic voltage
levels. The A port is able to accept I/O voltages ranging from 1.65 V to 3.6 V, while the B port can accept I/O
voltages from 2.3 V to 5.5 V. The device is a pass-gate architecture with edge-rate accelerators (one-shots) to
improve the overall data rate. 10-kΩ pullup resistors, commonly used in open-drain applications, have been
conveniently integrated so that an external resistor is not needed. When TCA9406 is disabled the internal pull up
resistors are also disabled. While this device is designed for open-drain applications which makes it ideal for I2C
and SMBus applications, the device can also translate push-pull CMOS logic outputs.

8.2 Functional Block Diagram

VCCA VCCB

OE

One Shot One Shot

Accelerator Accelerator
Gate Bias

10 k
10 k
SCL_A SCL_B

One Shot One Shot

Accelerator Accelerator
Gate Bias

10 k 10 k
SDA_A SDA_B

8.3 Feature Description

8.3.1 Architecture
The TCA9406 architecture (see Figure 5) is an auto-direction-sensing based translator that does not require a
direction-control signal to control the direction of data flow from A to B or from B to A.
VCCA VCCB

One
One- One
One-
T1 T2
shot
shot shot
shot

R1 R2
10k 10k

Gate Bias

A B
N2

Figure 10. Architecture of a TCA9406 Cell

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Feature Description (continued)

These two bidirectional channels independently determine the direction of data flow without a direction-control
signal. Each I/O pin is automatically reconfigured as either an input or an output, which is how this auto-direction
feature is realized.
The TCA9406 is part of TI's "Switch" type voltage translator family and employs two key circuits to enable this
voltage translation:
1) An N-channel pass-gate transistor topology that ties the A-port to the B-port
and
2) Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
For bidirectional voltage translation, pullup resistors are included on the device for dc current sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at approximately one threshold voltage (VT) above
the VCC level of the low-voltage side. Data can flow in either direction without guidance from a control signal.
The O.S. rising-edge rate accelerator circuitry speeds up the output slew rate by monitoring the input edge for
transitions, helping maintain the data rate through the device. During a low-to-high signal rising edge, the O.S.
circuits turn on the PMOS transistors (T1, T2) to increase the current drive capability of the driver for
approximately 30 ns or 95% of the input edge, whichever occurs first. This edge-rate acceleration provides high
ac drive by bypassing the internal 10-kΩ pullup resistors during the low-to-high transition to speed up the signal.
The output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase. To
minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn off
before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulse-width
number provided in the Timing Requirements section of this data sheet.

8.3.2 Input Driver Requirements

The continuous dc-current "sinking" capability is determined by the external system-level open-drain (or push-
pull) drivers that are interfaced to the TCA9406 I/O pins. Since the high bandwidth of these bidirectional I/O
circuits is used to facilitate this fast change from an input to an output and an output to an input, they have a
modest dc-current "sourcing" capability of hundreds of micro-Amps, as determined by the internal 10-kΩ pullup
resistors.
The fall time (tfA, tfB) of a signal depends on the edge-rate and output impedance of the external device driving
TCA9406 data I/Os, as well as the capacitive loading on the data lines.
Similarly, the tPHL and max data rates also depend on the output impedance of the external driver. The values for
tfA, tfB, tPHL, and maximum data rates in the data sheet assume that the output impedance of the external driver is
less than 50 Ω.

8.3.3 Output Load Considerations

TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TCA9406 output sees, so it is recommended that this lumped-load capacitance be
considered to avoid O.S. re-triggering, bus contention, output signal oscillations, or other adverse system-level
affects.

8.3.4 Enable and Disable

The TCA9406 has an OE input that is used to disable the device by setting OE low, which places all I/Os in the
Hi-Z state. When TCA9406 is disabled, the internal pull up resistors are also disabled meaning if no external pull
up resistors are present then the SDA/SCL lines will be left floating. The disable time (tdis) indicates the delay
between the time when OE goes low and when the outputs are disabled (Hi-Z). The enable time (ten) indicates
the amount of time the user must allow for the one-shot circuitry to become operational after OE is taken high.
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Feature Description (continued)

8.3.5 Pullup Resistors on I/O Lines
Each A-port I/O has an internal 10-kΩ pullup resistor to VCCA, and each B-port I/O has an internal 10-kΩ pullup
resistor to VCCB. If a smaller value of pullup resistor is required, an external resistor must be added from the I/O
to VCCA or VCCB (in parallel with the internal 10-kΩ resistors). Adding lower value pullup resistors will effect VOL
levels, however. The internal pullups of the TCA9406 are disabled when the OE pin is low.

8.4 Device Functional Modes

The TCA9406 device has two functional modes, enabled and disabled. To disable the device set the OE input
low, which places all I/Os in a high impedance state. Setting the OE input high will enable the device.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TCA9406 can be used to bridge the digital-switching compatibility gap between two voltage nodes to
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point
topology for interfacing devices or systems operating at different interface voltages with one another. Its primary
target application use is for interfacing with open-drain drivers on the data I/Os such as I2C or SMBus, where the
data is bidirectional and no control signal is available.

9.2 Typical Application

Optional Resistors

1.8 V 3.3 V
0.1 PF

VCCA V
VCCB
CCB

SDA_A SDA_B
Master SCL_A SCL_B I2C
I2C Bus
Bus Devices
OE

Design Notes: OE can be tied directly to 1.8 V (VCCA) to always be in ENABLE mode.

Figure 11. Typical Application Circuit

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 1. And make sure the VCCA ≤ VCCB.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 1.65 to 3.6 V
Output voltage range 2.3 to 5.5 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the TCA9406 device to determine the input voltage
range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value
must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the TCA9406 device is driving to determine the output voltage
range
– The TCA9406 device has 10-kΩ internal pullup resistors. External pullup resistors can be added to reduce
the total RC of a signal trace if necessary.

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9.2.3 Application Curve

Figure 12. Level-Translation of a 2.5-MHz Signal

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10 Power Supply Recommendations

During operation, ensure that VCCA ≤ VCCBat all times. The sequencing of each power supply will not damage the
device during the power up operation, so either power supply can be ramped up first. The output-enable (OE)
input circuit is designed so that it is supplied by VCCA and when the (OE) input is low, all outputs are placed in the
high-impedance state. To ensure the high-impedance state of the outputs during power up or power down, the
OE input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and VCCB are
fully ramped and stable. The minimum value of the pulldown resistor to ground is determined by the current-
sourcing capability of the driver.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, the following common printed-circuit board layout guidelines are
recommended:
• Bypass capacitors should be used on power supplies and should be placed as close as possible to the VCCA,
VCCB pin, and GND pin.
• Short trace lengths should be used to avoid excessive loading.
• PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than
the one-shot duration, approximately 30 ns, ensuring that any reflection encounters low impedance at the
source driver.

11.2 Layout Example

Legend
Via to power plane
Via to GND plane (inner layer)
TCA9406
To system To system
1 SDA_B SCL_B 8
0.1 F

2 GND VCCB 7 Bypass capacitor

Bypass capacitor 0.1 F
Keep OE low until VCCA
3 VCCA OE 6
and VCCB are powered up

4 SDA_A SCL_A 5
To controller To controller

Figure 13. TCA9406 Layout Example

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12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

24 Submit Documentation Feedback Copyright © 2010–2018, Texas Instruments Incorporated

Product Folder Links: TCA9406

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TCA9406DCTR ACTIVE SM8 DCT 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 NF9
(R, Z)
TCA9406DCUR ACTIVE VSSOP DCU 8 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 (F9, NF9R)
NZ
TCA9406YZPR ACTIVE DSBGA YZP 8 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 7W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Oct-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCA9406DCTR SM8 DCT 8 3000 177.8 12.4 3.45 4.4 1.45 4.0 12.0 Q3
TCA9406DCTR SM8 DCT 8 3000 180.0 13.0 3.35 4.5 1.55 4.0 12.0 Q3
TCA9406DCUR VSSOP DCU 8 3000 180.0 9.0 2.25 3.4 1.0 4.0 8.0 Q3
TCA9406DCUR VSSOP DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3
TCA9406YZPR DSBGA YZP 8 3000 180.0 8.4 1.11 2.1 0.56 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 21-Oct-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TCA9406DCTR SM8 DCT 8 3000 183.0 183.0 20.0
TCA9406DCTR SM8 DCT 8 3000 182.0 182.0 20.0
TCA9406DCUR VSSOP DCU 8 3000 182.0 182.0 20.0
TCA9406DCUR VSSOP DCU 8 3000 202.0 201.0 28.0
TCA9406YZPR DSBGA YZP 8 3000 182.0 182.0 20.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DCU0008A SCALE 6.000
VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE

3.2
TYP C
3.0
A
0.1 C
PIN 1 INDEX AREA SEATING
6X 0.5 PLANE
8
1

2X
2.1
1.5
1.9
NOTE 3

4
5
0.25
8X
0.17
2.4
B 0.08 C A B
2.2
NOTE 3

SEE DETAIL A

0.12 0.9
GAGE PLANE 0.6

0.1
0 -6 0.35 0.0
(0.13) TYP
0.20

DETAIL A
A 30

TYPICAL

4225266/A 09/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-187 variation CA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DCU0008A VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE

SEE SOLDER MASK

8X (0.85) SYMM DETAILS

(R0.05) TYP

8X (0.3) 1 8

SYMM
6X (0.5)

4 5

(3.1)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 25X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4225266/A 09/2014
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DCU0008A VSSOP - 0.9 mm max height
SMALL OUTLINE PACKAGE

8X (0.85)
SYMM
(R0.05) TYP

8X (0.3) 1 8

SYMM
6X (0.5)

4 5

(3.1)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 25X

4225266/A 09/2014
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DCT0008A SCALE 3.500
SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE

C
4.25
TYP
3.75 SEATING PLANE
A PIN 1 ID
AREA 0.1 C

6X 0.65
8
1

3.15 2X
2.75 1.95
NOTE 3

4
5
0.30
8X
0.15
2.9 0.13 C A B 1.3
B
2.7 1.0
NOTE 4

SEE DETAIL A (0.15) TYP

0.25
GAGE PLANE

0.1
0 -8 0.6 0.0
0.2

DETAIL A
TYPICAL

4220784/C 06/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

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 EXAMPLE BOARD LAYOUT
DCT0008A SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE

8X (1.1)
SYMM
(R0.05)
1 TYP
8

8X (0.4)
SYMM

6X (0.65)
5
4

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220784/C 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DCT0008A SSOP - 1.3 mm max height
SMALL OUTLINE PACKAGE

8X (1.1) SYMM
1
8

8X (0.4)
SYMM

6X (0.65)
5
4

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4220784/C 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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 PACKAGE OUTLINE
YZP0008 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

B E A

BALL A1
CORNER

C
0.5 MAX

SEATING PLANE
0.19
0.15 0.05 C
BALL TYP

0.5 TYP

C
SYMM
1.5
TYP
D: Max = 1.918 mm, Min =1.858 mm
B
E: Max = 0.918 mm, Min =0.858 mm
0.5
TYP
A

0.25
8X 1 2
0.21
0.015 C A B
SYMM

4223082/A 07/2016
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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 EXAMPLE BOARD LAYOUT
YZP0008 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP
8X ( 0.23)
1 2

(0.5) TYP

B
SYMM

SYMM

LAND PATTERN EXAMPLE

SCALE:40X

SOLDER MASK 0.05 MAX 0.05 MIN ( 0.23)

OPENING SOLDER MASK
OPENING

( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4223082/A 07/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

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 EXAMPLE STENCIL DESIGN
YZP0008 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.5) TYP

8X ( 0.25)
(R0.05) TYP
1 2

(0.5)
TYP

B
SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:40X

4223082/A 07/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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