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Vending Machine1 UVM

This document provides a coding test for a vending machine RTL design with 4 parts: 1. Write a UVM testbench architecture and interface file. 2. Print the design topology using the configuration class and database. 3. Write a driver class and monitor class with test logic. 4. Write a scoreboard class to check the test logic. The RTL provided is for a coin collector module with inputs for coins and a reset, and outputs for the done signal and 7-segment displays. It uses a state machine to track the coin value and display the appropriate amount.

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Sudeep Krishnappa
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93 views

Vending Machine1 UVM

This document provides a coding test for a vending machine RTL design with 4 parts: 1. Write a UVM testbench architecture and interface file. 2. Print the design topology using the configuration class and database. 3. Write a driver class and monitor class with test logic. 4. Write a scoreboard class to check the test logic. The RTL provided is for a coin collector module with inputs for coins and a reset, and outputs for the done signal and 7-segment displays. It uses a state machine to track the coin value and display the appropriate amount.

Uploaded by

Sudeep Krishnappa
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Training Services

Setting standards in VLSI Design

CODING TEST
Total Hour:- Max. Marks:- 20

For the following RTL Source code

1. Write a UVM (TB Architecture) and interface file. 05 M

2. Print the Topology using configuration class and config_db 05 M

3. Write Driver Class and Monitor Class with Logic 05 M

4. Write Scoreboard class with Logic 05 M

RTL (Vending Machine)

module coincol (clock,reset,coin_in,done_out,lsb7seg_out,msb7seg_out);


input clock,reset;
input [1:0]coin_in;
output done_out;
output reg [6:0]lsb7seg_out;
output reg [6:0]msb7seg_out;
reg [2:0]prestate,nextstate;
parameter STATE00 = 3'b000,
STATE25 = 3'b001,
STATE50 = 3'b010,
STATE75 = 3'b011,
STATE100 = 3'b100;

always @(posedge clock)


begin
if(reset)
prestate <= STATE00;
else
prestate <= nextstate;
end

1
VLSI Training Services
Setting standards in VLSI Design

always @(*)
begin
case(prestate)
STATE00 :
begin
if(coin_in == 2'b00)
nextstate = STATE25;
else if(coin_in == 2'b01)
nextstate = STATE50;
else if(coin_in == 2'b10)
nextstate = STATE100;
else
nextstate = STATE00;
end
STATE25 :
begin
if(coin_in == 2'b00)
nextstate = STATE50;
else if(coin_in == 2'b01)
nextstate = STATE75;
else if(coin_in == 2'b10)
nextstate = STATE100;
else
nextstate = STATE25;
end
STATE50 :
begin
if(coin_in == 2'b00)
nextstate = STATE75;
else if(coin_in == 2'b01 || coin_in == 2'b10)
nextstate = STATE100;
else

2
VLSI Training Services
Setting standards in VLSI Design

nextstate = STATE50;
end
STATE75 :
begin
if(coin_in == 2'b00 || coin_in == 2'b01 || coin_in == 2'b10)
nextstate = STATE100;
else
nextstate = STATE75;
end
default : nextstate = STATE00;
endcase
end

assign done_out = (prestate == STATE100) ? 1'b1 : 1'b0;


always @(prestate)
begin
case(prestate)
STATE25 :
begin
lsb7seg_out = 7'b0100100;
msb7seg_out = 7'b0010100;
end
STATE50 :
begin
lsb7seg_out = 7'b0100010;
msb7seg_out = 7'b1000000;
end
STATE75 :
begin
lsb7seg_out = 7'b1111000;
msb7seg_out = 7'b0010010;
end

3
VLSI Training Services
Setting standards in VLSI Design

STATE100 :
begin
lsb7seg_out = 7'b0001001;
msb7seg_out = 7'b0001000;
end
default :
begin
lsb7seg_out = 7'b1000000;
msb7seg_out = 7'b1000000;
end
endcase
end
endmodule

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