LTC2245

14-Bit, 10Msps
Low Power 3V ADC
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FEATURES DESCRIPTIO
■ Sample Rate: 10Msps The LTC®2245 is a 14-bit 10Msps, low power 3V A/D
■ Single 3V Supply (2.7V to 3.4V) converter designed for digitizing high frequency, wide
■ Low Power: 60mW dynamic range signals. The LTC2245 is perfect for de-
■ 74.4dB SNR manding imaging and communications applications with
■ 90dB SFDR AC performance that includes 74.4dB SNR and 90dB
■ No Missing Codes SFDR for signals well beyond the Nyquist frequency.
■ Flexible Input: 1VP-P to 2VP-P Range DC specs include ±1LSB INL (typ), ±0.5LSB DNL (typ) and
■ 575MHz Full Power Bandwidth S/H
no missing codes over temperature. The transition noise
■ Clock Duty Cycle Stabilizer is a low 1LSBRMS.
■ Shutdown and Nap Modes
■ Pin Compatible Family A single 3V supply allows low power operation. A separate
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit) output supply allows the outputs to drive 0.5V to 3.6V
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit) logic.
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit) A single-ended CLK input controls converter operation. An
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit) optional clock duty cycle stabilizer allows high perfor-
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit) mance at full speed for a wide range of clock duty cycles.
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
, LTC and LT are registered trademarks of Linear Technology Corporation.
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit) All other trademarks are the property of their respective owners.
■ 32-Pin (5mm × 5mm) QFN Package
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APPLICATIO S
■ Wireless and Wired Broadband Communication
■ Imaging Systems
■ Spectral Analysis
■ Portable Instrumentation

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TYPICAL APPLICATIO Typical INL, 2V Range
2.0
REFH FLEXIBLE 1.5
REFL REFERENCE
1.0
OVDD
INL ERROR (LSB)

0.5
+ D13
14-BIT • 0
ANALOG INPUT CORRECTION OUTPUT
PIPELINED •
INPUT S/H LOGIC DRIVERS
ADC CORE • –0.5
– D0
–1.0
OGND
–1.5
CLOCK/DUTY
CYCLE –2.0
0 4096 8192 12288 16384
CONTROL
CODE
2245 TA01 2245 G01

CLK

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LTC2245
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ABSOLUTE AXI U RATI GS PACKAGE/ORDER I FOR ATIO
OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................. 4V TOP VIEW

SENSE
MODE
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V

VCM

D13
D12
D11
VDD

OF
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V) 32 31 30 29 28 27 26 25
Digital Input Voltage .................... –0.3V to (VDD + 0.3V) AIN+ 1 24 D10
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V) AIN– 2 23 D9

Power Dissipation ............................................ 1500mW REFH 3 22 D8

REFH 4 21 OVDD
Operating Temperature Range 33
REFL 5 20 OGND
LTC2245C ............................................... 0°C to 70°C
REFL 6 19 D7
LTC2245I .............................................–40°C to 85°C VDD 7 18 D6
Storage Temperature Range ..................–65°C to 125°C GND 8 17 D5
9 10 11 12 13 14 15 16

CLK
SHDN
OE
D0
D1
D2
D3
D4
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD IS GND (PIN 33)
MUST BE SOLDERED TO PCB

ORDER PART NUMBER QFN PART MARKING

LTC2245CUH 2245*
LTC2245IUH
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.

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CO VERTER CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution ● 14 Bits
(No Missing Codes)
Integral Differential Analog Input ● –4 ±1 4 LSB
Linearity Error (Note 5)
Differential Differential Analog Input ● –1 ±0.5 1 LSB
Linearity Error
Offset Error (Note 6) ● –12 ±2 12 mV
Gain Error External Reference ● –2.5 ±0.5 2.5 %FS
Offset Drift ±10 µV/°C
Full-Scale Drift Internal Reference ±30 ppm/°C
External Reference ±5 ppm/°C
Transition Noise SENSE = 1V 1 LSBRMS

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A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN +
Analog Input Range (AIN – AIN –) 2.7V < VDD < 3.4V (Note 7) ● ±0.5V to ±1V V
VIN,CM Analog Input Common Mode (AIN+ + AIN–)/2 Differential Input (Note 7) ● 1 1.5 1.9 V
Single Ended Input (Note 7) ● 0.5 1.5 2 V
IIN Analog Input Leakage Current 0V < AIN+, AIN– < VDD ● –1 1 µA
ISENSE SENSE Input Leakage 0V < SENSE < 1V ● –3 3 µA
IMODE MODE Pin Leakage ● –3 3 µA
tAP Sample-and-Hold Acquisition Delay Time 0 ns
tJITTER Sample-and-Hold Acquisition Delay Time Jitter 0.2 psRMS
CMRR Analog Input Common Mode Rejection Ratio 80 dB
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DY A IC ACCURACY The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input ● 72.3 74.4 dB
70MHz Input 73.2 dB
SFDR Spurious Free Dynamic Range 5MHz Input ● 76 90 dB
2nd or 3rd Harmonic 70MHz Input 85 dB
SFDR Spurious Free Dynamic Range 5MHz Input ● 84 95 dB
4th Harmonic or Higher 70MHz Input 95 dB
S/(N+D) Signal-to-Noise Plus Distortion Ratio 5MHz Input ● 71.7 74.4 dB
70MHz Input 73.1 dB
IMD Intermodulation Distortion fIN1 = 4.3MHz, fIN2 = 4.6MHz 90 dB

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I TER AL REFERE CE CHARACTERISTICS (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.475 1.500 1.525 V
VCM Output Tempco ±25 ppm/°C
VCM Line Regulation 2.7V < VDD < 3.4V 3 mV/V
VCM Output Resistance –1mA < IOUT < 1mA 4 Ω

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DIGITAL I PUTS A D DIGITAL OUTPUTS The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
LOGIC INPUTS (CLK, OE, SHDN)
VIH High Level Input Voltage VDD = 3V ● 2 V
VIL Low Level Input Voltage VDD = 3V ● 0.8 V
IIN Input Current VIN = 0V to VDD ● –10 10 µA
CIN Input Capacitance (Note 7) 3 pF
LOGIC OUTPUTS
OVDD = 3V
COZ Hi-Z Output Capacitance OE = High (Note 7) 3 pF
ISOURCE Output Source Current VOUT = 0V 50 mA
ISINK Output Sink Current VOUT = 3V 50 mA
VOH High Level Output Voltage IO = –10µA 2.995 V
IO = –200µA ● 2.7 2.99 V
VOL Low Level Output Voltage IO = 10µA 0.005 V
IO = 1.6mA ● 0.09 0.4 V
OVDD = 2.5V
VOH High Level Output Voltage IO = –200µA 2.49 V
VOL Low Level Output Voltage IO = 1.6mA 0.09 V
OVDD = 1.8V
VOH High Level Output Voltage IO = –200µA 1.79 V
VOL Low Level Output Voltage IO = 1.6mA 0.09 V

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POWER REQUIRE E TS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 9) ● 2.7 3 3.4 V
OVDD Output Supply Voltage (Note 9) ● 0.5 3 3.6 V
IVDD Supply Current ● 20 23 mA
PDISS Power Dissipation ● 60 69 mW
PSHDN Shutdown Power SHDN = H, OE = H, No CLK 2 mW
PNAP Nap Mode Power SHDN = H, OE = L, No CLK 15 mW

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TI I G CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fs Sampling Frequency (Note 9) ● 1 10 MHz
tL CLK Low Time Duty Cycle Stabilizer Off ● 40 50 500 ns
Duty Cycle Stabilizer On ● 5 50 500 ns
(Note 7)
tH CLK High Time Duty Cycle Stabilizer Off ● 40 50 500 ns
Duty Cycle Stabilizer On ● 5 50 500 ns
(Note 7)
tAP Sample-and-Hold Aperture Delay 0 ns
tD CLK to DATA delay CL = 5pF (Note 7) ● 1.4 2.7 5.4 ns
Data Access Time After OE↓ CL = 5pF (Note 7) ● 4.3 10 ns
BUS Relinquish Time (Note 7) ● 3.3 8.5 ns
Pipeline 5 Cycles
Latency

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Integral nonlinearity is defined as the deviation of a code from a
may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve.
Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band.
reliability and lifetime. Note 6: Offset error is the offset voltage measured from –0.5 LSB when
Note 2: All voltage values are with respect to ground with GND and OGND the output code flickers between 00 0000 0000 0000 and
wired together (unless otherwise noted). 11 1111 1111 1111.
Note 3: When these pin voltages are taken below GND or above VDD, they Note 7: Guaranteed by design, not subject to test.
will be clamped by internal diodes. This product can handle input currents Note 8: VDD = 3V, fSAMPLE = 10MHz, input range = 1VP-P with
of greater than 100mA below GND or above VDD without latchup. differential drive.
Note 4: VDD = 3V, fSAMPLE = 10MHz, input range = 2VP-P with differential Note 9: Recommended operating conditions.
drive, unless otherwise noted.

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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point FFT, fIN = 5.1MHz,
Typical INL, 2V Range Typical DNL, 2V Range –1dB, 2V Range
2.0 1.0 0
0.8 –10
1.5
–20
0.6
1.0 –30
0.4
DNL ERROR (LSB)
INL ERROR (LSB)

–40
AMPLITUDE (dB)

0.5 0.2 –50

0 0 –60
–0.2 –70
–0.5
–80
–0.4
–1.0 –90
–0.6
–100
–1.5 –0.8 –110
–2.0 –1.0 –120
0 4096 8192 12288 16384 0 4096 8192 12288 16384 0 1 2 3 4 5
CODE CODE FREQUENCY (MHz)
2245 G01 2245 G02 2245 G03

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TYPICAL PERFOR A CE CHARACTERISTICS
8192 Point 2-Tone FFT,
8192 Point FFT, fIN = 70.1MHz, fIN = 4.3MHz and 4.6MHz,
–1dB, 2V Range –1dB, 2V Range Grounded Input Histogram
0 0 25000
–10 –10 22016
–20 –20
20000 18803
–30 –30
–40

AMPLITUDE (dB)
–40
AMPLITUDE (dB)

–50 15000
–50 13373

COUNT
–60 –60
–70 –70 10000
–80 –80 6919
–90 –90
5000
–100 –100 3227
–110 –110 853 278
43
–120 –120 0
0 1 2 3 4 5 0 1 2 3 4 5 8179 8180 8181 8182 8183 8184 8185 8186
FREQUENCY (MHz) FREQUENCY (MHz) CODE
2245 G04 2245 G05 2245 G06

SNR vs Input Frequency, –1dB, SFDR vs Input Frequency, –1dB, SNR and SFDR vs Sample Rate,
2V Range 2V Range 2V Range, fIN = 5MHz, –1dB
75 100 100
74
95 SFDR
73
90
SNR AND SFDR (dBFS)
72 90
SFDR (dBFS)
SNR (dBFS)

71
85
70 80

69 80 SNR

68 75 70
67
70
66
65 65 60
0 10 20 30 40 50 60 70 0 10 20 30 40 50 60 70 0 2 4 6 8 10 12 14
INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) SAMPLE RATE (Msps)
2245 G07 2245 G08 2225 G09

SNR vs Input Level, fIN = 5MHz, SFDR vs Input Level, fIN = 5MHz,
2V Range 2V Range
80 120
dBFS dBFS
110
70
100
60 90
SFDR (dBc AND dBFS)
SNR (dBc AND dBFS)

dBc
80
50
70
40 60
dBc 100dBc SFDR
50
30 REFERENCE LINE
40
20 30
20
10
10
0 0
–70 –60 –50 –40 –30 –20 –10 0 –80 –60 –40 –20 0
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS)
2245 G10 2245 G11

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TYPICAL PERFOR A CE CHARACTERISTICS
IVDD vs Sample Rate, IOVDD vs Sample Rate, 5MHz Sine
5MHz Sine Wave Input, –1dB Wave Input, –1dB, OVDD = 1.8V
25 1.0
0.9
2V RANGE 0.8
0.7
20
0.6

IOVDD (mA)
IVDD (mA)

1V RANGE
0.5
0.4
15
0.3
0.2
0.1
10 0
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14
SAMPLE RATE (Msps) SAMPLE RATE (Msps)
2245 G12 2245 G13

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PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input. outputs at high impedance. Connecting SHDN to VDD and
AIN- (Pin 2): Negative Differential Analog Input. OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
REFH (Pins 3, 4): ADC High Reference. Short together and results in sleep mode with the outputs at high impedance.
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with OE (Pin 11): Output Enable Pin. Refer to SHDN pin
an additional 2.2µF ceramic chip capacitor and to ground function.
with a 1µF ceramic chip capacitor. D0 – D13 (Pins 12, 13, 14, 15, 16, 17, 18, 19, 22, 23, 24,
REFL (Pins 5, 6): ADC Low Reference. Short together and 25, 26, 27): Digital Outputs. D13 is the MSB.
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as OGND (Pin 20): Output Driver Ground.
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground OVDD (Pin 21): Positive Supply for the Output Drivers.
with a 1µF ceramic chip capacitor. Bypass to ground with 0.1µF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF OF (Pin 28): Over/Under Flow Output. High when an over
ceramic chip capacitors. or under flow has occurred.
GND (Pin 8): ADC Power Ground. MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
CLK (Pin 9): Clock Input. The input sample starts on the offset binary output format and turns the clock duty cycle
positive edge.
stabilizer off. 1/3 VDD selects offset binary output format
SHDN (Pin 10): Shutdown Mode Selection Pin. Connect- and turns the clock duty cycle stabilizer on. 2/3 VDD selects
ing SHDN to GND and OE to GND results in normal 2’s complement output format and turns the clock duty
operation with the outputs enabled. Connecting SHDN to cycle stabilizer on. VDD selects 2’s complement output
GND and OE to VDD results in normal operation with the format and turns the clock duty cycle stabilizer off.

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PI FU CTIO S
SENSE (Pin 30): Reference Programming Pin. Connecting VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
SENSE to VCM selects the internal reference and a ±0.5V Bypass to ground with 2.2µF ceramic chip capacitor.
input range. VDD selects the internal reference and a ±1V
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
input range. An external reference greater than 0.5V and
exposed pad on the bottom of the package needs to be
less than 1V applied to SENSE selects an input range of
soldered to ground.
±VSENSE. ±1V is the largest valid input range.

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FUNCTIONAL BLOCK DIAGRA

AIN+

INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED SIXTH PIPELINED
S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE
AIN–

VCM 1.5V
REFERENCE SHIFT REGISTER
2.2µF AND CORRECTION

RANGE
SELECT

REFH REFL INTERNAL CLOCK SIGNALS OVDD

REF
SENSE BUF OF
D13
DIFF CLOCK/DUTY CONTROL OUTPUT •
REF CYCLE LOGIC DRIVERS •
AMP CONTROL •
D0

REFH 0.1µF REFL 2245 F01

OGND
CLK MODE SHDN OE
2.2µF

1µF 1µF

Figure 1. Functional Block Diagram

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TI I G DIAGRA
tAP

ANALOG N N+2 N+4

INPUT N+3 N+5
tH N+1
tL

CLK

tD

D0-D13, OF N–5 N–4 N–3 N–2 N–1 N

2245 TD01

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APPLICATIO S I FOR ATIO
DYNAMIC PERFORMANCE Intermodulation Distortion
If the ADC input signal consists of more than one spectral
Signal-to-Noise Plus Distortion Ratio
component, the ADC transfer function nonlinearity can
The signal-to-noise plus distortion ratio [S/(N + D)] is the produce intermodulation distortion (IMD) in addition to
ratio between the RMS amplitude of the fundamental input THD. IMD is the change in one sinusoidal input caused by
frequency and the RMS amplitude of all other frequency the presence of another sinusoidal input at a different
components at the ADC output. The output is band limited frequency.
to frequencies above DC to below half the sampling
If two pure sine waves of frequencies fa and fb are applied
frequency.
to the ADC input, nonlinearities in the ADC transfer func-
Signal-to-Noise Ratio tion can create distortion products at the sum and differ-
ence frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
The signal-to-noise ratio (SNR) is the ratio between the etc. The 3rd order intermodulation products are 2fa + fb,
RMS amplitude of the fundamental input frequency and 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
the RMS amplitude of all other frequency components distortion is defined as the ratio of the RMS value of either
except the first five harmonics and DC. input tone to the RMS value of the largest 3rd order
intermodulation product.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all Spurious Free Dynamic Range (SFDR)
harmonics of the input signal to the fundamental itself. The Spurious free dynamic range is the peak harmonic or
out-of-band harmonics alias into the frequency band spurious noise that is the largest spectral component
between DC and half the sampling frequency. THD is excluding the input signal and DC. This value is expressed
expressed as: in decibels relative to the RMS value of a full scale input
THD = 20Log (√(V22 + V32 + V42 + . . . Vn2)/V1) signal.
where V1 is the RMS amplitude of the fundamental fre- Input Bandwidth
quency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this The input bandwidth is that input frequency at which the
data sheet uses all the harmonics up to the fifth. amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.

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APPLICATIO S I FOR ATIO
Aperture Delay Time the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
The time from when CLK reaches mid-supply to the instant
third, fourth and fifth stages, resulting in a fifth stage
that the input signal is held by the sample and hold circuit.
residue that is sent to the sixth stage ADC for final
Aperture Delay Jitter evaluation.

The variation in the aperture delay time from conversion to Each ADC stage following the first has additional range to
conversion. This random variation will result in noise accommodate flash and amplifier offset errors. Results
when sampling an AC input. The signal to noise ratio due from all of the ADC stages are digitally synchronized such
to the jitter alone will be: that the results can be properly combined in the correction
logic before being sent to the output buffer.
SNRJITTER = –20log (2π • fIN • tJITTER)
SAMPLE/HOLD OPERATION AND INPUT DRIVE
CONVERTER OPERATION
As shown in Figure 1, the LTC2245 is a CMOS pipelined Sample/Hold Operation
multistep converter. The converter has six pipelined ADC Figure 2 shows an equivalent circuit for the LTC2245
stages; a sampled analog input will result in a digitized CMOS differential sample-and-hold. The analog inputs are
value five cycles later (see the Timing Diagram section). connected to the sampling capacitors (CSAMPLE) through
For optimal AC performance the analog inputs should be NMOS transistors. The capacitors shown attached to each
driven differentially. For cost sensitive applications, the input (CPARASITIC) are the summation of all other capaci-
analog inputs can be driven single-ended with slightly tance associated with each input.
worse harmonic distortion. The CLK input is single-ended.
The LTC2245 has two phases of operation, determined by LTC2245
the state of the CLK input pin. VDD
CSAMPLE
4pF
Each pipelined stage shown in Figure 1 contains an ADC, AIN+
15Ω

a reconstruction DAC and an interstage residue amplifier. CPARASITIC

1pF
In operation, the ADC quantizes the input to the stage and VDD
CSAMPLE
the quantized value is subtracted from the input by the 15Ω
4pF

DAC to produce a residue. The residue is amplified and AIN–

CPARASITIC
output by the residue amplifier. Successive stages operate 1pF

out of phase so that when the odd stages are outputting VDD

their residue, the even stages are acquiring that residue CLK
and vice versa.
When CLK is low, the analog input is sampled differentially 2245 F02

directly onto the input sample-and-hold capacitors, inside Figure 2. Equivalent Input Circuit
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is During the sample phase when CLK is low, the transistors
held. While CLK is high, the held input voltage is buffered connect the analog inputs to the sampling capacitors and
by the S/H amplifier which drives the first pipelined ADC they charge to and track the differential input voltage.
stage. The first stage acquires the output of the S/H during When CLK transitions from low to high, the sampled input
this high phase of CLK. When CLK goes back low, the first voltage is held on the sampling capacitors. During the hold
stage produces its residue which is acquired by the phase when CLK is high, the sampling capacitors are
second stage. At the same time, the input S/H goes back disconnected from the input and the held voltage is passed
to acquiring the analog input. When CLK goes back high, to the ADC core for processing. As CLK transitions from
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APPLICATIO S I FOR ATIO
high to low, the inputs are reconnected to the sampling the sampling capacitor. Ideally the input circuitry should
capacitors to acquire a new sample. Since the sampling be fast enough to fully charge the sampling capacitor
capacitors still hold the previous sample, a charging glitch during the sampling period 1/(2FENCODE); however, this is
proportional to the change in voltage between samples will not always possible and the incomplete settling may
be seen at this time. If the change between the last sample degrade the SFDR. The sampling glitch has been designed
and the new sample is small, the charging glitch seen at to be as linear as possible to minimize the effects of
the input will be small. If the input change is large, such as incomplete settling.
the change seen with input frequencies near Nyquist, then
For the best performance, it is recommended to have a
a larger charging glitch will be seen.
source impedance of 100Ω or less for each input. The
Single-Ended Input source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
For cost sensitive applications, the analog inputs can be harmonics, especially the second.
driven single-ended. With a single-ended input the har-
monic distortion and INL will degrade, but the SNR and Input Drive Circuits
DNL will remain unchanged. For a single-ended input, AIN+
Figure 3 shows the LTC2245 being driven by an RF
should be driven with the input signal and AIN– should be
connected to VCM or a low noise reference voltage between transformer with a center tapped secondary. The second-
0.5V and 1.5V. ary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Terminating on the trans-
Common Mode Bias former secondary is desirable, as this provides a common
mode path for charging glitches caused by the sample and
For optimal performance the analog inputs should be hold. Figure 3 shows a 1:1 turns ratio transformer. Other
driven differentially. Each input should swing ±0.5V for turns ratios can be used if the source impedance seen by
the 2V range or ±0.25V for the 1V range, around a the ADC does not exceed 100Ω for each ADC input. A
common mode voltage of 1.5V. The VCM output pin (Pin disadvantage of using a transformer is the loss of low
31) may be used to provide the common mode bias level. frequency response. Most small RF transformers have
VCM can be tied directly to the center tap of a transformer poor performance at frequencies below 1MHz.
to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to VCM
ground close to the ADC with a 2.2µF or greater capacitor.
2.2µF
0.1µF T1
Input Drive Impedance ANALOG 1:1 25Ω AIN+
LTC2245
INPUT
0.1µF
As with all high performance, high speed ADCs, the 25Ω
12pF
dynamic performance of the LTC2245 can be influenced
25Ω
by the input drive circuitry, particularly the second and AIN–
third harmonics. Source impedance and reactance can T1 = MA/COM ETC1-1T 25Ω
influence SFDR. At the falling edge of CLK, the sample- RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2245 F03

and-hold circuit will connect the 4pF sampling capacitor to

the input pin and start the sampling period. The sampling Figure 3. Single-Ended to Differential Conversion
period ends when CLK rises, holding the sampled input on Using a Transformer

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APPLICATIO S I FOR ATIO
VCM LTC2245

HIGH SPEED 2.2µF VCM 4Ω 1.5V BANDGAP

1.5V
DIFFERENTIAL REFERENCE
AMPLIFIER 25Ω AIN+ 2.2µF
LTC2245 1V 0.5V
ANALOG +
INPUT +
CM 12pF RANGE
– – DETECT
25Ω AIN– AND
CONTROL
TIE TO VDD FOR 2V RANGE;
2245 F04 TIE TO VCM FOR 1V RANGE; SENSE
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V BUFFER
Figure 4. Differential Drive with an Amplifier
INTERNAL ADC
1µF HIGH REFERENCE
REFH
VCM

2.2µF
1k 1k 2.2µF 0.1µF
0.1µF DIFF AMP
25Ω +
ANALOG AIN
LTC2245
INPUT 1µF
REFL
12pF
INTERNAL ADC
LOW REFERENCE
25Ω AIN–
2245 F06
0.1µF 2245 F05

Figure 6. Equivalent Reference Circuit

Figure 5. Single-Ended Drive

Figure 4 demonstrates the use of a differential amplifier to Reference Operation

convert a single ended input signal into a differential input Figure 6 shows the LTC2245 reference circuitry consisting
signal. The advantage of this method is that it provides low of a 1.5V bandgap reference, a difference amplifier and
frequency input response; however, the limited gain band- switching and control circuit. The internal voltage refer-
width of most op amps will limit the SFDR at high input ence can be configured for two pin selectable input ranges
frequencies. of 2V (±1V differential) or 1V (±0.5V differential). Tying the
Figure 5 shows a single-ended input circuit. The imped- SENSE pin to VDD selects the 2V range; tying the SENSE
ance seen by the analog inputs should be matched. This pin to VCM selects the 1V range.
circuit is not recommended if low distortion is required. The 1.5V bandgap reference serves two functions: its
The 25Ω resistors and 12pF capacitor on the analog inputs output provides a DC bias point for setting the common
serve two purposes: isolating the drive circuitry from the mode voltage of any external input circuitry; additionally,
sample-and-hold charging glitches and limiting the the reference is used with a difference amplifier to gener-
wideband noise at the converter input. ate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.

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12
 LTC2245
U U W U
APPLICATIO S I FOR ATIO
The difference amplifier generates the high and low refer- The noise performance of the LTC2245 can depend on the
ence for the ADC. High speed switching circuits are clock signal quality as much as on the analog input. Any
connected to these outputs and they must be externally noise present on the clock signal will result in additional
bypassed. Each output has two pins. The multiple output aperture jitter that will be RMS summed with the inherent
pins are needed to reduce package inductance. Bypass ADC aperture jitter.
capacitors must be connected as shown in Figure 6.
Maximum and Minimum Conversion Rates
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown The maximum conversion rate for the LTC2245 is 10Msps.
in Figure 7. An external reference can be used by applying For the ADC to operate properly, the CLK signal should
its output directly or through a resistor divider to SENSE. have a 50% (±10%) duty cycle. Each half cycle must have
It is not recommended to drive the SENSE pin with a logic at least 40ns for the ADC internal circuitry to have enough
device. The SENSE pin should be tied to the appropriate settling time for proper operation.
level as close to the converter as possible. If the SENSE pin An optional clock duty cycle stabilizer circuit can be used
is driven externally, it should be bypassed to ground as if the input clock has a non 50% duty cycle. This circuit
close to the device as possible with a 1µF ceramic capacitor. uses the rising edge of the CLK pin to sample the analog
input. The falling edge of CLK is ignored and the internal
Input Range
falling edge is generated by a phase-locked loop. The input
The input range can be set based on the application. The clock duty cycle can vary and the clock duty cycle stabilizer
2V input range will provide the best signal-to-noise perfor- will maintain a constant 50% internal duty cycle. If the
mance while maintaining excellent SFDR. The 1V input clock is turned off for a long period of time, the duty cycle
range will have better SFDR performance, but the SNR will stabilizer circuit will require a hundred clock cycles for the
degrade by 5.8dB. PLL to lock onto the input clock. To use the clock duty
cycle stabilizer, the MODE pin should be connected to
Driving the Clock Input 1/3VDD or 2/3VDD using external resistors.
The CLK input can be driven directly with a CMOS or TTL The lower limit of the LTC2245 sample rate is determined
level signal. A differential clock can also be used along with by droop of the sample-and-hold circuits. The pipelined
a low-jitter CMOS converter before the CLK pin (see architecture of this ADC relies on storing analog signals on
Figure 8). small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating fre-
quency for the LTC2245 is 1Msps.
CLEAN
1.5V VCM
SUPPLY
4.7µF
2.2µF
12k
FERRITE
LTC2245 BEAD
0.75V SENSE
0.1µF
12k 1µF

CLK
2245 F07
LTC2245
100Ω

Figure 7. 1.5V Range ADC

2245 F08

IF LVDS USE FIN1002 OR FIN1018.

FOR PECL, USE AZ1000ELT21 OR SIMILAR

Figure 8. CLK Drive Using an LVDS or PECL to CMOS Converter

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LTC2245
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APPLICATIO S I FOR ATIO
DIGITAL OUTPUTS As with all high speed/high resolution converters, the
Table 1 shows the relationship between the analog input digital output loading can affect the performance. The
voltage, the digital data bits, and the overflow bit. digital outputs of the LTC2245 should drive a minimal
capacitive load to avoid possible interaction between the
Table 1. Output Codes vs Input Voltage digital outputs and sensitive input circuitry. The output
AIN+ – AIN– D13 – D0 D13 – D0 should be buffered with a device such as an ALVCH16373
(2V Range) OF (Offset Binary) (2’s Complement)
CMOS latch. For full speed operation the capacitive load
>+1.000000V 1 11 1111 1111 1111 01 1111 1111 1111 should be kept under 10pF.
+0.999878V 0 11 1111 1111 1111 01 1111 1111 1111
+0.999756V 0 11 1111 1111 1110 01 1111 1111 1110 Lower OVDD voltages will also help reduce interference
+0.000122V 0 10 0000 0000 0001 00 0000 0000 0001 from the digital outputs.
0.000000V 0 10 0000 0000 0000 00 0000 0000 0000
–0.000122V 0 01 1111 1111 1111 11 1111 1111 1111
–0.000244V 0 01 1111 1111 1110 11 1111 1111 1110
Data Format
–0.999878V 0 00 0000 0000 0001 10 0000 0000 0001 Using the MODE pin, the LTC2245 parallel digital output
–1.000000V 0 00 0000 0000 0000 10 0000 0000 0000 can be selected for offset binary or 2’s complement
<–1.000000V 1 00 0000 0000 0000 10 0000 0000 0000
format. Connecting MODE to GND or 1/3VDD selects offset
Digital Output Buffers binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format.
Figure 9 shows an equivalent circuit for a single output An external resistor divider can be used to set the 1/3VDD
buffer. Each buffer is powered by OVDD and OGND, iso- or 2/3VDD logic values. Table 2 shows the logic states for
lated from the ADC power and ground. The additional the MODE pin.
N-channel transistor in the output driver allows operation
Table 2. MODE Pin Function
down to low voltages. The internal resistor in series with
Clock Duty
the output makes the output appear as 50Ω to external MODE Pin Output Format Cycle Stablizer
circuitry and may eliminate the need for external damping
0 Offset Binary Off
resistors.
1/3VDD Offset Binary On
LTC2245 2/3VDD 2’s Complement On
OVDD
0.5V VDD 2’s Complement Off
VDD VDD TO 3.6V
0.1µF
Overflow Bit
OVDD
When OF outputs a logic high the converter is either
DATA
FROM
PREDRIVER
LOGIC
43Ω TYPICAL overranged or underranged.
DATA
LATCH
OUTPUT

OE
OGND

2245 F09

Figure 9. Digital Output Buffer

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 LTC2245
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APPLICATIO S I FOR ATIO
Output Driver Power Grounding and Bypassing
Separate output power and ground pins allow the output The LTC2245 requires a printed circuit board with a clean,
drivers to be isolated from the analog circuitry. The power unbroken ground plane. A multilayer board with an inter-
supply for the digital output buffers, OVDD, should be tied nal ground plane is recommended. Layout for the printed
to the same power supply as for the logic being driven. For circuit board should ensure that digital and analog signal
example if the converter is driving a DSP powered by a 1.8V lines are separated as much as possible. In particular, care
supply, then OVDD should be tied to that same 1.8V supply. should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up High quality ceramic bypass capacitors should be used at
to 1V and must be less than OVDD. The logic outputs will the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capaci-
swing between OGND and OVDD. tors must be located as close to the pins as possible. Of
particular importance is the 0.1µF capacitor between
Output Enable REFH and REFL. This capacitor should be placed as close
The outputs may be disabled with the output enable pin, OE. to the device as possible (1.5mm or less). A size 0402
OE high disables all data outputs including OF. The output ceramic capacitor is recommended. The large 2.2µF
Hi-Z state can be used to multiplex the data bus of several capacitor between REFH and REFL can be somewhat
LTC2245s. further away. The traces connecting the pins and bypass
capacitors must be kept short and should be made as wide
Sleep and Nap Modes as possible.
The converter may be placed in shutdown or nap modes The LTC2245 differential inputs should run parallel and
to conserve power. Connecting SHDN to GND results in close to each other. The input traces should be as short as
normal operation. Connecting SHDN to VDD and OE to VDD possible to minimize capacitance and to minimize noise
results in sleep mode, which powers down all circuitry pickup.
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output Heat Transfer
data to become valid because the reference capacitors have Most of the heat generated by the LTC2245 is transferred
to recharge and stabilize. Connecting SHDN to VDD and OE from the die through the bottom-side exposed pad and
to GND results in nap mode, which typically dissipates package leads onto the printed circuit board. For good
15mW. In nap mode, the on-chip reference circuit is kept electrical and thermal performance, the exposed pad
on, so that recovery from nap mode is faster than that from should be soldered to a large grounded pad on the PC
sleep mode, typically taking 100 clock cycles. In both sleep board. It is critical that all ground pins are connected to a
and nap modes, all digital outputs are disabled and enter ground plane of sufficient area.
the Hi-Z state.

2245fa

15
16
VCC VCC

J1 R2
C1 T1 74VCX16373MTD
LTC2245

ANALOG 24.9Ω
R1 0.1µF ETC1–1T 34 28
INPUT GND GND
OPT
5 1 R3 45 31
24.9Ω GND VCC
2 39 21
C2 GND GND
12pF 42 15
4 • •3 R4 VCC GND
24.9Ω 25 18
R5 LE2 VCC
U U

C3 50Ω 48 10
R6 LE1 GND
0.1µF VCM 24 4
C4 24.9Ω OE2 GND
1 7 3201S-40G1
0.1µF OE1 VCC
47 2 RN1D 33Ω 39 40
C5 LTC2245 I0 O0 39 40
1 12 46 3 RN1C 33Ω 37 38
4.7µF C6 AIN+ D0 I1 O1 37 38
W

L1 2 13 44 5 RN1B 33Ω 35 36
6.3V 1µF D1
BEAD AIN– I2 O2 35 36
3 14 43 6 RN1A 33Ω 33 34
VDD REFH D2 I3 O3 33 34
C7 C8 4 15 41 8 RN2D 33Ω 31 32
REFH D3 I4 O4 31 32
2.2µF 0.1µF 5 16 40 9 RN2C 33Ω 29 30
APPLICATIO S I FOR ATIO

REFL D4 I5 O5 29 30
6 17 38 11 RN2B 33Ω 27 28
U

R7 C10 C9 REFL D5 I6 O6 27 28
J3 1k 0.1µF 1µF 7 18 37 12 RN2A 33Ω 25 26
VDD VDD D6 I7 O7 25 26
CLOCK C12 C11 8 19 36 13 RN3D 33Ω 23 24
INPUT 0.1µF 0.1µF GND D7 I8 O8 23 24
NC7SVU04
9 22 35 14 RN3C 33Ω 21 22
CLK D8 I9 O9 21 22
10 23 33 16 RN3B 33Ω 19 20
R8 R9 SHDN D9 I10 O10 19 20
49.9Ω 1k
VDD VDD 11 24 32 17 RN3A 33Ω 17 18
JP1 JP2 OE D10 I11 O11 17 18
25 30 19 RN4D 33Ω 15 16
SHDN OE D11 I12 O12 15 16
C13 VDD
GND
VDD
GND 26 29 20 RN4C 33Ω 13 14
0.1µF D12 I13 O13 13 14
32 27 27 22 RN4B 33Ω 11 12
VDD VDD D13 I14 O14 11 12
C14 31 28 26 23 RN4A 33Ω 9 10
0.1µF VCM VCM OF I15 O15 9 10
C15 30 21 7 8
NC7SVU04 2.2µF SENSE OVDD VCC 7 8
R10 C16 C17 0.1µF
29 20 5 6
33Ω MODE OGND 0.1µF 5 6
GND 3 4
VCC 3 4
33 1 2
24LC025 R11 R13 1 2
JP3 SENSE 10k 10k
1 8
VDD A0 VCC R12
1 2 2 7
VDD JP4 MODE A1 WP 10k
NC7SV86P5X C18 3 6
VCM VDD VDD A2 SCL
VCC 0.1µF 4 5
3 4 1 2 A3 SDA
VCM
R14 LT1763 VDD
EXT REF 1k 2/3VDD R17
E1 5 6 3 4 1 8 VCC
105k OUT IN VDD
EXT REF 2 7 E2
R15 C26 ADJ GND
1/3VDD 3 6 E3
1k 5 6 10µF R18 VDD
GND GND
6.3V 100k 4 5 GND C25 3V C21 C22 C23 C24
C19 R16 BYP SHDN
GND C28 4.7µF E4 0.1µF 0.1µF 0.1µF 0.1µF
0.1µF 1k 7 8 C20 C27 1µF PWR 2245 TA02
0.1µF 0.01µF GND

2245fa
 LTC2245
U U W U
APPLICATIO S I FOR ATIO
Silkscreen Top Topside

Inner Layer 2 GND

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17
LTC2245
U U W U
APPLICATIO S I FOR ATIO
Inner Layer 3 Power Bottomside

Silkscreen Bottom

2245fa

18
 LTC2245
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)

0.70 ±0.05

5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)

PACKAGE OUTLINE

0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT BOTTOM VIEW—EXPOSED PAD
0.23 TYP
0.75 ± 0.05 R = 0.115 (4 SIDES)
5.00 ± 0.10
TYP
(4 SIDES) 31 32
0.00 – 0.05
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6) 1
2

3.45 ± 0.10
(4-SIDES)

(UH) QFN 0603

0.200 REF 0.25 ± 0.05

0.50 BSC
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED) MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
2. DRAWING NOT TO SCALE 5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

2245fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19
LTC2245
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LTC2227 12-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 71.4dB SNR, 90dB SFDR, 32-Pin QFN
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LTC2229 12-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 70.6dB SNR, 90dB SFDR, 32-Pin QFN
LTC2236 10-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
LTC2237 10-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 61.8dB SNR, 85dB SFDR, 32-Pin QFN
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LTC2239 10-Bit, 80Msps, 3V ADC, Lowest Power 211mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2245 14-Bit, 10Msps, 3V ADC, Lowest Power 60mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2246 14-Bit, 25Msps, 3V ADC, Lowest Power 75mW, 74.5dB SNR, 90dB SFDR, 32-Pin QFN
LTC2247 14-Bit, 40Msps, 3V ADC, Lowest Power 120mW, 74.4dB SNR, 90dB SFDR, 32-Pin QFN
LTC2248 14-Bit, 65Msps, 3V ADC, Lowest Power 205mW, 74.3dB SNR, 90dB SFDR, 32-Pin QFN
LTC2249 14-Bit, 80Msps, 3V ADC, Lowest Power 222mW, 73dB SNR, 90dB SFDR, 32-Pin QFN
LTC2250 10-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2251 10-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 61.6dB SNR, 85dB SFDR, 32-Pin QFN
LTC2252 12-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2253 12-Bit, 125Msps, 3V ADC, Lowest Power 395mW, 70.2dB SNR, 88dB SFDR, 32-Pin QFN
LTC2254 14-Bit, 105Msps, 3V ADC, Lowest Power 320mW, 72.4dB SNR, 88dB SFDR, 32-Pin QFN
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2245fa

Linear Technology Corporation LT 0106 REV A • PRINTED IN USA

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