DATASHEET

ENSEMBLE™ FAMILY
E1 SERIES
EMBEDDED MICROCONTROLLERS

Datasheet
Alif Semiconductor www.alifsemi.com
ADTS0008 v2.5—October 2023
 E1 Series

EXTREME LOW POWER MCU: CORTEX-M55 CPU w/HELIUM VECTOR EXT, ETHOS-U55 NPU, DEEP
SECURITY, 2D GPU, MIPI-DSI, CAMERA I/F, ANALOG, 4.5MB SRAM, 1.5MB MRAM

Features
High-Efficiency MCU Core l 4KB Always-On SRAM with Battery Back-up
l Arm® Cortex®-M55 Core, up to 160 MHz, with Consuming 40 nA
Helium™ Vector Processing Extension, Double- l Up to 512KB Zero Wait-State
Precision FPU, 512KB of SRAM 0-wait State External Memory Interfaces
Tightly Coupled Memory, 32KB Instruction and l 1× Octal SPI at up to 100 MHz for up to 100
Data Caches, Armv8.1-M ISA with Arm MB/s SDR, 200 MB/s DDR, with Inline AES
TrustZone®, and 4.37 CoreMark®/MHz Decryption, XIP Mode Support, HyperBus
Performance Benchmark Protocol Support, Enabling External Memory
l High-Performance 400-MHz 64-bit AXI Bus
Expansion
Fabric l 1× SD® v4.2, eMMC™ v5.1 Channel with DMA

Efficient Micro NPU for ML/AI Acceleration Secure Enclave

l 1× Arm Ethos™-U55 Neural Processing Unit—
l Hardware-based Root-of-Trust (RoT) with
128 MAC/cycle up to 46 GOPS, On-the-Fly Unique Device ID
Weight Decompression with Dedicated DMA l Secure Key Generation and Storage, Secure

Controller Certificate Storage

l 800× Performance Uplift from Cortex-M4 for
l Factory-provisioned Private Keys

Inference Time (Source: Arm. MobileNet V2 1.0 l Crypto Accelerators—AES (up to AES-256), ECC

Model for Object Classification) (up to 384 bits), SHA (up to SHA-256), RSA (up to
l 76× Less Energy Consumed when Using Ethos-
RSA-3072), and NIST compliant TRNG
U55 Together with Cortex-M55 (Source: Arm. l Secure Debugging with Certificate

Measured on Alif Semiconductor Ensemble Authentication

Device. MobileNet V2 1.0 Model for Object
Timing Control and Measurement
Classification) l 8× Universal High-Resolution 32-bit Timers

Extreme-Low Power Technology Capable of Motor and LED Lighting Control

l Autonomous Intelligent Power Management l 1× Watchdog Timer

(aiPM™) l 2× Low-Power 32-bit Timers

l FD-SOI Low Leakage Process l 1× Real-Time Counter

l 1.6 µA Consumed in STOP Mode with LPRTC, l 4× Quadrature Encoder Counters

LPTIMER, LPCMP, BOR; 4KB SRAM Retained, Serial Communication Interfaces

Wake Pins l 1× USB 2.0 HS/FS Host/Device with DMA
l As Low as 27 µA/MHz Dynamic Consumption for
l 1× SDIO v4.1 Channel with DMA
High-Efficiency Cortex-M55 l 1× CAN FD Channel up to 10 Mbps
l Multiple Power Domains, Dynamic Power
l 1× MIPI® I3C® Channel

Gating, Voltage and Clock Scaling, DC-DC l 4× I2C Channels up to 1 Mbps Throughput

Converter l 1× Low-Power I2C Channel

l 6× UART Channels up to 2.5 Mbps (2× with RS-

On-Chip Application Memory
l High Endurance MRAM Non-Volatile Memory 485 Driver Control)
l 1.5MB l 1× Low-Power UART Channel

l SRAM l 4× SPI Channels up to 50 Mbps Throughput

l 4.25MB l 1× Low-Power SPI Channel

l Optional Data Retention of 256KB or 512KB

Consuming 3.05 μA or 6.1 μA

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Analog Interface Capabilities l CRC Calculation Accelerator with Programmable

l 2× 12-bit ADC (12 Single-Ended Inputs) Polynomials
l 1× 24-bit ADC (4 Differential Inputs) l Programmable Low Supply Voltage Detect
l Programmable Gain Instrumentation Warning (Brown-Out Detect)
Amplifier (1× to 128×) l Power-On Reset and Brown Out Reset
l 1× 12-bit DAC (1 channel) l Real-Time Clock
l 2× High-Speed Analog Comparators with 2.5-ns l JTAG/SWD Debug Interface
Response (8 Inputs) Operating Parameters
l 1× Low-Power Analog Comparator (4 Inputs) l 1.75 V to 4.2 V Primary Supply Range

l Internal Temperature Sensor l 1.08 V to 1.98 V I/O Supply Range (1.8 V I/O)

l Internal Precision Reference Voltage l 3.0 V to 4.2 V I/O Supply Range (3.3 V Flex I/O)

l 1.62 V to 4.2 V Battery Back-up Supply Range

Camera Interfaces
l -40 °C to 105 °C Industrial Ambient Temperature
l 1× Low-Power Camera Parallel Interface (LPCPI),

up to 8 bits Range
l -40 °C to 125 °C Industrial Junction Temperature
Display Interfaces Range
l Graphics LCD Controller

l 1× Display Parallel Interface (DPI), up to 24-bit

Packages
l FBGA194, 0.5 mm Pitch
RGB
l 1× 2-Lane MIPI DSI®

Graphics
l D/AVE 2D Graphics Processing Unit E1
Audio Interfaces FBGA
l 2× I2S Synchronous Stereo Audio Interfaces

l 1× Low-Power I2S Stereo Audio Interface

l 4× 2-channel Pulse Density Modulation (PDM)

Microphone Inputs (8 Mono Microphones)

l 4× 2-channel Low-Power PDM Microphone

Inputs (8 Mono Microphones)

General Input/Output
l Up to 120× 1.8-V GPIOs (Shared with

Peripherals)
l Up to 8× Selectable 1.8-V to 3.3-V GPIOs (Shared

with Peripherals)
Clock Generation
l Internal Low-Frequency RC Oscillator (32.7 kHz,

±4%)
l Internal High-Frequency RC Oscillator (Up to

76.8 MHz, ±1%)

l External High-Frequency Crystal Oscillator or

Quartz Crystal (24 MHz to 38.4 MHz)

l External Low-Power Crystal Oscillator or Quartz

Crystal (32.768 kHz)

l One User Fractional Mode PLL

System
l Global Event Mapping to Configurable Triggers

l 2× 32-Channel General DMA Controllers

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Features 2 3.12.1 NVIC Overview 32

1 Preface 6 3.12.2 IRQRTR Overview 32
2 Device Overview 7 3.12.3 EVTRTR Overview 33
2.1 Device Description 7 3.13 DMA Management 35
2.2 Device Block Diagram 8 3.13.1 DMA Architecture Overview 35
2.3 Device Features Summary and Comparison 9 3.13.2 DMA Controllers Overview 36
3 Functional Overview 11 3.14 Timers and Counters 36
3.1 Real-Time Processor 11 3.14.1 LPTIMER Overview 36
3.1.1 M55-HE Overview 11 3.14.2 UTIMER Overview 37
3.2 Neural Processing Unit (NPU) 12 3.14.3 WDT_RTSS Overview 41
3.2.1 NPU-HE Overview 12 3.14.4 LPRTC Overview 41
3.3 2D-Graphics Accelerator (GPU) 13 3.15 General-Purpose Input/Output Module 42
3.4 Secure Enclave Subsystem (SESS) 14 3.16 Communication Peripherals 45
3.4.1 Security Architecture Overview 14 3.16.1 CANFD Overview 45
3.4.2 Cryptographic Services 15 3.16.2 CRC Overview 46
3.5 Interconnect 15 3.16.3 I2C Overview 47
3.6 Power Supply Management 17 3.16.4 I2S Overview 48
3.6.1 Power Domains 17 3.16.5 I3C Overview 50
3.6.2 Voltage Supplies 20 3.16.6 PDM Overview 50
3.6.3 Power Modes 21 3.16.7 SPI Overview 52
3.6.4 Power Supply Supervisors 22 3.16.8 UART Overview 54
3.7 Reset Management Overview 23 3.16.9 USB Overview 57
3.8 Clock Generation and Control 24 3.17 External Memory Interfaces 58
3.9 Signal Multiplexing and I/O Buffer 3.17.1 Cryptographic OSPI Overview 58
Configuration 26 3.17.2 SDMMC Overview 60
3.9.1 Signal Multiplexing 26 3.18 Camera Interfaces 62
3.9.2 I/O Buffer Configuration 27 3.18.1 CPI Overview 62
3.10 Inter-Processor Communication 29 3.19 Display Interfaces 64
3.10.1 HWSEM Overview 29 3.19.1 DPI Controller Overview 64
3.10.2 MHU Overview 29 3.19.2 DSI Overview 65
3.11 Memories 30 3.20 Analog Peripherals 67
3.11.1 MRAM Overview 30 3.20.1 ADC Overview 67
3.11.2 SRAM Overview 30 3.20.2 DAC12 Overview 68
3.11.3 TCM Overview 31 3.20.3 CMP Overview 68
3.11.4 External Memory Expansion Options 31 3.20.4 LPCMP Overview 69
3.11.5 Memory Mapping 32 3.20.5 TSENS Overview 70
3.12 Interrupts and Events Management 32 3.20.6 Analog Signals 70

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3.21 Debug Infrastructure 71 5.7.4 External Memory Interfaces 127

4 Pin Assignments 73 5.7.5 Camera Interfaces 130
4.1 Pin Location per Package Type 73 5.7.6 Display Interfaces 130
4.1.1 FBGA194 Package Pin Location Assignment 73 5.7.7 Debug Interface 131
4.2 Pin Function Options by Location 75 6 Package Information 133
4.3 Pin Function Multiplexing 101 6.1 Device Marking Definition 133
5 Electrical Characteristics 105 6.2 Package Specifications 136
5.1 Absolute Maximum Ratings 105 6.2.1 FBGA194 Package Information 136
5.1.1 Maximum Supply Current 105 6.3 Storage Conditions 137
5.1.2 Maximum Performance Ratings 105 7 Ordering Information 138
5.2 Operating Conditions 106 8 Legal and Support Information 139
5.2.1 General Operating Conditions 106 8.1 Disclaimers 139
5.2.2 Device Power Modes 108 8.2 Related Documents and Tools 139
5.2.3 Power Sequence 111 8.3 Contact Information 139
5.2.4 Reference Voltage Characteristics 111 8.4 Trademarks 140
5.2.5 Electrical Sensitivity Characteristics 112 8.5 Abbreviations 140
5.3 Clock Characteristics 112 9 Revision History 158
5.3.1 External Clock Source Characteristics 112
5.3.2 Internal Clock Source Characteristics 112
5.3.3 PLL Characteristics 113
5.4 Memory Characteristics 114
5.5 I/O Buffer Characteristics 115
5.5.1 I/O Parameter Test Conditions 115
5.5.2 LVCMOS DC Specifications 115
5.5.3 Dual-Voltage (Flex) LVCMOS DC
Specifications 115
5.5.4 MIPI DSI DC Specifications 116
5.5.5 USB DC Specifications 116
5.6 Analog Peripherals Characteristics 116
5.6.1 ADC Characteristics 116
5.6.2 DAC12 Characteristics 117
5.6.3 CMP Characteristics 117
5.6.4 LPCMP Characteristics 118
5.7 Timing Characteristics 119
5.7.1 Timing Test Conditions 119
5.7.2 Timers and Counters 120
5.7.3 Communication Peripherals 122

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1 Preface
This document contains fundamental technical information for the Alif Semiconductor E1 series devices.
Device information herein includes features description, electrical and mechanical characteristics with
specifications, and ordering information.
There are references to third-party technical documents as noted within this document.
For more information on processors, peripheral functions, and programming settings, refer to the
corresponding device series-specific Hardware Reference Manual.
For managing software configurations of device resources, power, pins, clocks, DMA requests, interrupts, and
various other additional settings, refer to the Alif Conductor tool.

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2 Device Overview

2.1 Device Description

The families of fusion processors and microcontrollers (MCUs) from Alif Semiconductor create a scalable and
compatible continuum of highly integrated embedded processor devices for use in low-end to high-end
intelligent IoT end-point applications. Architected for power efficiency and long battery life, these devices
deliver high computation and ML/AI capability, multi-layered security, computer vision, and highly interactive
human-machine interface.
Individual device selections within a family of devices scale up starting with single-core MCUs, dual-core
MCUs, triple- core MCU/MPU fusion processors, and quad- core MCU/MPU fusion processors to match
specific applications. Across all devices are common peripherals, common power management schemes, and
a common interconnection fabric making it easy to re-use software and hardware over many varied projects.
This document covers the single-core E1 embedded microcontrollers series from the Ensemble™ family.
Power efficiency—In addition to the use of FD-SOI silicon technology, aiPM provides fine granular control
over portions of the device, resulting in extreme power conservation that consumes only what is needed,
when its needed, at any given instant based on use case.
Computation and ML/AI — Single- core design with one Arm Cortex- M55 Real- Time core, optimized for
extreme low power operation. Machine Learning and AI tasks are accelerated by single Arm Ethos-U55
neural processing unit generating as much as 46 GOPS. E1 devices can operate with an RTOS, while using only
the on-chip memory resources. Additional RAM or Flash memory may be accessed externally through a high-
speed Octal SPI interface supporting XIP mode and HyperBus protocol. An in-line AES decryption module in
the Octal SPI interface ensures the confidentiality of the data and/or code stored in the external memory
devices.
Connectivity—E1 devices support many wired interfaces including USB, SDIO, CANFD, I3C, I2C, and more.
Security—An isolated Secure Enclave manages the entire life cycle of the end application from manufacture,
to deployment, to secure Firmware Over-The-Air updates, and to retirement. A unique Root-of-Trust existing
in the enclave enables a trusted on- chip platform for key generation, secure storage, secure boot,
cryptographic acceleration, and more. The Secure Enclave also enables certificate-based secure debugging.
Computer Vision—Integrated camera interface enables connection of low-power image sensors for AI image
classification using the Arm Ethos- U55 NPU. Biometric ID, face detection, object classification, barcode
reading, and other vision applications can execute while consuming very little energy.
Sensor Fusion and Voice Processing—The Arm Ethos-U55 NPU and the Helium vector extension on the
Cortex-M55 CPU can be utilized to enable extremely fast and energy efficient processing of digitized sensor
inputs from multiple sources. Helium accelerates DSP functions and Ethos brings ML-enhanced processing to
portable applications measuring human metrics, mechanical vibrations, sounds, as well as speech processing
such as key word spotting and interpreting voice commands through microphone inputs via LPPDM and LPI2S
interfaces.
Color Display—Integrated color display interfaces, including MIPI DSI, can drive a wide range of display
panels with vivid graphics supported by the on-chip 2D graphics processing unit for attractive user interfaces.

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2.2 Device Block Diagram

Figure 2-1 presents a simplified diagram of the operating regions and main internal components of the Alif Semiconductor E1 Series of devices.
Figure 2-1 Device Block Diagram

E1 Series
High-Speed Display Secure Debug High-Efficiency
Communica�on and Enclave Real-Time Processor Subsystem
Memory Expansion
LPSPI LPI2C Camera
JTAG Ba�ery Backed
USB CDC Debug LPCPI
LPUART
Authen�ca�on SWD LPGPIO
DPI NVIC DMA Audio
SDMMC and
SDIO MIPI DSI System and MHU WDT LPI2S LPPDM LPTIMER
CoreSight
Firewall Control Mul�core Cortex-M55 EVTRTR LPCMP
Graphics
+ Helium AI/ML
D/AVE 2D LPRTC
Security (M55-HE)
(GPU2D) Unit Ethos-U55 LFXO LFRC
TCM (NPU-HE)
(SRAM4, SRAM5)
POR BOD
CPU and NPU
Instr Data
SERAM Cache Cache Memory Backup SRAM

High-Performance Interconnect Fabric

High-Speed Non-Vola�le XIP and/or Data Serial System

Cache Timer/Counter Communica�on Analog Reset Control IRQRTR
Bulk
SRAM0 AES Decoder UTIMER I3C ADC12
Power Control Clock Control
MRAM QEC I2C ADC24
Octal SPI
Data Transfer SPI DAC12 Clock Genera�on Configura�on
DMA
UART CMP HFXO
EVTRTR I/O Pin
CANFD TSENS HFRC
Audio Mux
I2S VREF PLL
I/O
PDM GPIO
External Memory
Shared Internal Memory Expansion Shared Peripherals System Control

intro-001
Color Key: High-Performance Region High-Efficiency Region Always-On Region

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2.3 Device Features Summary and Comparison

Table 2-1 presents device features supported and package options.
Table 2-1 Device Features and Peripherals
Feature Definition
Package options FBGA194
Processors and Accelerators
High-Efficiency Arm Cortex-M55 M55-HE Up to 160 MHz
Arm Ethos-U55 Neural Processing Units NPU-HE Up to 46 GOPS
D/AVE 2D Graphics Processing Unit GPU2D Yes
Security Subsystem
Secure Enclave SE Yes
Memory
On-Chip Non-volatile Application Memory MRAM 1.5MB
On-Chip Application SRAM SRAM 4.25MB
Timers and Counters
Low-Power Timer LPTIMER 2 × 32-bit
Universal Timer UTIMER 8 × 32-bit
Watchdog Timer WDT 1
Quadrature Encoder Counter QEC 4
Low-Power Real-Time Counter LPRTC 1
General Input and Output
120 (1.8 V)
General Purpose I/O pins GPIO
Up to 8 (1.8 V to 3.3 V)
Communication Peripherals
Controller Area Network CANFD 1
I2C 4
Inter-Integrated Circuit
LPI2C 1
I2S 2
Inter-IC Sound
LPI2S 1
MIPI Improved Inter-Integrated Circuit I3C 1
PDM 4× 2-channel
Pulse Density Modulation
LPPDM 4× 2-channel
SPI 4
Serial Peripheral Interface
LPSPI 1
UART 6
Universal Asynchronous Receiver/Transmitter
LPUART 1
Universal Serial Bus USB USB 2.0 HS/FS Host/Device
Secure Digital Input Output SDIO SDIO v4.1 (1)

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Feature Definition
External Memory Interfaces
Octal SPI OSPI 1
Secure Digital Multimedia Card SDMMC SD v4.2, eMMC v5.1 (1)
Camera Subsystem
Camera Parallel Interface LPCPI Up to 8-bit
Display Subsystem
Graphics LCD Controller CDC 1
Display Parallel Interface DPI Up to 24-bit RGB
MIPI Display Serial Interface DSI 2-Lane
Analog Peripherals
2 × 12-bit
ADC12
(Up to 12 inputs)
Analog-to-Digital Converter
1 × 24-bit
ADC24
(Up to 4 differential inputs)
Digital-to-Analog Converter DAC12 1 × 12-bit
2
High-Speed Comparator CMP
(8 inputs)
1
Low Power Comparator LPCMP
(4 inputs)
Temperature Sensor TSENS Yes
1. SDIO, SD, and eMMC are functions of memory card controller. There is only one memory card controller in the device.
2. For devices supporting optional features, refer to Section 7 Ordering Information.

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3 Functional Overview

3.1 Real-Time Processor

3.1.1 M55-HE Overview

The Cortex-M55 High-Efficiency (M55-HE) processor implements the Armv8.1-M Mainline architecture that
includes support for the M-profile Vector Extension (MVE), also known as Helium™. The M55-HE achieves
high compute efficiency across scalar and vector operations, operating up to 160 MHz.
The M55-HE memories are based on ultra-low leakage memory cells which results in low power consumption
in sleep mode. The choice of TCM retention allows application-optimized tradeoff between current leakage
during sleep and fast wake-up time.
The device includes a single M55-HE processor that resides in the High-Efficiency Real-Time Subsystem (RTSS-
HE). The RTSS-HE also includes various memories and peripherals.
The M55-HE processor supports the following main features:
n CPU revision: r1p0
n CPU core logic that includes:
l In-order, four-stage integer pipeline with early completion of common arithmetic instructions

l Instruction Fetch Unit (IFU) with 32-bit instruction fetch data width

l Data Processing Unit (DPU) with 64-bit load/store data width

l Support for up to 2 × 32-bit vector load operations in parallel

n Extension Processing Unit (EPU) that works closely with the CPU core to support:
l Scalar floating-point (VFPv5) operations: half-, single-, and double-precision

l Vectored operations through MVE (Helium)

o Integer
o 128-bit SIMD floating-point: half- and single-precision

n Double-Precision FPU
n Support for other Extensions such as:
l Armv8.1-M Main Extension (16-bit and 32-bit Thumb instruction set)

l Armv8-M Security Extension (TrustZone)

l DSP Extension

l DSP Debug Extension

l Reliability, Availability, and Serviceability (RAS) Extension

l Unprivileged Debug Extension (UDE)

n Memory architecture that includes:

l Memory Authentication Unit (MAU) for memory access control:

o Secure Memory Protection Unit (MPU) supporting 16 regions

o Non-secure MPU supporting 16 regions
o Security Attribution Unit (SAU) supporting 8 regions
o TCM Gate Units (TGU):
o Instruction TGU (ITGU) protecting 16 address regions, each 16KB in size
o Data TGU (DTGU) protecting 16 address regions, each 16KB in size

l Memory system:

o 32KB L1 Instruction Cache (IRAM)

o 32KB L1 Data Cache (DRAM)
o 256KB Instruction TCM (ITCM); access to ITCM is over a single interface

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o 256KB Data TCM (DTCM); access to DTCM is over four interfaces

o Master AXI (M-AXI) interface for high latency memory or peripheral access
n Interrupt control:
l Nested Vectored Interrupt Controller (NVIC) for low-latency interrupt processing:

o Supports 480 external interrupts, with 256 priority levels per interrupt

l Wakeup interrupt control to allow the processor to enter low-power state:

o Internal Wakeup Interrupt Controller (IWIC)

o External Wakeup Interrupt Controller (EWIC)

n Secure and non-secure Vector Table Offset Register (VTOR)

n Debug and trace support:
l Full set debug:

o Breakpoint Unit (BPU) with 8 comparators

o Data Watchpoint and Trace (DWT) unit with 4 comparators and Performance Monitoring Unit

(PMU)
l Trace infrastructure

l CoreSight-compliant Debug Access Port (DAP):

o Supports dynamic switching—Serial Wire / JTAG Debug Port (SWJ-DP)

3.2 Neural Processing Unit (NPU)

The Arm Ethos-U55 Neural Processing Unit (NPU) is a Machine Learning (ML) coprocessor that improves the
inference performance of neural networks. The Ethos-U55 combined with the Artificial Intelligence (AI)
capable Cortex-M55 processor provides up to 800× uplift in ML performance over Cortex-M4F based
systems.
The NPU targets 8-bit and 16-bit integer quantized Convolutional Neural Networks (CNN) and Recurrent
Neural Networks (RNN). The NPU includes a Direct Memory Access (DMA) controller that can read and write
to external memory. The DMA controller reads the neural network description and transfers the input and
output feature maps.
The device includes up to one NPU coprocessor in the device High-Efficiency Region—NPU-HE.

3.2.1 NPU-HE Overview

The NPU-HE supports the following main features:
n Up to 46 GOPS performance using up to 128 MAC/cycle
n Network support: CNN, RNN
n On-the-fly weight decompression (8-bit weights)
n 8-bit and 16-bit activations (input data)
n Activation functions:
l ReLU, ReLU1, ReLU6, and Leaky ReLU (LReLU)

l Tanh

l Sigmoid

l Configurable Look-Up Table (LUT)

l None or bypass

n Element-wise operations:
l Element-wise ADD and SUB

l Element-wise Multiplication (MUL)

l Element-wise Min and Max

l Element-wise ABS

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l Element-wise Shift Left (SHL) and Shift Right (SHR)

l Element-wise Count-Leading Zero (CLZ)
n 24KB of internal shared memory (SHRAM)
n Integrated DMA controller
n Layer-by-layer visibility with Performance Monitoring Units (PMUs)

3.3 2D-Graphics Accelerator (GPU)

The D/AVE 2D Graphics Processing Unit (GPU2D) provides hardware acceleration for sophisticated vector-
based graphical applications.
The GPU2D supports the following main features:
n Subpixel accurate rendering
n Resolutions of up to 2048 × 2048 pixels
n Operating clock frequency at 400 MHz. GPU render pipeline produces one pixel per clock cycle.
n 16 blending modes
n Patterns and gradients with alpha channel on all primitives
n Render to texture
n Textures up to 2048 × 1024 pixels
n Texture blending
n Bilinear filtering
n Graphical primitives available:
l Block Image Transfers (BLIT)—direct and stretch

l Box

l Circle—filled or empty (ring)

l Convex polygon

l Line

o Supported caps:
o Butt
o Round
o Square
o Supported line joins:
o Bevel
o Miter
o Round
o Supporting different start and end widths

l Quad

l Triangle

l Triangle fan

l Triangle list

l Triangle stripe

l Wedge-filled or empty

n Graphical primitives attributes:

l Anti-aliasing

l Blend modes

l Color

l Edge blur

l Linear alpha gradient

l Pattern

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l Texture
U/V clamp, repeat support
o
o No-, linear-, bilinear-filtering support
o Run-Length Encoding (RLE)

n Supported color coding formats:

l Input

o ARGB8888, RGB565, ARGB4444, ARGB1555, ALPHA8, AI44, RGBA8888, RGBA4444, RGBA5551, I8,

I4, I2, I1, ALPHA4, ALPHA2, ALPHA1

l Output

o ARGB8888, RGB565, ARGB4444, ALPHA8, RGBA8888, RGBA4444

3.4 Secure Enclave Subsystem (SESS)

3.4.1 Security Architecture Overview

The device contains an advanced Secure Enclave (SE) that is responsible for managing the device security.
The SE is an isolated subsystem with its own dedicated resources. The isolated subsystem reduces the attack
surface for the SE along with the minimal software interfaces that are restricted to the Inter-Process
Communication (IPC) Message Handling Units (MHUs).
The SE boots first on Power-On-Reset (cold start). It runs the First Stage bootloader code from a private,
immutable ROM. The SE performs certificate-based integrity and authenticity check on the Second Stage
bootloader. It is loaded to the SE SRAM (SERAM) and the flow of execution is transferred to it. This
mechanism enables the secure update of the Second Stage bootloader on the field. The boot process
continues with processing of the application-specific device configuration. The SE applies configuration
settings that partition the system resources (memory and peripherals) between the different application
cores. Next, the SE bootloader performs a signature verification of the installed application binaries. If
needed, it copies the specified binaries to their designated SRAM regions. Finally, a designated core is
released from Reset to run its application. This completes the secure boot procedure. The remaining cores
can be booted by the SE in response to a service request.
The SE is also involved in the process of waking up from STOP mode. When a wakeup event is triggered, the
SE CPU boots first. It checks if the SERAM is retained and continues the execution flow there. The SERAM
code maps the wakeup event to an application core and promptly boots it. If the SERAM is not retained, then
the SE validates the wakeup source and boots the RTSS-HE core. The retention of SERAM in the Secure
Enclave or the SRAM (M55-HE TCM) in the RTSS-HE offers trade-off options between the leakage current and
the wakeup time of the device.
The SE provides traditional security functions such as:
n Secure boot
n Secure device configuration
n HW Root-of-Trust (RoT)
n Key management
n Signature validation
n Crypto operations
n Life cycle management
The Supervisor is responsible to:
n Manage the OEM provisioning process and the Life Cycle State (LCS)
n Apply the system configuration settings to the security firewalls and security HW in the system
n Securely boot the Real-time core (M55-HE) as defined by the user's configuration file

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3.4.2 Cryptographic Services

The Secure Enclave (SE) supports a variety of Runtime Security and Cryptographic services that enable the
OEM’s application code to control security functions for the device and request cryptographic operations.
These runtime services make use of IPC.
The Runtime Cryptographic services include the ability of the OEM application code to make requests for
standard and device-specific cryptographic operations like:
n Creating keys
n Using the keys to encrypt or decrypt
n Return the device certificate
n Authenticate the device
n Validate the signature of images against the provisioned keys in the device
n Secure boot a core
n Write to MRAM memory
n Process Alif Semiconductor’s firmware updates

3.5 Interconnect
The system interconnect provides the means of connecting bus masters (CPU cores, DMA controllers) to
memory modules and peripherals. It is based on the Arm AMBA bus architecture utilizing a mix of AXI, AHB
and APB buses.
The backbone of the device interconnect is based on an AXI4 bus, featuring multiple master and slave ports.
The processing subsystems have their own local buses connected as masters to the main AXI bus. The
memory blocks and the peripheral subsystems connect as slaves to the main AXI bus. Some peripherals (such
as SDMMC and USB) also can act as bus masters and connect via both master and slave ports. The master
ports serve their DMA controllers to transfer data without CPU intervention, while the slave ports are
intended for accessing their registers.
Each master and slave port connects to the main AXI bus through Firewall Components (FC). They enforce
run-time configurable access rights policy and address translation. Transaction gating is based on master ID,
transaction type (instruction or data fetch) and TrustZone-defined secure world context. The FC configuration
settings are set by the SE during the secure boot process. The applications specify their desired access paths
and address regions in a dedicated region of the on-chip Non-Volatile Memory (NVM), which is MRAM. The
SE applies these settings during the device boot process.
The device interconnect supports the following main features:
n High-performance AXI4 bus protocol
n 64-bit wide read and write data paths
n 400 MHz bus clock frequency
n Burst-based transactions for optimizing bandwidth efficiency
n TrustZone aware
n Firewall controller and 14 firewall components to enforce secure policy constraining the bus master’s
access to the device resources
n Firewall security monitoring function raising an interrupt when unauthorized access is attempted
Figure 3-1 provides a high-level overview of the system interconnect implementation in the device.

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Figure 3-1 Interconnect Overview

Main AXI bus Subsystem 64-bit Subsystem 32-bit Subsystem 32-bit

64-bit 400 MHz AXI bus AHB bus APB bus

Debug SRAM0

Secure MRAM AES

MHU OSPI
Enclave (NVM) Decoder

DPI,
MIPI DSI GPU2D
CDC
SPI

UTIMER, DMA0,
SDMMC USB
QEC EVTRTR0

High-Efficiency Real-Time Processor System

HWSEM, UART, I3C, ADC, CMP,
DMA2, I2S, PDM
M55-HE NPU-HE LPCPI GPIO I2C CANFD DAC
EVTRTR2

Interconnect-001
LPGPIO, LPTIMER, LPUART, LPI2S, PINMUX, Clock Power Firewall
MHU IRQRTR
LPCMP LPRTC LPSPI, LPI2C LPPDM Reset Control Control Control

NOTE

For managing software configurations of device resources, power, pins, clocks, DMA requests,
interrupts, and various other additional settings, refer to the Alif Conductor tool.

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3.6 Power Supply Management

The device has three operating regions that encapsulate top-level functions from a power consumption
perspective:
n Always-On (AON) Region—a group of rudimentary functions that are always powered when a battery or
other constant power source is connected to the VDD_BATT pin.
n High-Efficiency (HE) Region—a group of compute, sensing, AI functions designed to operate at the
highest efficiency. Many tasks can be performed in this region to conserve power and/or extend battery
life before waking up the HP Region.
n High-Performance (HP) Region—a group of compute, AI, Human-Machine Interface (HMI), and high-
speed connectivity functions designed to operate at maximum performance. These functions are
invoked only as required to conserve energy.
The device block diagram (see Figure 2-1) illustrates these three operating regions and the functions
available within each of the regions.
A smart power management scheme named aiPM (autonomous intelligent Power Management) utilizes a
hierarchy of multiple power domains, multiple internal voltage supplies, and multiple power modes to power
on, in fine granularity, portions of the device only when they are needed based on use case, and off when not
needed. Powering on and off portions of the device occurs automatically in hardware as required, but the
power management policies are configured by software.
Multiple power domains—There are six independent power domains in the device, each one with a
dedicated power controller that is coordinated by digital logic and software configuration for automatic
transitions—from power-up to full GO mode, and all modes in between. This scheme achieves optimum
power efficiency based on the dynamic power demand of the device at any given moment in time.
Multiple voltage supplies—There are internal device voltage supplies consisting of a series of Low Drop-Out
(LDO) regulators and a dual-mode DC-to-DC buck converter (DC-DC) to generate 0.55 V, 0.8 V, and 1.8 V
voltage rails that are automatically switched on and off as required for optimum performance and efficiency.
Multiple power modes—Below are top-level device modes listed from highest to lowest power
consumption:
n GO—any or all processing cores operate up to their max frequency
n READY—all processing cores are clock-gated off, but peripherals can run
n IDLE—all processing cores are powered off, but some peripherals can run
n STANDBY—all processing cores are powered off, but a few low-power peripherals can run
n STOP—entire device is powered off except the AON Region where rudimentary low-power peripherals
and wake-up sources are active, as well as optional battery-backed SRAM blocks

3.6.1 Power Domains

The device Power Domains (PD) are managed by a Power Sequence Controller (PSC) and several Power Policy
Units (PPU). The PSC is a state machine that monitors a fixed set of inputs and automatically acts to turn
power on or off in power domains at the lower levels. PPUs take inputs from the PSC, inputs from the device
condition status, and inputs from configuration settings from the application code, then PPUs act
autonomously to turn on or off power to the domains, and PPUs also control domain clock sources. Thus, the
operational processes of the PSC and PPUs automatically and dynamically achieve the best power
consumption based on instantaneous power demand.
Figure 3-2 illustrates the power domains, control hierarchy, transition possibilities, and relevance to the
three operating regions of the device. The power-up sequence of the shown regions and domains is:

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1. If VDD_BATT is connected to a battery, the PD-0 domain and the AON Region are Always-On.
2. The PD-2 domain is first to power up.
3. The next order of powering up the domains depends on whether the device executes an initial boot
(cold), or a wake up (warm).
PDs in each of the three device regions are defined as follows:
n AON Region
l PD-0, AON power and control

n HE Region
l PD-2, High Efficiency Region power and control

l PD-3, Real Time Subsystem-High Efficiency (RTSS-HE)

n HP Region
l PD-5, Secure Enclave Subsystem (SESS)

l PD-6, Shared Peripherals / Shared System Resources (SYST)

l PD-8, Debug Subsystem (DBSS)

Figure 3-2 Device Power Domain Hierarchy and Transitions

High-Performance Region

USB PHY Analog MIPI PHY

PD-5 PD-6 PD-8
SESS SYST DBSS

High-Efficiency Region

PD-3 Enable Enable

RTSS-HE

PPU-3 PPU-5 PPU-6

PSC-STBY
PD-2 (HE Region Power and Control)

PD-3 PD-5
M55-HE
SE SRAM
TCM
Enable

AON Region Reten�on Reten�on

Enable Enable

PSC-STOP
PD-0 (AON Region Power and Control)
Reten�on
Enable

Backup
PWR-001

SRAM

For more details about PDs power-up and transitions, see the device series-specific Hardware Reference
Manual.
Table 3-1 illustrates which specific resources are available within each of the power domains, and how the
power domains are related to the three operational regions.

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Table 3-1 Device Resources per Power Domain

AON Region High-Efficiency Region High-Performance Region

PD-0 PD-2 PD-5 PD-6 PD-8

PD-3
PSC-STOP PPU-3 M55-HE SE CPU GPIO SWD
LPTIMER PPU-5 M55-HE L1 Cache SE SRAM (SERAM) MRAM
LPCMP PPU-6 M55-HE TCM (SRAM4, SRAM5) Security Unit Bulk SRAM (SRAM0)
LPGPIO PINMUX NPU-HE System Controls DMA0
LPRTC LPUART LPCPI SEUART USB
BOD LPI2C LPPDM CANFD
POR EWIC LPI2S GPU2D
VTOR IRQRTR LPSPI DSI
LFRC JTAG DMA2 DPI/CDC
LFXO HFRC MHU OSPI
VBAT HFXO WDT_HE UTIMER
ANA PLL EVTRTR2 QEC
STOP_MODE PPU-HE I3C
CGU I2C
Optional SRAM Retention: AON SPI
• Backup SRAM I2S
• M55-HE TCM (SRAM4, SRAM5) PDM
• SE SRAM (SERAM) UART
ADC12
ADC24
CMP
TSENS
VREF
HWSEM
SDMMC/SDIO
EVTRTR0
AXI Bus

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3.6.2 Voltage Supplies

The device power domains are supplied with voltages from several internal supply sources. Power domains
that feature SRAM retention have dual voltage supplies.
The device voltage supply and distribution system is architected to:
n Implement the aiPM strategy to dynamically power on only what is needed within the most optimum
region of the device
n Minimize leakage current in STOP and STANDBY modes
n Rapidly exit low power modes upon a wake-up event
n Minimize dynamic current consumption in GO mode
Figure 3-3 illustrates the voltage distribution inside the device including highly efficient LDO regulators and a
DC-DC buck converter. Very few external power sources are required because of the power management
capability within the device to generate multiple voltage rails and to correctly sequence the supplies during
power up and power down.
Figure 3-3 Device Voltage Distribution

PMU
LDO-0 VAON_RET
AON SRAM Retain
Band Gap PD-0, AON Power
Backup SRAM
LFXO LFRC and Control
VDD_BATT
LDO-1 VAON
Power and Control
Func�ons
PD-2, HE Region Power and Control Digital I/O
LDO-2 VTCM_RET
VDD_IO_1V8
TCM/SRAM Retain
1.8-V I/O Pin 1.8-V IOs
Drive
M55-HE TCM VDD_IO_FLEX
Flex I/O Pin 1.8/3.3-V IOs
HFXO PLL PD-3 Drive
RTSS-HE

DC-DC (buck) VREG_CORE_0V8

VDD_BUCK Low and High VREG_CORE_0V8
Power Modes

PD-5 PD-6 PD-8 VREG_DIG_1V8

SESS SYST DBSS
LDO-3
Secure Enclave Bulk SRAM0
SRAM (no retain)

VDD_MAIN Band Gap HFRC MRAM

Analog
VDD_USB_3V3
LDO-4 VREG_DIG_1V8
MRAM USB PHY USB bus

LDO-5 VDD_ANA
Analog
Analog Peripherals VREF_P
VSS
LDO-6 VMIPI_PHY
MIPI PHY MIPI DSI
MIPI PHY
PWR-002

VREG_MIPI_1V8

For more information about power supply voltage ranges and general operating conditions, see Section 5.2.1
General Operating Conditions.
Table 3-2 presents power supply signals and provides descriptions to their functions.

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Table 3-2 Power Supply Signal Descriptions

Signal Name Pin Name Type(1) Description
VDD_MAIN VDD_MAIN PWR Main power supply
VDD_BATT VDD_BATT PWR Battery-backed domain power input
VDD_BUCK VDD_BUCK PWR Internal DC-DC converter power input
VDD_USB_3V3 VDD_USB_3V3 PWR USB power input
VDD_IO_FLEX VDD_IO_FLEX PWR GPIO flex pads (1.8 V(2) - 3.3 V) power input
VDD_IO_1V8 VDD_IO_1V8 PWR GPIO standard pads (1.8 V) power input
VREG_DIG_1V8 VREG_DIG_1V8 PWR Internal 1.8 V regulator output
VREG_AUX_1V8 VREG_AUX_1V8 PWR Auxiliary 1.8 V regulator output
MIPI PHY power input
VDD_MIPI_1V8 VDD_MIPI_1V8 PWR
(connect to VREG_MIPI_1V8)
VREG_MIPI_1V8 VREG_MIPI_1V8 PWR Internal MIPI PHY 1.8 V power output
Main digital supply
VDD_CORE_0V8 VDD_CORE_0V8 PWR
(connect to VREG_CORE_0V8)
MIPI PHY 0.8 V supply decoupling.
VREG_MIPI_0V8 VREG_MIPI_0V8 PWR
Connect to decoupling capacitors only.
VREG_CORE_0V8 VREG_CORE_0V8 PWR Internal DC-DC converter power output
Digital power supply to analog blocks
VDD_SX_0V8 VDD_SX_0V8 PWR
(connect to VREG_CORE_0V8)
Digital power supply to PLL and Band Gaps
VDD_PLL_0V8 VDD_PLL_0V8 PWR
(connect to VREG_CORE_0V8)
VREG_AON VREG_AON (3) PWR Output of internal always-on LDO
VREG_LP_1V8 VREG_LP_1V8 PWR Output of internal low-power LDO
VREF_P VREF_P A External positive voltage reference for ADC
VSW VSW PWR DC-DC converter switching output (connect to inductor)
VSS_BUCK VSS_BUCK GND DC-DC converter ground
VSS_ANA VSS_ANA GND Analog ground
VSS VSS GND Digital ground
1. Please refer to the Application Note regarding PCB Layout Guidance covering decoupling methods for all power pins on Ensemble
devices.
2. VDD_IO_FLEX should be connected to VDD_IO_1V8 when 1.8-V mode is used.
3. This pin must always be connected to ground through a 1-µF capacitor in series with a 4.7 kΩ resistor to ground.

For more information about power supply voltage ranges and general operating conditions, see Section 5.2.1
General Operating Conditions.

3.6.3 Power Modes

Using aiPM, this device provides significant flexibility to balance power, performance, and wake-up time per
application use case. The device-level power modes described in Table 3-4 make use of the power domains
and the voltage supplies, described in Section 5.2.1 General Operating Conditions, to achieve this balance.
Within each power mode the clock speed and clock gating can be fine-tuned for each core and peripheral to
reduce power consumption.

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Table 3-3 Individual CPU States Summary

CPU State Description
RUN When a CPU core is running and executing code.
SLEEP When a CPU core is clock gated and can quickly resume.
OFF(1) When a CPU core is powered down.
1. If RTSS-HE is powered down, then the LPCPI, LPI2S, LPPDM, and LPSPI in the same subsystem are also powered down.

Table 3-4 Device Power Mode Summary

Device Power Wake-Up
Description
Mode Peripherals
GO RTSS-HE is in RUN state. See Table 3-3. All
READY RTSS-HE is in SLEEP state. See Table 3-3. All
IDLE RTSS-HE is in OFF state. See Table 3-3. All(1)
LPUART, LPI2C, plus
STANDBY RTSS-HE is powered down. STOP mode
peripherals
RTSS-HE and shared resources in the HE Regions are powered down. Few LPTIMER, LPCMP,
STOP
peripherals remain on with extremely low leakage. LPRTC, and LPGPIO
1. If RTSS-HE is powered down, then the LPCPI, LPI2S, LPPDM, and LPSPI in the same subsystem are also powered down.

For more details about specific power consumption and wake-up times per power mode, see Section 5.2.2
Device Power Modes.

3.6.4 Power Supply Supervisors

The device has integrated supervisory circuits for Brown-Out Reset (BOR), Brown-Out Detect (BOD), and
Power-On-Reset (POR).
There is one POR circuit, VBAT_POR, which monitors the VDD_BATT (AON Region) and keeps the entire
device in reset if VDD_BATT is below the threshold.
The BOD circuit monitors the VDD_MAIN power supply and generates interrupts when the voltage falls
below a programmable threshold. The BOR circuit monitors the VDD_MAIN power supply and causes an
immediate reset to the main SoC when the voltage falls below a programmable threshold.
The POR circuit is described briefly in Section 3.7 Reset Management Overview.
Table 3-5 summarizes the power supply supervisory functions.
Table 3-5 Power Supply Supervisory Functions
Power Supply Supervisor Type Supervisory Function
VDD_BATT POR Fixed threshold, affects the whole device.
Programmable threshold, reset affects PD-2 and
VDD_MAIN BOR
above.
Programmable threshold, triggers interrupts to
VDD_MAIN BOD
the M55-HE and SE, and a request to DMA.

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3.7 Reset Management Overview

A reset brings the entire device (cold reset) or part of the device (warm reset) to a known good state.
The reset subsystem of the device is based on a Reset Controller (RSTC). The RSTC handles top-level reset
conditions—VBAT_POR and software reset requests.
Figure 3-4 shows the main reset sources in the device.
Figure 3-4 Top-Level Reset Diagram

Device

BOR

Threshold

VBAT_POR SoC POR

Secure SE Resets
Enclave

Debug +3.3 V
Main SoC
VDD_BATT
VBAT Domain VDD_MAIN
(PD-0)
3.0 V

RST-001
POR_N NSRST

Table 3-6 lists the main reset sources along with their types and functions.
Table 3-6 Device Main Reset Sources
Reset Source Hardware/Software Description
System cold Reset pin.
Asserting this pin is equivalent to turning the device power
POR_N pin
HW off. After deasserting the signal, the device completes a full
(active-low)
power on cycle, which is equivalent to a cold start.
No logic or memory retains its state.
System warm Reset pin.
NSRST pin Typically, an external debugger asserts this reset pin.
HW
(active-low) It resets all logic in the device except for PD-0 peripherals,
debug logic, and the JTAG interface.
Fundamental POR.
VBAT_POR keeps the entire device in reset during a power-
VBAT_POR monitor HW
on ramp-up until VDD_BATT reaches the operational
threshold.
Brown-out reset.
BOR monitor HW and SW BOR monitor asserts a reset to the main SoC when VDD_
MAIN falls below a programmable threshold.

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Reset Source Hardware/Software Description

Warm reset by Secure Enclave.
Secure Enclave Reset SW Initializes all logic except for PD-0, the debug logic, and the
JTAG interface.
High-efficiency subsystem (RTSS-HE) reset.
SW_HE_RST SW Warm reset by Secure Enclave.
RTSS-HE reset reasons logged to RTSS_HE_RESET register.

Table 3-7 presents Reset signals and provides descriptions to their functions.
Table 3-7 Reset Signal Descriptions
Signal Name Pin Name Type Description
NSRST NSRST I JTAG reset (system reset) active low
POR_N POR_N I Power-On-Reset (cold reset) active low

3.8 Clock Generation and Control

The device clocking scheme includes several clock domains, PLL, clock dividers, clock multiplexers, and four
oscillators. The PLL has two clock outputs.
The device clock sources are as follows:
n Low-Frequency Resistor-Capacitor (LFRC) oscillator—a low-power, internal RC oscillator powered by
VDD_BATT. This oscillator is used during the power-up sequence, with a typical clock frequency accuracy
of 32.7 kHz ±4%.
n Low-Frequency crystal Oscillator (LFXO)—a low-power oscillator that can be used with a high-accuracy
32.768 kHz external crystal. This oscillator is powered by VDD_BATT. It is enabled at power-up and is the
typical clock source for LPRTC. The LFXO oscillator input may optionally be configured in bypass mode
for connection to an external 32.768 kHz clock source.
n High-Frequency Resistor-Capacitor (HFRC) oscillator—a low-power internal RC oscillator that is able to
generate frequencies of up to 76.8 MHz. When the LFXO clock source is available, the HFRC oscillator
can be trimmed to reach an accuracy of ±1% or better. The HFRC oscillator is available in all power
modes except for STOP mode. This oscillator can be used during a power-up sequence for rapid
initialization and fast start-up.
n High-Frequency crystal Oscillator (HFXO)—a power-optimized oscillator that can be used with an
external crystal with a frequency between 24 MHz and 38.4 MHz. This oscillator is enabled by software
after initial device configuration and is the source clock for the PLL. The HFXO oscillator input may
optionally be configured in bypass mode for connection to an external high-speed clock
source/oscillator.
n Phase-Locked Loop (PLL)—a power-optimized, fast-locking clock multiplier with fractional mode. It has
two clock outputs used to supply most of the device subsystems, modules, and interconnects.
Figure 3-5 provides a high-level overview of the clocking scheme implementation in the device.

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Figure 3-5 Device Clocking Scheme Overview

Device
0 Hz
SYST_ACLK
SYSPLL_CLK (Bulk SRAM, NIC-400 AXI bus, peripherals)
MUX 1/1 MUX
400 MHz
SYST_HCLK
HFXO_OUT (AHB buses, peripherals)
1/2
SYST_PCLK
(APB buses, peripherals)
1/4
HFRC/X

HFXO/Z MUX SYST_REFCLK

MUX

38.4 MHz
19.2 MHz
9.6 MHz 100 MHz 100M_CLK
1/8
4.8 MHz
PLL_CLK1
2.4 MHz
1.2 MHz
PLL
600 kHz
38.4 MHz

300 kHz PLL_CLK3

1/2
150 kHz
37.5 kHz
HFXO_P/EXT CLK
HFXO 1/Z HFOSC_CLK
HFXO_N MUX
HFRC 1/X 1/2
76.8 MHz
38.4 MHz
19.2 MHz
9.6 MHz
4.8 MHz
2.4 MHz
1.2 MHz
600 kHz
300 kHz 480 MHz 60 MHz
1/8
75 kHz
80 MHz
1/6
MUX RTSS_HE_CLK
120 MHz (M55-HE, U55-HE)
1/4 MUX
x2 160 MHz
1/3

160M_CLK

HFRC/X

HFRC/X/2
1/2
HFXO/Z x2 MUX

HFXO/Z

20 MHz USB_CLK
1/24

128K_CLK 10M_CLK
1/48
76M8_CLK
32.7 kHz
LFRC S32K_CLK
LFXO_P/EXT CLK MUX
32.768 kHz
LFXO
LFXO_N

Note: The programmable dividers values shown are a�er reset.

CLK-001

Color Key: Fixed Programmable

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NOTE

For managing software configurations of device resources, power, pins, clocks, DMA requests,
interrupts, and various other additional settings, refer to the Alif Conductor tool.

Table 3-8 presents clock interface signals and provides descriptions to their functions.
Table 3-8 Clock Signal Descriptions
Signal Name Pin Name Type Description
HFXO_OUT_A P3_6 O High-frequency clock output to external devices
HFXO_OUT_B P9_3 O High-frequency clock output to external devices
HFXO_P HFXO_P I High-frequency oscillator input
HFXO_N HFXO_N O High-frequency oscillator output
LFXO_P LFXO_P I Low-frequency oscillator input
LFXO_N LFXO_N O Low-frequency oscillator output

3.9 Signal Multiplexing and I/O Buffer Configuration

3.9.1 Signal Multiplexing
The device offers a sophisticated signal-to-pin multiplexing scheme. Each I/O pin may be assigned to one of
up to eight peripheral signals, and vice versa, a peripheral signal may be routed to up to four I/O pins. This
assignment is pseudo-static and must be performed once during boot time.
The multiplexed pins are divided into 8-pin groups, also referred to as 'ports'. A pin identifier 'Pn_i' may be
used, where n is the port number and i is the pin number within that port. A pin may be referenced also with
the GPIO peripheral's signal name 'GPIOn_i' because it shares the same numbering convention. For more
information on the GPIO peripheral, see Section 3.15 General-Purpose Input/Output Module.
MIPI-DSI, USB PHY pins, and power and ground pins have fixed functions and cannot be multiplexed.
Figure 3-6 shows the P0_0 multiplexing as an example. The Pn_i[PINMUX] register bitfield, where n = i = 0,
selects a peripheral signal to be available on P0_0. The multiplexer switches three signals at a time: IN, OUT,
and OEN (output enable). OEN could be dynamically driven by the peripheral, for example by the I2C which
needs to change the Data pin direction very frequently. For many other peripherals OEN could be static, and
for GPIO it is programmable via its Data Direction register. The analog peripherals are not multiplexed
between themselves and all three can read P0_0 when [PINMUX] = 7. For more information on configuration
registers, refer to the corresponding device series-specific Hardware Reference Manual.

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Figure 3-6 I/O Signal Multiplexing (P0_0 Example)

VDD_IO_1V8

GPIO0_0
GPIO0 0
OSPI0_D0
OSPI 1
UART0_RX
UART0 2
OUT

MUX/DEMUX
I3C_SDA
I3C 3
Digital
IN P0_0
UT0_0 I/O Buffer
UTIMER 4 OEN
LPCAM_HSYNC
LPCAM 5

6
ADC120_IN0 ANA_S0
ADC120 7

Configura�on
ADC24_IN0_P
ADC24

Selec�on
CMP0_IN0
CMP0

pinmux-002
Analog
P0_0 Register

Figure 3-7 shows the LPGPIO pin sharing. Because Port 15 is located in the always-on domain (VBAT
powered), here pin sharing is achieved differently. That is, there is no multiplexing as such. In this example,
LPTIMER0 gets access to P15_0 via the LPGPIO module. LPGPIO controls the pin direction depending on the
value written to its Data Direction register.
Figure 3-7 LPGPIO/LPTIMER Pin Sharing (P15_0 Example)

VDD_IO_FLEX

OUT
LPTMR0_OUT
IN Digital
LPTIMER0 LPTMR0_CLK LPGPIO P15_0
OEN I/O Buffer

Configura�on
pinmux-003

LPGPIO_CTRL_0 Register

3.9.2 I/O Buffer Configuration

Figure 3-8 shows a top-level block diagram of a digital I/O buffer module. I/O buffer consists of configurable
output buffer (driver), input buffer (receiver), pull-up/pull-down block, and protective diodes.

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Figure 3-8 I/O Buffer Block Diagram

OEN Digital I/O Pin Buffer Logic
(from peripheral)

OUT I/O Pin

(from peripheral)
Driver

Driver Config

Receiver Config

IN
(to peripheral)
Receiver

Weak
Pullup
Pull Config
Bus Keeper

Weak
Pulldown

PINMUX-001
The I/O buffer has the following main features:
n Configurable direction (input, output or both)
n Selectable driver-disabled state:
l No pull (Hi-Z, floating)

l Weak pull-up

l Weak pull-down

l Bus keeper (keeps the last state seen on the pin)

n Configurable drive strength

n Configurable slew rate
n Output driver can be open drain or push-pull type
n Input may have a Schmitt trigger enabled which adds hysteresis to signal transitions
n Dedicated power rails:
l VDD_IO_FLEX for the 1.8-V/3.3-V pins (GPIO7_[4-7] and GPIOV_[0-3])

l VDD_IO_1V8 for the 1.8-V pins

The Pn_i registers contain bitfields controlling the following parameters:

n Driver type—[DRV] (open drain or push-pull)
n Output drive strength—[E] (2 mA, 4 mA, 8 mA, or 12 mA)
n Driver disabled state—[P] (Hi-Z, Pull-up, Pull-down, or Bus Keeper)
n Slew rate—[SR] (slow [half-speed] or fast)
n Schmitt trigger enable—[SMT]
n Receiver enable—[REN]
Similar I/O buffer controls exist also for Port 15 in the LPGPIO_CTRL_n[DRIVER] and LPGPIO_CTRL_n
[RECEIVER] register bitfields.

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NOTE

For more information on configuration registers, refer to the corresponding device series-specific
Hardware Reference Manual.
For managing software configurations of device resources, power, pins, clocks, DMA requests,
interrupts, and various other additional settings, refer to the Alif Conductor tool.

3.10 Inter-Processor Communication

3.10.1 HWSEM Overview

The Hardware Semaphore (HWSEM) provides a mechanism for coordinating the concurrency between
processor cores when they access shared resources—memory regions or peripherals.
The device includes 16 HWSEM modules with individual interrupt requests. Each of the semaphores can be
assigned depending on the application needs.
Each HWSEM module supports the following main features:
n Acquire, Release, and Reset functions as atomic operation
n Single-processor access at a time
n An internal acquisition counter for enabling processor owning of a HWSEM to acquire it multiple times
n An interrupt assertion once the HWSEM becomes available

3.10.2 MHU Overview

The Message Handling Unit (MHU) provides point-to-point communication between the Secure Enclave
processor and the Real-Time processor (M55-HE). The MHU is an interrupt-based communication between
two processing entities.
The device includes up to 4 unidirectional MHU modules.
Each of the MHU modules supports the following main features:
n Two memory mapped register frames—Sender and Receiver
n Unidirectional communication interface
n Read and write access—32-bit word aligned
n Dual transport channels
n Different transport protocols—Doorbell, Single-Word transfer, and Multi-Word
n Dedicated interrupt lines for the Sender and Receiver
The software responsibilities are:
n To request the Receiver to be powered
n To ensure that the Sender remains powered until the transfer has been finished
n To use Ready to Send protocol to send the transfer
Each processor entity includes only one of the Sender or Receiver frame. To ensure a bi-directional (full-
duplex) communication between the entities, two MHUs with reversed Sender and Receiver parts are
implemented.

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3.11 Memories

3.11.1 MRAM Overview

The MRAM module is a type of non-volatile random-access memory which stores information in magnetic
elements.
The MRAM operates at 33 MHz clock frequency over 128-bit data bus. The 128-bit (16-byte) word represents
the minimum sector size for the MRAM. The smaller granularity offers much better efficiency compared to
the legacy flash memory modules. It takes flash memories longer to be programmed/erased due to their
much larger sector sizes.
The MRAM module implements a state machine controlling the erase and programming sequence of 16-byte
memory blocks. This operation is transparent to the CPU core.
The MRAM controller implements read cache and write buffer mechanism that enables the concurrent read
and write operations. This greatly benefits the implementation of multi-core applications that are not
required to coordinate the access to the MRAM. Up to four bus masters can originate concurrent write
operations, while the number of concurrent read operations is not limited.
The MRAM supports the following main features:
n Size up to 1.5MB
n High endurance (more than 100 000 erase cycles)
n More than 10 years data retention (at 125 °C junction temperature)
n 16 ECC bits for each 128-bit data word
n 2× 16 bytes read cache to accelerate access to frequently used data and non-16-byte aligned read
requests
n Built-in state machine controlling 16-byte program/erase cycle (no need of driver)
n Concurrent write (up to four bus masters) and read operations (no need for synchronization between
them)
n DMA write operation with up to 128 bytes in each DMA write cycle data payload

3.11.2 SRAM Overview

The device contains the following types of on-chip SRAM memories:
n User SRAM available for all bus masters:
l Bulk SRAM: SRAM0

l M55-HE TCM: SRAM4 (M55-HE ITCM) and SRAM5 (M55-HE DTCM), with optional retention

n Processor cache memories:

l M55-HE Level 1 cache

n Backup SRAM (with optional retention)

It is possible to configure address ranges within SRAM0 through SRAM5 to appear as contiguous address
space to the M55 core through configuration of the firewall controllers. For more information on the
firewalls, refer to the corresponding device series-specific Hardware Reference Manual, Section Interconnect
Firewall Functional Description.
The embedded bulk SRAM is a general-purpose memory to be shared among all applications. It has 64-bit
wide data bus and provides read/write operation at 400 MHz.
The TCM is an SRAM block providing high-bandwidth and low latency access. The TCM is primarily used by
the M55 core it is attached to. Alternatively, it can be shared with other bus masters in the device.

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The cache memory is a high-performance SRAM accelerating the CPU access to frequently used instructions
and data. The M55 processor has Level 1 cache memories dedicated to the M55 core.
The data retention of SRAM is used for context saving during low power modes.
The device includes the following quantities of SRAM with their performance characteristics:
n User SRAM available to all bus masters:
l Up to 4.5MB:
o 4MB bulk SRAM0
o 0.25MB SRAM4 (M55-HE ITCM) + 0.25MB SRAM5 (M55-HE DTCM), with optional data retention

l 400 MHz parallel read/write access

n Real-time processor (M55) cache memories:

l Level 1 Cache: 32KB Instruction and 32KB Data

n Backup SRAM:
l 4KB in power domain PD-0

l 100 MHz read/write access

l Optional data retention by VDD_BATT (see Section 3.6.2 Voltage Supplies for details)

NOTE

User SRAM size and availability is device part number dependent. For more information on SRAM
blocks enabled for each part number and their sizes, see Section 7 Ordering Information.

3.11.3 TCM Overview

The Tightly Coupled Memory (TCM) is a high-bandwidth and low latency memory. The TCM enables the
Cortex-M55 core to perform vector operations with high efficiency and process interrupts with minimum
latency. The TCM access time is a single clock cycle with no wait states. The TCM interface is based on
Harvard architecture—it has one instruction memory (ITCM0) bus and four data memory (DTCM0/1/2/3)
buses, all 32-bit wide.
The M55-HE core can use the ITCM for storing data and can fetch instructions out of the DTCM. In this
scenario, the TCM access time is slower and vector operations are not supported.
The Cortex-M55 core has the following TCM configurations:
n M55-HE:
l 256KB of ITCM and 4 × 64KB of DTCM (total of 512KB)
l 1 × 32-bit ITCM and 4 × 32-bit DTCM memory buses

l Single-cycle read/write access at 160 MHz

l Concurrent share of TCM with the other processing entities via AHB slave port

l Optional content retention through VDD_BATT

3.11.4 External Memory Expansion Options

The device provides two options to expand the memory using external devices:
n 1× SDMMC interface
n 1× OSPI interface
The SDMMC interface can be used to access embedded or external memory cards with clock frequency up to
50 MHz. The data bus is up to 8 bits wide. This external memory interface is suitable for expanding the bulk

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data storage capacity in the form of an external flash-based file system. The SDMMC interface supports
legacy 4-bit cards as well.
The OSPI interface can be used to access external flash memory devices. The OSPI supports Double Data Rate
(DDR) mode transferring 8-bit data on both edges of the clock signal. The maximum clock frequency is up to
100 MHz delivering raw DDR bandwidth of up to 200 MB/s.
The OSPI interface could access the memory in two modes—directly (through register read/write operations)
or indirectly (through memory-mapped operations). The indirect access supports eXecute-in-Place (XIP)
mode which translates the instruction fetch operations to proper address and data read transactions. This
way, the external memory devices expand the available non-volatile memory.
The OSPI interface supports legacy Single, Dual, Quad, or Octal SPI flash memory devices.
The OSPI interface also supports the HyperBus protocol in direct and indirect modes. This enables the
integration of external Static or Pseudo-Static RAM devices.
The OSPI interface can be attached to a flash or SRAM devices based on the application needs.
The device includes an AES decoder which is implemented in hardware and enables on-the-fly decoding of
the external memory content. This allows protecting the OSPI code or the confidentiality of the data stored
in external devices. The decoder effectively adds no latency while maintaining the overall external memory
interface bandwidth.

3.11.5 Memory Mapping

Refer to the device series-specific Hardware Reference Manual for details on the memory mapping.

3.12 Interrupts and Events Management

3.12.1 NVIC Overview

The Nested Vectored Interrupt Controller (NVIC) resides in the M55-HE processor, and it is closely integrated
with the Cortex-M55 core to achieve low-latency interrupt processing.
The NVIC module supports the following main features:
n Maintaining the current execution priority of the Cortex-M55 processor
n Maintaining the pending and active status of all exceptions that are supported
n Invoking preemption when a pending exception has priority
n Providing wake-up signals to wake up the Cortex-M55 processor from deep sleep mode
n Providing support to the Internal Wakeup Interrupt Controller (IWIC) and External Wakeup Interrupt
Controller (EWIC)
n Providing priority and exception information to other processor components
n 480 external interrupts, with 256 priority levels per interrupt

3.12.2 IRQRTR Overview

The shared Interrupt Router (IRQRTR) is intended to route interrupt signals from the device peripherals to all
processing entities. It has an input port wired to the interrupt sources and two output ports connected to the
Secure Enclave and the Real-Time Processing (M55-HE) interrupt controller.
The router configuration registers define which interrupt sources are enabled and their destination output
ports. Once configured, the router can be locked fully or partially so that further changes can be restricted.
The access to the IRQRTR configuration may be constrained based on the device security policy. In this
case, the interrupt routing can be indirectly setup by service call to the Secure Enclave.

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The IRQRTR supports the following main features:

n Manages up to 427 shared interrupts
n Configures routing of the interrupt signals to up to four processing entities
n Supports configuration access lockdown
n Reports tamper interrupts to the Secure Enclave

3.12.3 EVTRTR Overview

The device integrates a large number of peripherals that can generate events indicating changes in their
state, receiving of data or completion of an operation. The Event Router (EVTRTR) is a module that can
associate an event originated by one peripheral with an action executed by another.
The function of the EVTRTR is similar to the shared Interrupt Router (IRQRTR), which targets an interrupt
controller and ultimately a CPU core. Unlike the IRQRTR, the EVTRTR is connecting the event signal to a
peripheral that executes an action without involving any CPU core.
Modules generating such event signals include: GPIO, UTIMER, I2C, SPI, UART, and others. The EVTRTR passes
the signals through edge-detection circuits and gating logic before routing them to specific targets.
The device includes two Event Routers, each dedicated to a specific target:
n EVTRTR0, dedicated to DMA0 controller and UTIMER
n EVTRTR2, dedicated to DMA2 controller
Each EVTRTR provides the following main features:
n Software generated events
n Zero wait state for event routing between peripherals in the same clock domain
n Automatic synchronization of events and triggers between peripherals in different clock domains
n DMA channel enable, handshake status and type selection
Figure 3-9 provides a high-level overview of the EVTRTR implementation in the device.

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Figure 3-9 EVTRTR Overview

Device
EVTRTR0 DMA0 Controller
(DMA0_MUX)

128 Events 4-to-1 MUX CH0 32 Events

4-to-1 MUX CH1

...
4-to-1 MUX CH31

16 Events
MUX Config:
DMA_CTRLn[SEL]
(n = 0 to 31)
UT_EVENT[0-15] UTIMER

16 UTIMER Events

EVTRTR-001a
Device
EVTRTR2
EVTRTR DMA2
DMA0 Controller
(DMA0_MUX)

32 Events 4-to-1 CH0

MUX CH0 32 Events

4-to-1 CH1
MUX CH1
...

4-to-1CH31
MUX CH31 EVTRTR-001b

EVTRTR0 is also referred to as DMA0_MUX and expands the available 32 inputs of DMA0 by exposing the
DMA channels to 128 different peripheral events via 32 × 4-to-1 multiplexers. The first 16 multiplexed DMA0
requests are also routed as input triggers to the Universal Timer (UTIMER). This mechanism enables the
implementation of complex state machines involving the use of peripheral or time-based events that trigger
data transfers and/or timer triggers.
EVTRTR2 supports 32 input events/output DMA channels, without implementing events multiplexing.

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3.13 DMA Management

3.13.1 DMA Architecture Overview

The device features Direct Memory Access (DMA) controllers to offload the CPUs from repeated data
transfer tasks. The device has the following DMA controllers:
n USB embedded DMA controller
n SDMMC embedded DMA controller
n DMA0: Can be shared by all of the CPU cores and carries out data transfers from/to ADC, PDM, I2C, I3C,
CANFD, SPI, OSPI, and UART. DMA0 also supports multiple DMA triggers like GPIO pins and timer events.
n DMA2: Dedicated to the RTSS-HE subsystem and can move data from/to the Low Power (LP) peripherals
(such as LPUART), ADC, CANFD, and I3C. Additionally, BOD, LPTIMER, LPCAM_VSYNC, LPCAM_HSYNC,
and LPGPIO transitions can trigger DMA requests.
Figure 3-10 gives a high-level overview of the DMA architecture in the device.
Figure 3-10 DMA Architecture

Peripherals Peripherals

EVTRTR0 EVTRTR2

DMA Requests
USB SDMMC
DMA Requests

M55-HE

TCM

DMA DMA DMA0 DMA2

AXI

OSPI Peripherals
SRAM NVM
Memory (UART, I2C, SPI, etc.)
DMA_ARCH-001

The high-speed interface peripherals (USB and SDMMC) have their own, embedded DMA controllers. They
are optimized for the specific needs of these interfaces.
DMA0 and DMA2 are general-purpose, programmable, multi-channel, and TrustZone-aware DMA controllers
(DMACs). Each of them has 32 inputs for accepting DMA requests from various device peripherals and
triggers (for example, UART Tx and Rx, ADC conversion done, etc). The Event Routers positioned in front of
the DMA controllers provide support for DMA handshaking between peripherals and DMACs. Additionally,
EVTRTR0 provides 32 × 4-to-1 programmable multiplexers, which expose the 32 DMA0 inputs to 128 possible
DMA requests from peripherals, thus providing an increased flexibility. Each DMA controller supports 8

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internal data channels (FIFOs). All channels can perform independently programmed transactions including
different data lengths, source and destination addresses, single or burst transfers.
DMA0 security privilege of each channel is run-time programmable. DMA0 initiates transactions on the main
AXI bus with its unique Stream ID. Each of the 32 request interfaces can generate an interrupt request signal.
DMA2 is assigned to the M55-HE CPU core. DMA2 resides in the M55-HE domain and shares AXI-bus Stream
IDs (and security policy). The DMA2 request interface can generate individual interrupt requests, attached
locally to the M55-HE core.

3.13.2 DMA Controllers Overview

The device includes two copies of the general-purpose DMA Controller (DMAC):
n DMA0
n DMA2, dedicated to the RTSS-HE
Each DMAC supports the following main features:
n Flexible instruction set for programming DMA transfers
n Transfer types:
l Memory-to-memory

l Memory-to-peripheral

l Peripheral-to-memory

l Scatter-gather

n 32 peripheral request interfaces (DMA_Req/DMA_Ack)

n 8 DMA channels (VFIFOs)
n Flagging of various DMA events using 33 interrupt signals
l 32 interrupts, one per DMA request interface

l One data abort interrupt

n Dual slave interfaces, secure and non-secure, for accessing registers

n Programmable security state for each DMA channel
n Arm TrustZone technology
n 4 active AXI read transactions
n 4 active AXI write transactions
n 32 deep internal data buffer (MFIFO)
n 4 lines in the instruction cache with 8 words in a line
n 8 deep read instruction queue
n 8 deep write instruction queue
n Request acceptance capability of a peripheral request interface—4 requests

3.14 Timers and Counters

3.14.1 LPTIMER Overview

The 32-bit Low-Power Timer (LPTIMER) module counts down from a programmed value and generates an
interrupt when the count reaches zero. Two events can cause the timer to load the initial value from which it
counts down. The first event is when the timer is enabled after being reset or disabled, and the second event
is when the timer count reaches zero.
The device includes up to two independent LPTIMER modules (“channels”), accessible through a single bus.
Each LPTIMER module supports the following main features:
n 32-bit down counter
n Free-running and user-defined count modes

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n Asynchronous event counting

n Individual toggle output
n Individual interrupt output
n Independent clock input that can be connected either to internal clocks or to an external clock source
n Each odd numbered LPTIMER module can be concatenated with the previous even numbered LPTIMER
module to form up to a 64-bit timer
Table 3-9 presents LPTIMER interface signals and provides descriptions to their functions.
Table 3-9 LPTIMER Signal Descriptions
Pin
Signal Name Type Description
Name
LPTIMER0
LPTIMER0_CLK: LPTIMR0 input clock from pin.
LPTIMER0_OUT: LPTIMER0 toggle output. Changes state each time the
LPTMR0_CLK_IO P15_0 IO
timer counter reloads. The output is disabled to 0 each time the timer
is disabled.
LPTIMER1
LPTIMER1_CLK: LPTIMR1 input clock from pin.
LPTIMER1_OUT: LPTIMER1 toggle output. Changes state each time the
LPTMR1_CLK_IO P15_1 IO
timer counter reloads. The output is disabled to 0 each time the timer
is disabled.

3.14.2 UTIMER Overview

The 32-bit high-resolution Universal Timer (UTIMER) typically serves as a standard signal timing generator
and a pulse counter. In addition, the UTIMER can also be used to implement a quadrature encoder interface
and serve as a Quadrature Encoder Counter (QEC).
The device includes up to twelve independent UTIMER modules (“channels”), which are allocated as follows:
n Up to eight standard UTIMER modules: Channel 0 (UTIMER0) to Channel 7 (UTIMER7)
n Up to four UTIMER modules configured as QEC: Channel 12 (QEC0) to Channel 15 (QEC3)
In measurement mode, each UTIMER channel can capture the timing of internal events or external signal
pulse edges. In counting mode, each channel can count external pulses, internal events, or decode
quadrature pulse sequences.
As a signal generator, each UTIMER channel can be configured to produce PWM outputs with independent or
complementary polarity and has the following main characteristics:
n Outputs configurable option to automatically insert dead-time suitable for power stages with
asymmetric switching characteristics
n Multiple channels can be synchronized to drive three-phase inverters with variety of modulation
schemes
n Driving up to 4 three-phase motors at once
Each QEC channel is a multifunctional counter with two inputs that can be configured to support different
counting modes and an additional pin for zero signal used for reference run (zero-point calibration).
A QEC channel is intended to operate primarily as a decoder of a quadrature encoder pulse sequence. The
input signals are passed through a digital filter to improve the noise immunity of the circuit. The count
direction can be configured to depend on the phase difference between two signals (quadrature encoding) or
on the level of one of them (pulse and direction encoding). Alternatively, one of the signals can be configured
to increment and the other to decrement the timer counter values.

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Each UTIMER channel supports the following main features:

n Clocked at high-resolution 400 MHz clock with 2.5 ns accuracy when generating a PWM output or when
measuring input signal timing characteristics
n Dedicated digital inputs configurable as external synchronization sources or as fault signals that trigger
automatic shut-off of the output drivers
n 32-bit wide counters and compare registers
n Double-buffered compare registers to support update of PWM duty cycle to occur upon several events,
including at the middle or at the end of a PWM period. When buffer operation is enabled, it can be
configured to use single or double stage.
n Up to 2 high-resolution PWM outputs with independent or complimentary polarity
n Support of capturing events placed closely together when the channel is configured as a pulse counter
n Capture and compare modes
n Compare registers dedicated to ADC synchronization—on a match they trigger ADC conversion, thus
avoiding a power stage switching noise
n 8 interrupt events—some can be shared among channels to enable the implementation of complex state
machines that can operate in a deterministic manner
n Configurable to use two I/O pins as inputs and to drive the two I/O pins
Each QEC channel has the following main features:
n 32-bit wide counters and compare registers
n Decoding quadrature encoder pulse sequence
n Counting in pulse/direction or increment/decrement modes
n Measurement of pulse width, period, or duty cycle
n Digital filter on the input signals for up to 32 peripheral clock cycles
n Generation of interrupts on two compare/match events
n Internal clock frequency up to 400 MHz
n External signals frequency up to 50 MHz
Table 3-10 presents UTIMER interface signals and provides descriptions to their functions.
Table 3-10 UTIMER Signal Descriptions
Signal Name Pin Name Type Description
UTIMER0 A/B/C
UT0_T0_A P0_0
UT0_T0_B P5_0 IO UTIMER0 input event on channel A / output to driver A
UT0_T0_C P10_0
UT0_T1_A P0_1
UT0_T1_B P5_1 IO UTIMER0 input event on channel B / output to driver B
UT0_T1_C P10_1
UTIMER1 A/B/C
UT1_T0_A P0_2
UT1_T0_B P5_2 IO UTIMER1 input event on channel A / output to driver A
UT1_T0_C P10_2
UT1_T1_A P0_3
UT1_T1_B P5_3 IO UTIMER1 input event on channel B / output to driver B
UT1_T1_C P10_3
UTIMER2 A/B/C
UT2_T0_A P0_4
IO UTIMER2 input event on channel A / output to driver A
UT2_T0_B P5_4

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Signal Name Pin Name Type Description

UT2_T0_C P10_4
UT2_T1_A P0_5
UT2_T1_B P5_5 IO UTIMER2 input event on channel B / output to driver B
UT2_T1_C P10_5
UTIMER3 A/B/C
UT3_T0_A P0_6
UT3_T0_B P5_6 IO UTIMER3 input event on channel A / output to driver A
UT3_T0_C P10_6
UT3_T1_A P0_7
UT3_T1_B P5_7 IO UTIMER3 input event on channel B / output to driver B
UT3_T1_C P10_7
UTIMER4 A/B/C
UT4_T0_A P1_0
UT4_T0_B P6_0 IO UTIMER4 input event on channel A / output to driver A
UT4_T0_C P11_0
UT4_T1_A P1_1
UT4_T1_B P6_1 IO UTIMER4 input event on channel B / output to driver B
UT4_T1_C P11_1
UTIMER5 A/B/C
UT5_T0_A P1_2
UT5_T0_B P6_2 IO UTIMER5 input event on channel A / output to driver A
UT5_T0_C P11_2
UT5_T1_A P1_3
UT5_T1_B P6_3 IO UTIMER5 input event on channel B / output to driver B
UT5_T1_C P11_3
UTIMER6 A/B/C
UT6_T0_A P1_4
UT6_T0_B P6_4 IO UTIMER6 input event on channel A / output to driver A
UT6_T0_C P11_4
UT6_T1_A P1_5
UT6_T1_B P6_5 IO UTIMER6 input event on channel B / output to driver B
UT6_T1_C P11_5
UTIMER7 A/B/C
UT7_T0_A P1_6
UT7_T0_B P6_6 IO UTIMER7 input event on channel A / output to driver A
UT7_T0_C P11_6
UT7_T1_A P1_7
UT7_T1_B P6_7 IO UTIMER7 input event on channel B / output to driver B
UT7_T1_C P11_7

Table 3-11 presents UTIMER QEC interface signals and provides descriptions to their functions.
Table 3-11 UTIMER QEC Signal Descriptions
Signal Name Pin Name Type Description
QEC0 A/B/C

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Signal Name Pin Name Type Description

QEC0_X_A P3_0
QEC0_X_B P8_4 I QEC0 input event on channel A
QEC0_X_C P13_0
QEC0_Y_A P3_1
QEC0_Y_B P8_5 I QEC0 input event on channel B
QEC0_Y_C P13_1
QEC0_Z_A P3_2
QEC0_Z_B P8_6 I QEC0 input for zero signal
QEC0_Z_C P13_2
QEC1 A/B/C
QEC1_X_A P3_3
QEC1_X_B P8_7 I QEC1 input event on channel A
QEC1_X_C P13_3
QEC1_Y_A P3_4
QEC1_Y_B P9_0 I QEC1 input event on channel B
QEC1_Y_C P13_4
QEC1_Z_A P3_5
QEC1_Z_B P9_1 I QEC1 input for zero signal
QEC1_Z_C P13_5
QEC2 A/B/C
QEC2_X_A P3_6
QEC2_X_B P9_2 I QEC2 input event on channel A
QEC2_X_C P13_6
QEC2_Y_A P3_7
QEC2_Y_B P9_3 I QEC2 input event on channel B
QEC2_Y_C P13_7
QEC2_Z_A P4_0
QEC2_Z_B P9_4 I QEC2 input for zero signal
QEC2_Z_C P14_0
QEC3 A/B/C
QEC3_X_A P4_1
QEC3_X_B P9_5 I QEC3 input event on channel A
QEC3_X_C P14_1
QEC3_Y_A P4_2
QEC3_Y_B P9_6 I QEC3 input event on channel B
QEC3_Y_C P14_2
QEC3_Z_A P4_3
QEC3_Z_B P9_7 I QEC3 input for zero signal
QEC3_Z_C P14_3

Table 3-12 presents UTIMER common interface signals and provides descriptions to their functions.
Table 3-12 UTIMER Common Signal Descriptions
Signal Name Pin Name Type Description
Common A/B/C

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Signal Name Pin Name Type Description

FAULT0_A P4_4
FAULT0_B P8_0 I Fault signal 0. Used to trigger automatic shut-off of the output drivers.
FAULT0_C P14_4
FAULT1_A P4_5
FAULT1_B P8_1 I Fault signal 1. Used to trigger automatic shut-off of the output drivers.
FAULT1_C P14_5
FAULT2_A P4_6
FAULT2_B P8_2 I Fault signal 2. Used to trigger automatic shut-off of the output drivers.
FAULT2_C P14_6
FAULT3_A P4_7
FAULT3_B P8_3 I Fault signal 3. Used to trigger automatic shut-off of the output drivers.
FAULT3_C P14_7

3.14.3 WDT_RTSS Overview

The Real-Time Subsystem Watchdog Timer module, hereinafter referred to as WDT_RTSS, is a timer based on
a 32-bit down-counter. The basic function of the WDT_RTSS is to count for a fixed period, during which it
expects to be serviced by the system, indicating normal operation. The WDT_RTSS provides a mechanism to
detect errant system behavior and recover from an unknown state by causing non-maskable interrupt of the
system if the count period elapses without intervention.
The device includes one WDT_RTSS module:
n WDT_HE: Dedicated to the Arm Cortex-M55 High-Efficiency (M55-HE) processor
The WDT_RTSS module supports the following main features:
n 32-bit down-counter
n Counter decrements by one on each positive watchdog clock edge
n Configurable NMI generation upon watch period expiration

3.14.4 LPRTC Overview

The Low-Power Real-Time Counter (LPRTC) module is a configurable high-range binary counter, which can
generate an interrupt on a user-specified interval.
The device includes one LPRTC module located in the PD-0 power domain, allowing it to run even when the
device is in the lowest power state and power is present on VDD_BATT.
The LPRTC module supports the following main features:
n 32.768 kHz typical reference clock
n 32-bit incrementing counter
n 16-bit programmable prescaler
n Interrupt generation upon programmed count match
n Counter wrap mode
The LPRTC module can be utilized for the following use cases:
n Real-time clock—to keep track of the current time
n Long-term exact chronometer—to keep track of time from now up to 136 years in the future (when
clocked with a 1 Hz clock signal)
n Alarm function—to generate an interrupt after a programmed number of cycles
n Long time base counter—when clocked with a kHz range clock signal from either LFXO or LFRC

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3.15 General-Purpose Input/Output Module

The General-Purpose Input/Output (GPIO) module provides means for driving and reading from digital I/O
pins when they are not used by other peripheral (like UART, I2C, etc.). GPIO module can be used for tasks like
lighting LEDs or reading the state of push-buttons, switches, etc. The GPIO module also offers switch contact
debounce and interrupt capabilities.
The device includes up to sixteen GPIO modules with support of up to 128 I/O pins in total. The I/O signals
are distributed as follows:
n GPIO[0-14]: 8 I/O signals each
n LPGPIO: 8 I/O signals
The GPIO modules are integrated in two power domains:
n Power Domain PD-6: GPIO[0-14]
n Power Domain PD-0 (AON): LPGPIO
Each GPIO module supports the following main features:
n Data register allows driving and reading each GPIO pin individually
n Data Direction register selects pin direction – input or output
n Debounce function driven by the 32-k clock for switch/push-button contacts debouncing (GPIO[0-14])
n Individual interrupt generation for every pin of GPIO[0-14] and LPGPIO
n Common (combined) interrupt generation for the pin events of LPGPIO
n The LPGPIO interrupt can be used as a wake-up source for the M55-HE core
Table 3-13 presents GPIO interface signals and provides descriptions to their functions.
Table 3-13 GPIO Signal Descriptions
Signal Name Pin Name Type Description
GPIO0
GPIO0_0 P0_0 IO General-purpose input/output(1)
GPIO0_1 P0_1 IO General-purpose input/output(1)
GPIO0_2 P0_2 IO General-purpose input/output(1)
GPIO0_3 P0_3 IO General-purpose input/output(1)
GPIO0_4 P0_4 IO General-purpose input/output(1)
GPIO0_5 P0_5 IO General-purpose input/output(1)
GPIO0_6 P0_6 IO General-purpose input/output(1)
GPIO0_7 P0_7 IO General-purpose input/output(1)
GPIO1
GPIO1_0 P1_0 IO General-purpose input/output(1)
GPIO1_1 P1_1 IO General-purpose input/output(1)
GPIO1_2 P1_2 IO General-purpose input/output(1)
GPIO1_3 P1_3 IO General-purpose input/output(1)
GPIO1_4 P1_4 IO General-purpose input/output(1)
GPIO1_5 P1_5 IO General-purpose input/output(1)
GPIO1_6 P1_6 IO General-purpose input/output(1)
GPIO1_7 P1_7 IO General-purpose input/output(1)
GPIO2
GPIO2_0 P2_0 IO General-purpose input/output(1)
GPIO2_1 P2_1 IO General-purpose input/output(1)
GPIO2_2 P2_2 IO General-purpose input/output(2)

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Signal Name Pin Name Type Description

GPIO2_3 P2_3 IO General-purpose input/output(1)
GPIO2_4 P2_4 IO General-purpose input/output(1)
GPIO2_5 P2_5 IO General-purpose input/output(1)
GPIO2_6 P2_6 IO General-purpose input/output(1)
GPIO2_7 P2_7 IO General-purpose input/output(1)
GPIO3
GPIO3_0 P3_0 IO General-purpose input/output
GPIO3_1 P3_1 IO General-purpose input/output
GPIO3_2 P3_2 IO General-purpose input/output
GPIO3_3 P3_3 IO General-purpose input/output
GPIO3_4 P3_4 IO General-purpose input/output
GPIO3_5 P3_5 IO General-purpose input/output
GPIO3_6 P3_6 IO General-purpose input/output
GPIO3_7 P3_7 IO General-purpose input/output
GPIO4
GPIO4_0 P4_0 IO General-purpose input/output
GPIO4_1 P4_1 IO General-purpose input/output
GPIO4_2 P4_2 IO General-purpose input/output
GPIO4_3 P4_3 IO General-purpose input/output
GPIO4_4 P4_4 IO General-purpose input/output
GPIO4_5 P4_5 IO General-purpose input/output
GPIO4_6 P4_6 IO General-purpose input/output
GPIO4_7 P4_7 IO General-purpose input/output
GPIO5
GPIO5_0 P5_0 IO General-purpose input/output
GPIO5_1 P5_1 IO General-purpose input/output
GPIO5_2 P5_2 IO General-purpose input/output
GPIO5_3 P5_3 IO General-purpose input/output
GPIO5_4 P5_4 IO General-purpose input/output
GPIO5_5 P5_5 IO General-purpose input/output
GPIO5_6 P5_6 IO General-purpose input/output
GPIO5_7 P5_7 IO General-purpose input/output
GPIO6
GPIO6_0 P6_0 IO General-purpose input/output
GPIO6_1 P6_1 IO General-purpose input/output
GPIO6_2 P6_2 IO General-purpose input/output
GPIO6_3 P6_3 IO General-purpose input/output
GPIO6_4 P6_4 IO General-purpose input/output
GPIO6_5 P6_5 IO General-purpose input/output
GPIO6_6 P6_6 IO General-purpose input/output
GPIO6_7 P6_7 IO General-purpose input/output
GPIO7
GPIO7_0 P7_0 IO General-purpose input/output
GPIO7_1 P7_1 IO General-purpose input/output
GPIO7_2 P7_2 IO General-purpose input/output

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Signal Name Pin Name Type Description

GPIO7_3 P7_3 IO General-purpose input/output
GPIO7_4 P7_4 IO General-purpose input/output
GPIO7_5 P7_5 IO General-purpose input/output
GPIO7_6 P7_6 IO General-purpose input/output
GPIO7_7 P7_7 IO General-purpose input/output
GPIO8
GPIO8_0 P8_0 IO General-purpose input/output
GPIO8_1 P8_1 IO General-purpose input/output
GPIO8_2 P8_2 IO General-purpose input/output
GPIO8_3 P8_3 IO General-purpose input/output
GPIO8_4 P8_4 IO General-purpose input/output
GPIO8_5 P8_5 IO General-purpose input/output
GPIO8_6 P8_6 IO General-purpose input/output
GPIO8_7 P8_7 IO General-purpose input/output
GPIO9
GPIO9_0 P9_0 IO General-purpose input/output
GPIO9_1 P9_1 IO General-purpose input/output
GPIO9_2 P9_2 IO General-purpose input/output
GPIO9_3 P9_3 IO General-purpose input/output
GPIO9_4 P9_4 IO General-purpose input/output
GPIO9_5 P9_5 IO General-purpose input/output
GPIO9_6 P9_6 IO General-purpose input/output
GPIO9_7 P9_7 IO General-purpose input/output
GPIO10
GPIO10_0 P10_0 IO General-purpose input/output
GPIO10_1 P10_1 IO General-purpose input/output
GPIO10_2 P10_2 IO General-purpose input/output
GPIO10_3 P10_3 IO General-purpose input/output
GPIO10_4 P10_4 IO General-purpose input/output
GPIO10_5 P10_5 IO General-purpose input/output
GPIO10_6 P10_6 IO General-purpose input/output
GPIO10_7 P10_7 IO General-purpose input/output
GPIO11
GPIO11_0 P11_0 IO General-purpose input/output
GPIO11_1 P11_1 IO General-purpose input/output
GPIO11_2 P11_2 IO General-purpose input/output
GPIO11_3 P11_3 IO General-purpose input/output
GPIO11_4 P11_4 IO General-purpose input/output
GPIO11_5 P11_5 IO General-purpose input/output
GPIO11_6 P11_6 IO General-purpose input/output
GPIO11_7 P11_7 IO General-purpose input/output
GPIO12
GPIO12_0 P12_0 IO General-purpose input/output
GPIO12_1 P12_1 IO General-purpose input/output
GPIO12_2 P12_2 IO General-purpose input/output

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Signal Name Pin Name Type Description

GPIO12_3 P12_3 IO General-purpose input/output
GPIO12_4 P12_4 IO General-purpose input/output
GPIO12_5 P12_5 IO General-purpose input/output
GPIO12_6 P12_6 IO General-purpose input/output
GPIO12_7 P12_7 IO General-purpose input/output
GPIO13
GPIO13_0 P13_0 IO General-purpose input/output
GPIO13_1 P13_1 IO General-purpose input/output
GPIO13_2 P13_2 IO General-purpose input/output
GPIO13_3 P13_3 IO General-purpose input/output
GPIO13_4 P13_4 IO General-purpose input/output
GPIO13_5 P13_5 IO General-purpose input/output
GPIO13_6 P13_6 IO General-purpose input/output
GPIO13_7 P13_7 IO General-purpose input/output
GPIO14
GPIO14_0 P14_0 IO General-purpose input/output
GPIO14_1 P14_1 IO General-purpose input/output
GPIO14_2 P14_2 IO General-purpose input/output
GPIO14_3 P14_3 IO General-purpose input/output
GPIO14_4 P14_4 IO General-purpose input/output
GPIO14_5 P14_5 IO General-purpose input/output
GPIO14_6 P14_6 IO General-purpose input/output
GPIO14_7 P14_7 IO General-purpose input/output
LPGPIO
GPIOV_0 P15_0 IO Low-power general-purpose input/output
GPIOV_1 P15_1 IO Low-power general-purpose input/output
GPIOV_2 P15_2 IO Low-power general-purpose input/output
GPIOV_3 P15_3 IO Low-power general-purpose input/output
GPIOV_4 P15_4 IO Low-power general-purpose input/output
GPIOV_5 P15_5 IO Low-power general-purpose input/output
GPIOV_6 P15_6 IO Low-power general-purpose input/output
GPIOV_7 P15_7 IO Low-power general-purpose input/output
1. Serves also as analog input. See Section 3.20.6 Analog Signals.
2. Serves also as analog input/output. See Section 3.20.6 Analog Signals.

3.16 Communication Peripherals

3.16.1 CANFD Overview

The Controller Area Network (CANFD) module performs serial communication according to the CAN protocol.
The CAN bus interface uses the basic CAN principle and meets all constraints of the CAN Specification 2.0B
active. The CANFD module supports both classic CAN and CAN with Flexible Data-rate (FD) specifications.
The device includes up to one CANFD module.
The CANFD module supports the following main features:

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n CAN specifications:
l CAN 2.0B (up to 8 bytes payload, verified by Bosch reference model)
l CAN FD (up to 64 bytes payload, ISO 11898-1:2015 or non-ISO Bosch)

n Free programmable data rates:

l Data rates up to 10 Mbps

l CAN FD rates are limited by the transceiver and the clock frequency of the CAN controller

n Programmable baud rate prescaler (1 to 1/256)

n One receive buffer and two transmit buffers—primary transmit buffer (PTB) and secondary transmit
buffer (STB):
l Buffer size: 640 words

l Number of buffer slots: 16

n 3× independent and programmable internal 29-bit acceptance filters

n Extended features:
l Single Shot Transmission mode (for PTB and/or for STB)

l Listen-Only mode

l Loop Back mode (internal and external)

l Transceiver Standby mode

n Extended status and error report:

l Capturing of last occurred Kind Of Error (KOER) and arbitration lost position

l Programmable Error Warning Limit

n 32-bit synchronous Host controller interfaces

n Configurable interrupt sources
n Dual port memory block for frame buffer
n CiA 603 32-bit timestamping
n Compatible with AUTOSAR
n Optimized for SAE J1939
Table 3-14 presents CANFD interface signals and provides descriptions to their functions.
Table 3-14 CANFD Signal Descriptions
Signal Name Pin Name Type Description
CANFD A/B/C
CAN_RXD_A P7_0 I CANFD serial data input (from external CAN transceiver)
CAN_RXD_B P0_4 I CANFD serial data input (from external CAN transceiver)
CAN_RXD_C P12_4 I CANFD serial data input (from external CAN transceiver)
CAN_TXD_A P7_1 O CANFD serial data output (to external CAN transceiver)
CAN_TXD_B P0_5 O CANFD serial data output (to external CAN transceiver)
CAN_TXD_C P12_5 O CANFD serial data output (to external CAN transceiver)
CAN_STBY_A P7_3 O CANFD transceiver standby mode signal
CAN_STBY_B P0_6 O CANFD transceiver standby mode signal
CAN_STBY_C P12_6 O CANFD transceiver standby mode signal

3.16.2 CRC Overview

The Cyclic Redundancy Check (CRC) calculation module can produce 8-, 16-, and 32-bit codes for variety of
polynomials. This function is used to validate the integrity of a communication packet received or the
integrity of a binary image that is an update candidate. This is achieved by computing and comparing the CRC
code with the one received after the data packet transmission.
The device includes up to two CRC modules.
Each CRC module has the following main features:

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n Built-in support for the following CRC algorithms:

l CRC-8-CCITT
l CRC-16

l CRC-16-CCITT

l CRC-32

l CRC-32C

n Support of customized polynomials configured by register settings

n 8- or 32-bits of data processed at a time
n Configurable byte and bit swapping of data

3.16.3 I2C Overview

The Inter-Integrated Circuit (I2C) module is a synchronous, master/slave serial communication bus which is
suitable for different system control applications.
The device includes:
n Up to four I2C modules in Shared Peripherals
n One Low-Power I2C (LPI2C) slave-only module in the RTSS-HE
The I2C modules support the following main features:
n Operating bus speed:
l Standard Speed (SS) mode (up to 100 kbps)
l Fast Speed (FS) mode (up to 400 kbps)

l Fast Speed Plus (FS+) mode (up to 1 Mbps)

n Master or slave operation

n 7- or 10-bit addressing
n 7- or 10-bit combined format transfers
n 32-byte deep receive and transmit FIFOs
n Bulk transmit mode
n CBUS addresses are ignored
n Interrupt or polled-mode operation
n Bit and byte waiting at all bus speeds
n DMA handshaking interface
n Programmable SDA hold time
n Bus clear feature
The LPI2C module supports the following main features:
n Operating bus speed:
l Standard Speed (SS) mode (up to 100 kbps)
l Fast Speed (FS) mode (up to 400 kbps)

n Slave operation only

n 7-bit addressing only
n 8-byte deep inbound and outbound FIFOs
n Interrupt or polled-mode operation
Table 3-15 presents I2C interface signals and provides descriptions to their functions.
Table 3-15 I2C Signal Descriptions
Signal Name Pin Name Type Description
I2C0 A/B/C/D
I2C0_SCL_A P0_3
IO I2C0 serial clock line. Open-drain output driver, requires external pull-up.
I2C0_SCL_B P3_4

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Signal Name Pin Name Type Description

I2C0_SCL_C P7_1
I2C0_SCL_D P10_5
I2C0_SDA_A P0_2
I2C0_SDA_B P3_5
IO I2C0 serial data line. Open-drain output driver, requires external pull-up.
I2C0_SDA_C P7_0
I2C0_SDA_D P10_4
I2C1 A/B/C/D
I2C1_SCL_A P0_5
I2C1_SCL_B P3_7
IO I2C1 serial clock line. Open-drain output driver, requires external pull-up.
I2C1_SCL_C P7_3
I2C1_SCL_D P10_7
I2C1_SDA_A P0_4
I2C1_SDA_B P3_6
IO I2C1 serial data line. Open-drain output driver, requires external pull-up.
I2C1_SDA_C P7_2
I2C1_SDA_D P10_6
I2C2 A/B/C
I2C2_SCL_A P0_6
I2C2_SCL_B P5_1 IO I2C2 serial clock line. Open-drain output driver, requires external pull-up.
I2C2_SCL_C P5_6
I2C2_SDA_A P0_7
I2C2_SDA_B P5_0 IO I2C2 serial data line. Open-drain output driver, requires external pull-up.
I2C2_SDA_C P5_7
I2C3 A/B/C
I2C3_SCL_A P1_1
I2C3_SCL_B P9_7 IO I2C3 serial clock line. Open-drain output driver, requires external pull-up.
I2C3_SCL_C P9_5
I2C3_SDA_A P1_0
I2C3_SDA_B P9_6 IO I2C3 serial data line. Open-drain output driver, requires external pull-up.
I2C3_SDA_C P9_4
LPI2C A/B
LPI2C_SCL_A P7_4
I LPI2C serial clock line. Slave-only, requires external pull-up.
LPI2C_SCL_B P5_2
LPI2C_SDA_A P7_5
IO LPI2C serial data line. Open-drain output driver, requires external pull-up.
LPI2C_SDA_B P5_3

3.16.4 I2S Overview

The Inter-IC Sound (I2S™) is a low pin count, serial bus standard for a stereo audio data link between ADCs,
DACs, CODECs, DSPs, and others. As the I2S only handles the transfer of audio data, the control and sub-
coding signals need to be transferred separately using a different bus interface (such as I2C).
The device includes:
n Up to two I2S modules in Shared Peripherals
n One Low-Power I2S module (LPI2S) in the RTSS-HE
Each I2S module supports the following main features:

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n I2S transmitter and receiver based on the Philips I2S serial protocol
n One stereo channel for transmitter and one for receiver
n Full duplex communication due to the independence of transmitter and receiver
n Master mode of operation
n Two input clock sources: 76.8 MHz or external audio clock
n 8, 16, 32, 44.1, 48, 88.2, 96, and 192 kHz sampling frequencies
n 16, 24, or 32 clocks word-select (left/right audio channel select)
n 12, 16, 20, 24, and 32 bits of audio data resolution
n FIFO depth of 16 words for each of receiver and transmitter
n Programmable FIFO thresholds
n DMA hardware handshaking interface
n 32-bit APB data bus
Table 3-16 presents I2S interface signals and provides descriptions to their functions.
Table 3-16 I2S Signal Descriptions
Signal Name Pin Name Type Description
I2S0 A/B
I2S0_SCLK_A P3_0
O I2S0 serial clock
I2S0_SCLK_B P4_3
I2S0_SDI_A P1_6
I I2S0 serial data input line
I2S0_SDI_B P4_1
I2S0_SDO_A P1_7
O I2S0 serial data output line
I2S0_SDO_B P4_2
I2S0_WS_A P3_1
O I2S0 word select line
I2S0_WS_B P4_4
I2S1 A/B
I2S1_SCLK_A P3_4
O I2S1 serial clock
I2S1_SCLK_B P12_2
I2S1_SDI_A P3_2
I I2S1 serial data input line
I2S1_SDI_B P12_0
I2S1_SDO_A P3_3
O I2S1 serial data output line
I2S1_SDO_B P12_1
I2S1_WS_A P4_0
O I2S1 word select line
I2S1_WS_B P12_3
LPI2S A/B/C
LPI2S_SCLK_A P2_6
LPI2S_SCLK_B P10_3 O LPI2S serial clock
LPI2S_SCLK_C P13_6
LPI2S_SDI_A P2_4
LPI2S_SDI_B P10_1 I LPI2S serial data input line
LPI2S_SDI_C P13_4
LPI2S_SDO_A P2_5
LPI2S_SDO_B P10_2 O LPI2S serial data output line
LPI2S_SDO_C P13_5
LPI2S_WS_A P2_7
LPI2S_WS_B P10_4 O LPI2S word select line
LPI2S_WS_C P13_7

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3.16.5 I3C Overview

The MIPI Improved Inter-Integrated Circuit (I3C) provides an interface to external I3C devices.
The device includes one I3C module.
The I3C module supports the following main features:
n Main Master function only
n Data rates:
l Fast Speed (FS) mode

l Fast Speed Plus (FS+) mode

l Single Data Rate (SDR) (up to 10 Mbps)

l High Data Rate—Double Data Rate (HDR-DDR) (up to 20 Mbps)

n Support for legacy I2C devices

n Separate command and data buffers for each of the transfers
n Buffer depths (each location can hold 4 bytes of data):
l Commands buffer: 8 (16 locations)

l Response buffer: 8 (8 locations)

l Transmit and receive data buffers: 64 (64 locations) each

n Up to 216 write/read bytes with a single command

n CRC/parity generation and validation
n Broadcast and directed Common Command Code (CCC) transfers
n DMA support through hardware handshake interface
n Autonomous clock stalling
n Device address table for addressing multiple slaves
n Dedicated buffer for capturing information from ENTDAA CCC command
n Detects arbitration loss due to incoming In-Band Interrupt (IBI) and subsequently re-transmits the
command
n Use of duty cycle to achieve lower effective speed for SDR transfers to work with slower I3C slaves
n Programmable Serial Data (SDA) transmit hold
n Programmable retry count for transfers that are addressed by slaves
n IBI with 16 locations of IBI Status and 64 locations of IBI Payload
n Byte support for vendor specific Broadcast and Directed CCC Transfers
Table 3-17 presents I3C interface signals and provides descriptions to their functions.
Table 3-17 I3C Signal Descriptions
Signal Name Pin Name Type Description
I3C A/B/C/D
I3C_SCL_A P0_1
I3C_SCL_B P1_3
IO I3C serial clock line
I3C_SCL_C P3_3
I3C_SCL_D P7_7
I3C_SDA_A P0_0
I3C_SDA_B P1_2
IO I3C serial data line
I3C_SDA_C P3_2
I3C_SDA_D P7_6

3.16.6 PDM Overview

The Pulse Density Modulation (PDM) module provides an interface to Digital Microphones (DMIC). The DMIC
signal first gets amplified, and then sampled at a high rate and quantized by a DMIC's internal PDM

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modulator. The device PDM module provides clock and decodes the received 1-bit PDM stream into 16-bit
values in Pulse Code Modulation (PCM) format.
The device includes:
n One PDM module in Shared Peripherals
n One Low-Power PDM module (LPPDM) in the RTSS-HE
Each PDM module supports the following main features:
n 4× 2-channel PDM microphone inputs for total support of up to 8 PDM channels (mono DMICs) for
PDM module
n 4× 2-channel PDM microphone inputs for total support of up to 8 PDM channels (mono DMICs) for
LPPDM module
n Audio signal bandwidth of up to 96 kHz
n DMA controller interface for storing audio samples
n 16-bit PCM output per channel
n Selection between 9 modes of PDM clock frequencies from 512 kHz to 4.8 MHz (oversampling). The
mode applies to all channels.
n Microphone sleep mode when at 128 kHz PDM clock
n Independent phase adjustment per channel to allow beam forming
n Independent gain adjustment per channel
n Independent peak detector per channel with programmable thresholds
n Peak detection interrupt per channel producing wake-up event
n Independent programmable DC blocking Infinite Impulse Response (IIR) filter per channel
n Independent programmable Finite Impulse Response (FIR) filter per channel
n FIFO with a capability to store up to 8 PCM samples for each channel for CPU to read
n Programmable FIFO watermark level to generate data available interrupt
n FIFO overrun error interrupt
Table 3-18 presents PDM interface signals and provides descriptions to their functions.
Table 3-18 PDM Signal Descriptions
Signal Name Pin Name Type Description
PDM A/B/C
AUDIO_CLK_A P8_0
AUDIO_CLK_B P9_6 I PDM and I2S clock input
AUDIO_CLK_C P12_0
PDM_C0_A P0_5
PDM_C0_B P3_1 O PDM clock output 0 to DMIC (shared by channels 0 and 1)
PDM_C0_C P6_1
PDM_C1_A P0_7
PDM_C1_B P3_3 O PDM clock output 1 to DMIC (shared by channels 2 and 3)
PDM_C1_C P6_3
PDM_C2_A P6_7
O PDM clock output 2 to DMIC (shared by channels 4 and 5)
PDM_C2_B P11_4
PDM_C3_A P5_2
O PDM clock output 3 to DMIC (shared by channels 6 and 7)
PDM_C3_B P11_5
PDM_D0_A P0_4
PDM_D0_B P3_0 I PDM data input 0 from DMIC (shared by channels 0 and 1)
PDM_D0_C P6_0

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Signal Name Pin Name Type Description

PDM_D1_A P0_6
PDM_D1_B P3_2 I PDM data input 1 from DMIC (shared by channels 2 and 3)
PDM_D1_C P6_2
PDM_D2_A P5_0
I PDM data input 2 from DMIC (shared by channels 4 and 5)
PDM_D2_B P5_4
PDM_D3_A P5_1
I PDM data input 3 from DMIC (shared by channels 6 and 7)
PDM_D3_B P5_5
LPPDM A/B
LPPDM_C0_A P2_1
O LPPDM clock output 0 to DMIC (shared by channels 0 and 1)
LPPDM_C0_B P3_4
LPPDM_C1_A P2_3
O LPPDM clock output 1 to DMIC (shared by channels 2 and 3)
LPPDM_C1_B P3_6
LPPDM_C2_A P7_4
O LPPDM clock output 2 to DMIC (shared by channels 4 and 5)
LPPDM_C2_B P11_2
LPPDM_C3_A P7_6
O LPPDM clock output 3 to DMIC (shared by channels 6 and 7)
LPPDM_C3_B P11_3
LPPDM_D0_A P2_0
I LPPDM data input 0 from DMIC (shared by channels 0 and 1)
LPPDM_D0_B P3_5
LPPDM_D1_A P2_2
I LPPDM data input 1 from DMIC (shared by channels 2 and 3)
LPPDM_D1_B P3_7
LPPDM_D2_A P7_5
I LPPDM data input 2 from DMIC (shared by channels 4 and 5)
LPPDM_D2_B P11_6
LPPDM_D3_A P7_7
I LPPDM data input 3 from DMIC (shared by channels 6 and 7)
LPPDM_D3_B P11_7

3.16.7 SPI Overview

The Serial Peripheral Interface (SPI) module is a programmable low pin count, full-duplex master or slave
synchronous serial interface.
The device includes:
n Up to four SPI modules in Shared Peripherals
n One Low-Power SPI module (LPSPI) in the RTSS-HE
The SPI modules support the following main features:
n 32-bit data bus width for AHB interface (SPI modules) and APB interface (LPSPI module)
n Standard SPI mode
n Up to four slave select lines for the SPI modules, one slave select line for the LPSPI module
n Multi-master contention detection
n Programmable delay on the sample time of received serial data bit when configured in Master mode
n Separate Transmit and Receive FIFO buffers:
l Buffer width of 32 bits

l Buffer depth of 16 words

n DMA requests
n Combined interrupt lines and active high-level interrupts
n Operation modes:
l Serial Master or Slave modes for the high-speed SPI modules

l Master mode only for LPSPI

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n Programmable frame formats:

l Motorola Serial Peripheral Interface
l Texas Instruments Synchronous Serial Protocol (SSP)

l National Semiconductor Microwire

n Programmable data transfer clock bit rate for dynamic control of the serial bit rate
n Programmable data item size (4 to 32 bits) for each data transfer
Table 3-19 presents SPI interface signals and provides descriptions to their functions.
Table 3-19 SPI Signal Descriptions
Signal Name Pin Name Type Description
SPI0 A/B/C
SPI0_SCLK_A P1_2
SPI0_SCLK_B P5_3 IO SPI0 serial clock (driven by master)
SPI0_SCLK_C P7_2
SPI0_SS0_A P1_3
In Master mode, slave select 0 output. In Slave mode, slave
SPI0_SS0_B P5_2 IO
select 0 input from an external master.
SPI0_SS0_C P7_3
SPI0_SS1_A P1_4
O SPI0 slave select 1 (driven by master)
SPI0_SS1_B P3_5
SPI0_SS2_A P1_5
O SPI0 slave select 2 (driven by master)
SPI0_SS2_B P3_6
SPI0_SS3_A P5_4
O SPI0 slave select 3 (driven by master)
SPI0_SS3_B P8_2
SPI0_MISO_A P1_0
SPI0_MISO_B P5_0 IO SPI0 master in slave out
SPI0_MISO_C P7_0
SPI0_MOSI_A P1_1
SPI0_MOSI_B P5_1 IO SPI0 master out slave in
SPI0_MOSI_C P7_1
SPI1 A/B/C
SPI1_SCLK_A P2_6
SPI1_SCLK_B P8_5 IO SPI1 serial clock (driven by master)
SPI1_SCLK_C P14_6
SPI1_SS0_A P2_7
In Master mode, slave select 0 output. In Slave mode, slave
SPI1_SS0_B P6_4 IO
select 0 input from an external master.
SPI1_SS0_C P14_7
SPI1_SS1_A P3_7
O SPI1 slave select 1 (driven by master)
SPI1_SS1_B P6_5
SPI1_SS2_A P4_0
O SPI1 slave select 2 (driven by master)
SPI1_SS2_B P6_6
SPI1_SS3_A P4_1
O SPI1 slave select 3 (driven by master)
SPI1_SS3_B P6_7
SPI1_MISO_A P2_4
SPI1_MISO_B P8_3 IO SPI1 master in slave out
SPI1_MISO_C P14_4
SPI1_MOSI_A P2_5 IO SPI1 master out slave in

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Signal Name Pin Name Type Description

SPI1_MOSI_B P8_4
SPI1_MOSI_C P14_5
SPI2 A/B
SPI2_SCLK_A P4_4
IO SPI2 serial clock (driven by master)
SPI2_SCLK_B P9_4
SPI2_SS0_A P4_5 In Master mode, slave select 0 output. In Slave mode, slave
IO
SPI2_SS0_B P9_5 select 0 input from an external master.
SPI2_SS1_A P4_6
O SPI2 slave select 1 (driven by master)
SPI2_SS1_B P9_6
SPI2_SS2_A P4_7
O SPI2 slave select 2 (driven by master)
SPI2_SS2_B P9_7
SPI2_SS3_A P13_3 O SPI2 slave select 3 (driven by master)
SPI2_SS3_B P10_0 O SPI2 slave select 3 (driven by master)
SPI2_MISO_A P4_2
IO SPI2 master in slave out
SPI2_MISO_B P9_2
SPI2_MOSI_A P4_3
IO SPI2 master out slave in
SPI2_MOSI_B P9_3
SPI3 A/B
SPI3_SCLK_A P12_6 IO SPI3 serial clock (driven by master)
SPI3_SCLK_B P10_7 IO SPI3 serial clock (driven by master)
SPI3_SS0_A P12_7 In Master mode, slave select 0 output. In Slave mode, slave
IO
SPI3_SS0_B P11_0 select 0 input from an external master.
SPI3_SS1_A P13_0 O SPI3 slave select 1 (driven by master)
SPI3_SS1_B P11_1 O SPI3 slave select 1 (driven by master)
SPI3_SS2_A P13_1 O SPI3 slave select 2 (driven by master)
SPI3_SS2_B P11_2 O SPI3 slave select 2 (driven by master)
SPI3_SS3_A P13_2 O SPI3 slave select 3 (driven by master)
SPI3_SS3_B P11_3 O SPI3 slave select 3 (driven by master)
SPI3_MISO_A P12_4 IO SPI3 master in slave out
SPI3_MISO_B P10_5 IO SPI3 master in slave out
SPI3_MOSI_A P12_5 IO SPI3 master out slave in
SPI3_MOSI_B P10_6 IO SPI3 master out slave in
LPSPI A/B
LPSPI_SCLK_A P7_6
IO LPSPI serial clock (driven by master)
LPSPI_SCLK_B P11_6
LPSPI_MISO_A P7_4
IO LPSPI master in slave out
LPSPI_MISO_B P11_4
LPSPI_MOSI_A P7_5
IO LPSPI master out slave in
LPSPI_MOSI_B P11_5
LPSPI_SS_A P7_7
IO LPSPI slave select output
LPSPI_SS_B P11_7

3.16.8 UART Overview

The Universal Asynchronous Receiver/Transmitter (UART) module implements asynchronous serial
communication interface based on standard Non-Return-to-Zero (NRZ) frame format.

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The device includes:

n Up to six UART modules in Shared Peripherals
n One Low-Power UART module (LPUART) in the RTSS-HE
n One UART module in the SESS (SEUART)—not accessible by user application
The UART modules are integrated in the following power domains:
n Power Domain PD-6: UART[0-5]
n Power Domain PD-2: LPUART
n Power Domain PD-5: SEUART
Each UART module supports the following main features:
n Full duplex operation
n Programmable baud rates up to 2.5 Mbps with a fractional baud rate divisor
n Interrupt driven or DMA controlled data transfer
n Auto flow control compatible with 16750 devices
n Configurable character length—5, 6, 7, 8 or 9 bits
n Optional parity bit—Even, Odd, Stick
n Number of stop bits—1, 1.5, 2 bits
n Line break generation and detection
n CTS/RTS signals for hardware flow control
n Drive enable output for RS485 interface support on UART[4-5] only
n Transmit (Tx) and Receive (Rx) FIFO depth of 32 characters
n Loopback mode for test and troubleshooting
n False start bit detection
n Compatible with the industry standard 16550 devices
Table 3-20 presents UART interface signals and provides descriptions to their functions.
Table 3-20 UART Signal Descriptions
Signal Name Pin Name Type Description
UART0 A/B
UART0_RX_A P0_0
I UART0 serial data input
UART0_RX_B P1_4
UART0_TX_A P0_1
O UART0 serial data output
UART0_TX_B P1_5
UART0_CTS_A P0_2
I UART0 clear to send
UART0_CTS_B P6_6
UART0_RTS_A P0_3
O UART0 request to send
UART0_RTS_B P6_7
UART1 A/B
UART1_RX_A P0_4
I UART1 serial data input
UART1_RX_B P1_6
UART1_TX_A P0_5
O UART1 serial data output
UART1_TX_B P1_7
UART1_CTS_A P0_6
I UART1 clear to send
UART1_CTS_B P5_6
UART1_RTS_A P0_7
O UART1 request to send
UART1_RTS_B P5_7
UART2 A/B

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Signal Name Pin Name Type Description

UART2_RX_A P1_0
I UART2 serial data input
UART2_RX_B P2_0
UART2_TX_A P1_1
O UART2 serial data output
UART2_TX_B P2_1
UART2_CTS_A P6_2
I UART2 clear to send
UART2_CTS_B P6_4
UART2_RTS_A P6_3
O UART2 request to send
UART2_RTS_B P6_5
UART3 A/B
UART3_RX_A P1_2
I UART3 serial data input
UART3_RX_B P2_2
UART3_TX_A P1_3
O UART3 serial data output
UART3_TX_B P2_3
UART3_CTS_A P5_4
I UART3 clear to send
UART3_CTS_B P7_2
UART3_RTS_A P5_5
O UART3 request to send
UART3_RTS_B P7_3
UART4 A/B/C
UART4_RX_A P3_0
UART4_RX_B P12_1 I UART4 serial data input
UART4_RX_C P5_0
UART4_TX_A P3_1
UART4_TX_B P12_2 O UART4 serial data output
UART4_TX_C P5_1
UART4_DE_A P6_0
O UART4 RS485 driver enable
UART4_DE_B P12_3
UART5 A/B/C
UART5_RX_A P3_4
UART5_RX_B P11_3 I UART5 serial data input
UART5_RX_C P5_2
UART5_TX_A P3_5
UART5_TX_B P11_4 O UART5 serial data output
UART5_TX_C P5_3
UART5_DE_A P6_1
O UART5 RS485 driver enable
UART5_DE_B P11_7
LPUART A/B
LPUART_RX_A P7_6
I LPUART serial data input
LPUART_RX_B P9_1
LPUART_TX_A P7_7
O LPUART serial data output
LPUART_TX_B P9_2
LPUART_CTS_A P7_4
I LPUART clear to send
LPUART_CTS_B P3_6
LPUART_RTS_A P7_5
O LPUART request to send
LPUART_RTS_B P3_7

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Signal Name Pin Name Type Description

SEUART
SEUART_RX SEUART_RX I SEUART serial data input
SEUART_TX SEUART_TX O SEUART serial data output

3.16.9 USB Overview

The Universal Serial Bus (USB) provides an expandable, bi-directional, hot-pluggable, serial interface that
allows to plug different peripherals into a USB port and have them automatically configured and ready to
use. USB host and devices use memory FIFO buffers to implement data endpoints used to accept or send
data from and to its endpoint counterpart.
The device includes one USB module. The USB module consists of an xHCI USB2.0 Dual-Role Device
(DRD) controller, a FIFO RAM, and an on-chip PHY.
The USB module supports the following main features:
n Compliant with USB Specification 2.0
n Four bi-directional endpoints including the bi-directional control endpoint 0
n Same programming model for Low-Speed (LS) (1.5 Mbit/s, host mode only), Full-Speed (FS) (12 Mbit/s),
and High-Speed (HS) (480 Mbit/s) bit rates
n Internal DMA controller
n Power-saving features (clock gating)
n Link Power Management (LPM) protocol
n Hardware-controlled LPM support in Host mode
n Single 1865 × 64-bit RAM, accommodating registers, descriptor cache, Rx buffers and Tx prefetch
l Dynamic FIFO memory allocation for endpoints

n Keep-alive feature in LS mode and (micro-)SOFs in FS and HS modes

n (micro-)SOFs (Start-of-Frame)
n Software-controlled standard USB commands (USB SETUP commands detected and forwarded to
application for decoding)
n Hardware-controlled USB bus level and packet level error handling
n Low CPU utilization needs
l Driver involved only in setting up transfers and high-level error recovery

l Hardware handles data packing and routing to a specific pipe

n Descriptor caching and data prefetching used to meet system performance in high-latency systems
n Interrupt moderation
n On-chip PHY via an USB 2.0 Transceiver Macrocell Interface (UTMI+)
Table 3-21 presents USB interface signals and provides descriptions to their functions.
Table 3-21 USB Signal Descriptions
Signal Name Pin Name Type Description
USB_DP USB_DP IO USB 2.0 differential data (positive)
USB_DM USB_DM IO USB 2.0 differential data (negative)
USB_VBUS USB_VBUS A USB VBUS-sense input
USB_IO_ID USB_IO_ID A USB A/B-device detect—leave unconnected (Device) or tie to ground (Host)
USB_REXT USB_REXT P External calibration resistor (200 Ω ±1%) to GND

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3.17 External Memory Interfaces

3.17.1 Cryptographic OSPI Overview

The cryptographic OSPI implementation in the device consists of the Octal Serial Peripheral Interface (OSPI)
module and the ancillary Advanced Encryption Standard (AES) engine.
The OSPI is an intelligent peripheral offering various memory expansion options. The OSPI can work either in
a direct access mode to directly read and write data to the external SPI memory, or in a decryption mode
where the incoming data is decrypted on-the-fly via the AES engine.
The device includes one OSPI module, assisted by a dedicated AES engine for the cryptographic operations.
The OSPI module supports the following main features:
n Single, Dual, Quad, or Octal SPI Master mode operation
n Up to 100 MHz clock for up to 100 MB/s Single Data Rate (SDR) and 200 MB/s Dual Data Rate (DDR)
support
n HyperBus protocol support for integration of HyperRAM™ modules
n Programmable instruction length, address length, wait cycles and data frame size
n Programmable option to skip address and instruction phase
n Read data strobe support in DDR mode for higher frequencies
n Support of Motorola Serial Peripheral Interface protocol
n DMA controller interface
n Programmable delay on the sample time of Received Serial Data (RXD) bit compensating routing delays
n Programmable frame size of each data transfer from 4 to 32 bits
n 256 words deep Rx and Tx FIFO buffers
n Execute-in-Place (XIP) support for read and write transfers—translates memory access requests to SPI
transactions for code memory expansion. This mode supports the following main features:
l Programmable instruction length and address length in XIP mode

l Data frame size mapping directly from AHB transfers

l Fixed data frame size for all the transfers

l Continuous transfer mode for read transactions

l Data mask support

l Configurable data pre-fetch during XIP read transaction

l Concurrent XIP and non-XIP transactions

n eXpanded SPI (xSPI) with all the command formats as described in JEDEC xSPI version 1.0
n Two xSPI command modes:
l 1S-1S-1S—one IO signal used during command transfer, command modifier transfer, and data

transfer. All phases are SDR.

l 8D-8D-8D—eight IO signals used during command transfer, command modifier transfer, and data

transfer. All phases are DDR.

The AES engine supports the following main features:
n On-the-fly decryption, transparent for the OSPI read transactions from external memory
n Electronic Codebook (ECB) mode of operation
n 256-bit long AES keys
n Secure setup and lockup of the decryption keys by the Secure Enclave at boot time
Table 3-22 presents OSPI interface signals and provides descriptions to their functions.

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CAUTION
The following pin multiplexing options are recommended:
- For OSPI, the OSPI0_D[0-7]_B data bus signals are recommended to be used for 100 MHz operation.
OSPI0_D[0-7]_A and OSPI0_D[0-7]_C data bus signals are recommended to be used for 50 MHz
operation.

Table 3-22 OSPI Signal Descriptions

Signal Name Pin Name Type Description
OSPI Data Bus A/B/C
OSPI0_D0_A P0_0
OSPI data input/output 0 in enhanced SPI modes. Data output (MOSI) in
OSPI0_D0_B P2_0 IO
standard SPI mode.
OSPI0_D0_C P6_0
OSPI0_D1_A P0_1
OSPI data input/output 1 in enhanced SPI modes. Data input (MISO) in
OSPI0_D1_B P2_1 IO
standard SPI mode.
OSPI0_D1_C P6_1
OSPI0_D2_A P0_2
OSPI0_D2_B P2_2 IO OSPI data 2
OSPI0_D2_C P6_2
OSPI0_D3_A P0_3
OSPI0_D3_B P2_3 IO OSPI data 3
OSPI0_D3_C P6_3
OSPI0_D4_A P0_4
OSPI0_D4_B P2_4 IO OSPI data 4
OSPI0_D4_C P6_4
OSPI0_D5_A P0_5
OSPI0_D5_B P2_5 IO OSPI data 5
OSPI0_D5_C P6_5
OSPI0_D6_A P0_6
OSPI0_D6_B P2_6 IO OSPI data 6
OSPI0_D6_C P6_6
OSPI0_D7_A P0_7
OSPI0_D7_B P2_7 IO OSPI data 7
OSPI0_D7_C P6_7
OSPI Clock, Slave Select, Data Strobe A/B/C
OSPI0_SCLKN_A P3_5
OSPI0_SCLKN_B P3_1 O OSPI serial clock (negative)
OSPI0_SCLKN_C P12_1
OSPI0_SCLK_A P1_7
OSPI0_SCLK_B P3_0 O OSPI serial clock
OSPI0_SCLK_C P12_0
OSPI0_RXDS_A P3_4
OSPI read data strobe (RXDS) when input. Data mask (TXD_DM) when
OSPI0_RXDS_B P1_6 IO
output.
OSPI0_RXDS_C P12_2
OSPI0_SS0_A P1_4 IO OSPI slave select 0

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Signal Name Pin Name Type Description

OSPI0_SS0_B P3_2
OSPI0_SS0_C P12_3
OSPI0_SS1_A P1_5
OSPI0_SS1_B P3_3 IO OSPI slave select 1
OSPI0_SS1_C P12_4

3.17.2 SDMMC Overview

The Secure Digital / MultiMediaCard (SDMMC) module provides an interface to embedded MultiMediaCard
(eMMC™), Secure Digital® (SD®) card, and SD Input/Output (SDIO). The communication between the SDMMC
module and eMMC/SD/SDIO device is performed according to the eMMC/SD/SDIO protocol.
The device includes one SDMMC module.
The SDMMC module supports the following main features:
n SD card interface:
l 4-bit data bus

l Complaint with SD Host Controller Standard Specification v4.20

l Complaint with SD Physical Layer Specification v6.00

l Backward compatible with earlier SD card specifications

l UHS-I mode

l Speed modes:

o Default-Speed (DS)
o High-Speed (HS)
o SDR12
o SDR25
o SDR50

n SDIO interface:
l 4-bit data bus

l Complaint with SD Specifications Part E1 SDIO Specification Version 4.10

l SDIO read wait

l SDIO card interrupts in both 1-bit and 4-bit modes

l Wake-up on card interrupt

n eMMC interface:
l 4-bit/8-bit data bus

l Complaint with JEDEC eMMC 5.1 Specification (JESD84-B51)

l Backward compatible with earlier eMMC specifications

l Speed legacy modes:

o High Speed SDR

l Boot operation and alternative boot operation

n 32-bit slave AHB and master AXI interface

n Data transfer types for SD and eMMC:
l CPU

l SDMA

l ADMA2

l ADMA3

n Clocking:
l Supports independent clocks for the Host controller, slave interface, and master interface

l Supports gating of Host controller base clock, if Host controller is inactive

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l Supports context aware functional clock gates

n Interrupt outputs:
l Combined and separate interrupt outputs

l Interrupt enabling and masking

n Data buffering:
l Automatic packing/unpacking of data to fit buffer width

Table 3-23 presents SDMMC interface signals and provides descriptions to their functions.

CAUTION
The following pin multiplexing options are recommended:
For SDMMC, the SD_*_C signals are recommended to be used for 50 MHz operation. SD_*_A, SD_*_
B, and SD_*_D signals are recommended to be used for 25 MHz operation.

Table 3-23 SDMMC Signal Descriptions

Signal Name Pin Name Type Description
SDMMC Data Bus A/B/C/D
SD_D0_A P5_0
SD_D0_B P13_0
IO SDMMC data line 0
SD_D0_C P8_0
SD_D0_D P6_0
SD_D1_A P5_1
SD_D1_B P13_1
IO SDMMC data line 1
SD_D1_C P8_1
SD_D1_D P6_1
SD_D2_A P5_2
SD_D2_B P13_2
IO SDMMC data line 2
SD_D2_C P8_2
SD_D2_D P6_2
SD_D3_A P5_3
SD_D3_B P13_3
IO SDMMC data line 3
SD_D3_C P8_3
SD_D3_D P6_3
SD_D4_A P5_4
SD_D4_B P13_4
IO SDMMC data line 4
SD_D4_C P8_4
SD_D4_D P6_4
SD_D5_A P5_5
SD_D5_B P13_5
IO SDMMC data line 5
SD_D5_C P8_5
SD_D5_D P6_5
SD_D6_A P5_6
SD_D6_B P13_6
IO SDMMC data line 6
SD_D6_C P8_6
SD_D6_D P6_6

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Signal Name Pin Name Type Description

SD_D7_A P5_7
SD_D7_B P13_7
IO SDMMC data line 7
SD_D7_C P8_7
SD_D7_D P6_7
SDIO Command, Clock, Reset A/B/C/D
SD_CMD_A P7_0 IO SDMMC command/response line
SD_CMD_B P14_0 IO SDMMC command/response line
SD_CMD_C P9_0 IO SDMMC command/response line
SD_CMD_D P4_2 IO SDMMC command/response line
SD_CLK_A P7_1 O SDMMC host to card clock line
SD_CLK_B P14_1 O SDMMC host to card clock line
SD_CLK_C P9_1 O SDMMC host to card clock line
SD_CLK_D P4_1 O SDMMC host to card clock line
SD_RST_A P7_2 O SDMMC reset line
SD_RST_B P14_2 O SDMMC reset line
SD_RST_C P9_2 O SDMMC reset line
SD_RST_D P4_3 O SDMMC reset line

3.18 Camera Interfaces

3.18.1 CPI Overview

The digital Camera Parallel Interface (CPI) enables pixel data reception from external CMOS sensors and
camera modules. The data transfer rate is limited by the maximum supported pixel clock and data bus width.
The device includes:
n One Low-Power CPI (LPCPI) controller in the RTSS-HE
The LPCPI controller supports the following main features:
n Up to 55 MHz pixel clock
n Up to 8-bit data bus width
n Programmable polarity for the pixel clock, horizontal and vertical synchronization signals
n Single frame capture (snapshot) mode
n Pixel clock output to external camera sensor
The LPCPI controller supports the following specific features:
n External camera sensor source:
l Data modes: 1-, 2-, 4-, and 8-bit
l Programmable MSB/LSB selection

l Transfer 10-bit pixel encoding over 8-bit wide data bus

Table 3-24 presents LPCPI interface signals and provides descriptions to their functions.

CAUTION
- For LPCAM_PCLK and LPCAM_XVCLK signals, recommended to be used are LPCAM_PCLK_A and
LPCAM_XVCLK_A pin multiplexing options.

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Table 3-24 LPCPI Signal Descriptions

Signal Name Pin Name Type Description
LPCPI Data Bus A/B/C
LPCAM_D0_A P8_0
LPCAM_D0_B P2_4 I LPCPI pixel data from external camera sensor bit [0]
LPCAM_D0_C P1_4
LPCAM_D1_A P8_1
LPCAM_D1_B P2_5 I LPCPI pixel data from external camera sensor bit [1]
LPCAM_D1_C P1_5
LPCAM_D2_A P8_2
LPCAM_D2_B P2_6 I LPCPI pixel data from external camera sensor bit [2]
LPCAM_D2_C P1_6
LPCAM_D3_A P8_3
LPCAM_D3_B P2_7 I LPCPI pixel data from external camera sensor bit [3]
LPCAM_D3_C P1_7
LPCAM_D4_A P8_4
LPCAM_D4_B P3_0 I LPCPI pixel data from external camera sensor bit [4]
LPCAM_D4_C P2_0
LPCAM_D5_A P8_5
LPCAM_D5_B P3_1 I LPCPI pixel data from external camera sensor bit [5]
LPCAM_D5_C P2_1
LPCAM_D6_A P8_6
LPCAM_D6_B P3_2 I LPCPI pixel data from external camera sensor bit [6]
LPCAM_D6_C P2_2
LPCAM_D7_A P8_7
LPCAM_D7_B P3_3 I LPCPI pixel data from external camera sensor bit [7]
LPCAM_D7_C P2_3
LPCPI Clock and Sync A/B/C
LPCAM_HSYNC_A P10_0
LPCAM_HSYNC_B P0_0 I LPCPI line valid from external camera sensor
LPCAM_HSYNC_C P1_0
LPCAM_VSYNC_A P10_1
LPCAM_VSYNC_B P0_1 I LPCPI vertical synchronization from external camera sensor
LPCAM_VSYNC_C P1_1
LPCAM_PCLK_A P10_2
LPCAM_PCLK_B P0_2 I LPCPI pixel clock from external camera sensor
LPCAM_PCLK_C P1_2
LPCAM_XVCLK_A P10_3
LPCAM_XVCLK_B P0_3 O LPCPI pixel clock to external camera sensor
LPCAM_XVCLK_C P1_3

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3.19 Display Interfaces

3.19.1 DPI Controller Overview

The Display Parallel Interface (DPI) provides a 24-bit RGB data bus either directly to LCD and TFT panels with
a resolution of up to WXGA (1280 × 800) or to the MIPI DSI Controller. In addition to the 24 data lines, the
interface includes pixel clock up to 50 MHz, horizontal and vertical synchronization pulses, and data enable
signals with configurable polarity.
The device includes a single Configurable DPI Controller (CDC).
The CDC supports the following main features:
n Configurable resolution and refresh rate
n Two display layers
n Programmable background color
n Color Look-Up Table (CLUT) with 256 × 24-bit entries per layer for indexed pixel formats
n Flexible blending between the layers using alpha value (pixel alpha or constant alpha)
n Color keying: defining transparent color for pixel formats without alpha channel
n Windowing: blending a programmable rectangular area of one layer into the other
n Gamma correction
n Dithering (2 bits per color component): providing softer color transitions for displays with less color
depth
n Multiple input pixel formats selectable per layer:
l ARGB8888, RGBA8888, RGB888, RGB565, ARGB1555, ARGB4444

l AL44 (4-bit alpha + 4-bit luminance) and L8 (8-bit luminance)

n RGB888 output pixel format

n Master Bus Interface (MBI): 64-bit AXI interface used for pixel data transfer
n Slave Bus Interface (SBI): 32-bit APB interface used for configuration
Table 3-25 presents DPI interface signals and provides descriptions to their functions.
Table 3-25 DPI Signal Descriptions
Signal Name Pin Name Type Description
DPI Data Bus A/B
CDC_D0_A P8_0
O DPI RGB pixel data output bit B[0]
CDC_D0_B P11_0
CDC_D1_A P8_1
O DPI RGB pixel data output bit B[1]
CDC_D1_B P11_1
CDC_D2_A P8_2
O DPI RGB pixel data output bit B[2]
CDC_D2_B P11_2
CDC_D3_A P8_3
O DPI RGB pixel data output bit B[3]
CDC_D3_B P11_3
CDC_D4_A P8_4
O DPI RGB pixel data output bit B[4]
CDC_D4_B P11_4
CDC_D5_A P8_5
O DPI RGB pixel data output bit B[5]
CDC_D5_B P11_5
CDC_D6_A P8_6
O DPI RGB pixel data output bit B[6]
CDC_D6_B P11_6
CDC_D7_A P8_7
O DPI RGB pixel data output bit B[7]
CDC_D7_B P11_7

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Signal Name Pin Name Type Description

CDC_D8_A P9_0
O DPI RGB pixel data output bit G[0]
CDC_D8_B P12_0
CDC_D9_A P9_1
O DPI RGB pixel data output bit G[1]
CDC_D9_B P12_1
CDC_D10_A P9_2
O DPI RGB pixel data output bit G[2]
CDC_D10_B P12_2
CDC_D11_A P9_3
O DPI RGB pixel data output bit G[3]
CDC_D11_B P12_3
CDC_D12_A P9_4
O DPI RGB pixel data output bit G[4]
CDC_D12_B P12_4
CDC_D13_A P9_5
O DPI RGB pixel data output bit G[5]
CDC_D13_B P12_5
CDC_D14_A P9_6
O DPI RGB pixel data output bit G[6]
CDC_D14_B P12_6
CDC_D15_A P9_7
O DPI RGB pixel data output bit G[7]
CDC_D15_B P12_7
CDC_D16_A P10_0
O DPI RGB pixel data output bit R[0]
CDC_D16_B P13_0
CDC_D17_A P10_1
O DPI RGB pixel data output bit R[1]
CDC_D17_B P13_1
CDC_D18_A P10_2
O DPI RGB pixel data output bit R[2]
CDC_D18_B P13_2
CDC_D19_A P10_3
O DPI RGB pixel data output bit R[3]
CDC_D19_B P13_3
CDC_D20_A P10_4
O DPI RGB pixel data output bit R[4]
CDC_D20_B P13_4
CDC_D21_A P10_5
O DPI RGB pixel data output bit R[5]
CDC_D21_B P13_5
CDC_D22_A P10_6
O DPI RGB pixel data output bit R[6]
CDC_D22_B P13_6
CDC_D23_A P10_7
O DPI RGB pixel data output bit R[7]
CDC_D23_B P13_7
DPI Clock and Sync A/B
CDC_DE_A P5_4
O DPI pixel data enable
CDC_DE_B P0_7
CDC_PCLK_A P5_3
O DPI pixel clock
CDC_PCLK_B P2_3
CDC_HSYNC_A P5_5
O DPI horizontal synchronization
CDC_HSYNC_B P4_1
CDC_VSYNC_A P5_6
O DPI vertical synchronization
CDC_VSYNC_B P4_0

3.19.2 DSI Overview

The MIPI Display Serial Interface (DSI) facilitates the communication and data transfer to a MIPI DSI
compliant display panel. The interface is realized through a MIPI DSI host controller that implements the

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protocol functions defined in the MIPI DSI Specification, and a MIPI D-PHY module acting as the physical
layer.
The device includes a single DSI implementation.
The DSI supports the following main features:
n Conformity to MIPI standards:
l MIPI Alliance Specification for Display Serial Interface (DSI) Version 1.2—16 June 2014
l MIPI Alliance Standard for Display Pixel Interface v2.00 (DPI-2)—15 September 2005

l MIPI Alliance Specification for Stereoscopic Display Formats (SDF) v1.0—22 November 2011

l MIPI Alliance Specification for D-PHY v1.2, 01 August 2014

n PPI between the DSI host controller and the D-PHY transmitter
n Up to two D-PHY TX data lanes
n Up to 2.5 Gbps throughput per lane
n Bidirectional communication and escape mode support through data lane 0
n End of Transmission Packet (EoTp)
n ECC and checksum capabilities
n Fault recovery schemes
n Stereoscopic (3D) image data transmission
n Video mode only
n Configurable MIPI Display Pixel Interface (DPI) to system level that provides:
l Data transfer in Video mode:

o Real-time pixel stream

o Shut Down Peripheral and Color Mode commands

l DPI interface color coding mappings into a 30-bit interface:

o 16-bit RGB
o 18-bit RGB
o 24-bit RGB

l Programmable polarity of all DPI interface signals

l The maximum resolution and frame rate are limited by the pixel clock and the available DSI physical

link bandwidth (defined by the number of lanes and the maximum speed per lane)
n Slave interface used for the transmission of generic commands
n Independently programmable virtual channel ID for the DPI and slave interfaces
n DPI payload FIFO with 1024 × 32-bit slots depth
n Generic command FIFO with 16 × 32-bit slots depth
n Generic payload FIFO with 128 × 32-bit slots depth
n Generic read FIFO with 32 × 32-bit slots depth
n Video mode pattern generator with the following capabilities:
l Vertical and horizontal color bar generation without DPI stimuli

l PHY Bit-Error Ratio (BER) pattern without DPI stimuli

The DSI does not support the following features:

n Command mode
n VESA® Display Stream Compression (DSC) standard
Table 3-26 presents MIPI DSI interface signals and provides descriptions to their functions.
Table 3-26 MIPI DSI Signal Descriptions
Signal Name Pin Name Type Description
MIPIDSI_0_P MIPIDSI_0_P IO DSI D-PHY Tx differential data lane 0 (positive)
MIPIDSI_0_N MIPIDSI_0_N IO DSI D-PHY Tx differential data lane 0 (negative)
MIPIDSI_1_P MIPIDSI_1_P O DSI D-PHY Tx differential data lane 1 (positive)

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Signal Name Pin Name Type Description

MIPIDSI_1_N MIPIDSI_1_N O DSI D-PHY Tx differential data lane 1 (negative)
MIPIDSI_C_P MIPIDSI_C_P O DSI D-PHY Tx differential clock lane (positive)
MIPIDSI_C_N MIPIDSI_C_N O DSI D-PHY Tx differential clock lane (negative)
MIPI_REXT MIPI_REXT P DSI D-PHY Tx external reference resistor (200 Ω, ±1%) connection

3.20 Analog Peripherals

3.20.1 ADC Overview

The Analog-to-Digital Converter (ADC) modules are 12-bit/24-bit, multi-input units used for analog signals
conversion into digital values.
The device includes two ADC12 and one ADC24 modules.
ADC12 modules support the following main features:
n 12-bit Successive Approximation Register (SAR) ADC
n Conversion rate of up to 2.5 MSPS
n 6 external inputs and two internal inputs:
l 6 external pins may be configured to 6 single-ended or 3 differential inputs

l One input from the on-chip temperature sensor (TSENS)

l One input from internal voltage reference

ADC24 supports the following main features:

n 24-bit Sigma-Delta ADC
n Conversion rate of up to 16 kSPS
n 4 external differential inputs
ADC12 and ADC24 common features:
n Programmable gain instrumentation amplifier (up to 38 dB gain)
n On-chip offset calibration and factory calibrated gain error
n Widely programmable sample time
n Hardware averaging option (up to 256 samples) for enhanced Signal-to-Noise Ratio (SNR)
l ADC12 must use hardware averaging at all times, with a minimum of two samples per average

n Flexible digital user interface:

l Programmable input scan modes:
o Single-shot or continuous conversions
o A sequencer can be programmed to loop over a selection of inputs

l Conversions can be triggered also externally by UTIMER events or QEC pins

l Conversion results can be stored into sample registers and to SRAM via DMA

l Hardware data shift:

o 1 to 12 bits left shift

o 1 to 12 bits right shift (up to 8 bits for the averaging function plus 4 bits more)

l Threshold and window detection options. A comparator logic can generate interrupts when an input

signal passes programmable thresholds

n Designed for low power operation:
l ADC sample rate is selectable via a clock divider

l ADC power consumption decreases as sample rate decreases

n The ADC12, ADC24, as well as other analog peripherals, are powered from a dedicated internal 1.8-V
LDO

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For information on ADC interface signals and their descriptions, see Section 3.20.6 Analog Signals.

3.20.2 DAC12 Overview

The Digital-to-Analog Converter (DAC12) module converts 12-bit digital values into analog voltage signals.
The analog output range is between 0 V and 1.8 V in LP mode.
The device includes one DAC12 module.
The DAC12 module supports the following main features:
n Up to 1 MHz conversion rate at 12-bit resolution
n Accepts unsigned binary or two’s complement signed digital data
n Programmable output current up to 1.5 mA
n Programmable load capacitance compensation
n Internal 1.8-V voltage reference
n Excellent high-frequency Power Supply Rejection Ratio (PSRR)
n Maximum current output up to 1.5 mA
n Software-selectable low-power (LP) or high-performance (HP) modes
l HP mode handles larger resistive load at the expense of higher power consumption

l LP mode handles slow sample rate and light resistive load for power savings

For information on DAC interface signals and their descriptions, see Section 3.20.6 Analog Signals.

3.20.3 CMP Overview

The High-Speed Comparator (CMP) module is a rail-to-rail, multi-input, analog comparator with
programmable reference voltage and hysteresis.
The device includes up to two CMP modules.
Each CMP module supports the following main features:
n Reference voltage from DAC6, internal Vref, or external pins
n Programmable hysteresis
n Windowing (gating) driven by one of four events from UTIMER and QEC
n Comparator result inverter
n Configurable number of taps for filtering
n Interrupt generation after filtering
n Response time: < 5 ns
n Power supply from internal 1.8-V LDO (LDO-5)

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Figure 3-11 CMP Overview

Device
CMP[0-1]
CMP[0-1]_IN0 0
IRQ
CMP[0-1]_IN1 1
AMUX
CMP[0-1]_IN2 2

CMP[0-1]_IN3 3
CMP[0-1]_OUT
VREF_IN0 0

VREF_IN1 1
Internal AMUX
2 MUX
Vref
1 0
DAC6 3

UT0_T1

UT0_T0

CMP-004
For information on CMP interface signals and their descriptions, see Section 3.20.6 Analog Signals.
Table 3-27 presents the CMP digital outputs.
Table 3-27 CMP Signal Descriptions
Signal Name Pin Name Type Description
CMP Outputs A/B
CMP0_OUT_A P7_3
O CMP0 comparison result output
CMP0_OUT_B P14_7
CMP1_OUT_A P7_2
O CMP1 comparison result output
CMP1_OUT_B P14_6

3.20.4 LPCMP Overview

The Low-Power Comparator (LPCMP) module is a low power, rail-to-rail, analog comparator with selectable
reference voltage and hysteresis.
The device includes a single LPCMP module located in the PD0 domain.
The LPCMP supports the following main features:
n Up to four external pins for voltage monitoring
n Voltage reference from:
l Internal AON 0.8-V voltage reference or

l External VREF pins

n Programmable hysteresis
n Power supply from VDD_IO_1V8 pin
n Response time: < 10 µs
For information on LPCMP interface signals and their descriptions, see Section 3.20.6 Analog Signals.

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3.20.5 TSENS Overview

The Temperature Sensor (TSENS) generates a voltage VTEMP that varies linearly with temperature.
The TSENS is connected internally to an input channel of each ADC12 module. The ADC converts the sensor
output voltage into a digital value. The actual temperature can be obtained using the ADC12 driver.
The sensor provides good linearity and accuracy of better than 2.4 °C. Additional calibration can be applied to
obtain accuracies below 1 °C.

3.20.6 Analog Signals

Table 3-28 shows how the analog signals are mapped simultaneously to functions of the analog modules.
Each signal can be used by more than one module at a time.
Table 3-28 Analog Signal Functions Mapping
Function by Module
Signal Name
ADC12 ADC24 DAC CMP LPCMP
ANA_S0 ADC120_IN0 ADC24_IN0_P CMP0_IN0
ANA_S1 ADC120_IN1 ADC24_IN1_P CMP1_IN0
ANA_S2 ADC120_IN2 ADC24_IN2_P
ANA_S3 ADC120_IN3 ADC24_IN3_P
ANA_S4 ADC120_IN4 ADC24_IN0_N CMP0_IN3
ANA_S5 ADC120_IN5 ADC24_IN1_N CMP1_IN3
ANA_S6 ADC121_IN0 ADC24_IN2_N CMP0_IN1
ANA_S7 ADC121_IN1 ADC24_IN3_N CMP1_IN1
ANA_S8 ADC121_IN2
ANA_S9 ADC121_IN3
ANA_S10 ADC121_IN4
ANA_S11 ADC121_IN5
ANA_S12 CMP0_IN2
ANA_S13 CMP1_IN2
ANA_S14
ANA_S15
ANA_S16 VREF_IN0
ANA_S17 VREF_IN1
ANA_S18 DAC12_0_OUT VREF_IN2
ANA_S19
ANA_S20 LPCMP_IN0
ANA_S21 LPCMP_IN1
ANA_S22 LPCMP_IN2
ANA_S23 LPCMP_IN3

Table 3-29 presents the analog signals with the respective mapping to the analog modules and provides
descriptions to their functions.
Table 3-29 Analog Signal Descriptions
Signal Name Pin Name Type Description
ADC120_IN0 (ADC120 input 0)
ANA_S0 P0_0 A
ADC24_IN0_P (ADC24 differential input 0 positive)

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Signal Name Pin Name Type Description

CMP0_IN0 (CMP0 input 0)
ADC120_IN1 (ADC120 input 1)
ANA_S1 P0_1 A ADC24_IN1_P (ADC24 differential input 1 positive)
CMP1_IN0 (CMP1 input 0)
ADC120_IN2 (ADC120 input 2)
ANA_S2 P0_2 A
ADC24_IN2_P (ADC24 differential input 2 positive)
ADC120_IN3 (ADC120 input 3)
ANA_S3 P0_3 A
ADC24_IN3_P (ADC24 differential input 3 positive)
ADC120_IN4 (ADC120 input 4)
ANA_S4 P0_4 A ADC24_IN0_N (ADC24 differential input 0 negative)
CMP0_IN3 (CMP0 input 3)
ADC120_IN5 (ADC120 input 5)
ANA_S5 P0_5 A ADC24_IN1_N (ADC24 differential input 1 negative)
CMP1_IN3 (CMP1 input 3)
ADC121_IN0 (ADC121 input 0)
ANA_S6 P0_6 A ADC24_IN2_N (ADC24 differential input 2 negative)
CMP0_IN1 (CMP0 input 1)
ADC121_IN1 (ADC121 input 1)
ANA_S7 P0_7 A ADC24_IN3_N (ADC24 differential input 3 negative)
CMP1_IN1 (CMP1 input 1)
ANA_S8 P1_0 A ADC121_IN2 (ADC121 input 2)
ANA_S9 P1_1 A ADC121_IN3 (ADC121 input 3)
ANA_S10 P1_2 A ADC121_IN4 (ADC121 input 4)
ANA_S11 P1_3 A ADC121_IN5 (ADC121 input 5)
ANA_S12 P1_4 A CMP0_IN2 (CMP0 input 2)
ANA_S13 P1_5 A CMP1_IN2 (CMP1 input 2)
ANA_S14 P1_6 A -
ANA_S15 P1_7 A -
ANA_S16 P2_0 A VREF_IN0 (CMP0-CMP1 and LPCMP reference voltage input 0)
ANA_S17 P2_1 A VREF_IN1 (CMP0-CMP1 and LPCMP reference voltage input 1)
DAC12_0_OUT (DAC120 output)
ANA_S18 P2_2 A
VREF_IN2 (LPCMP reference voltage input 2)
ANA_S19 P2_3 A -
ANA_S20 P2_4 A LPCMP_IN0 (LPCMP input 0)
ANA_S21 P2_5 A LPCMP_IN1 (LPCMP input 1)
ANA_S22 P2_6 A LPCMP_IN2 (LPCMP input 2)
ANA_S23 P2_7 A LPCMP_IN3 (LPCMP input 3)

3.21 Debug Infrastructure

To support the debug of multiple cores running simultaneously, the device provides an extensive debug
infrastructure, compliant with the Arm® Debug Interface Architecture Specification ADIv6.0. The debug
features include:
n JTAG debug support
n Serial Wire Debug (SWD) support
n External debug of SE or RTSS-HE by an off-chip debugger
n Debug through power down for RTSS-HE

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n Debug from reset for all systems

n Support for single or multi-system debug
n Trace and cross trigger capabilities
Table 3-30 presents JTAG interface signals and provides descriptions to their functions.
Table 3-30 JTAG Signal Descriptions
Signal Name Pin Name Type Description
JTAG
JTAG_TCK P4_4 I JTAG test clock input
JTAG_TMS P4_5 I JTAG test mode select input
JTAG_TDI P4_6 I JTAG test data input
JTAG_TDO P4_7 O JTAG test data output
JTAG_TDATA0 P4_0 O JTAG trace data output 0
JTAG_TDATA1 P4_1 O JTAG trace data output 1
JTAG_TDATA2 P4_2 O JTAG trace data output 2
JTAG_TDATA3 P4_3 O JTAG trace data output 3
JTAG_TRACECLK P3_7 O JTAG trace clock output

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4 Pin Assignments

4.1 Pin Location per Package Type

4.1.1 FBGA194 Package Pin Location Assignment

Figure 4-1 presents a simplified diagram of the FBGA194 package pin locations and pin functions after reset.
Figure 4-1 FBGA194 Pin Location Assignment Diagram
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

VDD_ VDD_SX_ VDD_IO_ GPIO12_ SEUART_ SEUART_ GPIO13_ GPIO13_

A HFXO_N HFXO_P GPIO3_1 GPIO8_3 GPIO7_3 GPIO6_7 GPIO6_2 GPIO6_0 GPIO5_0 GPIO4_6 GPIO4_5
PLL_0V8 0V8 1V8 5 TX RX 7 5

VDD_
GPIO14_ GPIO13_
B N.C. VSS GPIO7_1 GPIO8_4 CORE_ GPIO3_0 GPIO8_0 GPIO7_0 GPIO6_3 GPIO5_7 GPIO5_6 GPIO5_3 GPIO5_1 GPIO4_7 GPIO4_4 GPIO4_3 GPIO4_1
0 6
0V8

C N.C. GPIO8_1 GPIO8_2 VSS GPIO4_2

GPIO12_ GPIO12_ VDD_IO_

D GPIO7_2
7 3 1V8

VDD_ VDD_
GPIO12_ GPIO13_ GPIO13_ GPIO12_ GPIO12_
E CORE_ GPIO3_2 GPIO6_6 GPIO6_5 GPIO6_4 GPIO6_1 GPIO5_5 GPIO5_4 GPIO5_2 CORE_
6 3 4 2 1
0V8 0V8

GPIO12_ GPIO13_ GPIO12_

F GPIO3_5 GPIO3_4 GPIO4_0
4 2 0

GPIO14_ GPIO13_ GPIO13_

G GPIO3_3 GPIO9_2 GPIO2_4
2 1 0

GPIO14_
H GPIO8_5 GPIO9_3 GPIO2_3 GPIO2_6 GPIO2_5
1

GPIO11_
J GPIO8_7 GPIO8_6 GPIO9_4 N.C. VSS N.C. NSRST GPIO2_2 GPIO1_7 GPIO2_7
5

GPIO11_ GPIO14_
K GPIO9_1 GPIO9_0 GPIO9_6 VSS VSS VSS GPIO1_3 GPIO2_1 GPIO2_0
4 6

GPIO11_ GPIO14_ GPIO14_

L GPIO9_5 VSS GPIO9_7 GPIO3_7 VSS GPIO1_2 GPIO1_5 GPIO1_6
7 5 7

GPIO10_ GPIO10_ GPIO10_

M GPIO1_1 N.C. GPIO1_4
1 0 4

VREG_
GPIO10_ GPIO10_ GPIO10_
N GPIO0_5 VREF_P MIPI_
2 3 5
1V8

GPIO10_ GPIO11_ GPIO10_ VDD_

P GPIO0_6 VSS_ANA
7 0 6 MAIN

GPIO11_ GPIO11_ GPIO11_ GPIO11_ GPIO14_ GPIO14_ USB_IO_ VDD_

R GPIO0_4 GPIO0_3 GPIO0_2 GPIO0_1 GPIO1_0 GPIO0_7 GPIO0_0
1 2 3 6 3 4 ID BUCK

VDD_
T GPIO7_4 GPIO7_5 VSW
BATT

VREG_ VREG_
U GPIO7_7 GPIOV_2 GPIO7_6 POR_N
AON DIG_1V8

VDD_ VREG_
USB_ MIPIDSI_ MIPIDSI_ MIPIDSI_ MIPI_ VSS_
V GPIOV_3 GPIOV_0 GPIOV_4 GPIOV_6 GPIO3_6 CORE_ USB_DM VSS N.C. N.C. N.C. LFXO_P AUX_
REXT 1_N C_P 0_N REXT BUCK
0V8 1V8
VREG_
VDD_IO_ VDD_IO_ USB_ VDD_ MIPIDSI_ MIPIDSI_ MIPIDSI_ VDD_ VREG_ VREG_
W GPIOV_1 GPIOV_5 GPIOV_7 USB_DP N.C. N.C. N.C. LFXO_N CORE_
FLEX 1V8 VBUS USB_3V3 1_P C_N 0_P MIPI_1V8 MIPI_0V8 LP_1V8
0V8

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For detailed information about package outlines, thermal characteristics, and markings, see Section 6.2.1
FBGA194 Package Information.

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4.2 Pin Function Options by Location

Table 4-1 describes the pin functions available as multiplexed on each pin.

CAUTION
The following pin multiplexing options are recommended:
- For OSPI, the OSPI0_D[0-7]_B data bus signals are recommended to be used for 100 MHz operation. OSPI0_D[0-7]_A and OSPI0_D[0-7]_C
data bus signals are recommended to be used for 50 MHz operation.
- For SDMMC, the SD_*_C signals are recommended to be used for 50 MHz operation. SD_*_A, SD_*_B, and SD_*_D signals are
recommended to be used for 25 MHz operation.
- For LPCAM_PCLK and LPCAM_XVCLK signals, recommended to be used are LPCAM_PCLK_A and LPCAM_XVCLK_A pin multiplexing options.

Table 4-1 Pin Function Options by Location

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type
Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO0_0 IO 0
OSPI0_D0_A IO 1
UART0_RX_A I 2
LVCMOS
P0_0 R19 I3C_SDA_A IO 3 P0_0 VDD_IO_1V8
ANALOG
UT0_T0_A IO 4
LPCAM_HSYNC_B I 5
ANA_S0 A 7
GPIO0_1 IO 0
OSPI0_D1_A IO 1
UART0_TX_A O 2
LVCMOS
P0_1 R13 I3C_SCL_A IO 3 P0_1 VDD_IO_1V8
ANALOG
UT0_T1_A IO 4
LPCAM_VSYNC_B I 5
ANA_S1 A 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO0_2 IO 0
OSPI0_D2_A IO 1
UART0_CTS_A I 2
LVCMOS
P0_2 R12 I2C0_SDA_A IO 3 P0_2 VDD_IO_1V8
ANALOG
UT1_T0_A IO 4
LPCAM_PCLK_B I 5
ANA_S2 A 7
GPIO0_3 IO 0
OSPI0_D3_A IO 1
UART0_RTS_A O 2
LVCMOS
P0_3 R11 I2C0_SCL_A IO 3 P0_3 VDD_IO_1V8
ANALOG
UT1_T1_A IO 4
LPCAM_XVCLK_B O 5
ANA_S3 A 7
GPIO0_4 IO 0
OSPI0_D4_A IO 1
UART1_RX_A I 2
PDM_D0_A I 3 LVCMOS
P0_4 R10 P0_4 VDD_IO_1V8
I2C1_SDA_A IO 4 ANALOG
UT2_T0_A IO 5
CAN_RXD_B I 6
ANA_S4 A 7
GPIO0_5 IO 0
OSPI0_D5_A IO 1
UART1_TX_A O 2
PDM_C0_A O 3 LVCMOS
P0_5 N15 P0_5 VDD_IO_1V8
I2C1_SCL_A IO 4 ANALOG
UT2_T1_A IO 5
CAN_TXD_B O 6
ANA_S5 A 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO0_6 IO 0
OSPI0_D6_A IO 1
UART1_CTS_A I 2
PDM_D1_A I 3 LVCMOS
P0_6 P15 P0_6 VDD_IO_1V8
I2C2_SCL_A IO 4 ANALOG
UT3_T0_A IO 5
CAN_STBY_B O 6
ANA_S6 A 7
GPIO0_7 IO 0
OSPI0_D7_A IO 1
UART1_RTS_A O 2
PDM_C1_A O 3 LVCMOS
P0_7 R15 P0_7 VDD_IO_1V8
I2C2_SDA_A IO 4 ANALOG
UT3_T1_A IO 5
CDC_DE_B O 6
ANA_S7 A 7
GPIO1_0 IO 0
UART2_RX_A I 1
SPI0_MISO_A IO 2
LVCMOS
P1_0 R14 I2C3_SDA_A IO 3 P1_0 VDD_IO_1V8
ANALOG
UT4_T0_A IO 4
LPCAM_HSYNC_C I 5
ANA_S8 A 7
GPIO1_1 IO 0
UART2_TX_A O 1
SPI0_MOSI_A IO 2
LVCMOS
P1_1 M15 I2C3_SCL_A IO 3 P1_1 VDD_IO_1V8
ANALOG
UT4_T1_A IO 4
LPCAM_VSYNC_C I 5
ANA_S9 A 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO1_2 IO 0
UART3_RX_A I 1
SPI0_SCLK_A IO 2
LVCMOS
P1_2 L15 I3C_SDA_B IO 3 P1_2 VDD_IO_1V8
ANALOG
UT5_T0_A IO 4
LPCAM_PCLK_C I 5
ANA_S10 A 7
GPIO1_3 IO 0
UART3_TX_A O 1
SPI0_SS0_A IO 2
LVCMOS
P1_3 K15 I3C_SCL_B IO 3 P1_3 VDD_IO_1V8
ANALOG
UT5_T1_A IO 4
LPCAM_XVCLK_C O 5
ANA_S11 A 7
GPIO1_4 IO 0
OSPI0_SS0_A IO 1
UART0_RX_B I 2
LVCMOS
P1_4 M19 SPI0_SS1_A O 3 P1_4 VDD_IO_1V8
ANALOG
UT6_T0_A IO 4
LPCAM_D0_C I 5
ANA_S12 A 7
GPIO1_5 IO 0
OSPI0_SS1_A IO 1
UART0_TX_B O 2
LVCMOS
P1_5 L18 SPI0_SS2_A O 3 P1_5 VDD_IO_1V8
ANALOG
UT6_T1_A IO 4
LPCAM_D1_C I 5
ANA_S13 A 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO1_6 IO 0
OSPI0_RXDS_B IO 1
UART1_RX_B I 2
LVCMOS
P1_6 L19 I2S0_SDI_A I 3 P1_6 VDD_IO_1V8
ANALOG
UT7_T0_A IO 4
LPCAM_D2_C I 5
ANA_S14 A 7
GPIO1_7 IO 0
OSPI0_SCLK_A O 1
UART1_TX_B O 2
LVCMOS
P1_7 J18 I2S0_SDO_A O 3 P1_7 VDD_IO_1V8
ANALOG
UT7_T1_A IO 4
LPCAM_D3_C I 5
ANA_S15 A 7
GPIO2_0 IO 0
OSPI0_D0_B IO 1
UART2_RX_B I 2 LVCMOS
P2_0 K19 P2_0 VDD_IO_1V8
LPPDM_D0_A I 3 ANALOG
LPCAM_D4_C I 5
ANA_S16 A 7
GPIO2_1 IO 0
OSPI0_D1_B IO 1
UART2_TX_B O 2 LVCMOS
P2_1 K18 P2_1 VDD_IO_1V8
LPPDM_C0_A O 3 ANALOG
LPCAM_D5_C I 5
ANA_S17 A 7
GPIO2_2 IO 0
OSPI0_D2_B IO 1
UART3_RX_B I 2 LVCMOS
P2_2 J15 P2_2 VDD_IO_1V8
LPPDM_D1_A I 3 ANALOG
LPCAM_D6_C I 5
ANA_S18 A 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO2_3 IO 0
OSPI0_D3_B IO 1
UART3_TX_B O 2
LVCMOS
P2_3 H15 LPPDM_C1_A O 3 P2_3 VDD_IO_1V8
ANALOG
LPCAM_D7_C I 5
CDC_PCLK_B O 6
ANA_S19 A 7
GPIO2_4 IO 0
OSPI0_D4_B IO 1
LPI2S_SDI_A I 2 LVCMOS
P2_4 G19 P2_4 VDD_IO_1V8
SPI1_MISO_A IO 3 ANALOG
LPCAM_D0_B I 5
ANA_S20 A 7
GPIO2_5 IO 0
OSPI0_D5_B IO 1
LPI2S_SDO_A O 2 LVCMOS
P2_5 H19 P2_5 VDD_IO_1V8
SPI1_MOSI_A IO 3 ANALOG
LPCAM_D1_B I 5
ANA_S21 A 7
GPIO2_6 IO 0
OSPI0_D6_B IO 1
LPI2S_SCLK_A O 2 LVCMOS
P2_6 H18 P2_6 VDD_IO_1V8
SPI1_SCLK_A IO 3 ANALOG
LPCAM_D2_B I 5
ANA_S22 A 7
GPIO2_7 IO 0
OSPI0_D7_B IO 1
LPI2S_WS_A O 2 LVCMOS
P2_7 J19 P2_7 VDD_IO_1V8
SPI1_SS0_A IO 3 ANALOG
LPCAM_D3_B I 5
ANA_S23 A 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO3_0 IO 0
OSPI0_SCLK_B O 1
UART4_RX_A I 2
P3_0 B6 PDM_D0_B I 3 P3_0 LVCMOS VDD_IO_1V8
I2S0_SCLK_A O 4
QEC0_X_A I 5
LPCAM_D4_B I 6
GPIO3_1 IO 0
OSPI0_SCLKN_B O 1
UART4_TX_A O 2
P3_1 A6 PDM_C0_B O 3 P3_1 LVCMOS VDD_IO_1V8
I2S0_WS_A O 4
QEC0_Y_A I 5
LPCAM_D5_B I 6
GPIO3_2 IO 0
OSPI0_SS0_B IO 1
PDM_D1_B I 2
P3_2 E2 I2S1_SDI_A I 3 P3_2 LVCMOS VDD_IO_1V8
I3C_SDA_C IO 4
QEC0_Z_A I 5
LPCAM_D6_B I 6
GPIO3_3 IO 0
OSPI0_SS1_B IO 1
PDM_C1_B O 2
P3_3 G2 I2S1_SDO_A O 3 P3_3 LVCMOS VDD_IO_1V8
I3C_SCL_C IO 4
QEC1_X_A I 5
LPCAM_D7_B I 6

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO3_4 IO 0
OSPI0_RXDS_A IO 1
UART5_RX_A I 2
P3_4 F2 LPPDM_C0_B O 3 P3_4 LVCMOS VDD_IO_1V8
I2S1_SCLK_A O 4
I2C0_SCL_B IO 5
QEC1_Y_A I 6
GPIO3_5 IO 0
OSPI0_SCLKN_A O 1
UART5_TX_A O 2
P3_5 F1 LPPDM_D0_B I 3 P3_5 LVCMOS VDD_IO_1V8
SPI0_SS1_B O 4
I2C0_SDA_B IO 5
QEC1_Z_A I 6
GPIO3_6 IO 0
HFXO_OUT_A O 1
LPUART_CTS_B I 2
P3_6 V5 LPPDM_C1_B O 3 P3_6 LVCMOS VDD_IO_1V8
SPI0_SS2_B O 4
I2C1_SDA_B IO 5
QEC2_X_A I 6
GPIO3_7 IO 0
JTAG_TRACECLK O 1
LPUART_RTS_B O 2
P3_7 L8 LPPDM_D1_B I 3 P3_7 LVCMOS VDD_IO_1V8
SPI1_SS1_A O 4
I2C1_SCL_B IO 5
QEC2_Y_A I 6

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO4_0 IO 0
JTAG_TDATA0 O 1
I2S1_WS_A O 3
P4_0 F18 P4_0 LVCMOS VDD_IO_1V8
SPI1_SS2_A O 4
QEC2_Z_A I 5
CDC_VSYNC_B O 6
GPIO4_1 IO 0
JTAG_TDATA1 O 1
I2S0_SDI_B I 2
P4_1 B19 SPI1_SS3_A O 3 P4_1 LVCMOS VDD_IO_1V8
QEC3_X_A I 4
SD_CLK_D O 5
CDC_HSYNC_B O 6
GPIO4_2 IO 0
JTAG_TDATA2 O 1
I2S0_SDO_B O 3
P4_2 C19 P4_2 LVCMOS VDD_IO_1V8
SPI2_MISO_A IO 4
QEC3_Y_A I 5
SD_CMD_D IO 6
GPIO4_3 IO 0
JTAG_TDATA3 O 1
I2S0_SCLK_B O 3
P4_3 B18 P4_3 LVCMOS VDD_IO_1V8
SPI2_MOSI_A IO 4
QEC3_Z_A I 5
SD_RST_D O 6
GPIO4_4 IO 0
JTAG_TCK I 1
P4_4 B17 I2S0_WS_B O 2 P4_4 LVCMOS VDD_IO_1V8
SPI2_SCLK_A IO 3
FAULT0_A I 4

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO4_5 IO 0
JTAG_TMS I 1
P4_5 A19 P4_5 LVCMOS VDD_IO_1V8
SPI2_SS0_A IO 2
FAULT1_A I 3
GPIO4_6 IO 0
JTAG_TDI I 1
P4_6 A18 P4_6 LVCMOS VDD_IO_1V8
SPI2_SS1_A O 2
FAULT2_A I 3
GPIO4_7 IO 0
JTAG_TDO O 1
P4_7 B16 P4_7 LVCMOS VDD_IO_1V8
SPI2_SS2_A O 2
FAULT3_A I 3
GPIO5_0 IO 0
UART4_RX_C I 2
PDM_D2_A I 3
P5_0 A16 SPI0_MISO_B IO 4 P5_0 LVCMOS VDD_IO_1V8
I2C2_SDA_B IO 5
UT0_T0_B IO 6
SD_D0_A IO 7
GPIO5_1 IO 0
UART4_TX_C O 2
PDM_D3_A I 3
P5_1 B14 SPI0_MOSI_B IO 4 P5_1 LVCMOS VDD_IO_1V8
I2C2_SCL_B IO 5
UT0_T1_B IO 6
SD_D1_A IO 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO5_2 IO 0
UART5_RX_C I 2
PDM_C3_A O 3
P5_2 E12 SPI0_SS0_B IO 4 P5_2 LVCMOS VDD_IO_1V8
LPI2C_SCL_B I 5
UT1_T0_B IO 6
SD_D2_A IO 7
GPIO5_3 IO 0
UART5_TX_C O 2
SPI0_SCLK_B IO 3
P5_3 B13 LPI2C_SDA_B IO 4 P5_3 LVCMOS VDD_IO_1V8
UT1_T1_B IO 5
SD_D3_A IO 6
CDC_PCLK_A O 7
GPIO5_4 IO 0
UART3_CTS_A I 2
PDM_D2_B I 3
P5_4 E11 SPI0_SS3_A O 4 P5_4 LVCMOS VDD_IO_1V8
UT2_T0_B IO 5
SD_D4_A IO 6
CDC_DE_A O 7
GPIO5_5 IO 0
UART3_RTS_A O 2
PDM_D3_B I 3
P5_5 E10 P5_5 LVCMOS VDD_IO_1V8
UT2_T1_B IO 4
SD_D5_A IO 5
CDC_HSYNC_A O 7

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO5_6 IO 0
UART1_CTS_B I 2
I2C2_SCL_C IO 3
P5_6 B12 P5_6 LVCMOS VDD_IO_1V8
UT3_T0_B IO 4
SD_D6_A IO 5
CDC_VSYNC_A O 7
GPIO5_7 IO 0
UART1_RTS_B O 2
P5_7 B11 I2C2_SDA_C IO 3 P5_7 LVCMOS VDD_IO_1V8
UT3_T1_B IO 4
SD_D7_A IO 5
GPIO6_0 IO 0
OSPI0_D0_C IO 1
UART4_DE_A O 2
P6_0 A12 P6_0 LVCMOS VDD_IO_1V8
PDM_D0_C I 3
UT4_T0_B IO 4
SD_D0_D IO 5
GPIO6_1 IO 0
OSPI0_D1_C IO 1
UART5_DE_A O 2
P6_1 E9 P6_1 LVCMOS VDD_IO_1V8
PDM_C0_C O 3
UT4_T1_B IO 4
SD_D1_D IO 5
GPIO6_2 IO 0
OSPI0_D2_C IO 1
UART2_CTS_A I 2
P6_2 A11 P6_2 LVCMOS VDD_IO_1V8
PDM_D1_C I 4
UT5_T0_B IO 5
SD_D2_D IO 6

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO6_3 IO 0
OSPI0_D3_C IO 1
UART2_RTS_A O 2
P6_3 B10 P6_3 LVCMOS VDD_IO_1V8
PDM_C1_C O 4
UT5_T1_B IO 5
SD_D3_D IO 6
GPIO6_4 IO 0
OSPI0_D4_C IO 1
UART2_CTS_B I 2
P6_4 E8 P6_4 LVCMOS VDD_IO_1V8
SPI1_SS0_B IO 4
UT6_T0_B IO 5
SD_D4_D IO 6
GPIO6_5 IO 0
OSPI0_D5_C IO 1
UART2_RTS_B O 2
P6_5 E7 P6_5 LVCMOS VDD_IO_1V8
SPI1_SS1_B O 4
UT6_T1_B IO 5
SD_D5_D IO 6
GPIO6_6 IO 0
OSPI0_D6_C IO 1
UART0_CTS_B I 2
P6_6 E6 P6_6 LVCMOS VDD_IO_1V8
SPI1_SS2_B O 4
UT7_T0_B IO 5
SD_D6_D IO 6
GPIO6_7 IO 0
OSPI0_D7_C IO 1
UART0_RTS_B O 2
P6_7 A9 PDM_C2_A O 3 P6_7 LVCMOS VDD_IO_1V8
SPI1_SS3_B O 4
UT7_T1_B IO 5
SD_D7_D IO 6

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO7_0 IO 0
SPI0_MISO_C IO 3
P7_0 B8 I2C0_SDA_C IO 4 P7_0 LVCMOS VDD_IO_1V8
SD_CMD_A IO 6
CAN_RXD_A I 7
GPIO7_1 IO 0
SPI0_MOSI_C IO 3
P7_1 B3 I2C0_SCL_C IO 4 P7_1 LVCMOS VDD_IO_1V8
SD_CLK_A O 6
CAN_TXD_A O 7
GPIO7_2 IO 0
UART3_CTS_B I 2
CMP1_OUT_A O 3
P7_2 D1 P7_2 LVCMOS VDD_IO_1V8
SPI0_SCLK_C IO 4
I2C1_SDA_C IO 5
SD_RST_A O 7
GPIO7_3 IO 0
UART3_RTS_B O 2
CMP0_OUT_A O 3
P7_3 A8 P7_3 LVCMOS VDD_IO_1V8
SPI0_SS0_C IO 4
I2C1_SCL_C IO 5
CAN_STBY_A O 7
GPIO7_4 IO 0
LPUART_CTS_A I 2
Dual Voltage
P7_4 T1 LPPDM_C2_A O 3 P7_4 VDD_IO_FLEX
LVCMOS
LPSPI_MISO_A IO 4
LPI2C_SCL_A I 5
GPIO7_5 IO 0
LPUART_RTS_A O 2
Dual Voltage
P7_5 T2 LPPDM_D2_A I 4 P7_5 VDD_IO_FLEX
LVCMOS
LPSPI_MOSI_A IO 5
LPI2C_SDA_A IO 6

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO7_6 IO 0
LPUART_RX_A I 2
Dual Voltage
P7_6 U3 LPPDM_C3_A O 4 P7_6 VDD_IO_FLEX
LVCMOS
LPSPI_SCLK_A IO 5
I3C_SDA_D IO 6
GPIO7_7 IO 0
LPUART_TX_A O 2
Dual Voltage
P7_7 U1 LPPDM_D3_A I 4 P7_7 VDD_IO_FLEX
LVCMOS
LPSPI_SS_A IO 5
I3C_SCL_D IO 6
GPIO8_0 IO 0
AUDIO_CLK_A I 2
FAULT0_B I 3
P8_0 B7 P8_0 LVCMOS VDD_IO_1V8
LPCAM_D0_A I 4
SD_D0_C IO 5
CDC_D0_A O 6
GPIO8_1 IO 0
FAULT1_B I 2
P8_1 C2 LPCAM_D1_A I 3 P8_1 LVCMOS VDD_IO_1V8
SD_D1_C IO 4
CDC_D1_A O 5
GPIO8_2 IO 0
SPI0_SS3_B O 2
FAULT2_B I 3
P8_2 C3 P8_2 LVCMOS VDD_IO_1V8
LPCAM_D2_A I 4
SD_D2_C IO 5
CDC_D2_A O 6

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO8_3 IO 0
SPI1_MISO_B IO 2
FAULT3_B I 3
P8_3 A7 P8_3 LVCMOS VDD_IO_1V8
LPCAM_D3_A I 4
SD_D3_C IO 5
CDC_D3_A O 6
GPIO8_4 IO 0
SPI1_MOSI_B IO 2
QEC0_X_B I 3
P8_4 B4 P8_4 LVCMOS VDD_IO_1V8
LPCAM_D4_A I 4
SD_D4_C IO 5
CDC_D4_A O 6
GPIO8_5 IO 0
SPI1_SCLK_B IO 2
QEC0_Y_B I 3
P8_5 H1 P8_5 LVCMOS VDD_IO_1V8
LPCAM_D5_A I 4
SD_D5_C IO 5
CDC_D5_A O 6
GPIO8_6 IO 0
QEC0_Z_B I 3
P8_6 J2 LPCAM_D6_A I 4 P8_6 LVCMOS VDD_IO_1V8
SD_D6_C IO 5
CDC_D6_A O 6
GPIO8_7 IO 0
QEC1_X_B I 3
P8_7 J1 LPCAM_D7_A I 4 P8_7 LVCMOS VDD_IO_1V8
SD_D7_C IO 5
CDC_D7_A O 6
GPIO9_0 IO 0
QEC1_Y_B I 3
P9_0 K2 P9_0 LVCMOS VDD_IO_1V8
SD_CMD_C IO 4
CDC_D8_A O 5

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 E1 Series

FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO9_1 IO 0
LPUART_RX_B I 1
P9_1 K1 QEC1_Z_B I 3 P9_1 LVCMOS VDD_IO_1V8
SD_CLK_C O 4
CDC_D9_A O 5
GPIO9_2 IO 0
LPUART_TX_B O 1
SPI2_MISO_B IO 3
P9_2 G5 P9_2 LVCMOS VDD_IO_1V8
QEC2_X_B I 4
SD_RST_C O 5
CDC_D10_A O 6
GPIO9_3 IO 0
HFXO_OUT_B O 1
P9_3 H5 SPI2_MOSI_B IO 4 P9_3 LVCMOS VDD_IO_1V8
QEC2_Y_B I 5
CDC_D11_A O 6
GPIO9_4 IO 0
SPI2_SCLK_B IO 3
P9_4 J5 I2C3_SDA_C IO 4 P9_4 LVCMOS VDD_IO_1V8
QEC2_Z_B I 5
CDC_D12_A O 6
GPIO9_5 IO 0
SPI2_SS0_B IO 3
P9_5 L1 I2C3_SCL_C IO 4 P9_5 LVCMOS VDD_IO_1V8
QEC3_X_B I 5
CDC_D13_A O 6
GPIO9_6 IO 0
AUDIO_CLK_B I 2
SPI2_SS1_B O 3
P9_6 K5 P9_6 LVCMOS VDD_IO_1V8
I2C3_SDA_B IO 4
QEC3_Y_B I 5
CDC_D14_A O 6

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO9_7 IO 0
SPI2_SS2_B O 3
P9_7 L5 I2C3_SCL_B IO 4 P9_7 LVCMOS VDD_IO_1V8
QEC3_Z_B I 5
CDC_D15_A O 6
GPIO10_0 IO 0
SPI2_SS3_B O 3
P10_0 M2 UT0_T0_C IO 4 P10_0 LVCMOS VDD_IO_1V8
LPCAM_HSYNC_A I 5
CDC_D16_A O 6
GPIO10_1 IO 0
LPI2S_SDI_B I 3
P10_1 M1 UT0_T1_C IO 4 P10_1 LVCMOS VDD_IO_1V8
LPCAM_VSYNC_A I 5
CDC_D17_A O 6
GPIO10_2 IO 0
LPI2S_SDO_B O 3
P10_2 N1 UT1_T0_C IO 4 P10_2 LVCMOS VDD_IO_1V8
LPCAM_PCLK_A I 5
CDC_D18_A O 6
GPIO10_3 IO 0
LPI2S_SCLK_B O 3
P10_3 N2 UT1_T1_C IO 4 P10_3 LVCMOS VDD_IO_1V8
LPCAM_XVCLK_A O 5
CDC_D19_A O 6
GPIO10_4 IO 0
LPI2S_WS_B O 3
P10_4 M5 I2C0_SDA_D IO 4 P10_4 LVCMOS VDD_IO_1V8
UT2_T0_C IO 5
CDC_D20_A O 7

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO10_5 IO 0
SPI3_MISO_B IO 3
P10_5 N5 I2C0_SCL_D IO 4 P10_5 LVCMOS VDD_IO_1V8
UT2_T1_C IO 5
CDC_D21_A O 7
GPIO10_6 IO 0
SPI3_MOSI_B IO 3
P10_6 P5 I2C1_SDA_D IO 4 P10_6 LVCMOS VDD_IO_1V8
UT3_T0_C IO 5
CDC_D22_A O 7
GPIO10_7 IO 0
SPI3_SCLK_B IO 3
P10_7 P1 I2C1_SCL_D IO 4 P10_7 LVCMOS VDD_IO_1V8
UT3_T1_C IO 5
CDC_D23_A O 6
GPIO11_0 IO 0
SPI3_SS0_B IO 4
P11_0 P2 P11_0 LVCMOS VDD_IO_1V8
UT4_T0_C IO 5
CDC_D0_B O 7
GPIO11_1 IO 0
SPI3_SS1_B O 3
P11_1 R1 P11_1 LVCMOS VDD_IO_1V8
UT4_T1_C IO 4
CDC_D1_B O 6
GPIO11_2 IO 0
LPPDM_C2_B O 3
P11_2 R2 SPI3_SS2_B O 4 P11_2 LVCMOS VDD_IO_1V8
UT5_T0_C IO 5
CDC_D2_B O 7

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO11_3 IO 0
UART5_RX_B I 2
LPPDM_C3_B O 3
P11_3 R5 P11_3 LVCMOS VDD_IO_1V8
SPI3_SS3_B O 4
UT5_T1_C IO 5
CDC_D3_B O 7
GPIO11_4 IO 0
UART5_TX_B O 2
PDM_C2_B O 3
P11_4 K8 P11_4 LVCMOS VDD_IO_1V8
LPSPI_MISO_B IO 4
UT6_T0_C IO 5
CDC_D4_B O 7
GPIO11_5 IO 0
PDM_C3_B O 3
P11_5 J9 LPSPI_MOSI_B IO 4 P11_5 LVCMOS VDD_IO_1V8
UT6_T1_C IO 5
CDC_D5_B O 7
GPIO11_6 IO 0
LPPDM_D2_B I 3
P11_6 R6 LPSPI_SCLK_B IO 4 P11_6 LVCMOS VDD_IO_1V8
UT7_T0_C IO 5
CDC_D6_B O 7
GPIO11_7 IO 0
UART5_DE_B O 2
LPPDM_D3_B I 3
P11_7 L9 P11_7 LVCMOS VDD_IO_1V8
LPSPI_SS_B IO 4
UT7_T1_C IO 5
CDC_D7_B O 7

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO12_0 IO 0
OSPI0_SCLK_C O 1
P12_0 F19 AUDIO_CLK_C I 2 P12_0 LVCMOS VDD_IO_1V8
I2S1_SDI_B I 3
CDC_D8_B O 5
GPIO12_1 IO 0
OSPI0_SCLKN_C O 1
P12_1 E18 UART4_RX_B I 2 P12_1 LVCMOS VDD_IO_1V8
I2S1_SDO_B O 3
CDC_D9_B O 5
GPIO12_2 IO 0
OSPI0_RXDS_C IO 1
P12_2 E15 UART4_TX_B O 2 P12_2 LVCMOS VDD_IO_1V8
I2S1_SCLK_B O 3
CDC_D10_B O 5
GPIO12_3 IO 0
OSPI0_SS0_C IO 1
P12_3 D18 UART4_DE_B O 2 P12_3 LVCMOS VDD_IO_1V8
I2S1_WS_B O 3
CDC_D11_B O 5
GPIO12_4 IO 0
OSPI0_SS1_C IO 1
P12_4 F5 SPI3_MISO_A IO 2 P12_4 LVCMOS VDD_IO_1V8
CAN_RXD_C I 4
CDC_D12_B O 5
GPIO12_5 IO 0
SPI3_MOSI_A IO 2
P12_5 A10 P12_5 LVCMOS VDD_IO_1V8
CAN_TXD_C O 4
CDC_D13_B O 5

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO12_6 IO 0
SPI3_SCLK_A IO 2
P12_6 E5 P12_6 LVCMOS VDD_IO_1V8
CAN_STBY_C O 4
CDC_D14_B O 5
GPIO12_7 IO 0
P12_7 D2 SPI3_SS0_A IO 3 P12_7 LVCMOS VDD_IO_1V8
CDC_D15_B O 5
GPIO13_0 IO 0
SPI3_SS1_A O 3
P13_0 G18 QEC0_X_C I 4 P13_0 LVCMOS VDD_IO_1V8
SD_D0_B IO 5
CDC_D16_B O 6
GPIO13_1 IO 0
SPI3_SS2_A O 2
P13_1 G15 QEC0_Y_C I 3 P13_1 LVCMOS VDD_IO_1V8
SD_D1_B IO 4
CDC_D17_B O 5
GPIO13_2 IO 0
SPI3_SS3_A O 2
P13_2 F15 QEC0_Z_C I 3 P13_2 LVCMOS VDD_IO_1V8
SD_D2_B IO 4
CDC_D18_B O 5
GPIO13_3 IO 0
SPI2_SS3_A O 2
P13_3 E13 QEC1_X_C I 3 P13_3 LVCMOS VDD_IO_1V8
SD_D3_B IO 4
CDC_D19_B O 5
GPIO13_4 IO 0
LPI2S_SDI_C I 2
P13_4 E14 QEC1_Y_C I 3 P13_4 LVCMOS VDD_IO_1V8
SD_D4_B IO 4
CDC_D20_B O 5

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO13_5 IO 0
LPI2S_SDO_C O 2
P13_5 A17 QEC1_Z_C I 3 P13_5 LVCMOS VDD_IO_1V8
SD_D5_B IO 4
CDC_D21_B O 5
GPIO13_6 IO 0
LPI2S_SCLK_C O 2
P13_6 B15 QEC2_X_C I 3 P13_6 LVCMOS VDD_IO_1V8
SD_D6_B IO 4
CDC_D22_B O 5
GPIO13_7 IO 0
LPI2S_WS_C O 2
P13_7 A15 QEC2_Y_C I 3 P13_7 LVCMOS VDD_IO_1V8
SD_D7_B IO 4
CDC_D23_B O 5
GPIO14_0 IO 0
P14_0 B9 QEC2_Z_C I 3 P14_0 LVCMOS VDD_IO_1V8
SD_CMD_B IO 4
GPIO14_1 IO 0
P14_1 H2 QEC3_X_C I 4 P14_1 LVCMOS VDD_IO_1V8
SD_CLK_B O 5
GPIO14_2 IO 0
P14_2 G1 QEC3_Y_C I 4 P14_2 LVCMOS VDD_IO_1V8
SD_RST_B O 5
GPIO14_3 IO 0
P14_3 R7 P14_3 LVCMOS VDD_IO_1V8
QEC3_Z_C I 4
GPIO14_4 IO 0
P14_4 R8 SPI1_MISO_C IO 2 P14_4 LVCMOS VDD_IO_1V8
FAULT0_C I 3
GPIO14_5 IO 0
P14_5 L11 SPI1_MOSI_C IO 2 P14_5 LVCMOS VDD_IO_1V8
FAULT1_C I 3

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
GPIO14_6 IO 0
CMP1_OUT_B O 1
P14_6 K12 P14_6 LVCMOS VDD_IO_1V8
SPI1_SCLK_C IO 2
FAULT2_C I 3
GPIO14_7 IO 0
CMP0_OUT_B O 1
P14_7 L12 P14_7 LVCMOS VDD_IO_1V8
SPI1_SS0_C IO 2
FAULT3_C I 3
GPIOV_0 IO Dual Voltage
P15_0 V2 LPGPIO_CTRL_0 VDD_IO_FLEX
LPTMR0_CLK_IO IO LVCMOS
GPIOV_1 IO Dual Voltage
P15_1 W2 LPGPIO_CTRL_1 VDD_IO_FLEX
LPTMR1_CLK_IO IO LVCMOS
Dual Voltage
P15_2 U2 GPIOV_2 IO LPGPIO_CTRL_2 VDD_IO_FLEX
LVCMOS
Dual Voltage
P15_3 V1 GPIOV_3 IO LPGPIO_CTRL_3 VDD_IO_FLEX
LVCMOS
P15_4 V3 GPIOV_4 IO LPGPIO_CTRL_4 LVCMOS VDD_IO_1V8
P15_5 W4 GPIOV_5 IO LPGPIO_CTRL_5 LVCMOS VDD_IO_1V8
P15_6 V4 GPIOV_6 IO LPGPIO_CTRL_6 LVCMOS VDD_IO_1V8
P15_7 W5 GPIOV_7 IO LPGPIO_CTRL_7 LVCMOS VDD_IO_1V8
SEUART_RX A14 SEUART_RX I LVCMOS VDD_IO_1V8
SEUART_TX A13 SEUART_TX O LVCMOS VDD_IO_1V8
B1, C1, J8, J11,
M18, V14, V15,
N.C. N.C. N.C.
V16, W14, W15,
W16
NSRST J12 NSRST I LVCMOS VDD_IO_1V8
POR_N U18 POR_N I LVCMOS VDD_IO_1V8
HFXO_P A4 HFXO_P I LVCMOS VDD_IO_1V8
HFXO_N A3 HFXO_N O LVCMOS VDD_IO_1V8
LFXO_P V17 LFXO_P I LVCMOS VDD_IO_1V8
LFXO_N W17 LFXO_N O LVCMOS VDD_IO_1V8

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
VREF_P N18 VREF_P A
VDD_MAIN P19 VDD_MAIN PWR
VDD_BATT T18 VDD_BATT PWR
VDD_BUCK R18 VDD_BUCK PWR
VDD_IO_FLEX W1 VDD_IO_FLEX PWR
VDD_IO_1V8 A5, D19, W3 VDD_IO_1V8 PWR
VDD_CORE_0V8 B5, E1, E19, V6 VDD_CORE_0V8 PWR
VREG_MIPI_0V8 W13 VREG_MIPI_0V8 PWR
VDD_MIPI_1V8 W12 VDD_MIPI_1V8 PWR
VDD_USB_3V3 W8 VDD_USB_3V3 PWR
VDD_SX_0V8 A2 VDD_SX_0V8 PWR
VDD_PLL_0V8 A1 VDD_PLL_0V8 PWR
B2, C18, J10, K9,
VSS K10, K11, L2, L10, VSS GND
V12
VSS_BUCK V19 VSS_BUCK GND
VSS_ANA P18 VSS_ANA GND
VREG_CORE_0V8 W18 VREG_CORE_0V8 PWR
VREG_AON U17 VREG_AON PWR
VREG_LP_1V8 W19 VREG_LP_1V8 PWR
VREG_DIG_1V8 U19 VREG_DIG_1V8 PWR
VREG_AUX_1V8 V18 VREG_AUX_1V8 PWR
VREG_MIPI_1V8 N19 VREG_MIPI_1V8 PWR
VSW T19 VSW PWR
USB_REXT V8 USB_REXT P USBPHY VDD_USB_3V3
USB_DP W7 USB_DP IO USBPHY VDD_USB_3V3
USB_DM V7 USB_DM IO USBPHY VDD_USB_3V3
USB_VBUS W6 USB_VBUS A USBPHY VDD_USB_3V3
USB_IO_ID R9 USB_IO_ID A USBPHY VDD_USB_3V3
MIPI_REXT V13 MIPI_REXT P DSIPHY VDD_MIPI_1V8
MIPIDSI_0_P W11 MIPIDSI_0_P O DSIPHY VDD_MIPI_1V8
MIPIDSI_0_N V11 MIPIDSI_0_N O DSIPHY VDD_MIPI_1V8

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FBGA194 Pin Type Multiplexing Configuration Register Buffer Type

Pin Name (1) Signal Name (3) Power Rail (8)
Pin Location (2) (4) Number (5) (6) (7)
MIPIDSI_1_P W9 MIPIDSI_1_P O DSIPHY VDD_MIPI_1V8
MIPIDSI_1_N V9 MIPIDSI_1_N O DSIPHY VDD_MIPI_1V8
MIPIDSI_C_P V10 MIPIDSI_C_P O DSIPHY VDD_MIPI_1V8
MIPIDSI_C_N W10 MIPIDSI_C_N O DSIPHY VDD_MIPI_1V8

The list below describes the column headers:

1. Pin Name—Name of the pin. Px_y pins have several functions (mux modes) to select from. The functions of other pins are fixed.
2. Pin Location—Pad or ball number of the corresponding device package.
3. Signal Name—Signal(s) that can be routed to the particular pin. If a signal is routable to more than one pin, a suffix _A, _B, _C, or _D is added to the signal
name for differentiation. A group of signals with the same suffix is also known as Pin Set.
4. Pin Type—Pin designation (for the multiplexed pins, it depends on the selected mux mode):
l A—Analog

l I—Digital Input

l O—Digital Output

l IO—Digital Bi-directional (Input/Output)

l R—Radio frequency

l P—Passive

l PWR—Power

l GND—Ground

l N/A—Not Available. This ball does not exist on the package.

l N.C.—No Connect

5. Multiplexing Number—Function number used in the pin configuration registers:

l 0 is the GPIO function

l 1 through 7 are possible alternative functions

l An empty box means Not Applicable

6. Configuration Register—Associated pin control register. For more information on registers, refer to the corresponding series-specific Hardware Reference
Manual, Section Signal Multiplexing and I/O Buffer Configuration.
7. Buffer Type—Associated I/O buffer type, if applicable:
l LVCMOS—1.8-V Low-Voltage CMOS digital I/O buffer

l Dual-Voltage (Flex) LVCMOS—1.8-V and 3.3-V LVCMOS digital I/O buffer

l Analog—Analog input or output

l RF—Radio Frequency input or output

l USBPHY—HS USB data bus PHY and I/Os

l CSIPHY—MIPI CSI camera PHY and I/Os

l DSIPHY—MIPI DSI display PHY and I/Os

8. Power Rail—I/O buffer power supply, if applicable.

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4.3 Pin Function Multiplexing

Table 4-2 describes the pin functions multiplexing options.
Table 4-2 Pin Function Multiplexing
Pin Name 0 1 2 3 4 5 6 7
P0_0 GPIO0_0 OSPI0_D0_A UART0_RX_A I3C_SDA_A UT0_T0_A LPCAM_HSYNC_B ANA_S0
P0_1 GPIO0_1 OSPI0_D1_A UART0_TX_A I3C_SCL_A UT0_T1_A LPCAM_VSYNC_B ANA_S1
P0_2 GPIO0_2 OSPI0_D2_A UART0_CTS_A I2C0_SDA_A UT1_T0_A LPCAM_PCLK_B ANA_S2
P0_3 GPIO0_3 OSPI0_D3_A UART0_RTS_A I2C0_SCL_A UT1_T1_A LPCAM_XVCLK_B ANA_S3
P0_4 GPIO0_4 OSPI0_D4_A UART1_RX_A PDM_D0_A I2C1_SDA_A UT2_T0_A CAN_RXD_B ANA_S4
P0_5 GPIO0_5 OSPI0_D5_A UART1_TX_A PDM_C0_A I2C1_SCL_A UT2_T1_A CAN_TXD_B ANA_S5
P0_6 GPIO0_6 OSPI0_D6_A UART1_CTS_A PDM_D1_A I2C2_SCL_A UT3_T0_A CAN_STBY_B ANA_S6
P0_7 GPIO0_7 OSPI0_D7_A UART1_RTS_A PDM_C1_A I2C2_SDA_A UT3_T1_A CDC_DE_B ANA_S7
P1_0 GPIO1_0 UART2_RX_A SPI0_MISO_A I2C3_SDA_A UT4_T0_A LPCAM_HSYNC_C ANA_S8
P1_1 GPIO1_1 UART2_TX_A SPI0_MOSI_A I2C3_SCL_A UT4_T1_A LPCAM_VSYNC_C ANA_S9
P1_2 GPIO1_2 UART3_RX_A SPI0_SCLK_A I3C_SDA_B UT5_T0_A LPCAM_PCLK_C ANA_S10
P1_3 GPIO1_3 UART3_TX_A SPI0_SS0_A I3C_SCL_B UT5_T1_A LPCAM_XVCLK_C ANA_S11
P1_4 GPIO1_4 OSPI0_SS0_A UART0_RX_B SPI0_SS1_A UT6_T0_A LPCAM_D0_C ANA_S12
P1_5 GPIO1_5 OSPI0_SS1_A UART0_TX_B SPI0_SS2_A UT6_T1_A LPCAM_D1_C ANA_S13
P1_6 GPIO1_6 OSPI0_RXDS_B UART1_RX_B I2S0_SDI_A UT7_T0_A LPCAM_D2_C ANA_S14
P1_7 GPIO1_7 OSPI0_SCLK_A UART1_TX_B I2S0_SDO_A UT7_T1_A LPCAM_D3_C ANA_S15
P2_0 GPIO2_0 OSPI0_D0_B UART2_RX_B LPPDM_D0_A LPCAM_D4_C ANA_S16
P2_1 GPIO2_1 OSPI0_D1_B UART2_TX_B LPPDM_C0_A LPCAM_D5_C ANA_S17
P2_2 GPIO2_2 OSPI0_D2_B UART3_RX_B LPPDM_D1_A LPCAM_D6_C ANA_S18
P2_3 GPIO2_3 OSPI0_D3_B UART3_TX_B LPPDM_C1_A LPCAM_D7_C CDC_PCLK_B ANA_S19
P2_4 GPIO2_4 OSPI0_D4_B LPI2S_SDI_A SPI1_MISO_A LPCAM_D0_B ANA_S20
P2_5 GPIO2_5 OSPI0_D5_B LPI2S_SDO_A SPI1_MOSI_A LPCAM_D1_B ANA_S21
P2_6 GPIO2_6 OSPI0_D6_B LPI2S_SCLK_A SPI1_SCLK_A LPCAM_D2_B ANA_S22
P2_7 GPIO2_7 OSPI0_D7_B LPI2S_WS_A SPI1_SS0_A LPCAM_D3_B ANA_S23
P3_0 GPIO3_0 OSPI0_SCLK_B UART4_RX_A PDM_D0_B I2S0_SCLK_A QEC0_X_A LPCAM_D4_B
P3_1 GPIO3_1 OSPI0_SCLKN_B UART4_TX_A PDM_C0_B I2S0_WS_A QEC0_Y_A LPCAM_D5_B
P3_2 GPIO3_2 OSPI0_SS0_B PDM_D1_B I2S1_SDI_A I3C_SDA_C QEC0_Z_A LPCAM_D6_B
P3_3 GPIO3_3 OSPI0_SS1_B PDM_C1_B I2S1_SDO_A I3C_SCL_C QEC1_X_A LPCAM_D7_B

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Pin Name 0 1 2 3 4 5 6 7
P3_4 GPIO3_4 OSPI0_RXDS_A UART5_RX_A LPPDM_C0_B I2S1_SCLK_A I2C0_SCL_B QEC1_Y_A
P3_5 GPIO3_5 OSPI0_SCLKN_A UART5_TX_A LPPDM_D0_B SPI0_SS1_B I2C0_SDA_B QEC1_Z_A
P3_6 GPIO3_6 HFXO_OUT_A LPUART_CTS_B LPPDM_C1_B SPI0_SS2_B I2C1_SDA_B QEC2_X_A
P3_7 GPIO3_7 JTAG_TRACECLK LPUART_RTS_B LPPDM_D1_B SPI1_SS1_A I2C1_SCL_B QEC2_Y_A
P4_0 GPIO4_0 JTAG_TDATA0 I2S1_WS_A SPI1_SS2_A QEC2_Z_A CDC_VSYNC_B
P4_1 GPIO4_1 JTAG_TDATA1 I2S0_SDI_B SPI1_SS3_A QEC3_X_A SD_CLK_D CDC_HSYNC_B
P4_2 GPIO4_2 JTAG_TDATA2 I2S0_SDO_B SPI2_MISO_A QEC3_Y_A SD_CMD_D
P4_3 GPIO4_3 JTAG_TDATA3 I2S0_SCLK_B SPI2_MOSI_A QEC3_Z_A SD_RST_D
P4_4 GPIO4_4 JTAG_TCK I2S0_WS_B SPI2_SCLK_A FAULT0_A
P4_5 GPIO4_5 JTAG_TMS SPI2_SS0_A FAULT1_A
P4_6 GPIO4_6 JTAG_TDI SPI2_SS1_A FAULT2_A
P4_7 GPIO4_7 JTAG_TDO SPI2_SS2_A FAULT3_A
P5_0 GPIO5_0 UART4_RX_C PDM_D2_A SPI0_MISO_B I2C2_SDA_B UT0_T0_B SD_D0_A
P5_1 GPIO5_1 UART4_TX_C PDM_D3_A SPI0_MOSI_B I2C2_SCL_B UT0_T1_B SD_D1_A
P5_2 GPIO5_2 UART5_RX_C PDM_C3_A SPI0_SS0_B LPI2C_SCL_B UT1_T0_B SD_D2_A
P5_3 GPIO5_3 UART5_TX_C SPI0_SCLK_B LPI2C_SDA_B UT1_T1_B SD_D3_A CDC_PCLK_A
P5_4 GPIO5_4 UART3_CTS_A PDM_D2_B SPI0_SS3_A UT2_T0_B SD_D4_A CDC_DE_A
P5_5 GPIO5_5 UART3_RTS_A PDM_D3_B UT2_T1_B SD_D5_A CDC_HSYNC_A
P5_6 GPIO5_6 RESERVED UART1_CTS_B I2C2_SCL_C UT3_T0_B SD_D6_A CDC_VSYNC_A
P5_7 GPIO5_7 UART1_RTS_B I2C2_SDA_C UT3_T1_B SD_D7_A
P6_0 GPIO6_0 OSPI0_D0_C UART4_DE_A PDM_D0_C UT4_T0_B SD_D0_D
P6_1 GPIO6_1 OSPI0_D1_C UART5_DE_A PDM_C0_C UT4_T1_B SD_D1_D
P6_2 GPIO6_2 OSPI0_D2_C UART2_CTS_A PDM_D1_C UT5_T0_B SD_D2_D
P6_3 GPIO6_3 OSPI0_D3_C UART2_RTS_A PDM_C1_C UT5_T1_B SD_D3_D
P6_4 GPIO6_4 OSPI0_D4_C UART2_CTS_B SPI1_SS0_B UT6_T0_B SD_D4_D
P6_5 GPIO6_5 OSPI0_D5_C UART2_RTS_B SPI1_SS1_B UT6_T1_B SD_D5_D
P6_6 GPIO6_6 OSPI0_D6_C UART0_CTS_B SPI1_SS2_B UT7_T0_B SD_D6_D
P6_7 GPIO6_7 OSPI0_D7_C UART0_RTS_B PDM_C2_A SPI1_SS3_B UT7_T1_B SD_D7_D
P7_0 GPIO7_0 SPI0_MISO_C I2C0_SDA_C SD_CMD_A CAN_RXD_A
P7_1 GPIO7_1 SPI0_MOSI_C I2C0_SCL_C SD_CLK_A CAN_TXD_A
P7_2 GPIO7_2 UART3_CTS_B CMP1_OUT_A SPI0_SCLK_C I2C1_SDA_C SD_RST_A
P7_3 GPIO7_3 UART3_RTS_B CMP0_OUT_A SPI0_SS0_C I2C1_SCL_C CAN_STBY_A
P7_4 GPIO7_4 LPUART_CTS_A LPPDM_C2_A LPSPI_MISO_A LPI2C_SCL_A

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Pin Name 0 1 2 3 4 5 6 7
P7_5 GPIO7_5 LPUART_RTS_A LPPDM_D2_A LPSPI_MOSI_A LPI2C_SDA_A
P7_6 GPIO7_6 LPUART_RX_A LPPDM_C3_A LPSPI_SCLK_A I3C_SDA_D
P7_7 GPIO7_7 LPUART_TX_A LPPDM_D3_A LPSPI_SS_A I3C_SCL_D
P8_0 GPIO8_0 AUDIO_CLK_A FAULT0_B LPCAM_D0_A SD_D0_C CDC_D0_A
P8_1 GPIO8_1 FAULT1_B LPCAM_D1_A SD_D1_C CDC_D1_A
P8_2 GPIO8_2 SPI0_SS3_B FAULT2_B LPCAM_D2_A SD_D2_C CDC_D2_A
P8_3 GPIO8_3 SPI1_MISO_B FAULT3_B LPCAM_D3_A SD_D3_C CDC_D3_A
P8_4 GPIO8_4 SPI1_MOSI_B QEC0_X_B LPCAM_D4_A SD_D4_C CDC_D4_A
P8_5 GPIO8_5 RESERVED SPI1_SCLK_B QEC0_Y_B LPCAM_D5_A SD_D5_C CDC_D5_A
P8_6 GPIO8_6 RESERVED QEC0_Z_B LPCAM_D6_A SD_D6_C CDC_D6_A
P8_7 GPIO8_7 RESERVED QEC1_X_B LPCAM_D7_A SD_D7_C CDC_D7_A
P9_0 GPIO9_0 RESERVED QEC1_Y_B SD_CMD_C CDC_D8_A
P9_1 GPIO9_1 LPUART_RX_B QEC1_Z_B SD_CLK_C CDC_D9_A
P9_2 GPIO9_2 LPUART_TX_B SPI2_MISO_B QEC2_X_B SD_RST_C CDC_D10_A
P9_3 GPIO9_3 HFXO_OUT_B SPI2_MOSI_B QEC2_Y_B CDC_D11_A
P9_4 GPIO9_4 SPI2_SCLK_B I2C3_SDA_C QEC2_Z_B CDC_D12_A
P9_5 GPIO9_5 SPI2_SS0_B I2C3_SCL_C QEC3_X_B CDC_D13_A
P9_6 GPIO9_6 AUDIO_CLK_B SPI2_SS1_B I2C3_SDA_B QEC3_Y_B CDC_D14_A
P9_7 GPIO9_7 SPI2_SS2_B I2C3_SCL_B QEC3_Z_B CDC_D15_A
P10_0 GPIO10_0 SPI2_SS3_B UT0_T0_C LPCAM_HSYNC_A CDC_D16_A
P10_1 GPIO10_1 LPI2S_SDI_B UT0_T1_C LPCAM_VSYNC_A CDC_D17_A
P10_2 GPIO10_2 LPI2S_SDO_B UT1_T0_C LPCAM_PCLK_A CDC_D18_A
P10_3 GPIO10_3 LPI2S_SCLK_B UT1_T1_C LPCAM_XVCLK_A CDC_D19_A
P10_4 GPIO10_4 LPI2S_WS_B I2C0_SDA_D UT2_T0_C CDC_D20_A
P10_5 GPIO10_5 SPI3_MISO_B I2C0_SCL_D UT2_T1_C CDC_D21_A
P10_6 GPIO10_6 SPI3_MOSI_B I2C1_SDA_D UT3_T0_C CDC_D22_A
P10_7 GPIO10_7 SPI3_SCLK_B I2C1_SCL_D UT3_T1_C CDC_D23_A
P11_0 GPIO11_0 SPI3_SS0_B UT4_T0_C CDC_D0_B
P11_1 GPIO11_1 SPI3_SS1_B UT4_T1_C CDC_D1_B
P11_2 GPIO11_2 LPPDM_C2_B SPI3_SS2_B UT5_T0_C CDC_D2_B
P11_3 GPIO11_3 UART5_RX_B LPPDM_C3_B SPI3_SS3_B UT5_T1_C CDC_D3_B
P11_4 GPIO11_4 UART5_TX_B PDM_C2_B LPSPI_MISO_B UT6_T0_C CDC_D4_B
P11_5 GPIO11_5 PDM_C3_B LPSPI_MOSI_B UT6_T1_C CDC_D5_B

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Pin Name 0 1 2 3 4 5 6 7
P11_6 GPIO11_6 LPPDM_D2_B LPSPI_SCLK_B UT7_T0_C CDC_D6_B
P11_7 GPIO11_7 UART5_DE_B LPPDM_D3_B LPSPI_SS_B UT7_T1_C CDC_D7_B
P12_0 GPIO12_0 OSPI0_SCLK_C AUDIO_CLK_C I2S1_SDI_B CDC_D8_B
P12_1 GPIO12_1 OSPI0_SCLKN_C UART4_RX_B I2S1_SDO_B CDC_D9_B
P12_2 GPIO12_2 OSPI0_RXDS_C UART4_TX_B I2S1_SCLK_B CDC_D10_B
P12_3 GPIO12_3 OSPI0_SS0_C UART4_DE_B I2S1_WS_B CDC_D11_B
P12_4 GPIO12_4 OSPI0_SS1_C SPI3_MISO_A CAN_RXD_C CDC_D12_B
P12_5 GPIO12_5 SPI3_MOSI_A CAN_TXD_C CDC_D13_B
P12_6 GPIO12_6 SPI3_SCLK_A CAN_STBY_C CDC_D14_B
P12_7 GPIO12_7 SPI3_SS0_A CDC_D15_B
P13_0 GPIO13_0 SPI3_SS1_A QEC0_X_C SD_D0_B CDC_D16_B
P13_1 GPIO13_1 SPI3_SS2_A QEC0_Y_C SD_D1_B CDC_D17_B
P13_2 GPIO13_2 SPI3_SS3_A QEC0_Z_C SD_D2_B CDC_D18_B
P13_3 GPIO13_3 SPI2_SS3_A QEC1_X_C SD_D3_B CDC_D19_B
P13_4 GPIO13_4 LPI2S_SDI_C QEC1_Y_C SD_D4_B CDC_D20_B
P13_5 GPIO13_5 LPI2S_SDO_C QEC1_Z_C SD_D5_B CDC_D21_B
P13_6 GPIO13_6 LPI2S_SCLK_C QEC2_X_C SD_D6_B CDC_D22_B
P13_7 GPIO13_7 LPI2S_WS_C QEC2_Y_C SD_D7_B CDC_D23_B
P14_0 GPIO14_0 QEC2_Z_C SD_CMD_B
P14_1 GPIO14_1 QEC3_X_C SD_CLK_B
P14_2 GPIO14_2 QEC3_Y_C SD_RST_B
P14_3 GPIO14_3 QEC3_Z_C
P14_4 GPIO14_4 SPI1_MISO_C FAULT0_C
P14_5 GPIO14_5 SPI1_MOSI_C FAULT1_C
P14_6 GPIO14_6 CMP1_OUT_B SPI1_SCLK_C FAULT2_C
P14_7 GPIO14_7 CMP0_OUT_B SPI1_SS0_C FAULT3_C

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5 Electrical Characteristics

5.1 Absolute Maximum Ratings

Stresses above the values listed under Table 5-1 may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions
may affect device reliability.
Table 5-1 Absolute Maximum Ratings
Parameter Condition Min Max Unit
VDD_MAIN -0.3 4.5 V
1.8-V mode -0.3 1.98 V
VDD_IO_FLEX
Chip power inputs 3.3-V mode -0.3 3.63 V
VDD_BATT -0.3 4.5 V
VDD_BUCK -0.3 4.5 V
Input/Output voltage range (1.8 V IOs) 0.3 1.98 V
Maximum junction temperature -40 150 °C

5.1.1 Maximum Supply Current

Table 5-2 summarizes maximum current consumption ratings at power terminals of the device.
Table 5-2 Maximum Supply Current
Parameter Condition Max Unit
IVDD_ALL Supply current into all power pins 600 mA
IVSS_ALL Supply current out of all ground pin(s) 1000 mA
IVDD_MAIN Supply current rating for the VDD_MAIN pins 10 mA
IVDD_VBAT Supply current rating for the VDD_BATT pins 1 mA
IVDDIO_1.8V Supply current rating for the VDD_IO_1V8 pins 500 mA
IVDDIO_3.3V Supply current rating for the VDD_IO_FLEX pins 200 mA
I1V8_IO Current sunk, sourced by any 1.8 V I/O pin 65 mA
I3V6_IO Current sunk, sourced by any 3.6 V I/O pin 35 mA
IIO_ALL Current sunk, sourced by all pins (I/O and control) 700 mA

5.1.2 Maximum Performance Ratings

Table 5-3 lists the maximum performance per module on this device.
Table 5-3 Maximum Performance Ratings
Parameter Max Unit
High-Efficiency Arm Cortex-M55 M55-HE 160 MHz
Ethos-U55 Neural Processing Units NPU-HE 160 MHz
D/AVE 2D Graphics Processing Unit GPU2D 400 MHz
Controller Area Network CANFD 10 Mbps

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Parameter Max Unit

I2C 1 MHz
Inter-Integrated Circuit
LPI2C 1 MHz
I2S(1) 192 kHz
Inter-IC Sound
LPI2S(1) 192 kHz
MIPI Improved Inter-Integrated Circuit I3C 20 Mbps
PDM 4.8 MHz
Pulse Density Modulator
LPPDM 4.8 MHz
SPI 50 MHz
Serial Peripheral Interface
LPSPI 25 MHz
UART 2.5 Mbps
Universal Asynchronous Receiver/Transmitter
LPUART 2.5 Mbps
Universal Serial Bus USB 480 Mbps
Octal SPI OSPI 100(2) MHz
SD Card 50(2) MHz
Memory Card Controller eMMC 50(2) MHz
SDIO 50(2) MHz
Camera Parallel Interface LPCPI 55 MHz
Display Parallel Interface DPI 50 MHz
MIPI Display Serial Interface DSI 2.5 Gbps/lane
ADC12 2.5 MSPS
Analog-to-Digital Converters
ADC24 16 kSPS
Digital-to-Analog Converters DAC12 1 MHz
1. Sampling frequency
2. Some pin multiplex options will reduce the max operating frequency. Please see Cautionary information at the start of Section 4.2
Pin Function Options by Location.

5.2 Operating Conditions

5.2.1 General Operating Conditions

Table 5-4 presents recommended operating conditions over free-air temperature range (unless otherwise
noted).
Table 5-4 General Operating Conditions
Parameter Min Typ Max Unit
VDD_MAIN(1) Main power supply 1.75 4.2 V
VDD_BATT Battery backed domain power input 1.62 4.2 V
VDD_BUCK Internal DC-DC converter power input 1.75 4.2 V
VDD_USB_3V3 USB power input 3.0 3.3 3.6 V
1.8-V mode(2) 1.62 1.8 1.98 V
VDD_IO_FLEX GPIO flex pads (1.8 V - 3.3 V) power input
3.3-V mode 3.0 3.3 4.2 V
VDD_IO_1V8 GPIO standard pads (1.8 V) power input 1.08 1.8 1.98 V
VREG_DIG_1V8 Internal 1.8 V regulator output 1.7 1.8 1.9 V
VREG_AUX_1V8 Auxiliary 1.8 V regulator output 1.7 1.8 1.9 V
VREF_P External positive voltage reference for ADC 1.2 1.8 1.9 V
VSS_BUCK DC-DC converter ground 0 V

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Parameter Min Typ Max Unit

VSS_ANA Analog ground 0 V
VSS Digital ground 0 V
ta Operating ambient temperature range Industrial (high) -40 105 °C
tj Operating junction temperature range Industrial (high) -40 125 °C
1. Please refer to the Application Note regarding PCB Layout Guidance covering decoupling methods for all power pins on Ensemble
devices.
2. VDD_IO_FLEX should be connected to VDD_IO_1V8 when 1.8-V mode is used.

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5.2.2 Device Power Modes

5.2.2.1 Power Modes Case Definition

NOTE

Specifications shown in Table 5-5 Power Modes Case Definition are subject to change.

Table 5-5 provides status of each module during different power modes of the device.
Table 5-5 Power Modes Case Definition
Current Wake Time to Reach
SRAM Main LP
Voltage Clock Wake-Up Consumption GO Mode
Power Mode MRAM Peripherals Peripherals
Regulation Bulk M55-HE 4KB Source Sources
Power Power Typ Units Typ Units
SRAM TCM Backup
GO Modes IVDD_MAIN when VDD_MAIN = 3.3 V
M55-HE running
CoreMark at 20(3) mA
160 MHz.
GO_1
NPU running
convolution MAC ON ON 125(3) μA/MHz
workload. ON with
PLL
clocks gated 15(3) mA
GO_2 M55-HE running
Any 96(3) μA/MHz
CoreMark at
interrupt
160 MHz. No NPU is
DC-DC ON ON All ON from a 13(3) mA N/A
GO_3 enabled.
powered
81(3) μA/MHz
peripheral
M55-HE running
2.1 mA
WHILE(1) at
GO_4
76.8 MHz. No NPU is OFF OFF
27 μA/MHz
enabled.
HFRC All OFF
M55-HE running
725 μA
WHILE(1) at
GO_5
19.2 MHz. No NPU is
38 μA/MHz
enabled.

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Current Wake Time to Reach

SRAM Main LP
Voltage Clock Wake-Up Consumption GO Mode
Power Mode MRAM Peripherals Peripherals
Regulation Bulk M55-HE 4KB Source Sources
Power Power Typ Units Typ Units
SRAM TCM Backup
READY Modes IVDD_MAIN when VDD_MAIN = 3.3 V
M55-HE in WFI(2) at ON with Any
RDY_1 ON PLL interrupt 8.7(4) mA < 100 ns
160 MHz. clocks gated
DC-DC OFF ON ON All ON from a
M55-HE in WFI at powered
RDY_2 OFF HFRC All OFF 1.4 mA < 200 ns
78.6 MHz. peripheral
IDLE Modes IVDD_MAIN when VDD_MAIN = 3.3 V
CPU and NPU cores
Any
IDLE_1 powered off. HFXO 2.5 mA 2-4 μs
interrupt
38.4 MHz clock. OFF but OFF but ON with
DC-DC OFF OFF All ON from a
CPU and NPU cores retained retained clocks gated
powered
IDLE_2 powered off. 600 kHz HFRC 900 μA 2-4 μs
peripheral(1)
clock.
STANDBY Modes IVDD_MAIN when VDD_MAIN = 3.3 V
Any
LPUART,
CPU and NPU cores interrupt
OFF but OFF but LPI2C ON +
STBY_1 powered off. HFRC DC-DC OFF OFF HFRC All OFF from a 65 μA 2-4 μs
retained retained STOP Mode
ready. powered
peripherals
peripheral
STOP Modes IVDD_BATT when VDD_BATT = 3.0 V
STOP_2 plus 512KB
OFF but
STOP_1 of M55-HE TCM 6150 nA
retained
SRAM retained. OFF but
LPRTC,
STOP_3 plus 4KB retained
LPTIMER,
STOP_2 Backup SRAM 1450 nA
CMP, BOD,
retained. Any
LFXO LPGPIO ON 1.1 ms
STOP_4 plus interrupt
STOP_3 LPTIMER, BOD, CMP, LDO OFF OFF All OFF from a 1400 nA
and LPGPIO active. powered
OFF
STOP_5 plus LPRTC peripheral
LPRTC +
STOP_4 running from OFF 1350 nA
LPGPIO ON
32.768 kHz LFXO.
32.7 kHz LFRC
STOP_5 running, all other LFRC LPGPIO ON 1250 nA
functions off. N/A

I/O Domain Adder for STOP in STOP Mode current

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Current Wake Time to Reach

SRAM Main LP
Voltage Clock Wake-Up Consumption GO Mode
Power Mode MRAM Peripherals Peripherals
Regulation Bulk M55-HE 4KB Source Sources
Power Power Typ Units Typ Units
SRAM TCM Backup
adder IVDD_IO_1V8
when VDD_IO_1V8 =
all cases.
1.8 V
200 nA
1. If RTSS-HE is powered down then the LPCPI, LPI2S, LPPDM, and LPSPI in the same subsystem are powered down too.
2. WFI: Wait for Interrupt.
3. At ACLK = 100 MHz, HCLK = 100 MHz.
4. At ACLK = 100 MHz, HCLK = 50 MHz, PCLK = 25 MHz.

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5.2.3 Power Sequence

Figure 5-1 shows the power-up and power-down sequencing of the device.
Figure 5-1 Power-Up/Power-Down Sequencing

VDD_BATT

VDD_MAIN

VDD_BUCK DC-DC converter stable

VDD_USB_3V3

VDD_IO_1V8

VDD_IO_FLEX

S32K_CLK

HFOSC_CLK

The following restrictions and considerations apply to Figure 5-1 Power-Up/Power-Down Sequencing:
n The power supply ramp-up time (10% to 90%) must be between 1 μs and 5 ms.
n During power-up phase, VDD_BATT power supply must come up at the same time or before the other
supplies. All other power supplies can come up in any order.
n During power-down phase, VDD_BATT power supply must come down at the same time or after the
other supplies. All other power supplies can come down in any order.
n The low-frequency S32K_CLK comes up after VDD_BATT.
n The high-frequency HFOSC_CLK comes up after DC-DC converter is stable.

5.2.4 Reference Voltage Characteristics

Table 5-6 presents reference voltage characteristics.
Table 5-6 Reference Voltage Characteristics
Parameter Conditions Min Typ Max Unit
VREFBUF_OUT Voltage reference output 1.7 1.8 1.9 V
TRIM Trim step resolution 6 7 mV
CLOAD Load capacitor 0.8 1 µF
ESR Equivalent series resistor of CLOAD 0.2 Ω
ILOAD Static load current 10 mA
ILINE_REG Line regulation 100 400 ppm/V
TCoeff Temperature coefficient 50 ppm/°C
DC 40 60 dB
PSRR Power supply rejection ratio
100 kHz 20 30 dB
tSTART Start-up time 100 µs
IDDA(VREFBUF) VREFBUF consumption from VDDA ILOAD = 0 µA 200 250 µA

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Parameter Conditions Min Typ Max Unit

ILOAD = 1 mA 1.2 mA

5.2.5 Electrical Sensitivity Characteristics

Table 5-7 presents Electrostatic Discharge (ESD) characteristics of the device.
Table 5-7 ESD Characteristics
Parameter Conditions Package Value Unit
ESDHBM All pins except for ones listed in(1) ESD Human Body Model (HBM) FBGA ±2000 V
ESD Charged Device Model
ESDCDM All pins FBGA ±250 V
(CDM)
1. ESDHBM for HFXO_P, HFXO_N, LFXO_P, and LFXO_N pins: ±1000 V

Table 5-8 presents latch-up characteristics of the device.

Table 5-8 Latch-up Characteristics
Parameter Conditions Value Unit
ILU Latch-Up current level Per JEDEC JESD 78 ±100 mA

5.3 Clock Characteristics

5.3.1 External Clock Source Characteristics

Table 5-9 presents the HFXO external clock source characteristics.
Table 5-9 External HFXO Clock Source Characteristics
Parameter Min Typ Max Unit
fc Frequency 38.4 MHz
CCS On chip shunt capacitance (programmable) 4 20 pF
ICC Current consumption at 3 V 60 μA
tj Period jitter 1 ps
ts Start-up time 200 μs
tacr Frequency accuracy 25 ppm

Table 5-10 presents the LFXO external clock source characteristics.

Table 5-10 External LFXO Clock Source Characteristics
Parameter Min Typ Max Unit
fc Frequency 32.768 kHz
CCS On chip shunt capacitance (programmable) 2 18 pF
ICC Current consumption at 3 V 150 nA
ts Start-up time 0.1 0.5 s
tacr Frequency accuracy 250 ppm

5.3.2 Internal Clock Source Characteristics

Table 5-11 presents the HFRC internal clock source characteristics.

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Table 5-11 Internal HFRC Clock Source Characteristics

Parameter Min Typ Max Unit
Frequency at 25 °C and VDD_BATT = 3 V
fc 65 76.8 88.8 MHz
(uncalibrated)
fcs Calibration step 2.5 MHz
ts Start-up time 0.5 1 μs
Frequency variation over temperature and
tj -1 1 %
voltage
ICC Current consumption 1.1 μA
tpj RMS period jitter 42 ps

Table 5-12 presents the LFRC internal clock source characteristics.

Table 5-12 Internal LFRC Clock Source Characteristics
Parameter Min Typ Max Unit
Frequency at 25 °C and VDD_BATT = 3 V
fc 32.7 kHz
(factory trimmed)
Frequency variation over temperature and
tj -4 4 %
voltage

5.3.3 PLL Characteristics

Table 5-13 presents the PLL characteristics.
Table 5-13 PLL Characteristics
Parameter Min Typ Max Unit
fC_IN Input clock frequency (HFXO only) 38.4 MHz
800 MHz
fC_OUT Output clock frequency
480 MHz
tSET Settling time 20 µs
fDC Output clock duty cycle 50 %
tj(CLK) Output clock jitter (period jitter) 2 ps
ICC Current consumption at 3 V supply 0.6 mA
ICC(PWR-DWN) Power-down current consumption 0.1 µA

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5.4 Memory Characteristics

Table 5-14 presents MRAM characteristics.
Table 5-14 MRAM Characteristics
Parameter Conditions Min Typ Max Unit
3.3 V device Write 30 mA
supply.
IMRAM MRAM current consumption Read 10 mA
25 °C ambient
temperature. Power down 50 μA
NMRAMR Number of read cycles Unlimited Cycles
NMRAME Number of erase cycles 100000 Cycles
Write operation, 16 bytes
(minimum number of bytes
51.6 μs
that can be written in one
tMRAMW16 Write time, non-DMA
write operation)
3.22 μs
Effective write time and rate
0.31 MB/s
DMA write operation, 128
bytes (maximum DMA cycle 56.1 μs
tMRAMWDMA Write time, DMA payload)
438 ns
Effective write time and rate
2.28 MB/s
69 276 ns
tMRAMR16 Read time Read operation, 16 bytes
58 232 MB/s

Table 5-15 presents SRAM characteristics.

Table 5-15 SRAM Characteristics
Achievable Read Throughput (MB/s) Achievable Write Throughput (MB/s)
Transaction Data
Memory Block Read Originating from: Write Originating from:
Width (Bytes)
M55-HE at 160 MHz M55-HE at 160 MHz
SRAM0 8 558 731
SRAM1 N/A N/A N/A
SRAM2 N/A N/A N/A
SRAM3 N/A N/A N/A
SRAM4 4 640 512
SRAM5 8 1.280 1.278

NOTE

User SRAM size and availability is device part number dependent. For more information on SRAM
block enabled for each part number and their size, see Section 7 Ordering Information.

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5.5 I/O Buffer Characteristics

5.5.1 I/O Parameter Test Conditions

Unless otherwise specified, typical values are taken at ta = 25 °C and typical supply voltages as specified in
Table 5-4 General Operating Conditions. Where statistical variation is relevant and unless otherwise
specified, typical values represent parts at the mean of the distribution.
Unless otherwise specified the minimum and maximum values are taken across the full temperature and
voltage range. Where statistical variation is relevant and unless otherwise specified, minimum and maximum
values represent parts that are three standard deviations away from the mean of the distribution.
All values are based on laboratory characterization.

5.5.2 LVCMOS DC Specifications

Table 5-16 presents the LVCMOS I/O DC specifications.
Table 5-16 LVCMOS DC Specifications (1.8 V Logic)
Parameter Min Typ Max Unit
Input
VIH Input logic high voltage 0.65 × VDD_IO_1V8 VDD_IO_1V8 + 0.3 V
VIL Input logic low voltage -0.3 0.35 × VDD_IO_1V8 V
Rpu Input pull-up resistance 50 kΩ
Rpd Input pull-down resistance 50 kΩ
Output
VOH(DC) DC Output logic high voltage VDD_IO_1V8 - 0.4 V
VOL(DC) DC Output logic low voltage 0.4 V
IOL Output drive current (programmable) 2, 4, 8, or 12 mA

5.5.3 Dual-Voltage (Flex) LVCMOS DC Specifications

Table 5-17 presents the dual-voltage (Flex) LVCMOS I/O DC specifications.
Table 5-17 Dual-Voltage (Flex) LVCMOS DC Specifications (1.8 V / 3.3 V Logic)
Parameter Min Typ Max Unit
Input
0.65 × VDD_IO_FLEX
VIH Input logic high voltage (1)
VDD_IO_FLEX(1) + 0.3 V

0.35 × VDD_IO_FLEX
VIL Input logic low voltage -0.3 (1)
V

Rpu Input pull-up resistance 50 kΩ

Rpd Input pull-down resistance 50 kΩ
Output
VOH(DC) DC Output logic high voltage VDD_IO_FLEX(1) - 0.4 V
VOL(DC) DC Output logic low voltage 0.4 V

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Parameter Min Typ Max Unit

IOL Output drive current (programmable) 2, 4, 8, or 12 mA
1. The voltage supply can be 1.8 V or 3.3 V.

5.5.4 MIPI DSI DC Specifications

The DSI interface (DSIPHY port type) electrical characteristics are compliant with MIPI Alliance Specification
for D-PHY v1.2.

5.5.5 USB DC Specifications

The USB interface (USBPHY port type) electrical characteristics are compliant with Universal Serial Bus
Specification Revision 2.0.

5.6 Analog Peripherals Characteristics

5.6.1 ADC Characteristics

Table 5-18 presents the ADC12 electrical characteristics.
Table 5-18 ADC12 Electrical Characteristics
Parameter Conditions Min Typ Max Unit
RES Resolution 12 Bits
Operational
fs 312 5000 kHz
speed
Gain error Internal ADC
EG 6.1 LSB
(calibrated) voltage supply =
Offset error 1.8 V from
EO 0.41 LSB
(calibrated) external 3.3 V
Integral supply (DC-DC)
EL 3 LSB
nonlinearity
Differential
ED 2 LSB
nonlinearity
2.5 MSPS (5.0 MHz, Ave(1) = 2) 9.10
1.25 MSPS (2.5 MHz, Ave = 2) 9.25
Internal ADC
Single- 0.5 MSPS (1 MHz, Ave = 2) 9.65
voltage
ended 1.25 MSPS (5 MHz, Ave = 4) 9.25
reference = 1.8 V
0.625 MSPS (2.5 MHz, Ave = 4) 10.00
Effective
0.25 MSPS (1 MHz, Ave = 4) 10.15
number of Bits
ENOB 2.5 MSPS (5.0 MHz, Ave = 2) 9.70
bits
1.25 MSPS (2.5 MHz, Ave = 2) 10.25
Ambient
0.5 MSPS (1 MHz, Ave = 2) 10.50
temperature =
Differential 1.25 MSPS (5 MHz, Ave = 4) 10.00
25 °C
0.625 MSPS (2.5 MHz, Ave = 4) 11.00
0.25 MSPS (1 MHz, Ave = 4) 11.25
Single-
Signal-to- 58.8
SNR ended 1.25 MSPS (2.5 MHz, Ave = 2) dB
noise ratio
Differential 64.8

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Parameter Conditions Min Typ Max Unit

Total Single-
-63.3
THD harmonic ended 1.25 MSPS (2.5 MHz, Ave = 2) dB
distortion Differential -68.8
Current fs = 5 MHz 0.50 0.80
IDDA mA
consumption fs = 2.5 MHz 0.30 0.47
1. Ave: Averaging factor

Table 5-19 presents the ADC24 electrical characteristics.

Table 5-19 ADC24 Electrical Characteristics
Parameter Conditions Min Typ Max Unit
RES Resolution 24 Bits
Internal ADC voltage supply = 1.8 V
fs Sampling rate 1 16 kSPS
provided by on-die DC-DC with
EG Gain error 1.5 % of FSR
external 3.3 V supply
EO Offset error 50 µV
Total harmonic 1 kSPS -80
THD Internal ADC voltage reference = 1.8 V dB
distortion 16 kSPS -74
Differential mode, PGA off 1 kSPS 106
SNR Signal to noise ratio dB
Ambient temperature = 25 °C 16 kSPS 93.5
Current
IDDA 0.45 1.0 mA
consumption

5.6.2 DAC12 Characteristics

Table 5-20 presents the DAC12 electrical characteristics.
Table 5-20 DAC12 Electrical Characteristics
Parameter Conditions Min Typ Max Unit
RES Resolution 12 Bits
fc Conversion rate 1.0 kHz
Internal ADC voltage supply =
Output drive
IOUT 1.8 V provided by on-die DC- High-performance mode 1.5 mA
current
DC with external 3.3 V supply
High-performance mode 1.5 % of
EG Gain error
Low-power mode 1.5 FSR
Internal ADC voltage High-performance mode 0.14 % of
EOff Offset error
reference = 1.8 V Low-power mode 0.1 FSR
Current High-performance mode 2.0 mA
IDDA Ambient temperature = 25 °C
consumption Low-power mode 150 µA
Integral High-performance mode -2 3.2
INL LSB
nonlinearity Low-power mode -1.5 2.6
Differential High-performance mode -2.2 1.5
DNL LSB
nonlinearity Low-power mode -1.1 1.8

5.6.3 CMP Characteristics

Table 5-21 presents the high-speed comparator electrical characteristics.

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Table 5-21 CMP Electrical Characteristics

Parameter Conditions Min Typ Max Unit
VIN Comparator input voltage range -0.3 VDD(1) + 0.3 V
VOFFSET_IN Input offset Full common mode range 20 mV
ICC Current consumption High-speed mode 200 µA
VHYS Hysteresis 0.7 V ≤ Vin ≤ VDD(1) - 0.7 V 5 30 mV
Ibias Comparator input bias current 10 nA
tRES Response time High-speed mode 5 ns
1. Power supply from LDO-5. For more information on configuration, refer to the CMP_COMP_REG2[ANA_PERIPH_LDO_CONT]
register field in the corresponding series-specific Hardware Reference Manual.

5.6.4 LPCMP Characteristics

Table 5-22 presents the low power comparator electrical characteristics.
Table 5-22 LPCMP Electrical Characteristics
Parameter Conditions Min Typ Max Unit
Analog supply voltage (from
VDDA 1.62 1.8 1.98 V
VDD_IO_1V8)
Comparator input voltage
VIN -0.3 VDDA + 0.3 V
range
VOFFSET_IN Input offset Full common mode range 20 mV
ICC Current consumption Low power mode 20 µA
VHYS Hysteresis 0.7 V ≤ Vin ≤ VDDA⁠–0.7 V 5 30 mV
Ibias Comparator input bias current 10 nA
tRES Response time Low power mode 10 µs

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5.7 Timing Characteristics

5.7.1 Timing Test Conditions

Table 5-23 shows general description of used symbols, adopted standards, terminology, and test process.
Unless otherwise specified, all timing parameters are characterized assuming load capacitance of 10 pF.
Table 5-23 Timing Test Conditions
Parameter Description
fop Operating frequency
tc Cycle time (period)
td Delay time
tdsbl Disable time
ten Enable time
th Hold time
ts Setup time
ttr Transition time
tv Valid time
tpd Pulse duration
tF Fall time
tR Rise time
VOH High-level output voltage
VOL Low-level output voltage
VIH High-level input voltage
VIL Low-level input voltage
VREF Reference voltage
tRES Timer resolution time
RES Timer resolution
tP_COUNTER Counter clock period
tMAX_COUNT Maximum possible count
f(baud) Maximum programmable baud rate
t(BUF) Bus free time
start Start bit
Cb Capacitive load
Dc Duty cycle
JIT Jitter
tCAS Clock after START condition
tCBT Clock before STOP condition
tCASr Clock after repeated START
tCBSr Clock before repeated START
tMMovrLAP Current master to secondary master overlap time during hand off
tMMLOCK Time internal where new master not driving SDA low
tBAC Bus available condition
TBIC Bus idle condition

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5.7.2 Timers and Counters

5.7.2.1 LPTIMER Timing Characteristics

Table 5-24 and Figure 5-2 present the LPTIMER timing characteristics.
Table 5-24 LPTIMER Timing Characteristics
No Parameter Min Typ Max Unit
Condition: fLPTIM_CLK = 128 kHz (refer to Table 5-12 Internal LFRC Clock Source Characteristics)
LPTM1 tRES Timer resolution time 7.8 μs
LPTM2 tP_COUNTER Cycle time counter 1 232 - 1 counts
LPTM3 tMAX_COUNT Maximum possible count per timer 32000 s
Condition: fLPTIM_CLK = 32.768 kHz (refer to Table 5-10 External LFXO Clock Source Characteristics)
LPTM1 tRES Timer resolution time 30.5 μs
LPTM2 tP_COUNTER Cycle time counter 1 232 - 1 counts
LPTM3 tMAX_COUNT Maximum possible count per timer 120000 s

Figure 5-2 LPTIMER Timing Diagram

Counter
Value

LPTM2

LPTM1 Time
LPTM3

5.7.2.2 UTIMER Timing Characteristics

Table 5-25 and Figure 5-3 present the UTIMER timing characteristics.
Table 5-25 UTIMER Timing Characteristics
No Parameter Min Typ Max Unit
Condition: fUTIM_CLK = 400 MHz
UTM1 tRES Timer resolution time 2.5 ns
UTM2 tP_COUNTER Cycle time counter 1 232 - 1 counts
UTM3 tPERIOD Timer period 5 × 10-9 10.74 s

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Figure 5-3 UTIMER Timing Diagram

Counter
Value

UTM2

UTM1 Time
UTM3

5.7.2.3 QEC Timing Characteristics

Table 5-26 and Figure 5-4 present the QEC timing characteristics.
Table 5-26 QEC Timing Characteristics
No Parameter Min Max Unit
QEC1 tpd_QEC_in Pulse duration, QEC input 10 ns
QEC2 tpd_QEC-IH Pulse duration, QEC index input high 10 ns
QEC3 tpd_QEC-IL Pulse duration, QEC index input low 10 ns
QEC4 tpd_QEC-SH Pulse duration, QEC strobe high 10 ns
QEC5 tpd_QEC-SL Pulse duration, QEC strobe low 10 ns
QEC6 td_QEC-CNTR Delay time, external clock to counter increment 10 ns

Figure 5-4 QEC Timing Diagram

QEC1

QEC_A/B

QEC2 QEC3

QEC_IL/QEC_IH

QEC4 QEC5

QEC_SL/QEC_SH
qec_01

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5.7.3 Communication Peripherals

5.7.3.1 CANFD Timing Characteristics

Table 5-27 and 5.7.3 present the CANFD timing characteristics.
Table 5-27 CANFD Timing Characteristics
No Parameter Min Max Unit
CAN1 f(baud) Maximum programmable baud rate 10 Mbps
CAN2 td_shift_TX Delay time, transmit shift register to Tx pin 10 ns
CAN3 td_RX_shift Delay time, Rx pin to receive shift register 30 ns

5.7.3.2 I2C Timing Characteristics

Table 5-28 and Figure 5-5 present the I2C timing characteristics.
Table 5-28 I2C Timing Characteristics
SS FS FS+
No Parameter Unit
Min Max Min Max Min Max
tc_SCL Cycle time 10 2.5 1 µs
I2C2 tpd_SCL-H Pulse duration, SCL high 0.450 1.320 0.500 µs
I2C3 tpd_SCL-L Pulse duration, SCL low 0.450 1.320 0.500 µs
I2C4 tR_SDA_SCL Rise time of SDA and SCL signals 20 300 20 300 20 120 ns
See table See table See table
I2C5 tF_SDA_SCL Fall time of SDA and SCL signals 300 300 120 ns
note(1) note(1) note(1)
I2C6 ts_SDA_SCL Setup time, SDA to SCL 0.1 0.1 0.1 µs
I2C7 th_SDA_SCL Hold time, SDA to SCL µs
Setup time, SCL to repeated START
I2C8 ts_SCL_start 0.6 0.26 0.26 µs
condition
th_start_
I2C9 Hold time, START condition to SCL 0.6 0.26 0.26 µs
SCL
I2C10 th_SCL_stop Setup time, SCL to STOP condition 0.6 0.26 0.26 µs
tBUF_start_ Bus free time between STOP and
I2C11 1.3 0.5 0.5 µs
stop START condition
Cb_bus Capacitive load for each bus line 50 50 50 pF
1. 20 × (VDD_IO_1V8 ÷ 5.5 V)

Figure 5-5 I2C Timing Diagram

SDA
I2C11
I2C4 I2C5
I2C2

SCL
I2C9 I2C6 I2C7 I2C4 I2C5 I2C8 I2C10
I2C3
Stop Start Repeated Stop
i2c_01

Start

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5.7.3.3 I2S Timing Characteristics

Table 5-29 and Figure 5-6 present the I2S timing characteristics.
Table 5-29 I2S Timing Characteristics
No Parameter Min Typ Max Unit
fop_SCK Operation frequency, SCK (serial clock) 2.27 2.5 2.78 MHz
I2S3 tc_SCK Cycle time, SCK (serial clock) 440 400 360 ns
I2S4 tpd_SCK-H Pulse duration, SCK high 160 ns
I2S5 tpd_SCK-L Pulse duration, SCK low 160 ns
I2S6 td_SCK_WS Delay time, SCK output low to WS valid 0.8 × tc_SCK ns
I2S7 td_SCK_SDOUT Delay time, SCK output low to SDOUT valid 0.8 × tc_SCK ns
I2S8 ts_SDIN_master Setup time, SDIN master mode 60 ns
I2S9 ts_SDIN_slave Setup time, SDIN slave mode 60 ns
I2S10 th_SDIN_master Hold time, SDIN master mode 100 ns
I2S11 th_SDIN_slave Hold time, SDIN slave mode 0 ns

Figure 5-6 I2S Master Mode Timing Diagram

I2S3 I2S5 I2S4
SCK
I2S6
WS
I2S7
SDOUT
I2S8 I2S10

i2s_01
SDIN

5.7.3.4 I3C Timing Characteristics

Table 5-30, Table 5-31, Figure 5-7, and Figure 5-8 present the I3C timing characteristics.
Table 5-30 I3C Open Drain Timing Characteristics
No Parameter Mode Min Max Unit
I3C1 tpd_SCL-L Pulse duration, SCL low Master 200 ns
I3C2 tpd_SCL-H Pulse duration, SCL high Master 200 ns
I3C3 tF_SDA Fall time, SDA Master 11 ns
I3C4 ts_SDA-OD Setup time, SDA open drain Master 3 ns
I3C5 tCAS Clock after START condition Master 38.4 ns
I3C6 tCBT Clock before STOP condition Master 19.2 ns
Current master to secondary master
I3C7 tMMovrLAP Master 212 ns
overlap time during hand off
I3C8 tBAC Bus available condition Master 1000 ns
I3C9 TBIC Bus idle condition Master 200000 ns
Time internal where new master not
I3C10 tMMLOCK Master 1000 ns
driving SDA Low

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Table 5-31 I3C Push-Pull Timing Characteristics

NO. PARAMETER MODE MIN MAX UNIT
I3C1 tc Cycle time, SCL Master 100000 77.52 ns
I3C2 tpd_SCL-L Pulse duration, SCL low Master 32 ns
I3C4 tpd_SCL-H Pulse duration, SCL high Master 32 ns
I3C5 td_SCL_SDA Delay time, SCL to SDA out Master 12 ns
I3C6 tR_SCL Rise time, SCL Master 12 ns
I3C7 tF_SCL Fall time, SCL Master 12 ns
Master in push-
I3C8 th_SDA Hold time, SDA 15 ns
pull
Master in push-
I3C9 ts_SDA Setup time, SDA 15 ns
pull
I3C10 tCASr Clock after repeated START Master 19.2 ns
I3C11 tCBSr Clock before repeated START Master 19.2 ns
Master,
Cb Capacitive load per bus line (SDA/SCL) 50 pf
Slave

Figure 5-7 I3C Open Drain Timing Diagram

I3C3 I3C4

SDA
I3C5 I3C6
I3C1

SCL
I3C2

Stop Start Repeated Stop

Start

i3c_02
Figure 5-8 I3C Push-Pull Timing Diagram

SDA
I3C11 I3C10 I3C5
I3C1 I3C5 I3C9
I3C2 I3C8 I3C9

SCL
I3C4 I3C7 I3C6
Stop Start Repeated Stop
Start
i3c_01

5.7.3.5 PDM Timing Characteristics

Table 5-32 and Figure 5-9 present the PDM timing characteristics.
Table 5-32 PDM Timing Characteristics
No Parameter Min Typ Max Unit
fOP Operating frequency, PDM_CLK 1.032 1.032 1.032 MHz

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No Parameter Min Typ Max Unit

PDM2 tW_CLK_H Pulse duration, CLK high 484 1 / fOP
PDM3 tW_CLK_L Pulse duration, CLK low 484 1 / fOP
PDM4 tSU_DAT Setup time, DAT 65 ns
PDM5 tH_DAT Hold time, DAT 0 ns

Figure 5-9 PDM Timing Diagram

CLK
PDM2 PDM3

PDM4 PDM5

DAT

5.7.3.6 SPI Timing Characteristics

Table 5-33, Figure 5-10, and Figure 5-11 present the SPI timing characteristics.
Table 5-33 SPI Timing Characteristics
No Parameter Min Typ Max Unit
SPI 20 ns
SP1 tc_SCLK Cycle time, SCLK
LPSPI 40 ns
SP2 tR_SCLK Rise time, SCLK 3 ns
SP3 tF_SCLK Fall time, SCLK 3 ns
SP4 tpd_CLK-L Pulse duration, SCLK low 0.45 × tc_SCKL ns
SP5 tpd_CLK-H Pulse duration, SCLK high 0.45 × tc_SCKL ns
SP6 ts_SS Setup time, SS 3 ns
SP7 th_SS Hold time, SS 0.5 0.6 0.8 ns
SP8 ts_MISO_SCLK Setup time, MISO to SCLK 3 ns
SP9 th_MISO_SCLK Hold time, MISO to SCLK 3 ns
SP10 td_MOSI_SS Delay time, MOSI to SS 3 ns
SP11 td_MOSI_SCLK Delay time, MOSI to SCLK 3 ns

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Figure 5-10 SPI Receive Timing Diagram

SP6 SP7
SS
SP1
SP4
SP5

SCLK CPOL=0

SP5
SP4

SCLK CPOL=1
SP8 SP8
SP9 SP9
CPHA=0
MISO bit n-1 bit n-2 bit n-3 bit n-4 bit 0
SP8
SP8
SP9 SP9

CPHA=1
MISO bit n-1 bit n-2 bit n-3 bit 1 bit 0

spi_01
Figure 5-11 SPI Transmit Timing Diagram
SP6 SP7
SS
SP1
SP4
SP5

SCLK CPOL=0

SP5
SP4

SCLK CPOL=1
SP10
SP11 SP11
CPHA=0
MOSI bit n-1 bit n-2 bit n-3 bit n-4 bit 0

SP11
SP11 SP11

CPHA=1
MOSI bit n-1 bit n-2 bit n-3 bit 1 bit 0
spi_02

5.7.3.7 UART Timing Characteristics

Table 5-34 and Figure 5-12 present the UART timing characteristics.
Table 5-34 UART Timing Characteristics
No Parameter Mode Min Max Unit
f(baud) Maximum programmable baud rate 2.5 Mbps
UT2 td_CTS_ST_TX Delay time, receive CTSn low to start bit low 100 200 ns
UT3 tpd_ST_TX Pulse duration, transmit start bit, low 400 400 ns

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No Parameter Mode Min Max Unit

UT4 tpd_DAT_TX Pulse duration, transmit data bit, high or low 400 400 ns
UT5 tpd_ST_RX Pulse duration, receive start bit, low 400 400 ns
UT6 tpd_DAT_RX Pulse duration, receive data bit, high or low 400 400 ns

Figure 5-12 UART Timing Diagram

UT2

CTS

UT3 UT4

TXD

Start Bit Data Bits

UT5 UT6

RXD

uart_01
Start Bit Data Bits

5.7.3.8 USB Timing Characteristics

The USB interface timing characteristics are compliant with Universal Serial Bus Specification Revision 2.0.

5.7.4 External Memory Interfaces

5.7.4.1 OSPI Timing Characteristics

Table 5-35 and Figure 5-13 present the OSPI timing characteristics.
Table 5-35 OSPI Timing Characteristics
No Parameter Min Typ Max Unit
fop Operating frequency 80 100(1) 120 MHz
O2 tc_CLK Cycle time, CLK 12.5 10 8.33 ns
O3 tpd_CLK-H Pulse duration, CLK high 0.45 × tc_CKL 0.45 × tc_CKL 0.45 × tc_CKL ns
O4 tpd_CLK-L Pulse duration, CLK low 0.45 × tc_CKL 0.45 × tc_CKL 0.45 × tc_CKL ns
O5 tR_CLK Rise time, CLK 0.05 × tc_CKL ns
O6 tF_CLK Fall time, CLK 0.05 × tc_CKL ns
O7 ts_DATA_IN Setup time, DATA input 3 ns
O8 th_DATA_IN Hold time, DATA input 0.8 0.6 0.5 ns
O9 td_DATA_OUT Delay time, DATA output 2.375 1.8 1.45 ns
O10 th_DATA_OUT Hold time, DATA output 0 ns
1. Some pin multiplex options will reduce the operating frequency. Please see Cautionary information at the start of Section 4.2 Pin
Function Options by Location.

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Figure 5-13 OSPI Timing Diagram

O5 O2 O3 O4 O6

CLK

O9 O10

DATA_OUT D0 D1 D2

O8
O7
DATA_IN D0 D1 D2

ospi_02
5.7.4.2 SDMMC Timing Characteristics
Table 5-36 and Figure 5-14 present the SDMMC timing characteristics in DS mode.
Table 5-36 SDMMC Timing Characteristics (DS mode)
No Parameter Min Max Unit
DS1 tc_CLK Cycle time, CLK 40(1) ns
DS2 tR_CLK Rise time, CLK 10 ns
DS3 tF_CLK Fall time, CLK 10 ns
DC_CLK Duty cycle 45 55 %
DS5 ts_CMD_CLK Setup time, CMD valid before CLK rising edge 11.7 ns
DS6 th_CMD_CLK Hold time, CMD valid after CLK rising edge 8.3 ns
DS7 ts_DATA_CLK Setup time, DATA valid before CLK rising edge 11.7 ns
DS8 th_DATA_CLK Hold time, DATA valid after CLK rising edge 8.3 ns
1. Some pin multiplex options will reduce the operating frequency. Please see Cautionary information at the start of Section 4.2 Pin
Function Options by Location.

Figure 5-14 SDMMC Timing Diagram (DS mode)

DS3 DS1

CLK
DS5 DS6 DS2

CMD
DS7 DS8

DATA
mmc_01

Table 5-37 and Figure 5-15 present the SDMMC timing characteristics in HS mode.
Table 5-37 SDMMC Timing Characteristics (HS mode)
No Parameter Min Max Unit
HS1 tc_CLK Cycle time, CLK 20 ns
HS2 tR_CLK Rise time, CLK 3 ns

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No Parameter Min Max Unit

HS3 tF_CLK Fall time, CLK 3 ns
DC_CLK Duty cycle 45 55 %
HS5 ts_CMD_CLK Setup time, CMD valid before CLK rising edge 6.3 ns
HS6 th_CMD_CLK Hold time, CMD valid after CLK rising edge 2.5 ns
HS7 ts_DATA_CLK Setup time, DATA valid before CLK rising edge 6.3 ns
HS8 th_DATA_CLK Hold time, DATA valid after CLK rising edge 2.5 ns

Figure 5-15 SDMMC Timing Diagram (HS mode)

HS3 HS1

CLK
HS5 HS6 HS2

CMD
HS7 HS8

DATA

mmc_01
Table 5-38 and Figure 5-16 present the SDMMC timing characteristics in SDR12/SDR25/SDR50 modes.
Table 5-38 SDMMC Timing Characteristics (SDR12/SDR25/SDR50)
No Parameter Mode Min Max Unit
SDR12 40 ns
MC1 tc_CLK Cycle time, CLK SDR25 20 ns
SDR50 10 ns
MC2 tR_CLK Rise time, CLK 3 ns
MC3 tF_CLK Fall time, CLK 3 ns
DC_CLK Duty cycle 45 55 %
SDR12 3 ns
MC5 ts_CMD_CLK Setup time, CMD valid before CLK rising edge SDR25 3 ns
SDR50 3 ns
SDR12 0.8 ns
MC6 th_CMD_CLK Hold time, CMD valid after CLK rising edge SDR25 0.8 ns
SDR50 0.8 ns
SDR12 3 ns
MC7 ts_DATA_CLK Setup time, DATA valid before CLK rising edge SDR25 3 ns
SDR50 3 ns
SDR12 0.8 ns
MC8 th_DATA_CLK Hold time, DATA valid after CLK rising edge SDR25 0.8 ns
SDR50 0.8 ns

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Figure 5-16 SDMMC Timing Diagram (SDR12/SDR25/SDR50)

MC3 MC1

CLK
MC5 MC6 MC2

CMD
MC7 MC8

DATA

mmc_01
5.7.5 Camera Interfaces

5.7.5.1 LPCPI Timing Characteristics

Table 5-39 and Figure 5-17 present the LPCPI timing characteristics.
Table 5-39 LPCPI Timing Characteristics
No Parameter Min Max Unit
LPCPI1 tc_MCLK Cycle time, PCLK 16.7 ns
LPCPI2 tpd_MCLK Pulse duration, PCLK 8.33 ns
LPCPI3 ts_VSYNC_PCLK Setup time, input vertical sync VSYNC valid before PCLK 3 ns
LPCPI4 th_VSYNC_PCLK Hold time, input vertical sync VSYNC valid after PCLK 3 ns
LPCPI5 ts_HSYNC_PCLK Setup time, input horizontal sync HSYNC valid before PCLK 3 ns
LPCPI6 th_HSYNC_PCLK Hold time, input horizontal sync HSYNC valid after PCLK 3 ns
LPCPI7 ts_DATA_PCLK Setup time, input DATA valid before PCLK 5 ns
LPCPI8 th_DATA_PCLK Hold time, input DATA valid after PCLK 5 ns

Figure 5-17 LPCPI Timing Diagram

LPCPI1 LPCPI2
PCLK
LPCPI3 LPCPI4
VSYNC
LPCPI5 LPCPI6

HSYNC
LPCPI7
LPCPI8

Dn-2 D0 Dn-2 Dn-1

cpi_01

DATA D0 Dn-1

5.7.6 Display Interfaces

5.7.6.1 DPI Timing Characteristics

Table 5-40 and Figure 5-18 present the DPI timing characteristics.

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Table 5-40 DPI Timing Characteristics

No Parameter Min Max Unit
DP1 tc Cycle time 20 ns
DC_CLK Duty cycle, PCLK 40 60 %
DP3 tR_CLK Rise time, PCLK 1 ns
DP4 tF_CLK Fall time, PCLK 1 ns
DP5 td_all_to_CLK Delay time, DE, VSYNC, HSYNC, DATA signals to PCLK 5 ns

Figure 5-18 DPI Timing Diagram

DP1 DP3 DP4
pixel clk fall reference
PCLK

pixel clk rise reference

PCLK

DP5

DE

DP5

VSYNC
DP5

HSYNC
DP5

DATA D1 D1 ... Dn

dpi_01
5.7.6.2 DSI Timing Characteristics
The DSI interface timing characteristics are compliant with MIPI Alliance Specification for Display Serial
Interface (DSI), Version 1.2, and MIPI Alliance Specification for D-PHY, Version 1.2.

5.7.7 Debug Interface

Table 5-41 and Figure 5-19 present the JTAG timing characteristics.
Table 5-41 JTAG Timing Characteristics
No Parameter Min Max Unit
JT1 tc Cycle time, TCK 50 100 ns
JT2 tpd_TCK-H Pulse duration, TCK high 24 49 ns
JT3 tpd_TCK-L Pulse duration, TCK low 24 49 ns
JT4 ts_TDI/TMS-TCK Setup time, TDI/TMS valid before TCK rising edge 7 7 ns
JT5 th_TDI/TMS-TCK Hold time, TDI/TMS valid after TCK rising edge 7 7 ns
JT6 td_TDO Delay time, TDO valid after TCK falling edge 7 7 ns

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Figure 5-19 JTAG Timing Diagram

JT1
JT3 JT2

TCK
JT6

TDO
JT5
JT4

TDI
TMS

jtag_01

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6 Package Information

6.1 Device Marking Definition

Figure 6-1 presents the top marking reference view.
Figure 6-1 FBGA Device Top Marking Reference

Pin 1 Indicator

AXXXXXXX
Product Part Number
XXXXXXXX
Suffix - ABCDEF YYWW
Lot Number XXXXXXXXX.XXX.XX

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Table 6-1 presents the part number decoding.

Table 6-1 Product Identification
Example Part Number: A E 1 0 1 F 4 0 7 15 42 U H

Device Manufacturer
A - Alif Semiconductor
Device Family
B - BLE-connected embedded microcontrollers
E - Ensemble, embedded processors
Device Series
0 - Service MCU
1 - Efficiency MCU
3 - Performance MCU
5 - Fusion processor MCU/MPU
7 - Extreme fusion processor MCU/MPU
Number of Application Processing Cores
0 - Zero cores
1 - One cores
2 - Two cores
Number of Real Time Processing Cores
0 - Zero cores
1 - One cores
2 - Two cores
Security Attribute
B - Basic security
F - Full security, complete life cycle management
Machine Learning and AI Capability
1 - MCU Vector Extension (Helium)
4 - Single Neural Processing Unit (Ethos) + MCU Vector Extension (Helium)
8 - Dual Neural Processing Units (Ethos) + MCU Vector Extension (Helium)
Wireless Capability
0 - No wireless
M - BLE + IEEE 802.15.4
Peripheral Set
0 through 9, A through Z = Level of peripheral selection mix, higher is typically more peripherals
On-Chip Application MRAM Size
MRAM memory size in MB
1st digit - N = None, 1 through 9 = 1MB through 9MB, A through F = 10MB through 15MB, 0 = 16MB
2nd digit - 0 = 0KB, 1 = 128KB, 2 = 256KB, 3 = 384KB, 5 = 512KB, 7 = 768KB
On-Chip Application SRAM Size
SRAM memory size in MB
1st digit - N = None, 1 through 9 = 1MB through 9MB, A through F = 10MB through 15MB, 0 = 16MB
2nd digit - 0 = 0KB, 1 = 128KB, 2 = 256KB, 3 = 384KB, 5 = 512KB, 7 = 768KB
Package Type and Pin Count
A - WLCSP208, 0.5 mm pitch
H - WLCSP90, 0.4 mm pitch

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Example Part Number: A E 1 0 1 F 4 0 7 15 42 U H

J - WLCSP49, 0.35 mm pitch
L - FBGA194, 0.5 mm pitch
P - FBGA117, 0.5 mm pitch
R - FBGA65, 0.5 mm pitch
5 - LQFP64, 0.5 mm pitch
Operating Temperature
S - Standard (see Section 5.2.1 General Operating Conditions)
E - Extended (see Section 5.2.1 General Operating Conditions)
H - Industrial (see Section 5.2.1 General Operating Conditions)

Table 6-2 presents the Suffix (characters after main part number) decoding.
Table 6-2 Suffix Definition
Position Description
A ID
B ID revision
C Firmware version
D Fab site. D = Dresden
E Final assembly site. M = Malaysia, K = South Korea
F Final test site. S = Singapore, E = USA
Space
Y
Calendar year of device production
Y
W
Work week of device production
W

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6.2 Package Specifications

6.2.1 FBGA194 Package Information

6.2.1.1 FBGA194 Thermal Operating Specifications

Table 6-3 provides thermal operating specifications for FBGA194 package.
Table 6-3 FBGA194 Thermal Operating Specifications
Parameter Value Unit
θJA Thermal resistance in natural convection (junction-to-free air) 21.1 °C/W
θJC Thermal resistance (junction-to-case) 17.0 °C/W
ΨJT Thermal characterization parameter (junction-to-package top) 21.0 °C/W

6.2.1.2 FBGA194 Package Outline

Figure 6-2 presents FBGA194 package outline.
Figure 6-2 FBGA194 Package Outline (1)

1. All linear dimensions are in millimeters.

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6.3 Storage Conditions

Table 6-4 defines specifics in the storage conditions.
Table 6-4 Storage Conditions
Parameter Min Max Unit
TSTG Storage temperature -40 150 °C
%RH Relative Humidity FBGA package: MSL3 (Moisture Sensitivity Level)

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7 Ordering Information
Table 7-1 presents the optional features for each orderable part number.
Table 7-1 Orderable Part Numbers
GPIO
Part Number MRAM SRAM Package Operating Temperature
(1.8 V)
AE101F4071542LH 1.5MB 4.5MB 120 FBGA194 Industrial

Table 7-2 shows the user SRAM banks with their corresponding sizes (in KB) available for each part number.
Table 7-2 Part Numbers SRAM Breakdown
SRAM4 (M55-HE SRAM5 (M55-HE
Part Number Total SRAM (KB) SRAM0 (KB) SRAM1 (KB) SRAM2 (KB) SRAM3 (KB)
ITCM) (KB) DTCM) (KB)
AE101F4071542LH 4608 4096 N/A N/A N/A 256 256

It is possible to configure address ranges within SRAM0 through SRAM5 to appear as contiguous address space to the M55 core through
configuration of the firewall controllers. For more information on the firewalls, refer to the corresponding device series-specific Hardware
Reference Manual, Section Interconnect Firewall Functional Description.
For complete part number decoding, refer to Section 6.1 Device Marking Definition.

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8 Legal and Support Information

8.1 Disclaimers
Portions Copyright © 2021 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare
are registered trademarks of Synopsys, Inc.
Legal Notice – Please Read
Alif Semiconductor™ reserves the right, without notice, to alter, edit, update, make corrections, and
improvements to Alif documentation and products at any time. It is the responsibility of customers to
maintain the most current versions of documentation before making any purchases from Alif. The
information found in this documentation is provided to purchasers solely for the purpose of enabling
hardware and software implementation of Alif products.
Alif neither takes any responsibility for, nor guarantees the appropriateness of, its products for a specific
purpose. Customers accept the responsibility for the selection and incorporation of Alif products into their
systems and Alif has no liability with respect thereto. ALIF ALSO DISCLAIMS ANY AND ALL LIABILITY WITH
RESPECT THERETO, INCLUDING WITHOUT LIMITATION, DIRECT, CONSEQUENTIAL, INDIRECT, SPECIAL AND
INCIDENTAL DAMAGES. ADDITIONALLY, ALIF DISCLAIMS AND EXCLUDES ALL WARRANTIES, WHETHER
STATUTORY, EXPRESS OR IMPLIED, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR
A PARTICULAR PURPOSE AND NON-INFRINGEMENT AND THOSE ARISING FROM COURSE OF DEALING AND
USAGE OF TRADE.
Alif Semiconductor and the Alif logo are trademarks of Alif. For more information about our trademarks,
please visit our website at https://alifsemi.com/legal/. The omission of any Alif trademark, product name or
any other name from this list does not constitute a waiver of Alif's intellectual property rights.
The recipient of this document does not have permission to copy, reprint, reproduce, duplicate, share, in any
form, in whole or in part, unless prior written consent from Alif is obtained.
Please contact an Alif representative at [email protected] if you have any questions regarding the
information in this document.
Alif sells products according to standards terms and conditions of sales, which can be found at:
https://alifsemi.com/legal/

8.2 Related Documents and Tools

n Alif Semiconductor E1 Series Hardware Reference Manual (HWRM)
n Alif Semiconductor E Series Software Reference Manual (SWRM)
For additional Alif Semiconductor technical documentation and software resources please visit:
n User Guides & App Notes
n Software & Tools
For managing software configurations of device resources, power, pins, clocks, DMA requests, interrupts, and
various other additional settings, refer to the Alif Conductor tool.

8.3 Contact Information

For more information visit our website Alif Semiconductor or contact us:
[email protected]
US HQ – Silicon Valley, CA

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7901 Stoneridge Drive, Suite 300

Pleasanton, CA 94588

8.4 Trademarks
The Alif logo, Ensemble, and aiPM are trademarks of Alif Semiconductor. For additional information about
Alif Semiconductor trademarks, refer to https://alifsemi.com/legal/.
Arm, Cortex, CoreSight, TrustZone, AMBA, Thumb, and Ethos are registered trademarks or trademarks of
Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Neon, and Helium are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Secure Digital and SD is a registered trademark of SD Card Association.
Synopsys & DesignWare are registered trademarks of Synopsys, Inc.
eMMC is trademarks of MultiMediaCard Association.
All other product or service names are the property of their respective owners.

8.5 Abbreviations

3GPP
3rd Generation Partnership Project

ACP
Accelerator Coherency Port

ADC
Analog to Digital Converter

AES
Advanced Encryption Standard

AHI
Application Host Interface

AI
Artificial Intelligence

aiPM
autonomous intelligent Power Management

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AON
Always On

API
Application Programming Interface

APSS
Application Processor Subsystem

ATOC
Application Table of Content

BER
Bit-Error Ratio

BLE
Bluetooth Low Energy

BLIT
Block Image Transfers

BOD
Brown-Out Detect

BOR
Brown-Out Reset

BPU
Breakpoint Unit

CAN
Controller Area Network

CANFD
Controller Area Network with Flexible Data rate

CCC
Common Command Code

CDC
Configurable DPI Controller

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CDM
Charged Device Model

CLUT
Color Look-Up Table

CMP
Comparator

CMSIS
Common Microcontroller Software Interface Standard

CNN
Convolutional Neural Network

CPI
Camera Parallel Interface

CPU
Central Processing Unit

CRC
Cyclic Redundancy Check

CSI
Camera Serial Interface

DAC
Digital to Analog Converter

DAP
Debug Access Port

DDR
Double Data Rate

DL
Display List / Download

DLR
Display List Reader

DM
Device Manufacturer

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DMA
Direct Memory Access

DMAC
Direct Memory Access Controller

DMIC
Digital Microphone

DPA
Differential Power Analysis

DPI
Display Parallel Interface / Display Pixel Interface

DPU
Data Processing Unit

DRD
Dual-Role Device

DSC
Display Stream Compression

DSI
Display Serial Interface

DTCM
Data Tightly-Coupled Memory

DWT
Data Watchpoint and Trace

ECB
Electronic Codebook

ECC
Error-Correcting Code / Elliptic-Curve Cryptography

eDRX
Extended Discontinuous Reception

EMC
Electromagnetic Compatibility

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EMFI
Electromagnetic Fault Injection

EMI
Electromagnetic Interference

EMS
Electromagnetic Susceptibility

EOL
End of Life

EoTp
End of Transmission Packet

EPU
Extension Processing Unit

ESD
Electrostatic Discharge

eSIM
Embedded Subscriber Identity Module

ETH
Ethernet

EVTRTR
Event Router

EWIC
External Wakeup Interrupt Controller

FC
Firewall Component

FIR
Finite Impulse Response

FSR
Full-Scale Range

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GIC
Generic Interrupt Controller

GNSS
Global Navigation Satellite Subsystem

GOPS
Giga Operations Per Second

GPIO
General-Purpose Input/Output

GPS
Global Positioning System

GPU
Graphics Processing Unit

HBM
Human Body Model

HCI
Host Communication Interface

HDR
High Data Rate

HE
High Efficiency

HFRC
High-Frequency Resistor-Capacitor

HFXO
High-Frequency Crystal Oscillator

HMI
Human Machine Interface

HP
High Performance

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HPP
High Performance Point

HUK
Hardware Unique Key

HWRM
Hardware Reference Manual

HWSEM
Hardware Semaphore

I2C
Inter-Integrated Circuit

I2S
Inter-IC Sound

I3C
Improved Inter-Integrated Circuit

IBI
In-Band Interrupt

ICMP
Internet Control Message Protocol

ICV
Integration Circuit Vendor

IDE
Integrated Design Environment

IFG
Interframe Gap

IFU
Instruction Fetch Unit

IIR
Infinite Impulse Response

IoT
Internet of Things

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IPC
Inter-Process Communication

IPI
Image Pixel Interface

IRQRTR
Interrupt Router

iSIM
Integrated Subscriber Identity Module

ISP
In-System Programming

ITCM
Instruction Tightly-Coupled Memory

iUICC
integrated Universal Integrated Circuit Card

IWIC
Internal Wakeup Interrupt Controller

LCD
Liquid Crystal Display

LCS
Life Cycle State

LDE
Lockdown Extension

LDO
Low Drop-Out

LE
Low Energy

LFRC
Low-Frequency Resistor-Capacitor

LFXO
Low-Frequency Crystal Oscillator

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LOM
Listen Only Mode

LP
Low-Power

LPCMP
Low-Power Comparator

LPGPIO
Low-Power General-Purpose Input/Output

LPI2C
Low-Power Inter-Integrated Circuit

LPI2S
Low-Power Inter-IC Sound

LPM
Link Power Management

LPP
Low Performance Point

LPPDM
Low-Power Pulse Density Modulation

LPRTC
Low-Power Real-Time Counter

LPSPI
Low-Power Serial Peripheral Interface

LPTIMER
Low-Power Timer

LSB
Least Significant Bit

LTE
Long-Term Evolution

LUT
Look-Up Table

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MAC
Media Access Controller

MAU
Memory Authentication Unit

MBI
Master Bus Interface

MCU
Microcontroller Unit

ME
Monitor Extension

MHU
Message Handling Unit

ML
Machine Learning

MMU
Memory Management Unit

MPE
Master Permission Entry

MPU
Memory Protection Unit

MRAM
Magnetoresistive Random-Access Memory

MSL
Moisture Sensitivity Level

MTL
MAC Transaction Layer

MVE
M-profile Vector Extension

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MWS
Mobile Wireless Standard

NMI
Non-Maskable Interrupt

NPP
Nominal Performance Point

NPU
Neural Processing Unit

NPU-HE
Neural Processing Unit-High Efficiency

NPU-HP
Neural Processing Unit-High Performance

NRZ
Non-Return-to-Zero

NS
Non-Secure

NVIC
Nested Vectored Interrupt Controller

NVM
Non-Volatile Memory

OCS
OEM-signed Configuration Settings

OEM
Original Equipment Manufacturer

OPP
Operating Performance Point

OSPI
Octal Serial Peripheral Interface

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OToC
OEM-signed Table of Contents

OTP
One Time Programmable

PCM
Pulse Code Modulation

PD
Power Domain

PDM
Pulse Density Modulation

PE
Protection Extension

PLL
Phase-Locked Loop

PMU
Performance Monitoring Unit

POR
Power-On-Reset

PPI
PHY Protocol Interface / Private Peripheral Interrupt

PPS
Precise Positioning Service

PPU
Power Policy Unit

PSC
Power Sequence Controller

PSM
Power Saving Mode

PSRAM
Pseudo-Static Random-Access Memory

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PSRR
Power Supply Rejection Ratio

PWM
Pulse Width Modulation

QEC
Quadrature Encoder Counter

RAI
Release Assistance Indication

RDC
Receiver Delay Compensation

RF
Radio Frequency

RFI
Radio Frequency Interference

RLE
Run-Length Encoding

RMA
Return Merchandise Authorization

RNN
Recurrent Neural Network

RO
Read Only

ROM
Read Only Memory

RoT
Root-of-Trust

RSA
Rivest–Shamir–Adleman

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RSE
Region Size Extension

RSTC
Reset Controller

RTC
Real-Time Counter

RTOS
Real-Time Operating System

RTSS
Real-Time Subsystem

RW
Read/Write

SAR
Successive Approximation Register

SAU
Security Attribution Unit

SBI
Slave Bus Interface

SCU
Snoop Control Unit

SDA
Serial Data

SDIO
Secure Digital Input/Output

SDMMC
Secure Digital / Embedded Multimedia Card

SDR
Single Data Rate

SE
Secure Enclave / Secure Enable

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SESS
Secure Enclave Subsystem

SFD
Start of Frame Data / Start Frame Delimiter

SGI
Software Generated Interrupt

SHA
Secure Hash Algorithm

SIM
Subscriber Identity Module

SIMD
Single Instruction Multiple Data

SJW
Synchronization Jump Width

SMP
Symmetric Multi-Processing

SNR
Signal-to-Noise Ratio

SPA
Simple Power Analysis

SPI
Serial Peripheral Interface / Shared Peripheral Interrupt

SRAM
Static Random-Access Memory

SSP
Synchronous Serial Protocol

SST
Single Shot Transmission

STB
Store Buffer

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STOC
System Table of Content

SWD
Serial Wire Debug

SWRM
Software Reference Manual

TCM
Tightly-Coupled Memory

TCP
Transmission Control Protocol

TDC
Transmitter Delay Compensation

TE
Translation Extension

TEE
Trusted Execution Environment

TFT
Thin-Film-Translator

TGU
TCM Gate Unit

TOC
Table of Content

TRNG
True Random Number Generator

TSENS
Temperature Sensor

UART
Universal Asynchronous Receiver/Transmitter

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UDE
Unprivileged Debug Extension

UDP
User Datagram Protocol

UI
Unit Interval / User Interface

UL
Upload

UPP
Ultra-Low Performance Point

USB
Universal Serial Bus

UTIMER
Universal Timer

VTOR
Vector Table Offset Register

WDT
Watchdog Timer

WFE
Wait For Event

WFI
Wait For Interrupt

XIP
eXecute-in-Place

XO
Execute Only

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ZI
Zero Initialized

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9 Revision History
Table 9-1 provides the history of changes to this document.
Table 9-1 Revision History
Date Revision Changes
Changes from previous revision include:
n Updated Section Features: On-Chip Application Memory, External Memory
Interfaces, Secure Enclave, Extreme-Low Power Technology, Serial Communication
Interfaces, Analog Interface Capabilities, Audio Interfaces, Clock Generation, and
Operating Parameters
n Updated CPU revision in Section 3.1.1 M55-HE Overview
n Updated Section 3.6.1 Power Domains
n Updated Figure 3-3 Device Voltage Distribution
n Updated Section 3.6.4 Power Supply Supervisors
n Updated Section 3.7 Reset Management Overview
n Updated Section 3.8 Clock Generation and Control
n Updated MRAM read cache size in Section 3.11.1 MRAM Overview
n Updated Section 3.11.2 SRAM Overview
n Updated Section 3.11.4 External Memory Expansion Options
n Updated Section 3.14.1 LPTIMER Overview
n Updated Section 3.16.3 I2C Overview
n Updated Section 3.16.6 PDM Overview
n Updated Section 3.17.1 Cryptographic OSPI Overview
n Updated Section 3.18.1 CPI Overview
n Updated Section 3.20.1 ADC Overview
n Updated Section 3.20.2 DAC12 Overview
October 2023 2.5 n Updated Section 3.20.3 CMP Overview
n Updated Section 3.20.4 LPCMP Overview
n Added VDD_PLL_0V8 power supply on ball A1 on FBGA194 package
n Removed SoC POR reset (VDD_POR)
n Updated power supplies naming - VDD_MIPI_0V8 to VREG_MIPI_0V8, VDD_3V3 to
VDD_MAIN, and VDD_BUCK_3V3 to VDD_BUCK accordingly
n Updated 4.1.1 FBGA194 Package Pin Location Assignment
n Updated CAUTION note in Section 4.2 Pin Function Options by Location
n Updated Table 4-1 Pin Function Options by Location
n Updated and moved Section 6.3 Storage Conditions under Section 6 Package
Information
n Updated Table 5-7 ESD Characteristics
n Updated OSPI, CPI, and LPCPI maximum supported frequencies in 5.1.2 Maximum
Performance Ratings
n Updated Table 5-4 General Operating Conditions
n Updated Table 5-5 Power Modes Case Definition
n Removed Section Supply Current Characteristics. Information is moved in Table 5-5
Power Modes Case Definition
n Removed Section Wake Up Times. Information is moved in Table 5-5 Power Modes
Case Definition
n Added values to Table 5-6 Reference Voltage Characteristics
n Removed EMC Characteristics section

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Date Revision Changes

n Updated Table 5-12 Internal LFRC Clock Source Characteristics
n Updated Table 5-14 MRAM Characteristics
n Updated Table 5-15 SRAM Characteristics
n Added IOL parameter to 5.5.2 LVCMOS DC Specifications
n Added IOL parameter to 5.5.3 Dual-Voltage (Flex) LVCMOS DC Specifications
n Updated Table 5-18 ADC12 Electrical Characteristics
n Updated Table 5-19 ADC24 Electrical Characteristics
n Updated Table 5-20 DAC12 Electrical Characteristics
n Updated Table 5-24 LPTIMER Timing Characteristics
n Updated Table 5-26 QEC Timing Characteristics
n Removed General-Purpose Input/Output section under Section 5.7 Timing
Characteristics
n Updated Table 5-27 CANFD Timing Characteristics and removed CANFD Timing
Diagram
n Updated Table 5-33 SPI Timing Characteristics
n Updated Table 5-34 UART Timing Characteristics
n Updated Table 5-35 OSPI Timing Characteristics
n Updated Table 5-36 SDMMC Timing Characteristics (DS mode)
n Updated Table 5-37 SDMMC Timing Characteristics (HS mode)
n Updated Table 5-38 SDMMC Timing Characteristics (SDR12/SDR25/SDR50)
n Updated Table 5-39 LPCPI Timing Characteristics
n Updated Table 5-40 DPI Timing Characteristics
n Updated Table 5-41 JTAG Timing Characteristics
n Updated Section 6.1 Device Marking Definition
n Updated Table 6-3 FBGA194 Thermal Operating Specifications
n Removed AE101F1061517LH Part Number
n Editorial enhancements
Changes from previous revision include:
n Updated Section Features: On-Chip Application Memory, External Memory
Interfaces, Secure Enclave, Extreme-Low Power Technology, Serial Communication
Interfaces, Analog Interface Capabilities, Operating Parameters, Audio Interfaces,
Clock Generation
n Updated LPTMR[x]_CLK_OUT to LPTMR[x]_CLK_IO
n Updated the number of supported LPPDM channel inputs
n Updated Table 3-1 Device Resources per Power Domain
n Updated Section 3.16.5 I3C Overview
n Updated Table 3-22 OSPI Signal Descriptions
June 2023 2.4 n Updated Caution notes in Section 3.17.1 Cryptographic OSPI Overview, Section
3.18.1 CPI Overview, and Section 4.2 Pin Function Options by Location
n Updated I3C maximum performance ratings in Table 5-3 Maximum Performance
Ratings
n Updated LPSPI maximum performance ratings in Table 5-3 Maximum Performance
Ratings
n Updated Table 5-5 Power Modes Case Definition
n Added values to Trim step resolution parameter in Table 5-6 Reference Voltage
Characteristics
n Removed Regulator Characteristics section
n Updated Table 5-7 ESD Characteristics

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Date Revision Changes

n Removed I/O Current Injection Characteristics table
n Removed OTP Memory Characteristics table
n Added values for IMRAM parameter in Table 5-14 MRAM Characteristics
n Removed LVCMOS VIL/VIH Curves figure
n Removed Dual-Voltage LVCMOS VIL/VIH Curves figure
n Updated Table 5-20 DAC12 Electrical Characteristics
n Added values to Table 5-28 I2C Timing Characteristics
n Added values to Table 5-29 I2S Timing Characteristics
n Added values to Table 5-30 I3C Open Drain Timing Characteristics and Table 5-31
I3C Push-Pull Timing Characteristics
n Added values to Table 5-32 PDM Timing Characteristics
n Added values to Table 5-33 SPI Timing Characteristics
n Updated Table 5-35 OSPI Timing Characteristics
n Updated all URLs to Alif Semiconductor documentation and products
Changes from previous revision include:
n Updated Section Features: Extreme-Low Power Technology, On-Chip Application
Memory, External Memory Interfaces, Operating Parameters, and Packages
n Updated temperature range
n Added FBGA194 package type
n Added four additional GPIO banks "GPIO[11-14]" for FBGA194 package
n Updated SEUART_RX_A to SEUART_RX and SEUART_TX_A to SEUART_TX
n Added Power-On-Reset (POR_N) pin
n Updated USB_VDD_3V3 to VDD_USB_3V3
n Merged VSS_GNSS, VSS_MIPI, VSS_PA, and VSS_MAIN internally into VSS digital
ground
n Removed ECC support for M55-HE and M55-HP SRAMs
n Updated Section 3.8 Clock Generation and Control
n Updated Section 3.15 General-Purpose Input/Output Module
n Updated Section 3.16.1 CANFD Overview
n Updated Section 3.17.1 Cryptographic OSPI Overview
n Updated Section 3.17.2 SDMMC Overview
March 2023 2.3
n Updated Section 3.19.1 DPI Controller Overview
n Updated Section 3.20.4 LPCMP Overview
n Added Table 3-2 Power Supply Signal Descriptions
n Added No Connect (N.C.) and Not Available (N/A) pins in Table 4-1 Pin Function
Options by Location
n Removed Section 4.4 Reserved and Unused Pin Recommendations. Relevant
information is provided in Table 4-1 Pin Function Options by Location
n Updated Table 5-1 Absolute Maximum Ratings
n Updated Table 6-4 Storage Conditions
n Updated Table 5-2 Maximum Supply Current
n Updated Table 5-3 Maximum Performance Ratings
n Updated Table 5-4 General Operating Conditions
n Updated Section 1.0.1 Supply Current Characteristics
n Added Table 1-6 STOP Power Mode Current Consumption (at VDD_IO_1V8 = 1.8 V)
n Added info to Section 5.2.3 Power Sequence
n Added Section 1.0.1 Wake Up Times
n Updated Table 5-6 Reference Voltage Characteristics

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 E1 Series

Date Revision Changes

n Updated Section 5.2.5 Electrical Sensitivity Characteristics
n Updated Table 5-9 External HFXO Clock Source Characteristics
n Updated Table 5-10 External LFXO Clock Source Characteristics
n Updated Table 5-11 Internal HFRC Clock Source Characteristics
n Updated Table 5-12 Internal LFRC Clock Source Characteristics
n Updated Table 5-13 PLL Characteristics
n Updated Section 5.5.1 I/O Parameter Test Conditions
n Updated Table 5-16 LVCMOS DC Specifications (1.8 V Logic)
n Updated Table 5-21 CMP Electrical Characteristics
n Updated Table 5-22 LPCMP Electrical Characteristics
n Removed TSENS Timing Characteristics
n Updated Table 5-24 LPTIMER Timing Characteristics
n Updated Table 5-25 UTIMER Timing Characteristics
n Updated Table 5-35 OSPI Timing Characteristics
n Updated cycle time parameter in Table 5-41 JTAG Timing Characteristics
n Updated Table 6-1 Product Identification
September 2022 2.0 Initial Release

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