CENG304 – Computer Architecture
Izmir Katip Celebi University
Spring 2023-2024
Lecture 05
H. Burak Akyol, Ph.D.
Main Components of Computers
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Single-Cycle Processor
◼ Single-cycle processors are a type of CPU design where each
instruction executes in a single clock cycle.
◼ Regardless of the complexity of the instruction, each
instruction takes the same amount of time to be executed.
◼ Simplifies the design while potentially limiting performance
compared to more complex architectures.
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Single-Cycle Processor
◼ add x2, x3, x4
◼ sw x5, 8(x6)
◼ Each instruction has different latencies. Therefore, cycle time is
determined based on the slowest instruction (the instruction with
the maximum latency). IKCU - CENG304 4
Processor Designing Stages
1- Instruction set architecture specification
2- Determination of the requirements of the ISA
3- Datapath design
a- Identification of datapath components that meet the requirements
b- Integration of the datapath components
4- Control unit design
a- Identification of control points
b- Designing the unit that controls
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Instruction Set Architecture Specification
ISA: Subset of RV32I
Instr. Operands Description
add rd, rs1, rs2 Adds the values in registers rs1 and rs2 and stores the result in register rd.
sub rd, rs1, rs2 Subtracts the value in register rs2 from the value in register rs1 and stores the result in register rd.
addi rd, rs1, imm12 Adds the value of immediate (imm) to the value in register rs1 and stores the result in register rd.
and rd, rs1, rs2 Performs a bitwise AND operation between the values in registers rs1 and rs2 and stores the result in register rd.
xor rd, rs1, rs2 Performs a bitwise XOR operation between the values in registers rs1 and rs2 and stores the result in register rd.
Loads a word from memory at the address formed by adding the immediate (imm) value to the value in register rs1
lw rd, imm12 (rs1)
and stores it in register rd.
Stores the value from register rs2 into memory at the address formed by adding the immediate (imm) value to the
sw rs2, imm12 (rs1)
value in register rs1.
beq rs1, rs2, imm12 Branches to the target address (PC + imm) if the values in registers rs1 and rs2 are equal.
jal rd, imm20 Jumps to the target address (PC + imm) and stores the address of the instruction following the jump in register rd.
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Determination of ISA Requirements
How many registers in register file?
32
How many bits wide are the registers?
32
How many registers can be read simultaneously?
2
Which operations must be possible?
Arithmetic: sum (add, addi, lw, sw, jal), subtract (sub, beq)
Logic: and, xor
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Datapath Design
The units used to store data or perform operations on data within the processor are called
datapath units. The processor's datapath is comprised of these units.
Which units do we need for the subset of RV32I;
◼ Program Counter
◼ Instruction Memory
(Harvard Architecture)
◼ Data Memory
◼ Register File
◼ Arithmetic Logic Unit
◼ Immediate Generator (Extender)
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Program Counter & Instruction Memory
◼ Instruction memory stores program
instructions and outputs the
instruction corresponding to the
given instruction address.
◼ Program counter (PC) holds the
address of the next instruction.
Since instructions are 32 bits wide
and byte addressing is used, the PC
increments by 4 after each clock
cycle.
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Register File
◼ Register file outputs the data from
the source registers specified by
register numbers or writes the given
data to the destination register
specified by the register number.
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Arithmetic & Logic Unit (ALU)
◼ It is the unit where arithmetic and
logic operations are performed.
◼ For the given example;
◼ sum
◼ sub
◼ and
◼ xor
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Immediate Generator
◼ According to ISA, immediate values
of different instructions can have
different bit lengths, and ALU
operates with 32-bit data. Hence,
the immediate values need to be
extended.
◼ The immediate generation unit
decodes the instruction, selects the
immediate value, and then extends
it (preserves the sign).
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Data Memory
◼ The data memory stores the data of
running programs and serves as the
unit that enables access to these
addresses.
◼ It can perform read or write
operations to the given address.
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Multiplexer (Mux)
◼ Multiplexer (mux) is a fundamental
component used to select one of
several input signals and pass it
through to the output based on a
selection signal.
◼ It essentially acts as a data selector.
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Branching Datapath
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Arithmetic and Logic Datapath
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Memory Datapath
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Entire Datapath
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Entire Datapath
◼ add & sub
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Entire Datapath
◼ addi
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Entire Datapath
◼ and & xor
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Entire Datapath
◼ lw
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Entire Datapath
◼ sw
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Entire Datapath
◼ beq
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Entire Datapath
◼ jal
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