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Hamming Code

The document discusses the implementation of Hamming codes for error control coding in Verilog. It begins with an introduction to error control coding and Hamming codes. It then describes the encoding procedure for Hamming codes, including generating the codewords from the data words using the generator matrix. The document presents the hardware implementation of Hamming codes in Verilog, including the Verilog code, circuit diagram, and simulation waveform showing the generated codewords. The conclusion states that linear block coding and Hamming codes can encrypt information for safe transmission and automatically correct errors.

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41 views

Hamming Code

The document discusses the implementation of Hamming codes for error control coding in Verilog. It begins with an introduction to error control coding and Hamming codes. It then describes the encoding procedure for Hamming codes, including generating the codewords from the data words using the generator matrix. The document presents the hardware implementation of Hamming codes in Verilog, including the Verilog code, circuit diagram, and simulation waveform showing the generated codewords. The conclusion states that linear block coding and Hamming codes can encrypt information for safe transmission and automatically correct errors.

Uploaded by

Narayana
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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International Journal of Research in Engineering and Science (IJRES)

ISSN (Online): 2320-9364, ISSN (Print): 2320-9356


www.ijres.org Volume 10 Issue 1 ǁ 2022 ǁ PP. 69-73

Verilog Implementation of Hamming Code for


Error Control Coding
M A Muneeb1; Namratha S2
*1
Pre-Final Year Undergraduate Student, Dept. of Electronics and Communication Engineering,
Guru Nanak Dev Engineering College, Bidar, Karnataka, India.
*2
Assistant Professor, Dept. of Electronics and Communication Engineering,
Guru Nanak Dev Engineering College, Bidar, Karnataka, India.
Corresponding Author: M A Muneeb

Abstract
This paper generally introduces to the method that is used for error control coding and particularly about
Hamming Codes. Theoretical generation of codes is done using the formula and hardware implementation is
done in Verilog (Hardware Description Language) using Xilinx Vivado Design Suite. Waveforms are given in
which the code generation can be seen.
Keywords: Error Control Coding, Hamming Code, VLSI, Encryption, Verilog.
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Date of Submission: 28-12-2021 Date of acceptance: 07-01-2022
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I. INTRODUCTION
As we all are moving towards globalization of technology where dependency of human beings on
technology keeps increasing day by day. The advancements in the technology brings all of us on a single
platform i.e., Internet. Communication is made easy with the help of Internet and multimedia. The information
can be shared by anyone and can be accessed from different parts of the world immediately and easily, one of
the most important thing to be kept in mind is the proper transmission of information. Cyber theft is increasing
and different ways to hack and crack the digital systems are made, so there is a need for encryption and
decryption techniques to properly transmit data from transmitter to receiver. In digital Communication, Error
Control Coding is the most effective way for encrypting the data for proper transmission.

II. ERROR CONTROL CODING


In the world of computing and communication, an error correction code (ECC) is employed for
controlling errors in data over unreliable or noisy communication channels. The main idea is that the sender
encodes the message with redundant information within the sort of an ECC. The added codewords allows the
receiver to detect a limited number of errors which will occur within the message, and sometimes to correct
these errors without the need of retransmission. The American mathematician R. Hamming explored this field
within the 1940s and invented the error-correcting code in 1950: the Hamming (7,4) code.
ECC contrasts with error detection there in errors that are encountered are often corrected, not simply
detected. The advantage is that a system using ECC doesn't require a reverse channel to request retransmission
of data when a mistake occurs. ECC is designed in such a way that it adds redundancy to the transmitted
information using an algorithm. A redundant bit could also be a mixed function of the many original
information bits.
ECC is generally classified into two categories: Block codes and Convolutional codes.
Block codes work on fixed-size blocks (packets) of bits or symbols of predetermined size. Practical block codes
can generally be hard-decoded in polynomial time to their block length.
Convolutional codes work on bit or symbol streams of arbitrary length. They are most frequently soft decoded
with the Viterbi algorithm, though other algorithms are sometimes used.

Fig.: Introduction of noise during transmission

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Verilog Implementation of Hamming Code for Error Control Coding

III. LINEAR BLOCK CODING


Linear block code is a type of error-correcting code in which the actual information bits are linearly
combined with the parity check bits so as to generate a linear codeword that is transmitted through the channel.
Each block of k-message bits is encoded into a block of n-bits (n>k) as shown. The check bits are
derived from the message bits and are added to them.

Fig.: Linear Block Coding Technique

IV. HAMMING CODE


Hamming codes comes under linear error-correcting codes. Hamming codes can detect one-bit and
two-bit errors, or correct one-bit errors without detection of uncorrected errors. Hamming codes are perfect
codes, that is, they achieve the highest possible rate for codes with their block length and minimum distance of
three. Richard W. Hamming invented Hamming codes in 1950 as a way of automatically correcting errors
introduced by punched card readers. In his original paper, Hamming elaborated his general idea, but specifically
focused on the Hamming (7,4) code which adds three parity bits to four bits of data.

4.1 Encoding procedure:


In linear block code, the first k bits of the codeword are the message bits i.e.

Fig. Formula for codewords generation

Let the Generator Matrix be ‘G’. It has two sub matrices namely, Identity Matrix (Ik) & Parity matrix (Pk). When
some data is multiplied with the identity matrix then same data is obtained, hence the name given is Identity
Matrix. Parity matrix is used to derive the parity bits in the codeword.

Fig. Generator Matrix in Terms of Identity Matrix and Parity Matrix

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Verilog Implementation of Hamming Code for Error Control Coding

Therefore, Codeword C can be calculated by,


C=D*G
Where C – Codeword
D - Data word
& G - Generator matrix

Let’s take D= [0101]


then
C = [0101] * G
taking in terms of matrix,

Solving, we get
C=0101100

Similarly, we can generate for other possible data words.

Possible data words given by the formula


Possible data words = 2k
Where k = No. of bits

As we are taking 4 bits,


Possible data words = 2k = 24 = 16

Fig. Possible data words and Codewords for the given parity

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Verilog Implementation of Hamming Code for Error Control Coding

V. HARDWARE IMPLEMENTATION
Modelling the circuit to generate codewords in Verilog HDL.
Tool Used – Xilinx Vivado Design Suite (2021.2 Edition)

5.1 Verilog Code

The circuit is designed using Hardware Description Language – Verilog.

Fig. Verilog Code

5.2 Circuit Diagram (RTL Schematic)

Fig. Circuit Diagram

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Verilog Implementation of Hamming Code for Error Control Coding

5.3 Waveform

The codewords that are generated by simulating the Verilog code can be seen in the waveform below.

Fig. Waveform representing codeword generation

VI. CONCLUSION
Thus, codewords can be generated using the linear block code method which is then transmitted so that
the encrypted information is safe and can be decoded at the receiver side. The main advantage of this method is
that we do not need to retransmit the information if error is detected. This method will automatically correct the
error. The future-work should provide insights into design of complete Circuit used for detecting and correcting
errors.

REFERENCES
[1]. Ambadas balu shinde, “Implementation of linear block code for Digital Communication System using Configurable FPGA”
Conference paper–January 2010. PVP Institute of Technology India.
[2]. R. W. Hamming. “Error detecting and error correcting codes” Bell System technical journal, vol. 29, no. 2, pp. 147–160, 1950.
[3]. A. Mazumdar and A. S. Rawat On “Adversarial Joint Source Channel Coding”. Information Theory Proceedings (ISIT), 2015 IEEE
International Symposium on. IEEE, 2015.
[4]. Arash Ahmadpour and A. Ahadpour Shal (2009) “A Novel formulation of hamming code” Conference Paper. Conference ID:
ECTI-CON 2009.

www.ijres.org 73 | Page

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