2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 110

Application of Improved PSO for Optimal Design of

CMOS Two-stage Op-amp using Nulling Resistor
Compensation Circuit
1
Bishnu Prasad De, 2K. B. Maji, 2R. Kar, 2D. Mandal, 3S. P. Ghoshal
1
Department of ECE, HIT, Haldia, India
2
Department of ECE, NIT Durgapur, India
3
Department of EE, NIT Durgapur, India
[email protected]

Abstract—In this paper, design of an analog VLSI circuit is In section III, PSO and CRPSO algorithms are described
proposed using an evolutionary optimization technique. Here, concisely. In section IV, discussion of simulation results for
CMOS two-stage op-amp using nulling resistor compensation the proposed technique are given. Lastly, conclusion of the
circuit is considered for the optimal design by utilizing an work is given in section V.
improved form of Particle Swarm Optimization (PSO) method
that is Craziness based Particle Swarm Optimization
(CRPSO).The concept of PSO is simple and it replicates the II. SPECIFICATIONS FOR DESIGN AND FORMULATION OF COST
nature of bird flocking. As compared to Genetic algorithm (GA), FUNCTION
PSO deals with less mathematical operators. Premature
CMOS two-stage op-amp using nulling resistor
convergence and stagnation problem are the two major
limitations of PSO technique. PSO has been already been compensation circuit (Fig. 1) is optimally designed in this
improved to CRPSO to eliminate the limitations of PSO and is paper.
now applied for the optimal design of analog VLSI circuit in this A. Design steps for CMOS two-stage op-amp using nulling
paper. Control parameters of CRPSO are nearly robust and it
resistor compensation circuit
produces near-global convergence. In this work, CRPSO is used
to optimize the sizes of the MOS transistors’ to minimize the
The specifications for design of the circuit are taken as
overall area occupied by the circuit. The results obtained from
CRPSO technique are validated with SPICE. SPICE based follows: slew rate (SR), voltage gain (Av), unity gain
simulation results show that CRPSO is much better technique bandwidth (UGB), maximum ICMR (VIC (max)), minimum
than previously reported techniques for the design of above ICMR (VIC (min)) and power dissipation (Pdiss).
mentioned circuit in terms of MOS area, gain, power dissipation
etc. The variables taken for the design are given as follows:
width of channel (W) and length of channel (L) for the MOS
Keywords—Analog IC; CMOS two-stage op-amp; Evolutionary
transistors presented in the circuit, compensation capacitance
Optimization Techniques; Nulling resistor.
(CC). The steps for the design of the circuit [9] are given as
follows:
I. INTRODUCTION
• Choose the minimum value for CC and put the
VLSI circuits in analog domain play a crucial character
for the design of analog IC. Exact sizing of MOS transistors’ output pole, p 2 at 2.2 times larger than UGB. For the phase
in VLSI circuit is a complex process. Evolutionary technique margin of 60º, it is presumed that right half plane zero, z1 is
is a proficient option for automation in sizing of MOS
transistors’ in analog IC. Eberhart et al. [1-2] developed the located outside ten times of UGB.
concept of PSO. Area of CMOS operational amplifier circuit CC > 0.22C L (1)
[3-4] is optimized by utilizing PSO technique. To obtain
maximum gain and UGB, folded cascode op-amp circuit is gm6
designed by PSO method in [5]. p2 = − (2)
CL
Here, the area optimized design of CMOS two-stage op-
amp using nulling resistor compensation circuit [6-7] is gm6
investigated utilizing CRPSO algorithm [8]. z1 = (3)
CC
The paper is written as follows: The design procedure
of the circuit is explained and the Cost Function (CF) is • Calculate I D 5 so as to assure SR and Pdiss .
defined in section II.
I D 5 = SR.C C (4)

978-1-5090-4724-6/17/$31.00 ©2017 IEEE

 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 111

• Calculate the transconductances of M1 and M2 from • To set VA = VB, VSG10 must be equal to VSG6.
C C andUGB . Therefore,

g m1 = 2π .UGB.C C (5) W11  I D11  W6 

=   (17)
L11  I D 6  L6 
W  W 
• Determine the values of  1  and  2  . I D5
 L1   L2  Choose I D11 = I D10 = I D 9 = (18)
W1 W 2 g m1 2
= = (6) W  I 
L1 L2 K n′ I D5
• Set  10  = 1. The ratio  D10  determines the
 W3 

W
 and  4

 from the maximum
 L10   I D5 
• Calculate
 L3   L4  W 
value of ICMR.
  of M9.
L
W3 W4 I D5
= = W9  I D10  W5 
L3 L4 K p [V DD − Vin (max) − Vtp (max) + Vtn (min)]2
′ =   (19)
L9  I D 5  L5 
(7)
• The aspect ratio of M8 is
W   W12 
• Estimate  5  and   from the minimum  W10  W6 
 L5   L12     I D 6
value of ICMR.  W8   C C   L10  L6 
  =   (20)
W5 W12 2I D5  L8   C C + C L  I D10
= = (8)
L5 L12 K n′ [VDS 5 ( sat )]2 • To examine that the RHP zero, z1 has been shifted
I L  on the top of the output pole, p2, initially compute Rz. VSG8
where V DS 5 ( sat ) = Vin (min) − V SS − Vtn (max) −  D5 1  is equal to VSG10. VSG10 is given by
 K n′ W1 
2 I D10
(9) VSG10 = + Vtp (21)
 W6  '  W10 
• Estimate   from (10). K p  
 L6   L10 
W6 W 4  g m 6  • Determine Rz
=   (10) 1
L6 L4  g m 4  Rz = (22)
W 
where g m6 ≥ 10 g m1 (11)
(
K  8  VSG10 − Vtp
'
p )
and g m 4 = K ′p (W4 / L4 ) I D5 (12)  L8 
• Determine I D 6 required for Pdiss . • z1 is computed as
−1
( g m6 ) 2 z1 = (23)
I D6 = (13) C 
2 K p' (W6 / L6 ) Rz CC −  C 
 g m6 
W 
• Estimate  7  to obtain the ratios of current For all realistic cases, the pole at the output is cancelled
 L7  by the zero.
between I D 6 and I D 5 . The parameters taken for the design of the circuit are given
below.
W 7 W5  I D6  Positive and negative supply voltage (V) are denoted as
=   (14)
L7 L5 I 
 D5  V DD and V SS , respectively; threshold voltage (V) of NMOS
• Check the voltage gain (Av) and power dissipation and PMOS are represented as Vtn and Vtp , respectively; V DS
as given in (15) and (16), respectively.
is the voltage drop between drain and source of MOS
2 g m 2 g m6 transistor (V), VGS is the voltage drop between gate and
Av = (15)
I D 5 .I D 6 ( λ n + λ p ) 2 source of MOS transistor (V). Transconductance parameters
Pdiss = ( I D 5 + I D 6 )(V DD + V SS ) (16) (µA/V2) for PMOS and NMOS are given as K ′p and K n′ ,
respectively; Channel length modulation parameters (V-1) for
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 112

PMOS and NMOS are denoted as λ p and λ n , respectively. { }

Vi(k+1) = r2 × sign(r3 ) ×Vi(k ) + (1 − r2 ) × C1 × r1 × pbesti(k ) − S (ik ) + (27)
I D is the drain current of MOS transistor. g m is the { }
(1− r2 ) × C2 × (1 − r1 ) × gbest(k ) − S (ik )
transconductance. where r1 , r2 and r3 represent the random numbers
For CRPSO, the size of initial population matrix is given as
(p×q), where p=10 and q=16. Rows (p) indicate the particle within 0 and 1 ; sign (r3 ) is represents in (28)
vectors present in the population and columns (q) indicate the sign(r3 ) = −1 where r3 ≤ 0.05
dimensions of particle vector, denoted as: (28)
=1 where r3 > 0.05
X = [ SR , Av , UGB , V IC (min) , V IC (max) , Pdiss , C C ,
Before changing its previous position, the velocity is
L1 , L 3 , L 5 , L 6 , L 7 , L 8 , L 9 , L10 , L11 ]. modified for each particle vector by using the term “craziness
craziness
velocity” ( vi ) and represented in (29).
Therefore, the total number of variables to be optimized
are q=16. Vi (k +1) = Vi (k +1) + P (r4 ) × sign(r4 ) × vicraziness (29)
The area taken by all the transistors in the circuit is defined as where r4 represents a random number within 0 and 1;
Cost Function (CF) and represented in (24).
a random parameter; P( r4 ) and sign (r4 ) are
craziness
12 v i is
CF =  (Wi × Li ) (24) given , respectively, as
i =1 P(r4 ) = 1 when r4 ≤ Pcr
The transistors required to design the circuit is 12. (30)
The ACO technique based circuit design results in CF of = 0 when r4 > Pcr
14.87µm2 [7]. Here, CRPSO technique is applied for sign(r4 ) = −1 when r4 ≥ 0.5
(31)
minimizing the CF. = 1 when r4 < 0.5
III. EVOLUTIONARY ALGORITHM USED where Pcr represents a predetermined probability of
A. Particle Swarm Optimization (PSO) craziness.
Parameters of CRPSO algorithm are provided in Table I.
PSO is an optimization technique dependent on population.
PSO is a very simple method, well explained in various
literature [1-2]. In the population, the velocity of particle IV. DISCUSSION OF SIMULATION RESULTS
vector is changed by the subsequent equation: MATLAB is used to implement the CRPSO technique to
( )
Vi (k +1) = w × Vi (k ) + C1 × rand 1 × pbest i(k ) − S i(k ) +
(25) design the circuit (Fig. 1).The input variables are shown in
(
C 2 × rand 2 × gbest (k ) − S i(k ) ) Table II. CRPSO is applied to attain the values of Cc , Wi and
Li where (i=1, 2,…, 12). For the authentication purpose,
where Vi (k ) represents the velocity of particle i at iteration Cadence (IC 5.1.41) is used to perform the transistor level
number k ; w represents the weighting function; C1 and simulations of the circuit. Simulation results based on CRPSO
technique as well as earlier reported techniques in latest
C2 represent the weighting factors; rand1 and rand 2 literature [6-7] are briefly described in the next section.
(k )
represent the random numbers within 0 and 1; Si represents A. Simulation results for CMOS two-stage op-amp using
(k ) nulling resistor compensation circuit
the current position of particle i at iteration k; pbesti
CRPSO is employed to design the circuit considering the
represents the personal best of particle i at iteration number k;
constraints as SR ≥40 V/µs, UGB ≥100 MHz, Av > 86dB,
gbest (k ) represents the group best at iteration number k. The −1V≤ ICMR ≤ 1 V, Pdiss ≤ 20 µW with the values of the
position of particle vector is changed by the subsequent
inputs as V DD = 1.2 V, V SS = -1.2 V, Vtn = 0.305V, Vtp = -
equation:
0.379V, K n′ =260µA/V2, K ′p = 82µA/V2. The constraints of
( k +1) (k ) ( k +1)
Si = Si + Vi (26) the design parameters are taken as C L = 0.05 pF, 0.011pF< Cc
B. Craziness based Particle Swarm Optimization (CRPSO) ≤ 10pF, 0.5 µm ≤Wi ≤ 10 µm, 0.13 µm ≤Li ≤ 1µm. Process
technology parameter used is 0.13µm. The previously stated
In birds’ flocking, a bird habitually modifies directions inputs and the constraints of the design parameters are given
unexpectedly. PSO is altered by presenting a different velocity in Tables II and III, respectively.
equation (27) correlated with various random numbers and the The total MOS area of 11.065 µm2 is obtained from
“craziness velocity”. This altered PSO is called as CRPSO [8]. CRPSO technique. Table IV demonstrates the optimal design
The velocity of particle vector is represented by the parameters achieved from CRPSO technique as well as other
subsequent equation: existing methods for the circuit. Using the design parameters,
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 113

the circuit is re-designed in SPICE to obtain the specifications

of the design. Simulation results for the circuit obtained from
SPICE are presented in Figs. 2-7, respectively.
Thakker et al. [6] have applied HPSO technique to realize
the similar circuit studied in this paper. HPSO based results
[6] have Av of 86.16 dB, UGB of 101 MHz, Pdiss of 21µW and
total MOS area of 29.275 µm2. Gupta et al. [7] have used
ACO and GA to design CMOS two-stage op-amp using
nulling resistor compensation circuit. ACO based results [7]
have Av of 77.21 dB, UGB of 0.1 MHz, Pdiss of 19.75µW and
total MOS area of 14.87 µm2. GA based results [7] have Av of
80.55 dB, UGB of 0.1037 MHz, Pdiss of 20.20µW and total
transistor area of 41.264 µm2. Here, CRPSO technique results
in Av of 88.61 dB, UGB of 111.2 MHz, Pdiss of 19.61µW and
total transistor area of 11.065 µm2, as given in Table V. Fig. 2. Slew rate of CMOS two-stage op-amp using nulling resistor
compensation circuit.
CRPSO technique produces much promising results for Av,
UGB, Pdiss and the total transistor area than the earlier reported
literature [6-7].

V. CONCLUSIONS
In this paper, CMOS two-stage op-amp using nulling
resistor compensation circuit is optimally designed by utilizing
the CRPSO technique. CRPSO is proficient to produce the
optimal design parameters for the circuit. The circuit is re-
designed in SPICE by utilizing the CRPSO based parameters.
Simulation results establish that CRPSO based optimal circuit
design achieves all the specifications of the design and
minimizes the total transistor area than previously reported
techniques. Seeing the simulation results, CRPSO shows its
ability to yield the near global optimal analog circuit design.
Fig. 3. Power dissipation of CMOS two-stage op-amp using nulling resistor
compensation circuit.

Fig. 1. CMOS two-stage op-amp using nulling resistor compensation circuit. Fig. 4. UGB, gain and phase of CMOS two-stage op-amp using nulling
resistor compensation circuit.
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 114

TABLE I. DIFFERENT PARAMETERS USED FOR CRPSO

ALGORITHM
Parameters CRPSO
Population Size (p) 10
Dimension of the optimization 16(Fig. 1)
problem (q)
Iteration Cycle 100
C1 2

C2 2
0.3
Pcr
0.0001
v craziness
TABLE II. INPUTS AND TECHNOLOGY TAKEN
Inputs, Technology Values considered
Fig. 5. CMRR of CMOS two-stage op-amp using nulling resistor VDD (V) 1.2
compensation circuit. VSS (V) -1.2
Vtp (V) -0.379
Vtn (V) 0.305
K n′ (µA/V2) 260

K ′p (µA/V2) 82

Technology 0.13µm

TABLE III. CONSTRAINTS OF THE DESIGN PARAMETERS FOR

CMOS TWO-STAGE OP-AMP USING NULLING RESISTOR
COMPENSATION CIRCUIT

Outputs Ranges considered

SR (V/µs) ≥ 40
Av (dB) >86
CL (pF) 0.05
CC (pF) 0.011 < Cc ≤ 10
UGB (MHz) ≥ 100
Fig. 6. Positive PSRR of CMOS two-stage op-amp using nulling resistor
ICMR (V) -1 ≤ ICMR ≤ 1
compensation circuit.
Pdiss (µW) ≤ 20
Length( Li ) in µm 0.13 ≤ L ≤ 1
Width (Wi ) in µm 0.5 ≤ W ≤ 10

TABLE IV.DESIGN PARAMETERS ATTAINED FOR CMOS TWO-

STAGE OP-AMP USING NULLING RESISTOR COMPENSATION
CIRCUIT
Design variables HPSO [6] ACO [7] GA[7] CRPSO
I0 (µA) 4.5 4.38 4 1.1
W1/L1 ; W2/L2 2.5/0.75 0.5/0.81 2/0.93 0.96/0.75
(µm/µm)
W3/L3 ; W4/L4 1.5/0.5 1.3/0.64 1.7/0.9 0.5/0.5
(µm/µm)
Fig. 7. Negative PSRR of CMOS two-stage op-amp using nulling resistor W5/L5 5.5/0.75 2.8/0.58 6/0.46 0.76/0.58
compensation circuit. ;W12/L12(µm/µm)
W6/L6 (µm/µm) 3.8/0.5 6.8/0.64 5.7/0.9 9.0966/0.5
W7/L7 (µm/µm) 7/0.75 4.6/0.58 9.7/0.46 4.95/0.5
W8/L8 (µm/µm) 1.5/0.25 1.6/0.68 8.8/0.98 1.115/0.25
W9/L9 (µm/µm) 3/0.75 1.5/0.58 4.2/0.46 0.58/0.58
W10/L10 (µm/µm) 4/0.75 0.5/0.17 6.5/0.76 0.53/0.53
W11/L11 (µm/µm) 4/0.75 0.5/0.17 5.1/0.76 0.57/0.57
CL (pF) 0.05 0.05 0.05 0.05
Cc (pF) 0.09 0.11 0.1 0.0275
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 115

TABLE V. COMPARISON OF SPECIFICATIONS OF DESIGN FOR

CMOS TWO-STAGE OP-AMP USING NULLING RESISTOR
COMPENSATION CIRCUIT
Specificatio HPSO ACO GA
Design Criteria
ns [6] [7] [7]
CRPSO References
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pp. 611-616, 1998.
Unity gain ≥ 100 101 0.1 0.1037 111.2 [3]R. A. Vural and T. Yildirim, “Analog circuit sizing via swarm
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analog circuit design using hierarchical particle swarm optimization”, IEEE
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[7] H. Gupta and B. Ghosh, “Analog Circuits Design Using Ant Colony
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[8] B. P. De, R. Kar, D. Mandal and S. P. Ghoshal, “Optimal High Speed

CMOS Inverter Design Using Craziness based Particle Swarm Optimization
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[9] P. Allen and D. Holberg, “CMOS analog circuit design”, 2nd edition, New
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