Switching Theory and Logic Design 4.3.6 Carry Look Ahead Adder ‘ The parallel adder discussed in the last paragraph is ripple cai carry output of each full-adder stage is connected to the carry higher-order stage. Therefore, the sum and carry outputs produced until the input carry occurs; this leads to a time process. This delay is known as carry propagation delay, which ca; considering the following addition. 0101 +0011 1000 i inp My f PUL of j 4 any sta, Me "Be cay ty delay in em x Nn be best om Addition of the LSB position produces a carry into the second position Tis when added to the bits of the second position (stage), produces a carry ints ten) ij position. The latter carry, when added to the bits of the third position, Prodi carry into the last position. The key thing to notice in this example is that the sun) generated in the last position (MSB) depends on the carry that was generated by addition in the previous positions. This means that, adder will not produce result until LSB carry has propagated through the intermediate full-adders, w represents a time delay that depends on the Propagation delay produced in an eal full-adder. For example, if each full-adder is considered to have a Propagation dsl of 30 ns, then S, will not reach its correct value until 90 ns after LSB cami generated. Therefore, total time required to perform addition is 90+30 = 120 ns | Obviously, this situation becomes much worse if we extend the adder cia add a greater number of bits. If the adder were hi Propagation delay could be 480 ns. One method of speeding up this process called look ahead-carry addition. This method utilizes logic gates to look at ¢ lower-order bits of the augend and addend to see if a higher-order carry is t! generated, Tt uses two functions : carry generate and cary propagate. Consider the circuit of the ful I adder shown in Fig. 4.27. Here, we define functions : carry generate and carry propagate. Sapp. andling 16-bit numbers, the ca by eliminating inter stage carry delyi Fig. 4.27 Full adder circuitatt Theory = 7 ‘ G = AB ‘ The output sum and carry can be expressed as ( 5, = PeC, \ Ga = GIRS gis called @ carry generate and it produces on carry when both A, and B, are ess of the input carry. P; is called a carry propagate because it is term regard th the propagation of the carry from C, to Cj... one, xd wil associate ) Now the Boolean function for the carry output of each stage can be written as follows- G = G+P,C Cy = G,+P,C, =G, +P, G+ P,Q) = G,+P,G, +P, PC, | ly | rel ae ' | | ait A | o—| 4 : -+ | O—>—. &, * Cy Cy Fig. 4.28 Logic diagram of a look-ahead carry generatorSwitching Theory and Logic Design Coe GM G=GHPG+AGsppe AQ) = G+ PG, +P3 PG, + PP, P,C, From the above Boolean function it can be seen that C. does C, and C, to propagate; in fact C, is propagated at the same wos e time ag ¢ Ye to SC ang oY The Boolean functions for each output carry are expressed in sum 2M thus they can be implemented using AND-OR logic or NAND-NANey Pot, | shows implementation of Boolean functions for Cy, Cy and C, using aa ig OR jg Using a look-ahead carry generator we can easily construct a Abit e with a look-ahead carry scheme. Fig. 4.29 shows a 4-bit parallel adder "8 a4, ahead carry scheme. As shown in the Fig. 4.29, each sum outo, “tha ut exclusive-OR gates. The output of first exclusive-OR gate ponte ae and | ay Look ahead carry generator Dp Cr itor Fig. 4.29 4-bit parallel adder with look ahead carry generand Logic Design 4-19 Combinational Logic Design ‘The carries are generated using look-ahead carry generator and ee | to the second exclusive-OR gate. Other inputs to exclusive-OR gate ff aes inp! ‘ond exclusive-OR gate generates sum outputs. Each output each i é 7 ; ed. delay of two levels of gate. Thus outputs S, through S, have equal 4 pt ion delay times: (Spas 5 a lookahead carry generator. Fig. 4.30 shows pin diagram and logic wy cn? Stig As shown in the logic symbol, the 74182 carry look ahead 5 tol f° a up to four pairs of active low carry propagate (Po,P1 ,P2,Ps) and ‘Ty et or ace 4GovGi,G2.Ga) signals and an active high carry input (C,) and provides va i "a active high carties (Cyr Cyayr Cyos) across four groups of binary adders. ‘ ae also has active low carry propagate ( P ) and carry generate ( G ) outputs ty ep may be used for further levels of look ahead. 449 2-4-1514 6 5 Ic 74182 Po Gp Py Gy. Pa Ge Pa.Gy Cn Ic 74182 Look ahead 13 | en generator Chey Save nex. Fig. 430 (a) Pin diagram Fig. 4.30 (b) Logic symbol Te logic equations provided at the outputs of 74182 are : Cau = Gy + Py Cy y Coy = G, +P, Gy +P, Py C, Cuz = G, +P, G, +P) Py Gy G = Gy4P) Gy +P P2G, + Py PLP Go P= BPPP >