Microprocessor

Microprocessor is programmable device that fetches the instructions, decodes,

executes and stores the results in the memory.

Registers Address Bus

ALU Timing and Control Unit Data Bus

Control Bus

Address Bus
Unidirectional and carries address from CPU to memory, input and output
devices.
Eg: 16 address lines ( A15, A14, A13, A12,……A2,A1,A0) / 16bit address bus
32 bit address bus(A31,,,, A1,A0)
Addressable memory locations/devices = 2^16 (65536)/1024= 64kb ,
Address lines: 10,14,16,20,24,32,36,40

Data Bus
Bi Directional and carries the data between CPU, memory and input and
output devices.
Eg: 16 data lines (D15, D14, D13, D12,…..D2,D1,D0) / 16 bit data bus
8 data line: 1111 0000
Size of data carried out is determined by data bus.
Size of Processor: 8 bit, 16 bit,32 bit, 64 bit
Control Bus
Carries the control signal between CPU, memory, and input and output
devices.
Eg: RD, WR, DT/R, CS, etc
Evolution of microprocessor
i) 4004 – 4 bit
ii) 8080, 8085 – 8 bit
iii) 8086, 80186, 80286, 80386(4GB), 80486 – 16 bit
Pentium, Pentium Pro, Pentium-II, III, IV-32 bit
iv) Dual core processor – 64 bit, (1 TB), 2.93GHz
Quad Core Processor – 64 bit, (1TB), 3.16GHz

Number System
0000 0000 – 00
0000 0001- 01
0000 0010 - 02
1100 1001 0000 0011 - C9 03; 05h + 05h =10: 0A
1000 0000 - 80
……..
1111 1110 -FE
1111 1111 - FF

Memory
1KB= 1K x B
1024 x 8bits – (2^10 x 8bits) 2kb – 1024*2 x 8bits = 2048=2^11
00 0000 0000 000 H
00 0000 0001 MOV A,B 001 H
00 0000 0010 MOV B,A 002 H
00 0000 0011 003 H
……….. 004H
………..
10 0000 0000 200 H
………..
11 1111 1110 3FE H
11 1111 1111
3FF H

Memory Size: 2Kb, 4Kb, 16Kb, 64Kb, 1Mb, 16Mb, 4Gb, 64Gb, 1 Tb

Features of 8085 Microprocessor

i) 8 bit microprocessor
ii) data bus – 8 lines, Address bus-16 lines (A15-A0),
2^16=65536/1024=64KB
iii) Interrupt sources – 5 hardware , 8- software
iv) Serial input/output – 1
v) Clock frequency -3MHz
vi) Operating voltage – 5v.
Pin Diagram of 8085

i) Address Bus (A0-A15)

ii) Data Bus(D0-D7)
iii) Control and status signals ALE: Address Latch Enable- Demultiplex
address and data bus
Control signals: RD, WR, ALE, IO/ M (IO-1, M-0)
 Status signals: S1,S0
iv) Interrupts and externally initiated signals
Interrupts : TRAP(Non Maskable), RST 7.5, RST 6.5, RST 5.5, and INTR

Externally initiated signals: RESET IN, RESET OUT, READY, HOLD,

HLDA

v) Serial I/O signals

SOD (Serial output Data )and SID( Serial input data)
vi) Clock signals
X1, X2 and CLOCK OUT
vii) Power supply
VCC and VSS

Status signals

S1 S0 Status
0 1 write
1 0 read
1 1 Opcode fetch
0 0 HALT
Example: IO/M- 1, S1-1, S0-0 - read- I/O
IO/M-0, S1-0, SO-1- write - memory
HOLD and HLDA

DMA – Direct Memory Access Controller

Demultiplexing of address bus and data bus

First Clock cycle:

AD0-AD7 : Multiplexed Address bus and Data bus

A0-A7 – Address Lines.

A8-A15- Address Bus

From Second Clock cycle onwards till the execution of current instruction:

AD0-AD7 : Multiplexed Address bus and Data bus

D0-D7 – Data lines

 A8-A15 – Address Bus

Architecture of 8085 microproccessor

Functional units of 8085

1) ALU 2) Registers 3) Timing and Control Unit

4) Interrupt control 5) Serial Input/Output control

1) ALU

As the name suggests, it performs arithmetic and logical operations like Addition,
Subtraction, AND, OR, etc. on 8-bit data.
2) Registers

Accumulator(A), General Purpose registers(B,C,D,E,H&L), Program counter(PC), Stack

Pointer(SP), Temporary register and Flag register.

Accumulator:

It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE

operations. It is connected to internal data bus & ALU.

General Purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L.
Each register can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their pairing combination is like
B-C (B), D-E(D) & H-L(HL).

Program counter

It points to the memory address of the next instruction that is going to be

executed.

Stack pointer

It is also a 16-bit register works like stack, which is always

incremented/decremented by 2 during push & pop operations.

Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.

Flag register
 It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1
depending upon the result stored in the accumulator.

D7 D6 D5 D4 D3 D2 D1 D0

S Z - AC - P - CY

 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)

Interrupt control
As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming
request. After the request is completed, the control goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.

Serial Input/output control

It controls the serial data communication by using these two instructions: SID
(Serial input data) and SOD (Serial output data).

Timing and control unit

It is for the generation of timing signals and the signals to control. All the
operations and functions both interior and exterior of a microprocessor are controlled
by this unit.
Example for flag register

1) FE h+ 35 h = __133_____

2) 53 h – 45h =_____0E___

8421

1) 1111 1110

0011 0101

1 001 1 0011 = 1 33; P=0 0000 0000 Z=1

CY-1, P-1, AC-1, Z-0, S-0

Format of Assembly Language Instructions

Mnemonics operands

Mnemonics: It gives information on what kind of operation has to be

carried out.

Mnemonics Destination Source

Operands: Data on which the operations has to be carried out.

Source and destination

Eg: i) MVI A, 05 ii) MOV A, B

MVI – Mnemonics A,05 – operands : A- destination, 05- source

Eg: LXI H, 2300

Addressing modes of 8085

X=5 , a=b ; int *q;

 Various methods of specifying the operands.

Types of addressing modes

Immediate, register, direct, indirect and implicit

Immediate Addressing mode:

The operand or data is provided as a part of the instruction.
Eg: i) MVI A, 55H ii) LXI H, 2300 iii) ADI 07H

MVI B, 67H

Register addressing mode

The operand/ data is present/resides in the register. The register is
mentioned in the instruction.
Eg: i) MOV B, C ii) MOV D,E
Memory Direct / Direct addressing mode

The operand is presents/resides in a memory location and the memory

location is mentioned in the instruction.

Eg: LDA 4500H, STA 2300

4500 FE

Memory Indirect addressing mode

The operand is present in the memory but memory location is not directly
specified in the instruction. HL – pointer register

Eg: LXI H, 4500H

MOV A, M
Implicit addressing mode

Address of operand is present in the mnemonic itself.

Eg: RAL, CMA

Instruction Sets of 8085

1) Data transfer group 2) Arithmetic group 3) logical group 4) Branch

control group 5) I/O and machine control group

Notations

Rs-A,B,C,D,E,H,L Rd - A,B,C,D,E,H,L Rp - B(B-C), D(D-E), H(H-L),SP,PC

8bit data- 00h-FFh 16bit data-0000h – FFFFh

16 bit address- 0000h-FFFFh M- Memory register

Load & store; load- memory to register, store-register to the memory

I) Data transfer group

1) MOV Rd, Rs ; (MOVE) ; copies the content from source to destination

MOV B, C ; (C ) B; x=y

MOV H, L ; (L ) H

MOV A, E ;

2) MVI Rd, 8 bit data ; ( Move Immediate) ;

MVI A, 55h ; 55h A

MVI B, 28h;

MVI D, 2A;

3) MVI M, 8 bit data ; (Move Immediate to memory register)

 LXI H 3334H

MVI M, 22h

4) LXI Rp, 16 bit data ; (Load 16 bit register with 16 bit data), SP, PC

LXI H, 3355h ; 33 H, 55 L

LXI B, 4466h; 44->B, 66->C

5) LDA 16bit address ( Load Accumulator)

LDA 2500h; (2500) A 2500 FE

After execution A will have FE

6) STA 16bit address (store accumulator)

STA 4300h ; A (4300) 4300 56

If A has 85h, after execution 4300 will have 85 4300 85

7) LDAX Rp (Load Accumulator Indirect)

LDAX B , LDAX D, LDAX H LDAX B

LDAX B: BC register pair holds Memory address, content in the memory

address will be copied to Accumulator.

If BC register pair holds (points) the memory address – 4500, then content
in the above address will be copied to A.
4500 29
After execution A has 29.

LXI B, 4500H
LDAX B

LDA 4500H

8) STAX Rp ( Store Accumulator Indirect)

STAX D, STAX B, STAX H

STAX D : DE register pair holds memory address, content in the Accumulator will
be copied to memory address pointed by DE register pair.

If DE register pair holds (points) the memory address 5300, and

Accumulator has 87h, after execution this instruction memory address 5300 has
87h.

LXI D, 5300H

STAX D

Before execution 5300 00

After execution
5300 87

9) LHLD 16 bit address (Load H and L registers directly)

LHLD 8302 8302 05->L

8303 0A->H

(8302) L ; content in the memory address 8302 will be placed in L Reg.

(8303)H ; content in the memory address 8303 will be placed in H Reg.
10) SHLD 16bit address (Store H and L registers directly)
SHLD 9304
9304 05
9305 0A
( L ) 9304 ; contents of L register is stored in the memory address of 9304.
(H) 9305; contents of H register is stored in the memory address of 9305.

11) XCHG (Exchange the contents of HL register pair with DE register pair)
HL – 3355 & DE – 7788
After execution of XCHG, HL has – 7788 and DE has 3355.

12) XTHL ( Exchange the SP with HL register pair)

SP has 8899 and HL has AABB
After execution of XTHL, SP has AABB and HL has 8899.

Memory Address 2000 to C reg.

LDA 2000; contents in the memory address 2000 load to Accumulator.
MOV C, A
1) Copy the contents from the memory addresses 2300 and 2301 to registers
B and C respectively.

Method 1
LDA 2300; (2300)placed in A
MOV B, A
LDA 2301; (2301) is placed in A
MOV C, A
Method 2
LHLD 2300; 2300  to L register, 2301  H
MOV B,L ; contents in L is copied to B.
MOV C, H; contents in H is copied to C.

1) Store the contents of C register to memory address 7000.

MOV A, C ; (C) A
STA 7000 ; (A)7000.
2) Store the contents of DE register pair to 8000.
Method1: MOV A,E
STA 8000
MOV A, D
STA 8001

II) Arithmetic instructions

ADD, SUB, INR, DCR and DAD
ADD and SUB
One of the operand/data should be in Accumulator (A) and second operand may
be in register or immediate value.
ADDITION
1) ADD Rs (Add register to Accumulator)
ADD H; ADD D;
ADD B ; (Accumulator) + (B)  Accumulator
A=23h ; B= 37h ; [ flags gets affected based on the sum)
5A; 0101 1010; Z=0, S=0, Cy=0, AC=0, P=1
2) ADD M (Add memory register to Accumulator)
 ADD M; (M) + (Accumulator )  Accumulator

3) ADI 8bit data ( Add immediate)

ADI 78H; 78+(Accumulator)  Accumulator; 78+59-> A

4) ADC Rs (Add register to Accumulator with carry)

ADC D; (D) + (Accumulator) + CY(0/1)  Accumulator
78H+29H+0
5) ADC M (Add memory register to Accumulator with carry)
ADC M; (M) + (Accumulator) + CY  Accumulator
6) ACI 8bit data (Add immediate with carry)
ACI 9A; 9A + (Accumulator) + CY  Accumulator

7) DAD Rp ( Add register pair to HL )

DAD D; (DE) + (HL)  HL
DAD B; (BC)+(HL) -> HL
SUBTRACTION
8) SUB Rs ( Subtract register from Accumulator)
SUB E; (A) – (E)  Accumulator

9) SUB M (subtract memory register from Accumulator)

SUB M; (Accumulator) – (M)  Accumulator

10) SUI 8bit data (subtract immediate value from Accumulator)

SUI 9B; (Accumulator) – 9B  Accumulator

11) SBB Rs (Subtract register from Accumulator with borrow)
SBB C; (Accumulator) – (C) – (CY-1)  Accumulator

12) SBB M (subtract memory register from Accumulator with borrow)

SBB M ; (Accumulator) – (M) – (CY)  Accumulator

13) SBI 8bit data (subtract immediate value from Accumulator with borrow)

SBI 5D; (Accumulator) – 5D – (CY)  Accumulator

INCREMENT and DECREMENT

14) INR R (Increment the register by 1)

INR B; (B) + 1  B [All flags gets affected except carry flag]

x=x+1; x++

FF +1= 1 00H-> B

15) INR M (Increment memory by 1)

16) INX Rp ; ( Increment register pair by 1)

INX H ; (HL) + 1  HL

INX B, INX D

17) DCR R (Decrement the register by 1)

DCR E; (E) - 1  E [All flags gets affected except carry flag]

18) DCR M; (Decrement the memory)

19) DCX Rp (Decrement register pair by 1)

DCX D; (DE) - 1  DE
FF+1= 1 00; 00H-1=

20) DAA (Decimal Adjust Accumulator)

To get valid BCD number. 22 + 99; 00 – 99,

MOV A, D

STA 6000

2) MVI C, 88

MOV A, C;

STA 7000

3) ADD D ( A) + (D)  A
STA 4500.

1) Place/Load the value 88h in A reg. and 99h in E reg., add these two
registers and store the sum in memory address of 8900.
2) Write a program to subtract the contents of H reg. from A reg. and store
the remainder in memory address of 9000 H.
3) Add the contents present in the memory locations 4000h and 4001 and
store the sum in 4002.

MOV A, C ;

STA 7000.

Store contents of DE reg. pair to 8000 and 8001.

Method1: MOV A,E

 STA 8000

MOV A, D

STA 8001

Method2:

XCHG ; H will D, L will E

SHLD 8000 ; L 8000, H 8001.

1) ADD E

STA 2000.

2) MVI A,88H

MVI E, 99H

ADD E

STA 8900h

3) SUB H

STA 9000H

LDA 4000h

MOV B, A

LDA 4001h

ADD B; (A) +(B)  A.

STA 4002
Write a program to subtract the contents of 8005 from contents of 8000. Store
the remainder in 9000.

LOGICAL INSTRUCTIONS

1) CMP R (Compare register with accumulator)

CMP B
A = R ; Zero flag is set
A<R; carry flag is set
A>R ; zero and carry flags are in reset
2) CMP M (Compare memory with accumulator)

3) CPI 8bit data (Compare immediate value with accumulator)

CPI A5;

4) ANA R (Logical AND register with accumulator)

ANA E ; (E) Ʌ (A)  (A)

5) ANA M (Logical AND memory register with accumulator)

6) ANI 8bit data (Logical AND immediate value with accumulator)

ANI 25;

7) ORA R (Logical OR register with accumulator)

ORA B; (A) V (B)  (A)

8) ORA M (Logical OR memory register with accumulator)

9) ORI 8bit data (Logical OR immediate value with accumulator)

10) XRA R (Logical XOR register with accumulator)

XRA C; (A) XOR (C)  (A)

11) XRA M (Logical XOR memory register with accumulator)

12) XRI 8bit data (Logical XOR immediate value with accumulator)

13) RLC (Rotate Accumulator Left)

CY D7 D6 D5 D4 D3 D2 D1 D0

0 1111 0000- 1 1110 0001

After execution of RLC

D7 D6 D5 D4 D3 D2 D1 D0 D7

14) RAL (Rotate Accumulator left through carry)

CY D7 D6 D5 D4 D3 D2 D1 D0, 0 1111 0000

After execution of RAL 1 1110 0000

D7 D6 D5 D4 D3 D2 D1 D0 CY

15) RRC (Rotate Accumulator Right)

CY D7 D6 D5 D4 D3 D2 D1 D0

After execution of RRC

DO D0 D7 D6 D5 D4 D3 D2 D1

16) RAR (Rotate Accumulator right through carry)

CY D7 D6 D5 D4 D3 D2 D1 D0

After execution of RRC

DO CY D7 D6 D5 D4 D3 D2 D1

17) CMA (Complement the accumulator)

18) CMC (Complement the carry flag)

19) STC (Set the carry flag)

Assume that Accumulator has the value 45h and carry flag is 0. Execute the RRC
for 4 times and what is the content of Accumulator?

0100 0101

1000 1010

0001 0101

0010 1010

0101 0100

0101 0100 54h

1) MVI A, 88h

MVI E, 99h

ADD E

STA 8900h

2) SUB H
 STA 9000h

3) LDA 4000h

MOV C, A

LDA 4001h

ADD C

STA 4002h

Load Accumulator with 45h and perform 2’s complement for the contents of
accumulator.

MVI A, 45h

CMA

INR A / ADI 01h

Branching Instructions
 Branching instructions are used to change the sequence of program
execution, ie, moves from one memory address to another memory address.

Types of branching instructions:

1) unconditional ( doesn’t check any conditions, and moves to target

address)

2) conditional (check the conditions and if condition is true then, moves to

target address)

1) JMP 16bit address ( Jump unconditionally)

JMP 2300h

LDA 4000h
MOV C, A
LDA 4001h
JMP 5600h
ADD C
5600: STA 4002h
2) JC 16bit address (Jump if carry flag is set/ jump on carry)

JC 1200

LDA 4000h
MOV C, A
LDA 4001h
ADD C
JC 5600h (loop1)
STA 4002h
-------
-------
Loop1(5600): STA 7600

3) JNC 16 bit address (Jump if carry flag is not set/jump on no carry)

 JNC 0025h LDA 4000h
MOV C, A
LDA 4001h
ADD C
JNC 5600h (loop1) (CY==0)
STA 4002h
-------
-------
Loop1(5600): STA 7600
4) JP 16 bit address (Jump on positive) (SF==0)

JP 2301h

5) JM 16 bit address (Jump on minus) (SF==1)

JM 4503h

6) JZ 16 bit address (Jump on zero) (ZF==1) MVI B,06h

JZ 6700h Loop2: DCR B
JZ loop1-T
JMP loop2
---
Loop1: STA 2300h
7) JNZ 16bit address (Jump on no zero), (ZF==0)

JNZ 3001h

8) CALL 16 bit address (call unconditionally)

CALL 2300h MOV C, A

LDA 4001h
ADD C
CALL 5600
4300: STA 4002h
-------
Subprogram, subroutine PC-> STACK -------
Loop1(5600): LXI B, 8900h
SUB H
 SUB L
RET

9) CC 16 bit address (call on carry)

10) CNC 16bit address (call on no carry)

11) CP 16bit address (call on positive)

12) CM 16bit address (call on minus)

13) CZ 16bit address (call on zero)

14) CNZ 16bit address (call on no zero)

15) CPE 16bit address (call on parity even)

16) CPO 16it address (call on parity odd)

17) RET (return unconditionally)

18) RC (return on carry)

19)RNC (return on no carry)

20) RP (return on positive)

21) RM (return on minus)

22) RZ (return on zero)

23) RNZ (return on no zero)

24) RPO (return on parity odd)

25) RPE (return on parity even)

26) RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7 (restart)

MVI A, 55h
CMA

INR A /// ADI 01h

Machine Control Instructions

1) NOP (No operation)

2) HLT (Halt)

3) DI (Disable Interrupt)

4) EI (Enable Interrupt)

5) RIM (Read Interrupt Mask)

6) SIM (Set Interrupt Mask)

Instructions related to stack

Stack is a portion in a read/write memory. It function as last in first out.

PUSH and POP are instructions to store and retrieve the data in stack respectively.

1) PUSH Rp (Push the contents of register pair onto stack)

PUSH B, PUSH D, PUSH H and PUSH PSW

PUSH B (Contents of BC register pair pushed onto stack)

PUSH D 2302 D

2303 C
SP-1 
2304 B
SP-1
2305
(Top of stack) SP
After execution of PUSH, SP decremented by 2.

2) POP Rp (Pop the contents of memory locations of stack onto register pair)

POP B, POP D, POP H and POP PSW

POP D, POP B
4502 22E
(Top of stack) SP

SP+1 4503 55D

SP+1 4504 96C

4505 0AB

After execution of POP instruction, SP 4506

incremented by 2.

LXI SP, 4502

Instructions related to data transfer between CPU and I/O devices

1) IN 8bit port address (Inputs the data from port address)

IN 28H ( (28) A)

2) OUT 8bit port address (Outputs the data to port address)

MVI A, 77H

OUT 56H (A) 56H

IN 67H

MOV C, A
STA 8300H

1) Write a program to add 2 8bit numbers present in the memory address of 2002
and 2003. Store the sum in the memory address of 4000 if carry is not set else
store it in 4500.

Classification of instruction based on instruction length

1) one byte or 1 word instruction

2) two byte or 2 word instruction

3) three byte or 3 word instruction

One byte instructions

One byte instructions consists of opcode and operand in a same byte.

XCHG, RAL, RRC, RLC, RAR, MOV A,B , ADD C

Two byte instructions

In Two byte instructions, first byte represents the opcode and second refers
8bit operand/8 bit address.

MVI A, 89H, IN 98H, ADI 67H

Three byte instructions

In three byte instructions, first byte represents the opcode, and second and
third bytes represent either 16bit data or 16 bit address.

LXI H, 2300H, JMP 8900H, LDA 4500H, STA 7800H

Interrupts of 8085

When microprocessor receives any interrupt signal from peripheral(s)

which are requesting its services, it stops its current execution and program
control is transferred to a sub-routine called Interrupt Service Routine (ISR),

INTR, RST 7.5, RST 6.5, RST 5.5, TRAP

RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.

Interrupts can be classified into various categories based on different parameters:

I) Hardware and Software Interrupts –

Hardware Interrupts:
When microprocessors receive interrupt signals through pins (hardware) of
microprocessor, they are known as Hardware Interrupts. There are 5
Hardware Interrupts in 8085 microprocessor. They are – INTR, RST 7.5, RST
6.5, RST 5.5, TRAP

Software Interrupts

Software Interrupts are those which are inserted in between the program
which means these are mnemonics of microprocessor. There are 8 software
interrupts in 8085 microprocessor. They are – RST 0, RST 1, RST 2, RST 3, RST
4, RST 5, RST 6, RST 7.

II) Vectored and Non-Vectored Interrupts

Vectored Interrupts
 Vectored Interrupts are those which have fixed vector address (starting
address of sub-routine) and after executing these, program control is transferred
to that address. Vector Addresses are calculated by the formula 8 * TYPE
Hardware Interrupts vector addresses are

INTERRUPT VECTOR ADDRESS

TRAP (RST 4.5) 0024 H

RST 5.5 002C H

RST 6.5 0034 H

RST 7.5 003C H

INTR Non Vectored Int.

For Software interrupts vector addresses are given by:

INTERRUPT VECTOR ADDRESS

RST 0 0000 H

RST 1 0008 H

RST 2 0010 H

RST 3 0018 H

RST 4 0020 H

RST 5 0028 H

RST 6 0030 H

RST 7 0038 H

Non vectored Interrupts

 Non-Vectored Interrupts are those in which vector address is not
predefined. The interrupting device gives the address of sub-routine for these
interrupts. INTR is the only non-vectored interrupt in 8085 microprocessor

III) Maskable and Non-Maskable Interrupts

Maskable interrupt:

Maskable Interrupts are those which can be disabled or ignored by the

microprocessor. These interrupts are either edge-triggered or level-triggered,
so they can be disabled. INTR, RST 7.5, RST 6.5, RST 5.5 are maskable
interrupts in 8085 microprocessor.

Non Maskable interrupt:

Non-Maskable Interrupts are those which cannot be disabled or ignored by

microprocessor. TRAP is a non-maskable interrupt. It consists of both level as well
as edge triggering and is used in critical power failure conditions.

IV) Priority Interrupts

When microprocessor receives multiple interrupt requests simultaneously,

it will execute the interrupt service request (ISR) according to the priority of the
interrupts.

TRAP - Highest Priority – Level Triggered

RST 7.5 - Rising edge triggered

RST 6.5 - Level Triggered

RST 5.5 - Level Triggered

INTR - Lowest Priority - Level Triggered

SIM (Set Interrupt Mask)

EI

MVI A, 09 0000 1001

SIM

Accumulator Pattern for SIM Instruction

D7 D6 D5 D4 D3 D2 D1 D0

M M M

SOD SDE - INTR MSE RST7.5 RST6.5 RST5.5

0000 1011

RIM (Read Interrupt Mask)

Accumulator Pattern for RIM Instruction

D7 D6 D5 D4 D3 D2 D1 D0

M0 M0 M1

SID I 7.5 I 6.5 I 5.50 IE RST7.5 RST6.5 RST5.5

1) Write a program to add 2 8bit numbers present in the memory address of 2002
and 2003. Store the sum in the memory address of 4000 if carry is not set else
store it in 4500.

LDA 2002H
MOV B, A

LDA 2003

ADD B

JNC loop1

STA 4500

JMP loop2

Loop1: STA 4000

Loop2: HLT

***************

JC loop1

STA 4000H

JMP loop2

Loop1:STA 4500H

Loop2: HLT

Write a program to add two 8 bit numbers present in the memory address of
2000 and 2001. Store the sum and carry in the memory address of 3000 and 3001
respectively.

FE

FF
 1111 1110

1111 1111

1 1111 1101 1 FD

MVI D, 00h

LDA 6000h

MOV B, A

LDA 6001h

ADD B

JNC loop1

INR D

Loop1: STA 7000h

MOV A, D

STA 7001h

0101 0101

0101 0101

A A 1010

MVI D, 00

LDA 2000
MOV B, A

LDA 2001

ADD B

JNC loop1

INR D

Loop1: STA 3000

MOV A, D

STA 3001

Write a program to subtract the data present in memory address of 5000h from
the data present in memory address of 5001h. Store the remainder in 6000h and
borrow in 6001h.

MVI D, 00

LDA 5000h

MOV B, A

LDA 5001

SUB B

JNC loop1

INR D

Loop1: STA 6000

MOV A, D
STA 6001