Computer Architecture
Assembly Programming
Lynolan Moodley
CSC2002S [email protected]
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What Makes a Computer?
INPUT
PROCESS OUTPUT
2
What Makes a Computer?
MEMORY
INSTRUCTIONS &
DATA
INPUT
PROCESS OUTPUT
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Von Neumann Architecture
• Instructions are data
• Programs can manipulate other programs
• Compilers, debuggers, operating systems
• Reflection classes in most languages
• Von Neumann bottleneck
• An issue: the processor is idle for a certain
amount of time while waiting for
instructions/data to be accessed from memory
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Standard Operation
Fetch-execute cycle:
• Fetch the next instruction from memory
• Increment the program counter
• Decode the instruction
• Read operands
• Execute operation
• Write result to memory
The program counter is the register containing the address of the instruction in the
program being executed.
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Instruction Philosophies
• Complex Instruction Set Computing (CISC)
• Usually in older architectures, eg: VAX, x86
• One instruction does a lot
• Reduced Instruction Set Computing (RISC)
• Simple instructions are executed rapidly
• Usually in more modern processors, eg: MIPS,
PowerPC, ARM
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E.g. of x86 instructions
• FXRSTOR – restore x87, MMX, XMM and MXCSR state
• FXSAVE – save x87 FPU, MMX technology and SSE state
• FXTRACT – extract exponent and significand
• FYL2X – compute y * log2x
• FYL2XP1 – compute y * log2(x+1)
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FXRSTORE Description
FXRSTOR reloads the x87 FPU, MMX technology,
XMM, and MXCSR registers from the 512-byte
memory image specified in the source operand. This
data should have been written to memory previously
using the FXSAVE instruction, and in the same format
as required by the operating modes. The first byte of
the data should be located on a 16-byte boundary.
There are three distinct layouts of the FXSAVE state
map: one for legacy and compatibility mode, a second
format for 64-bit mode FXSAVE/FXRSTOR with
REX.W=0, and the third format is for 64-bit mode with
FXSAVE64/FXRSTOR64.
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MIPS
• Microprocessor without Interlocked Pipelined
Stages
• A family of RISC architectures
• Clean scalable design
• Introduced in 1985
• Developed as 32-bit architecture, later as 64-bit
• Development ended – push to RISC-V
• QTSPIM: https://sourceforge.net/projects/spimsimulator/files/
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MIPS Instruction
• C++
• a = b + c;
• MIPS Assembly
• add a, b, c
• Machine code
• 00000010001100100100000000100000
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MIPS Instruction
C++
a = b + c + d + e;
MIPS Assembly
add a, b, c
add a, a, d
add a, a, e
OR
add a, b, c
add temp, d, e
add a, a, temp
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MIPS Instruction
C++
f = (g + h) - (i + j);
MIPS Assembly
add t0, g, h
add t1, i, j
sub f, t0, t1
OR
add f, g, h
sub f, f, i
sub f, f, j
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Assembler Directives
Top level directives
Directive Description
.text Indicates that following items are stored in the user text
segment, typically instructions
.data Indicates that following data items are stored in the data
segment
.globl sym Declare that symbol sym is global and can be referenced
from other files
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Terms
• 1 byte = 8 bits
• 1 halfword = 2 bytes
• 1 word = 2 halfwords = 4 bytes = 32 bits
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Assembler Directives
Data definitions
Directive Description
.word w1, …, wn Store n 4-byte quantities in successive memory words
.half h1, …, hn Store n 2-byte quantities in successive memory halfwords
.byte b1, …, bn Store n 1-byte quantities in successive memory bytes
.ascii str Store a non-null-terminated string in memory
.asciiz str Store a null-terminated string in memory
.float f1, …, fn Store n floating point single precision numbers in successive
memory locations
.double d1, …, dn Store n floating point double precision numbers in
successive memory locations
.space n Reserves n successive bytes of space
.align n Align the next datum on a 2n byte boundary
e.g. 22 = 4. Align next value on word boundary
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Variables
• A variable is a location in memory
• RAM is slow to access
• Processors contain many high-speed
memory slots on-chip, called registers,
that hold variable values OR memory
addresses (pointers) being used
• RISC instructions only work on registers
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