DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

QUESTION BANK
EE3302 - DIGITAL LOGIC CIRCUITS
Year/Sem : II / III Faculty: B. PANDY SELVI
UNIT 1 - NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES
PART A
1 What is the best example of digital system? [Apr/May 2023]
2 Define Nibble and byte. [Apr/May 2023]
3 Convert (101.01)2 to decimal number.[Apr/May-2019]
4 Perform subtraction on the following unsigned binary numbers using the 2's- complement of
the subtrahend (a) 11011 – 11001 (b) 110100 -10101[Nov/Dec-2018]
5 Convert (9B2.1A)H to its binary equivalent. [Nov/Dec-2021]
6 Convert a binary number (1101101)2 to decimal and octal numbers. [Apr/May-2019]
7 Convert (115)10 and (235)10 to hexadecimal numbers. [Nov/Dec-2018 &Nov/Dec-2017]
8 Convert: [Apr/May-2015]
(a)(475.25)8 to its decimal equivalent.
(b)(549.B4)16 to its binary equivalent.
9 Determine (377)10 in Octal and Hexa-Decimal equivalent. [Nov/Dec-2014]
10 Write about a gray code and mention it's advantages. [Nov/Dec-2018&-Nov/Dec-2017]
Draw the logical diagram of EX-OR gate using NAND gates. [Nov/Dec-2015]
11 State the associative property of Boolean algebra. [Apr/May-2018]
12 Reduce A(A + B). [Apr/May-2018]
13 Reduce a(b+bc’)+ab’ . [Apr/May-2017]
14 Define fan-in and fan-out. [Apr/May-2016]
15 Give each one example for error detecting code and error correcting code. [Apr/May-2019]
16 Construct OR gate and AND gate using NAND gate’s. [Nov/Dec-2016]
17 Define Tri-state gates. [Apr/May-2019]
18 Convert the following Excess - 3 numbers into decimal numbers. [Nov/Dec-2016]
(a)1011 (b)1001 0011 0111
19 Convert the following binary code into a Gray Code : (1010111000) 2. [Apr/May-2016]
20 Compare TLL and ECL logic families. [Nov/Dec-2022]
21 When is Quine McClusky method preferred for logic minimization? [Nov/Dec-2022]
22 List any four parameters that determine the characteristics of TTL logic family.[Nov/Dec-
2021]
23 Draw the circuit diagram of standard TTL NAND gate. [Nov/Dec-2020]
24 Draw the TTL based NAND gate. [Nov/Dec-2018]
25 Compare the totem-pole output with open-collector output? [Nov/Dec-2014]
26 A16-bit data word given by 1001100001110110 is to be transmitted by using a fourfold
repetition code. If the data word is broken into four blocks of four bits each, then write the
transmitted bit stream. [Nov/Dec-2020]
 PART-B
1 A)Given the two binary numbers X = 1010100 and Y = 1000011, perform the subtraction Y -
X by using 2's complements.(3) [Nov/Dec-2016]
B)Convert (23.625)10 to octal (base 8).(3) [Nov/Dec-2016]
Perform the following operation (756)8 - (437)8 + (725)16. Express the answer in octal
form.(8) [Nov/Dec 2015]
C)Briefly discuss weighted Binary code.(4) [Nov/Dec 2015]
2 Deduce the odd parity hamming code for the data: 1010. Introduce an error in the LSB of
the hamming code and deduce the steps to detect the error. [Apr/May-2016]
3 Explain in detail about error detecting and error correcting code.(13) [Nov/Dec-2018]
[EE6301- Nov/Dec-2017]
4 Explain in detail the usage of Hamming codes for error detection and error correction with
an example considering the data bits as 0101. (10) [Nov/Dec-2016]
5 Define Binary code. Demonstrate the Hamming code with an example. (13) [Apr/May-2019]
6 Design a odd-parity hamming code generator and detector for 4-bit data and explain their
logic. [Apr/May-2017]
7 Write short notes on following : (13) [EE6301-Nov/Dec-2018] [Nov/Dec-2017]
RTL (ii)DTL (iii)TTL (iv)ECL.
8 Explain TTL logic in detail along with its types.(13) [Apr/May-2019]
9 Explain the operation of TTL NAND gate with a neat circuit diagram. [Apr-May 2023]
10 Why is ECL called non saturating logic ? What is the main advantage accruing from this ?With
the help of a relevant circuit schematic, briefly describe the operation of ECL OR/NOR logic.
[Nov/Dec-2020]
11
Draw the circuit diagram and explain the working of TTL inverter with tri state out [Apr-May
2023]
12 Explain the concept and implementation of ECL logic family.[Apr-May 2023]
13 Draw the circuit of CMOS NOR gate and explain its operation. Mention any two points about
the advantages of CMOS over the other digital logic families.[Apr-May 2023]
14 Describe the working of a 2 input ECL NOR gate. [Nov/Dec-2022]
15 Explain the operation of 2 input CMOS NAND and NOR gate. [Nov/Dec-2022]
 UNIT – 2 - COMBINATIONAL CIRCUITS
PART A
1 Find the result of A + A' D + AC’. [Apr/May-2019]
2 State DeMorgan’s theorem
3 Write minterm & maxterm Boolean functions expressed by f(A, B, C) = Π(0, 3, 7). [Nov/Dec-
2020]
4 What is meant by canonical form? Give an example for POS and SOP canonical forms.
[Apr/May-2019]
5 Write the POS form of the SOP expression f (x, y, z) = x’yz + xyz' + xy’z. [Apr/May-2017]
6 Write the POS representation of the following SOP function: [Apr/May-2016]
f(x,y, z) = Σm (0, 1, 3, 5, 7).
7 Simplify the expression Z = AB + AB.(A.C). [Apr/May-2015]
8 Convert the given expression in canonical SOP form Y = AB + A'C + BC'. [Nov/Dec-2016]
9 Convert the given expression to the standard SOP form.
f(a,b,cz) = Σm (0, 1, 5,6,10,11,14,13,14,15). [Nov/Dec-2022]
10 Given F = B' + A' B + A' C': Identify redundant term using K-Map. [Nov/Dec-2014]
11 Define duality property. [Apr/May-2018]
12 What is a karnaugh map? [Apr/May-2018]
13 Mention the dependency of output in combinational circuits. [Nov/Dec-2018]
14 Design a Half Subtractor.[ Apr/May-2017]
15 What is the difference between half adder and full adder? [Nov/Dec-2021]
16 Draw the truth table of 2 :1 MUX. [Nov/Dec-2016]
17 Compare decoder and Demultiplexer. [Nov/Dec-2018] [EE6301-Nov/Dec-2017]
18 Give one application each Multiplexer and Decoder. [Nov/Dec-2014]
19 List out various applications of multiplexer? [Nov/Dec-2013]
20 Write the logic expression for Full adder and Full subtractor. [Apr/May-2019]
21 Convert (1001): to its equivalent Excess-3 code. [Nov/Dec-2022]
22 Write the truth table of a full subtractor. [Nov/Dec-2020]
23 Draw a logic diagram of a 4:1 line multiplexer. [May/June-2013]
24 Draw the logic diagram of a serial adder[Nov/Dec-2012]
25 Design a three bit even parity generator.[Nov/Dec-2020]

PART-B
1 Given the following Boolean function F = A' C + A' B + AB' C + BC. (13) [Nov/Dec-2018]
a. Express it in sum of min terms.
b. Find the minimal sum of products expression.
2 Obtain the minimum SOP using quine Mc Clusky's method. [Nov/Dec-2021]
3 i) Apply suitable Boolean laws and theorems to modify the expression for a two-
input EX-OR gate in such a way as to implement a two-input EX-OR gate by using
the minimum number of two-input NAND gates only. [Nov/Dec-2020]
ii) Write a simplified max term Boolean expression for Π(0, 4, 5, 6, 7, 10, 14)
using the Karnaugh mapping method. [Nov/Dec-2020]
4 i) Find the minterms of the following Boolean expression by first plotting the
function in a map : F= C’D+ABC’+ABD’+A’B’D[Nov/Dec-2020]

ii) Design a 4 bit gray to binary code converter. [Nov/Dec-2020]

5 Design a logic circuit that has three inputs, A, B, 0 and whose output will be HIGH only
when a majority of the inputs are HIGH. (15) [Nov/Dec-2018]
6 Implement the following function using only NAND gates : f(x,y, z) = Σm(0, 2, 4, 6)
[ Apr/May-2016]
7
Design a combinational circuit with three inputs, x, y and z, and the three outputs, A, B, and
C. when the binary input is 0, 1, 2, or 3, the binary output is one greater than the input.
When the binary' input is 4, 5, 6, or 7, the binary output is one less than the input.(15)
[Nov/Dec-2018]
8 Obtain the minimum SOP using K-map. F=Mo+M2+M4+M8+M9+M10+M11+M12+M13 [Apr-May 2023]
9 Simplify and implement the logic function F(A, B, C) =Σ(0, 1, 4, 5, 7) using logic gates.
[Apr/May- 2019]
10 Design a 3 bit comparator circuit and implement using logic gates. [Nov/Dec-2022]
11 Implement a full adder circuit using decoder and using multiplexer. [Nov/Dec-2021]
12 Draw the logic diagram of a 2-to-4 line decoder using NOR gates only. Include an enable
input. [Nov/Dec-2018]
13 Design a Combinational logic circuit to convert Binary to Gray code and write its truth table.)
[Apr/May-2019]
14 Design a full adder circuit using logic gates. [Apr/May-2019]
15 Design a 4-bit gray code to binary converter and express using logic gates. [Nov/Dec-2018]
16 Design a 4 x 2 priority encoder using logic gates. [Apr/May-2019]
17 Implement the following Boolean function using 4:1 Multiplexer. [Apr/May-2019]
F (W, X, Y, Z)=Σm (0, 1, 2, 4, 6, 9, 12, 14)
18 Using 8:1 multiplexer, realize the Boolean function
T=f (w,x,y,z) = m (0,1,2,4,5,7,8,9,12,13) [Apr-May 2023]
19 Implement the sum output of full adder using
4 x 1 multiplexer
2 x 1 multiplexer [Nov/Dec-2022]
20 Design a 2 bit magnitude comparator. [Nov/Dec-2021]
 UNIT – 3 SYNCHRONOUS SEQUENTIAL CIRCUITS
PART A
1 What are the classifications of sequential circuits? [Apr/ May 2023]
2 Difference between Combinational & Sequential Circuits.[Apr/ May2023]
3 Write down the characteristic table of JK. [Apr/May2019]
4 What is FSM? List its two basic types. [Apr/May2019]
5 Write the role of master clock generator in synchronous circuits. [Nov/Dec2018]
6 Comment about a preset table counter & ripple counter. [Nov/Dec2018]
7 Draw the sequential logic diagram for Parallel In Serial Out Shift register. [Apr/May2019]
8 Write the characteristic equation of JK flip flop and its truth table. [Apr/May2019]
9 Mention about race around condition in a flip flop. [Nov/Dec2018]
10 What is a presettable counter and ripple counter? [Nov/Dec2018]
11 What is a master slave flip flop? [Apr/May2018]
12 Give the comparison between synchronous and asynchronous counters. [Apr/May2018]
13 Give the characteristic equation and characteristic table of a T Flip Flop. [Apr/May2017]
14 State the differences between Moore and Melay state machines. [Apr/May2017]
15 Differentiate Mealy and Moore model. [Nov/Dec2016]
16 Draw the state diagram of JK flip flop. [Nov/Dec2016]
17 Give the characteristic equation and characteristic table of SR flip-flop. [Apr/May-2016]
18 State any two differences between Moore and Mealy state machines. [Apr/May-2016]
19 Draw the truth table and state diagram of SR flip-flop. [Nov/Dec-2015]
20 What is edge triggered flip fops? [Nov/Dec-2015]
21 Convert T Flip Flop to D Flip Flop. [Apr/May-2015]
22 State the rules for state assignment. [Apr/May-2015]
23 Show how the JK flip flop can be modified into a D flip flop or a T flip flop. [Nov/Dec-2014]
24 What are the different types of shift registers? [Nov/Dec-2021]
25 Differentiate mealy circuits from moore circuits. [Nov/Dec-2022]
26 Compare synchronous circuits with asynchronous circuits [Nov/Dec-2022]
27 Convert JK flipflop to D flip flop. [Nov/Dec-2021]
28 Compare level triggered flip flops and edge triggered flip flops. [Nov/Dec-2020]
29 Draw the timing diagram of four bit binary ripple counter each flip flop outputs. [Nov/Dec-
2020]

PART-B
1 What is meant by a Flip Flop? Write the characteristics equation, characteristics table and
draw logic of SR, JK and D flip flops. (2+4+4+3) [Apr/May-2019]
Explain the operation of SR flip-flop, T flip-flop and JK.(13) [Apr/May-2018]
2
3
Design a 2 bit even parity generator using more circuit and implement using D flip flops.
[Nov/Dec-2022]
Design a synchronous mod 6 counter using T flip flops. [Nov/Dec-2022]
4
5 Design a mod 6 counter using FFS. Draw the state transition diagram of
the same. [Nov/Dec-2021]
6 Design a sequential circuit with 4 flipflops ABCD. The next states of
B,C,D is equal to the present states of A, B, C respectively. The next state
of A is equal to the EXOR of present states of C and D. [Nov/Dec-2021]
7 i) With the help of a schematic arrangement, explain how a J-K flip-flop can be used
as a T flip-flop. [Nov/Dec-2020]
ii) Three four-bit BCD decade counters are connected in cascade. The MSB output of
the first counter is fed to the clock input of the second counter, and the MSB output
of the second counter is fed to the clock input of the third counter. If the counters
are negatively edge triggered and the input clock frequency is 256 kHz, what is the
frequency of the waveform available at the MSB of the third counter ? [Nov/Dec-
2020]

8 Design a 2-bit synchronous sequential down counter. [Apr/May-2019]

9 Explain in detail about different shift registers.(13) [Nov/Dec-2018] [Nov/Dec-2017]
10 Explain the operation of a 3-bit universal shift register. [Apr/May-2019]
11 Describe the design procedure with neat diagram about 4 bit bidirectional shift register with
parallel load. [Nov/Dec-2018]
12 Synthesis a 3 bit counter using T Flip Flop (State diagram, Excitation table, K-map, Logic
diagram [Apr/May-2019]
13 Explain Moore and Mealy models with the help of block diagrams. [Apr/May-2019]
14 Design a synchronous sequential logic circuit that goes through the sequence 0, 2, 4, 6, 8, 10,
12,14 repeatedly. Use D flip flops for your design. [Apr/May-2019]
15 Design a synchronous digital circuit, a Moore machine, which operates this traffic light at two
types of road crossing.(15) [Apr/May-2019]

16 Design a synchronous sequential circuit using JK for the given state diagram.[Apr-May 2023]
17 Draw the state table for the following state diagram. [Apr/May-2019]
 UNIT – 4 ASYNCHRONOUS SEQUENTIAL CIRCUITS AND
PROGRAMMABILITY LOGIC DEVICES
PART A
1 What is static 1 hazard? [Apr-May 2023]
2 How can the hazards in combinational circuit be removed? [Apr-May 2023]
3 Distinguish between PAL and PLA. [Nov/Dec-2022]
4 What are critical and non critical races? [Nov/Dec-2022]
5 What is programmable logic array? How it differs from ROM? [Nov/Dec-2021]
6 What are the steps for the design of asynchronous sequential circuit? [Nov/Dec-2021]
7 When dynamic hazard occurs in digital circuits? [Nov/Dec-2020]
8 Determine the size of the PROM required for implementing a dual 8 to 1 multiplexer
with common selection inputs logic circuits. [Nov/Dec-2020]
9 Define metastable state. [Apr/May-2019]
10 Draw the structure of PAL. [Apr/May-2019]
11 Draw the block diagram of asynchronous sequential circuit. [Nov/Dec-2018]
12 Outline about PLA. [Nov/Dec-2018]
13 Define race condition. How it can be eliminated. [Apr/May-2019]
14 Describe PROM. [Apr/May-2019]
15 What happens to the information stored in a memory location after it has been, read and
write operation? [Nov/Dec-2018] [Nov/Dec-2017]
16 What is Programmable Logic Array? [Nov/Dec-2018] [Nov/Dec-2017]
17 Define address and word. [Apr/May-2018]
18 Why was PAL developed? [Apr/May-2018]
19 What is a flow table? Give example. [Apr/May-2017]
20 State the difference between PROM, PAL and PLA. [Apr/May-2017]
21 What is static hazard and dynamic hazard? [Nov/Dec-2016]
22 Define races in asynchronous sequential circuits. [Nov/Dec-2016]
23 What are the two types of asynchronous sequential circuits? [Apr/May-2016]
24 State the difference between PROM, PLA and PAL. [Apr/May-2016]
25 What is PROM? [Nov/Dec-2015]
26 Compare pulsed mode and fundamental mode asynchronous circuit. [Nov/Dec-2015]
27 State the difference between static 0 and static 1 hazard. [Apr/May-2015]
28 What is a PROM? [Apr/May-2015]
29 What is a deadlock condition? [Nov/Dec-2014]
30 Draw the block diagram of PLA. [Nov/Dec-2014]
 PART-B
1 Develop the state diagram and primitive flow table for a logic system that has two
inputs S and R and a single output Q. The device is to be an edge triggered SR flip-flop
but without a clock. The device changes state on the rising edges of the two inputs.
Static input values are not to have any effect in changing the Q output.(13)[Apr-May
2023]
2 Design an asynchronous sequential circuit that has two inputs X2 and X 1 and one
output Z. The output is to remain a 0 as long as X1 is a 0. The first change in X2 that
occurs while X1 is a 1 will cause a Z to be a 1. Z is to remain a 1 until X1 returns to 0.
Construct a state diagram and flow table. Determine the output equations.
[Apr-May 2023]

3 An asynchronous sequential circuit has two internal states and one output. The
excitation and output functions describing the circuit are

Y1 = X1 + X1Y2' + X2Y1 ;Y2 = X2 + X1Y1’ Y2 + X1Y1 ; Z = X2 + Y1

Draw the logic diagram of the circuit.(5)

Derive the transition table and output map.(5)
Obtain a flow table for the circuit.(5)[Apr-May 2023]
4 Design an asynchronous binary toggle circuit that changes state with each rising edge
of clock input. Assume the initial output as zero. [Apr-May 2023]

5 i) Design a binary ripple counter that counts 000 and 111 and skips the remaining six
states, that is 001, 010, 011, 100, 101 and 110. Use presentable, clearable negative
edge-triggered J-K flip-flops with active LOW PRESET and CLEAR inputs. Also,
draw the timing waveforms and determine the frequency of different flip-flop outputs
for a given clock frequency, fc.
ii) You have two two-bit binary numbers A1 A0 and B1B0. Design a PLAdevice to
implement a magnitude comparator to produce outputs for A1 A0 being ‘equal to’, ‘not
equal to’, ‘less than’ and ‘greater than’ B1B0. [Nov/Dec-2020]
6 Design a 2-bit synchronous sequential down counter. [Apr/May-2019]
7 Design a Modulo-6 asynchronous binary up-counter. [Apr/May-2019]
8 Illustrate about hazards in sequential circuits and the steps to avoid hazards in it.
[Nov/Dec-2018]
9 Design an asynchronous circuit that will operate only for the first pulse received
whenever a control input is asserted from LOW to HIGH state. Further pulses will be
ignored. [Nov/Dec-2018]
10 Elaborate the concept of PROM, EPROM, EEPROM in detail. [Apr/May-2018]
11 Explain the operation of bipolar RAM cell with suitable diagram. [Apr/May-2018]
12 Write short notes on PLA and PAL.(7) [Nov/Dec-2017]
What is hazards? Explain hazards in digital circuits. (6) [Nov/Dec-2017]
13 Design a PLA structure using AND and OR logic for the following functions.(10)
F1= Σm(0, 1, 2, 3, 4, 7, 8, 11, 12, 15)
F2 = Σm (2, 3, 6, 7, 8, 9, 12, 13)
F3 = Σm (1, 3, 7, 8, 11, 12, 15)
F4= Σm (0, 1, 4, 8, 11, 12, 15) [Nov/Dec- 2016]
 Draw a PLA circuit to implement the functions (13) [Apr/May-2019]
14
15 Give the PLA realization of the given function using a PLA with 3 inputs, 4 AND gates
and 2 outputs. [Nov/Dec-2022]
16 Describe the concept and working of PLA. [Nov/Dec-2021]
17 i) What are complex programmable logic devices (CPLDs) ? Briefly outline salient
features of these devices and application areas where these devices fit the best.
ii) Show that a BCD ripple counter can be constructed using a four-bit binary ripple
counter with asynchronous clear and a NAND gate that detects the occurrence of count
1010. [Nov/Dec-2020]
18 Describe the concept, working and application of FPGA. [Nov/Dec-2021]
 UNIT-5 VHDL
PART – A
1 What are the types of gate arrays in ASIC? [Apr May 2023]
2 Give the different bitwise operators. [Apr May 2023]
3 What are generics in VHDL? [Nov/Dec2022]
4 List out the objects of VHDL. [Nov/Dec2022]
5 What is verilog? [Nov/Dec2021]
6 What is the structural gate level modeling? [Nov/Dec2021]
7 Explain in words and write HDL statements for the operations specified by the following
register transfer notation : If (S1 = 1) then (R0 ← R1) else if (S2 = 1) then (R0 ← R2).
[Nov/Dec2020]
8 What is the use of repeat statement in Verilog HDL ? [Nov/Dec2020]

9 State the purpose of test bench. [Apr/May2019]

10 Write a VHDL program for an EX NOR gate using behavioral coding. [Apr/May2019]

11 Draw the basic structure of MOS transistor. [Nov/Dec 2018]

12 List the languages that are combined together to get VHDL language. [Nov/Dec2018]

13 List the purpose of Test bench. [Apr/May2019]

14 Design a Half adder using HDL. [Apr/May2019]

15 Define modularity. [Nov/Dec2018]

16 List the languages that are combined together to get VHDL, language. [Nov/Dec2018]

17 Define Cache memory. [Apr/May2018]

18 Infer the concept of switch level modeling. [Apr/May2018]

19 Give the syntax for package declaration and package body in VHDL. [Apr/May2017]

20 Write the VHDL code for a 2 x 1, multiplexer using behavioral modeling.

[Apr/May2017]

21 Write VHDL behavioral model for D flip flop. [Nov/Dec2016]

22 Write the VHDL code for a logical gate which gives high output only when both the
inputs are high. [Nov/Dec2016]
23 What is data flow modeling in VHDL ? Give its basic mechanism. [Apr/May2016]

24 Write the VHDL code to realize a 2 x 1 multiplexer. [Apr/May2016]

25 State the advantage of package declaration over component declaration. [Nov/Dec 2014]

PART – B
1 Draw the VLSI design flow chart used for IC design and fabrication. (7) [Apr/May-2019]
Write down a VHDL code for 8 x 1 De multiplexer.(6) [Apr/May-2019]

2 Write a VHDL module that implements a full adder using an array of bit-vectors to
represent the truth table. (13)[Apr-May 2023]
3 Write HDL behavioral description of JK flipflop using if- else statement based on value
of present state. (8)[Apr-May 2023]
Write a VHDL program for 4 bit counter - Behavioral. [Nov/Dec-2021]
4
Write a VHDL program of Demultiplexer 1X4. [Nov/Dec-2021]
5

6 i) What is a hardware description language ? What are the requirements of a good HDL ?
Briefly describe the salient features of VHDL and Verilog.
ii) Write the VHDL code for four bit adder circuit. [Nov/Dec-2020]

7 i) Explain in detail about ASMD chart for digital system design.

ii) Explain in detail about ASM block with an example. [Nov/Dec-2020]
Describe RTL in HDL with an example.(13) [Apr/May-2019]
8
Write the HDL program for 2:1 multiplexer in Dataflow and Behavioral Description.(6)
9
[Apr/May-2019]
Write program in HDL to design 2 bit up/down counter.(7) [Apr/May-2019]
Implement a full adder circuit using PLA having three inputs, eight product terms, and
10
two outputs.(13) [Nov/Dec-2018]

Briefly explain the operations involved using RAM and compare Static RAM and
11
Dynamic RAM. (13) [Nov/Dec- 2018]
Give the different arithmetic operators and bitwise operators.(13) [Apr/May-2018]
12
Explain in detail about the principal of operation of RTL design. (13) [Apr/May-2018]
13

14 Draw the circuit of CMOS AND gate and explain its operation. Also implement using
VHDL. [Apr/May-2018]
15 Design a 4 bit code converter which converts given binary code into a code in which the
adjacent number differs by only 1 by the preceding number. Also, develop VHDL coding
for the above mentioned code converter. (15) [Nov/Dec-2016]

Write the VHDL code for the given state diagram, using behavioural modelling. Design it
16
using one-hot state -assignment and implement it using Programmable Array Logic
(PAL). (15) [Apr/May- 2017]

Signature of the Course faculty HOD/EEE